APURVA OKA

60E 32nd Street Apt 505 Chicago IL 60616 Email: aoka@iit.edu Phone: (312)-608-6017
OBJECTIVE:
Seeking a design and development position, where strong background, effective communication
and a complete knowledge in hardware, software development can be used to improve operations.
EDUCATION:
Master of Science (MS) in Electrical Engineering, Available: Dec 2009.
Illinois Institute of Technology (IIT), Chicago, IL
Bachelor of Engineering (BE) in Electronics, May 2007
University of Mumbai, India
PROFESSIONAL EXPERIENCE:
IIT, Graduate Assistant, Jan 09- Present
Achievement: “Master’s Level Exceptional Design and Presentation 2008-09”.
 Designed prefix adder (brent kung & kogge stone) and ripple carry adder using 45nm
predictive technology model. Dual threshold voltage (V th) transistor model and 45nm
technology was used for improvement in power delay and performance. HSIMPLUS (by
Synopsys) used to generate Spice Netlist using 45nm standard library files and Verilog code.
 Analyzed modified Spice netlist. Analyzed power & performance using Nanosim and Hspice. The
Dual Vth scheme reduced the power to the order of 10-06 W from 10-05 W.
 Development of Graphical User Interface (GUI) Tool in UNIX using C++& Perl/TCL to
automate generation/modification of Net list File.

Case New Holland (CNH), Student Intern, June 09 – August 09

 Designed and developed a desktop Graphical User Interface (GUI) application in VC++
for generating CRC checksum for input Intel Hex file from microcontroller using Visual studio™.
 Implemented a telematic GPS, fleet and security management Qualcomm system,
display.
 Performed and documented quality survey of electrical and electronic components for
construction equipments. Tested electrical components using Oscilloscope and Multi-meter.
 Documented tests and analysis reports for the Electrical components of the vehicle TLB.

Studio Spicuzza, Engineer, May 09 – July 09

 Built a Prototype for Touch Screen Guitar. Developed & performed Hardware/Software
testing.
RELATED PROJECTS:
CAD tool Design for Static Timing Analysis, Fall 2008
 Designed and developed Graphical User Interface using C++, TCL/Perl in UNIX for static
timing.
4 bit, 8 bit, 16 bit Carry look ahead adder using TCL/Tk, Fall 2008
 Implemented using TCL/TK with a hierarchy model with the user input taken from C/C+
+ files.
Sub band Implementation of Active Noise Control using C++ and Matlab. (Fall 2007)
 Designed M-Band filter bank, LMS Algorithm for appropriate step size µ and direction.
Division by Digit Recurrence algorithm for radix-2, Fall 2008
 Implemented the algorithm using VHDL on Xilinx™ ISE Virtex 4 FPGA.
Network Security ASIC Design, Spring 2008
 Designed and Implemented Message Digest 5 (MD5) ASIC using Verilog in Sun Solaris.

SKILLS:
Languages: C/C++, Matlab, Verliog/VHDL, TCL/Tk and Perl, Assembly Language (8086, 8051).
EDA Tools: Cadence 5.0, 6.1, Magic 6.5, Hspice, PSpice, NanoSim, Power Theater, Sue, Simvision,
Modelsim, Synopsys, Design Compiler, NcVerilog, Hsimplus, GCC Compiler, MinGW.
Operating Systems: Windows, Sun Solaris, UNIX, Linux.
Computer Skills: Microsoft Office (Word, PowerPoint, Excel, Access) and Visual Studio TM 2008.
ACTIVITIES:
 Member of IEEE. Head of Cultural Committee in Undergraduate College & Leader of Women’s
Org.