Resistance

In CMOS circuits, resistances can either be passive or active. Active resistances are
usually the resistance of the transistors when they are biased to operate in linear or
saturation region. The passive resistors are designed and implemented with different
materials on the chip.
e have two types of resistors in a !"SI circuit# useful and parasitic.
$%SISTA&C% '%SI(&
Resistance
t W
L
A
L
R
)
) ) = =
hat are the parameters that we have control over as a
designer*
, "
and +some control on selection of

,. 'ifferent resistivity,

, is achieved by using
diffusion, metal, poly, &-ell and .-ell materials.
Since thic/ness is process dependent then
t

for a given material is constant and is

commonly called the sheet resistance
s
R of a material.
W
L
R R
s
) =
&ow, if "0, as with the case of a s1uare shape, then $0
s
R .
In the above diagram both s1uares have the same resistance. $ is then measured as 2
.age 3 of 34
%5amples of evaluating resistance with the help of s1uare shapes are6
7or irregular width, $8corner 0 $s +9.:;<9.3a, where
a 0 32=
Other factors:- !ariation in resistivity across the resistor
depth, Temperature, !oltage and process variations may
affect the total resistance. 7or e5ample6
$esistor values are a function of temperature
> ) ) 3 ? , +
=
= 3
dT T dT T R T R
C C o
+ + = , dT = T Tnominal at 25* Celcius
Constants ta/en from the process manual
The resistance is layout dependent and is calculated from sheet resistance
, +
) , +
w w
L
R L R
S

=
, w is the width and w is the process variation actor!
The resistance values are a function of the voltage
> ) 3 ? , +
=
=
d" " d" " R " R
C C #
+ + + = d" is chan$e in volta$e
Constants ta/en from the process manual
.age = of 34
ST$@CT@$A" O!%$!I% O7 A $%SISTA&C% A&' ITS ASSOCIAT% .A$ASITIC
$%SISTA&C%S
7or each metal, $c is the contact resistance, and is measured as $c2Area.
Typical resistance values.
7or 9.4u process6
!alues are per s1uare
&< diffusion 6 A9 2 M36 9.9; 2
.< diffusion 6 3:9 2 M=6 9.9; 2
.olysilicon 6 3= 2 MB6 9.9B 2
.olycide6=-B 2 .-well6 =.4C 2
&-well6 3C 2
.age B of 34
Active resistors
These resistors are made with transistors. The resistors are made up from two
components6 The channel resistance and the drain and source resistance plus the contact
resistance.
Conductance in Linear & Saturation Regions:
In the linear region,
=
,, +
=
ds
t $s n
ds
d
"
ne$lectin$ " " %
"
&
=

Resistance o channel, $channel 0

, +
3
t $s n
" " %
t $s ds
" " " <
as
=
ds
" is very small
Similarly for the saturation region
9 =

ds
d
"
&
+neglecting channel modulation effect,
If the channel length modulation is not neglected, then
Conductance 0

=
> ?
=
t $s
n
" " Resistance 0

=
> ?
=
t $s n
" "
Conclusion' &n saturation re$ion, resistance (etween )rain and Source is usuall* a hi$h
value!
.age : of 34
3, 'rain2 Sources $esistance6
$'+S, 0 $sh ) number of s1uares < contact resistance.
The value of the drain and source resistances should be added to the channel resistance,.
A more accurate resistance, $channel, is given below ta/ing channel length modulation and
!
=
into account
$
CD
3
CE

"
----- !
(S
!
T
( )
!
'S
[ ]
----------------------------------------------------------------E
=
=, Channel $esistance6
This depends on the region of operation6
R
CH
2
K'
W
L
----- V
GS
V
T
( )
2

----------------------------------------------------
=
Contact resistance:
The contact resistance Rc is defined as $c0

c2A where

c is the specific contact

resistance and A is the contact area. Smaller contacts of higher impurities will increase
the resistance. $c assumes that the current through the contact flows uniformly. Dowever,
there is a current crowding phenomena around the corners and leading edges of the
contact.
Typical Contact resistance values for 0.! process:
Contact resistance6 .olyI to MetalI 49
!ia resistance6 Metal I to Metal II 3.4
!ia resistance6 Metal II to metal III 3.
CA"AC#T#$% LOA&S #' A C(OS #'$%RT%R
.age 4 of 34
Assume that we have an inverter driving another e1uivalent inverter. The second inverter
can be considered as a capacitive load as shown below.
The first order model capacitances include the drain capacitances of the driver and the
gate capacitances of the driven stage. Cw is the wiring capacitance.
&ote6 e usually neglect Cgsp and Cgsn while doing hand analysis of such circuits.
w $n $p dn dp L
C C C C C C + + + + =
.age ; of 34
TRA'S#%'T A'AL)S#S O* CA"AC#T#$% C#RC+#TS
Of importance is the transient behavior of the inverter and the speed at which we are able
to drive such an inverter. e assume a step is applied to the input of the inverter. As
shown below the pmos is off and the nmos initially starts in saturation. At this moment
the !dsn is high and the nMOS is in Saturation. As the load capacitor discharges then
!out decreases until !ds 0!gs-!t when the nMOS enters the linear region. Therefore
there are two stages in calculating the fall time of this inverter.
&efinitions
In response to a step input, the rise and fall times at the output are defined as6

Time ta/en for any signal to rise
from 39F to G9F of !dd is
called $ise Time or tr.
Time ta/en for the signal to fall
from G9F to 39F of !dd is
called 7all Time or tf.
&ow assume that a step input is applied to an inverter
.age A of 34
The propagation delay td is obtained by the 49F line as shown in the figure above. And
the propagation delay td can be calculated using the following e1uation6
=
plh phl
d
t t
t
+
=
.age H of 34
The fall ti,e- tf
e will analyIe the fall time in two steps, ie when the nmos is in saturation and then
when it is in linear region.
Initially when the step input is applied, the nMOS is on and in saturation as
!(S -!tn J !'S, now ignoring channel modulation, we have
=
> ?
=
tn $s
n
)+
" " & =

also,
dt
d" C
&
ds
CA,
.
=
.age G of 34
!in
I
DN $
i
n
.

$
i
n
.
/
$
i
n
.
0
VD
D
Vo
VDD-VT

(VDSAT)
Merging the two e1uations,
dt
Cd"
" "
ds
tn $s
n
=
=
> ?
=

=
"))
"tn ")) tn $s n
ds
t
t
" "
d" C
dt
G . 9
=
=
3
> ?
. =

= 3
, +
, 3 . 9 + =
tn dd n
dd tn L

" "
" " C
t

Similarly, for tf=, we have the transistor in the linear region,

tf= 0

=
"tn "))
"))
ds
ds tn $s n
ds
t
t
" " " "
d" C
dt
3 . 9
=
=
3
> ?
.

7all time then is given by tf 0 tf3 < tf=

R#S% A'& *ALL T#(% %1+AT#O'S
In order to get tfall +tf, we add tf= and tf3. 7ollowing many manipulations we get6
,> =9 3G ln+ 4 . 9
, 3 +
, 3 . 9 +
?
, 3 +
=
n
n
n
n "
C
t
dd n
L

,
dd
tn
"
"
n =
(rouping all the constants into C, the fall time is given as6
dd n
L

"
C
- t

=
, where - is a constant (etween . and / dependin$ on the process
If the same analysis are done for the trise +tr, we have
dd p
L
r
"
C
- t

=
trise and tfall, are dependent on 2", C" and !dd. e can only change C" and 2" through
design. !'' depends on the process.
#n order to e2uali3e t
rise
and t
fall
- ,a4e n r p
W W =
where
p
n
r

=
.age 39 of 34
&esign 5uidelines:
6eep the rise and fall ti,es e2ual and s,aller than the propagation delay of the
inverter. This will have an i,pact on speed and the power consu,ption of the
circuit.

"ropagation &elay
The following factors influence the delay of the inverter6
"oad Capacitance
Supply !oltage
Transistor SiIes
Kunction Temperature
Input Transition Time
7or any given process, we can e5press the delay +td, for an inverter as6
t
phl
0
, , + p "t " p
Cload
))
?
p "t "
p "t
)) ,
, =

< ln +
3
, , + :

))
))
"
p "t "
, >
t
plh
.
, , + n "t " n
Cload
))
?
n "t "
n "t
)) ,
, =

< ln +
3
, , + :

))
))
"
n "t "
, >
Since &, . are design parameters and !'' is technology dependent while n and p are
constants for a given process then the delay can be e5pressed as6

n
L
n
phl
C
A t

=
,
p
L
p plh
C
A t

=
The coefficients LAnM or LApM is obtained for a given process from analytical calculations
or better through S.IC% Simulation. That is, for a /nown C" and n, we usually
determine td+spice, for either tphl or tplh and then determine An or Ap. Once An and Apare
obtained, it can be used repeatedly for the same process. ie6
L
n spice d
n
C
t
A

=
Su,,ari3ing then-
t
phl
0
, , + p "t " p
Cload
))
?
p "t "
p "t
)) ,
, =

< ln +
3
, , + :

))
))
"
p "t "
, >
t
plh
.
, , + n "t " n
Cload
))
?
n "t "
n "t
)) ,
, =

< ln +
3
, , + :

))
))
"
n "t "
, >
.age 33 of 34
t.D" 0
")) n
A C , L

E
t."D 0
")) p
A C n L

E

t
r
C
"
C
.
!'' 3 p < + ,
---------------------------------------
= N + , 3 p < + ,
3 p < + ,
---------------------------- 3G =9p < + , ln < 0
t
r
:C
"
AE
.
C
.
!''
--------------------- 0
Assume normaliIed voltages
vin= !in2 !''
vo= !o2 !''
n 0 !T&2 !''
p 0 !T.2 !''
t
"7L
and t
f
decrease with the increase of 89L of the '(OS
t
"L7
and t
r
decrease with the increase of 89L of the "(OS
The delay of the inverter increases with the increase of the input
transition ti,es t
r
and t
f

.age 3= of 34
%ffect of the input Slope
All the previous e1uations involve the use of a step unit signal as input. Dowever real-life
signals are often ramps. In that case we will use the following e1uation to incorporate the
effect of the slope of tr and tf6
7irst Order Model
= =
,
=
+
r
phl
phl
t
t t
step
+ =
= =
,
=
+

plh
plh
t
t t
step
+ =
, +
=
3
plh phl d
t t t + =
Alternative 'elay Model +for the rise time,
, = 3 +
;
p
t
t t

dr dr
step
+ = ,
dd
t
"
"
p =
A"T%$&ATI!% '%"AO +tp, 7O$M@"A
7or the short channel transistor the following delay e1uation is also used6
,
3
+
=
+ ,
L
p
C
t
+
=
Also in the short channel model the source resistance becomes important and it has to be
ta/en into account, since it affects both the current and the voltage threshold.
Oet another model
tp 0
, +
T ))
)) L
" " A
" C

here A is a constant and P is another constant between 3.: and = depending upon the
technology us
.age 3B of 34
"L%AS% 'OT%6 All models presented here are appro5imate# we only use them as
guidelines when implementing circuits. Accurate delays are obtained only through
S#(+LAT#O'
Assignment #4
!"SI 'esign, CO%& :43
A CMOS inverter +I&!3,, with a physical layout shown in 7ig.3, drives a similar
inverter, and operates at a supply voltage of B.B!.
a. 'etermine the delay of the inverter I&!3.
b. hat will be the ma5imum speed of operation of I&!3 if it drives ten similar inverters
c. One of the methods to speed up the operation is to increase the siIe of the driver.
'etermine the 2"s of the .MOS and the &MOS transistors of I&!3 so that the speed in
part +b, is doubled, assuming that the supply voltage has been reduced by 39F. +Dint6
@se twice the diffusion capacitance of 7ig.3,.
d. 'etermine the dynamic power dissipation of the inverter +I&!3, for part c.
@se CMC technology parameters CMOSIS4Q
.age 3: of 34
7ig. 3 Inverter for design
.age 34 of 34
M3 !''

!in
:.9R


!out M3
;.4 R

=.4 R
B.9 R (nd
9.4 R

=.4R
B.9 R
=.9R