Design of an Interface Circuit for Integrated

Capacitive Sensors
Yang Wang
Department of Electronic Science and Technology
Anhui University
Hefei, China
Department of Electronics and Information
Zhejiang Wanli University
Ningbo, China

Jun-Ning Chen
Department of Electronic Science and Technology
Anhui University
Hefei, China
jnchen@ahu.edu.cn

sunny1978@126.com
Jiang Hu
Department of Electronics and Information
Zhejiang Wanli University
Ningbo, China

Dao-Ming Ke
Department of Electronic Science and Technology
Anhui University
Hefei, China
kezhang2@mail.hf.ah.cn

hujiang@zwu.edu.cn

capacitor circuit, the interface capacitor-voltage converter

circuit is designed. Simulating by Cadence software with
TSMC 0.18m CMOS process, the sensitivity of the
converter is 1mV/10fF. This circuit can decrease the effect
of bias voltage, amplifier offset, charge injection and clock
feed through.

AbstractIn this paper, an interface circuit for integrated

capacitive sensors is designed and simulated by Spectre of Cadence
software with TSMC 0.18m complementary metal oxide
semiconductor (CMOS) process. This circuit converts the
capacitance of sensing capacitor to the voltage change based on
switched-capacitor circuit. The results show the sensitivity of
1mV/10fF and the circuit removes the effect of bias voltage and
amplifier offset, decreases the influence of charge injection and
clock feed through.
Keywords-capacitive sensor; interface circuit; CMOS;
switched-capacitor;op amp

I.

II.

A. Structure of CMOS Capacitive Sensor

A sensing capacitor of CMOS-based capacitive sensors is

designed using standard CMOS technology and simple
post-processing steps. The capacitive sensor with comb
electrodes is researched in the paper. Fig.1 illustrates the
schematic structure of a CMOS capacitive sensor. The
sensing material of sensitive layer can detect the
environmental parameter change, which leads to the change
in the dielectric constant and hence in the capacitance.

INTRODUCTION

Capacitive sensors are one of the most important sensors,

which are used in industry, agriculture, home appliances, etc
[1, 2]. With the development of integrated circuit (IC), several
researchers have recently used the standard CMOS
technology to fabricate integrated sensors [3-7]. CMOS-based
capacitive sensors have benefit of small size, high
performance, easy mass-production and low cost.
The principle of capacitive sensors is to measure
capacitance variances with changes the environmental
parameter [8]. Integrated capacitive sensors include the
sensing capacitor, interface circuit and signal processing
circuit, etc [9, 10]. However, because of the change in
capacitance is very minute, the general order of magnitude is
pF, it is important to design high performance and precision
interface circuits for micro-capacitance detecting.
In this paper, an interface circuit for an integrated
capacitive sensor is researched. Based on switched-

978-1-4577-0321-8/11/$26.00 2011 IEEE

THEORY ANALYSIS

Figure 1. Schematic structure of CMOS capacitive sensor

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Thus, the capacitance is transformed the voltage output

change using switched-capacitor amplifier.
III.

CIRCUIT DESIGN

An interface circuit is described in this section based on

switched-capacitor circuit. The two-stage operational
amplifier and CMOS switches are designed.
A. Principle of Interface Circuit
Figure 2. Structure of comb electrodes

The senor interface circuit is illustrated by Fig.4. The

circuit contains three kinds of components: capacitors,
switches, and operational amplifier. The capacitance of
sensing capacitor Cs changes the environmental parameter.
The structure of reference capacitor Cr and sensing
capacitor Cs is the same. C f is a feedback capacitor, and

The integrated capacitive sensor with comb electrodes is

compatible with CMOS technology. The structure of comb
electrodes is shown in Fig.2. L is the length of aluminum
electrodes, s is the width of each electrode, and g is the
distance between adjacent electrodes.
After CMOS fabrication, the sensitive layer is deposited
in the post-processing step [11]. The sensing capacitance can
be increased and the sensitivity of capacitive sensors can be
improved using the structure of comb electrodes. Si substrate
can be ground to reduce the parasitic capacitance.

Ch is a storage capacitor. The voltage source Vbias offers

the op amp bias voltage.

According to charge conservation of the op amps
negative input, the equation is given by
Vo =

B. Principle of Switched-Capacitor Circuit

A switched-capacitor circuit is shown by Fig.3, where

three switches control the operation: s1 connects C1 to Vin ,
s2 connects C1 to ground, and s3 provides unity-gain
feedback [12]. Based on the principle of charge transference,
the output voltage change is calculated. Firstly, s1 and s3 are
on and s2 is off. The circuit is operating in sampling phase,
which is called (n 1)T state. For a high-gain operational
amplifier, the charge stored on negative input of the amplifier
is Q[(n 1)T ] . In nT state, s2 is on and s1 and s3 are off. The
circuit is operating in feedback phase, and the charge must be
transferred to C2 .
(1)
Q[( n 1)T ] = C1Vin
(2)
Q ( nT ) = C2 (0 Vout )
Based on charge conservation of the negative input, the
equation is described by
Vout =

C1
Vin
C2

C s Cr
Vin + Vbias
Cf

(4)

When s2 is on, the error voltage because of the op amp

offset and bias voltage are stored on capacitor Ch . When s2 is
off, the amplifier output consists of the signal voltage and the
voltage previously stored on Ch . Therefore, the output
voltage which contains only the signal voltage is described
by
Vout =

Cs Cr
Vin
Cf

(5)

The switch s2 is off slightly earlier than s2, which

decreases the influence of charge injection.
B. Op Amp Circuit

The op amp design requires the trade-off between the

multiple parameters, for example, high voltage gain, high
input impedance, output voltage swings, speed, power
consumption and so on. It is very important for the whole
circuit design to choose adequate parameters.

(3)

Figure 3. Schematic of switched-capacitor circuit

Figure 4. Schematic of interface circuit

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The two-stage op amp structure is designed (see Fig.5).

The first stage of the op amp is a folded cascode amplifier
supplying a higher gain, and the second stage is a
common-source amplifier supplying a greater output swing.
Based on TSMC 0.18m CMOS process, the op amp is
designed and simulated by the Spectre of Cadence software.
The circuit uses a single 3.3V power supply. The bias
voltages are Vb1 = 2.34V , Vb 2 = 1.1V and Vb 3 = 0.92V . The
current source is I ref = 20uA .
The open-loop gain of the op amp is 84.5dB at the low
frequency, the phase margin is 67.9o and the unity gain
bandwidth is 6.43MHz. The result is shown by Fig.6.

Figure 8. Input common-mode range of the op amp

Figure 9. Output voltage swing of the op amp

Figure 5. Op amp circuit

Figure 10. CMOS switch

Therefore, the voltage gain and op amp stability meet the

design requirement.
Fig.7 shows that common mode rejection ratio is
117.5dB. Input common-mode range of the op amp is 0~2.1V,
and the output voltage swing is 0.42V~2.35V (Fig.8 and
Fig.9). The slew rate of the op amp is 14.75V/us and static
power consumption is 1.7mw.
Figure 6. Open-loop gain and phase margin of the op amp

C. CMOS Switch

CMOS switch is used in place of a signal MOS switch,

which consists of a PMOS and a NMOS (see Fig.10). The
CMOS switch decreases the effect of charge injection and
clock feed through.
IV.

SIMULATION RESULTS OF INTERFACE CIRCUIT

The interface circuit for the capacitive sensors is

illustrated by Fig.11 using Cadence software. In the circuit,
Cr = 10 pF , C f = 10 pF and the capacitance of Cs
changes from 10pF to 15pF. Vin = 1V and the voltage source
supplied the negative of the op amp is 1V.

Figure 7. Common mode rejection ratio of the op amp

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The output voltage is discrete-time value, which can be

good for signal processing in the back.

When Cs is 11pF, the output voltage is equal to

100mV in Fig.12(a). The output voltage changes 500mV if
Cs is 15pF (see Fig.12(b)). The results are in agreement
with the output voltage in (5). The output voltage changes
from 0 to 0.5V with the change of Cs = 10 pF ~ 15 pF .
The sensitivity of the converter is 1mV/10fF through
fitting simulation data. The simulation results show that the
output voltage can remove the effect of bias voltage and
amplifier offset. The clock phase Phi1 and Not-Phi1 drop
slightly earlier than Phi and Not-Phi, which decreases the
effect of charge injection.

V.

CONCLUSIONS

The interface circuit for CMOS-based integrated

capacitive sensors is designed based on switched-capacitor
circuit in the paper. Simulating by Cadence software and
TSMC 0.18m CMOS process, the sensitivity of the
converter is 1mV/10fF. This circuit can remove the effect of
bias voltage and amplifier offset, decrease the influence of
charge injection and clock feed through. There is good
reference value to the capacitive sensors design.
ACKNOWLEDGMENT

This research work is supported by the open research

fund of Key Laboratory of MEMS of Ministry of Education,
Southeast University and Ningbo Natural Science
Foundation (2008A610010).
REFERENCES
[1]

C.Hierold, Intelligent CMOS sensors, The Thirteenth Annual

International Conference on Micro Electro Mechanical Systems, pp.1-6,
2000.
[2] V.M.Alexanderamishev, S.Kishore, F.M.Yang, Y.Q.Du and M.Zahn,
Interdigital sensors and transducers, Proceedings of the IEEE, Vol.92,
pp.811-845, 2004.
[3] E.Ghafar-Zadeh, M.Sawan and D.Therriault, A 0.18-um CMOS
capacitive sensor Lab-on-Chip, Sensors and Actuators A, vol.41,
pp.454-462, 2008.
[4] L.Gu, Q.A.Huang and M.Qin,A novel capacitive-type humidity sensor
using CMOS fabrication technology, Sensors and Actuators B, vol.99,
pp.491-498, 2004.
[5] H Eltoukhy and K Salama, A 0.18-um CMOS bioluminescence detection
Lab-on-Chip, IEEE Journal of Solid State Circuits, Vol.41, pp.651-662,
2006.
[6] Y.Y.Qiu, C.Azereso-Leme, L.R.Alcacer and J.E.Franca, A CMOS
humidity sensor with on-chip calibration, Sensors and Actuators A,
vol.92, pp.80-87, 2001.
[7] C.L.Dai, A capacitive humidity sensor integrated with micro heater and
ring oscillator circuit fabricated by CMOS-MEMS technique, Sensors
and Actuators B, vol.122, pp.375-380, 2007.
[8] E. Zampetti, S. Pantalei, A. Pecora, A. Valletta, L. Maioloa, A. Minotti, et
al, Design and optimization of an ultra thin flexible capacitive humidity
sensor, Sensors and Actuators B: Chemical, Vol.143, pp.302-307, 2009.
[9] M.S.C.Lu, Y.C.Chena and P.C.Huanga, 55 CMOS capacitive sensor
array for detection of the neurotransmitter dopamine, Biosensors and
Bioelectronics,Vol.26, pp.1093-1097, 2010.
[10] F.Reverter and O.Casas, Direct interface circuit for capacitive humidity
sensors, Sensors and Actuators A, Vol.143, pp.315-322, 2008.
[11] M.Kitsara, D.Goustouridisa, S.Chatzandroulis, M.Chatzichristidi, I.
Raptis, Th.Ganetsos, et al, Single chip interdigitated electrode capacitive
chemical sensor arrays, Sensors and Actuators B, Vol.127, pp.186-192,
2007.
[12] B.Razavi, Design of analog CMOS integrated circuits, New York:
Mc Graw-Hill Press, 2001.

Figure 11. Interface circuit for the capacitive sensors

(a)

(b)
Figure 12. Simulation results of the output voltage

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