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Overview
Register Model Requirements
Automated generation
3
Register Block
Register File
Memory
Register
Field
uvm_reg_block
uvm_reg_block
uvm_mem
uvm_reg
uvm_reg
uvm_reg_field
uvm_reg_field
uvm_reg
Address maps
model access via a specific interface / bus master
4
uvm_reg
uvm_reg_field
uvm_reg_block
uvm_reg_map
uvm_reg_adapter
predict(uvm_reg_item)
Predictor
uvm_reg_adapter
0110110110
0010100100
1100100001
Bus Agent
DUT
S
D
bus_item
0110110110
0010100100
active part
5
1100100001
get()
update()
field configuration
endclass: SYS_CTRL_0
hierarchical
build() of
regmodel
pre_read()
post_read()
pre_write()
post_write()
post_predict()
0 1
Clear
Write 1 0
0 0
After predictor
has observed
R/W
value before
predict()
uvm_reg_field
uvm_reg_data_t
uvm_reg_data_t
uvm_predict_e
uvm_path_e
uvm_reg_map
if (kind == UVM_PREDICT_WRITE)
value = (value === 2'b01) ? 2'b01 :
(value === 2'b10) ? 2'b00 : previous;
endfunction
endclass: control_reg_field_cbs
9
fld,
previous,
value,
kind,
path,
map);
value to be
set after
predict()
UVM_PREDICT_READ
UVM_PREDICT_WRITE
UVM_PREDICT_DIRECT
Locking field
name in
constructor
10
task my_scoreboard::update_rtc_count;
int unsigned cnt = 0;
Does not
use access
policy "RO"
forever begin
@(timer_event_e);
void'(m_regmodel.SYS_RTC_COUNT.predict(cnt++));
end
Possible to use
access policy &
callbacks
endtask: update_rtc_count
reg.predict(value, .kind(UVM_PREDICT_WRITE));
reg.predict(value, .kind(UVM_PREDICT_READ));
11
DUT Register
???
1
Don't update if
comparison is
disabled
task my_scoreboard::uncertainty_window;
forever begin
@(window_start_e);
class my_reg_field extends uvm_reg_field;
my_fld.set_compare(UVM_NO_CHECK);
@(window_end_e);
function void do_predict(. . .);
my_fld.set_compare(UVM_CHECK);
super.do_predict(rw, kind, be);
end
if (kind == UVM_PREDICT_READ)
endtask: uncertainty_window
if (get_compare() == UVM_NO_CHECK)
value = previous;
endfunction: do_predict
endclass: my_reg_field
12
calls set_item()
$cast(extra_info, item.extension);
extension is a
uvm_object
bus_trans.addr
= rw.addr;
bus_trans.data
= rw.data;
bus_trans.master_id = extra_info.master_id;
return bus_trans;
endfunction: reg2bus
13
gpio_config
gpo
gpi
property gpio_control_p @(gpio_change_e)
(gpo == (gpi ^ gpo_invert) & gpio_en);
endproperty
15
testbench
uvm_component
uvm_reg_block
reg_monitor
DUT
0110110110
0010100100
uvm_reg_block
0110110110
0010100100
1100100001
SVA
Properties
bit [3:0] gpio_config;
initial begin
m_reg_monitor = new ("m_reg_monitor", null);
m_reg_monitor.add_field("GPIO_CONFIG");
forever begin
m_reg_monitor.wait_write("GPIO_CONFIG");
gpio_config = m_reg_monitor.get("GPIO_CONFIG");
end
end
16
Conclusions
Register Modeling Standard is key to UVM
Inconsistent approach with OVM
UVM_REG has all features necessary
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