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Code: AE68
DECEMBER 2011
Time: 3 Hours
(B) ASIP
(D) All the above
d. The CACHE is usually designed using SRAM rather than DRAM because
(A)
(B)
(C)
(D)
Cost
Performance
Appears on the same chip as a processor
Both (A) and (B)
Code: AE68
g. The Sensor networks are large-scale embedded systems that may contain
(A) Millions of nodes
(C) Thousands of nodes
(B) Switch
(D) Hyper Node
i. In the write through technique, whenever we write to the cache, we also write
to
(A) Main memory
(C) Both (A) and (B)
a. What is a design metric? List pair of design metrics that may compete with one
another, providing an intuitive explanation of the reason behind the
competition.
(8)
b. List and define the three main IC technologies. What are the benefits of using
each of the three different IC technologies?
(8)
Q.3
Q.4
Q.5
(8)
(8)
a. Explain how PWM works and show the interface structure controlling
a DC motor with a PWM.
(8)
(8)
(6)
(10)
(8)
Code: AE68
Q.7
Q.8
Q.9
(8)
(8)
(8)
(8)
b. In RTOS environments, what are the rules Interrupt routines must follow
that do not apply to task code?
(8)
(8)
(8)