INTRODUCTION TO LOW

POWER RF-
RF-IC DESIGN
Dr. T K Bhattacharyya PART – I
E & ECE Dept.
Basics of RF Design
Advanced VLSI Design Lab.
IIT Kharagpur..

WHAT IS RF? Application area of the RF-

RF-IC designer
Frequency spectrum: Wireless communication
Radar
Navigation
Remote sensing
• Why Lumped parameters models failed ………………. RF identification

• Kirchoff's to Maxwell’s…….
Automobile and Highways
Sensors:
• Failure of two port circuit parameter (Z, Y,ABCD) ……..
Medical
• Scattering parameter( S-parameter) on the basis of Maxwell equation Radio- astronomy and space exploration
comes in …

Beauty of RF_IC Design:

Comparison of Analog and RF/MW
Link between Microwave Engineer and Design Engineer
1. On Discrete PCB component
Maxwell equation’s are
( Analog [Low frequency<100MHz] ) ( RF/MW[ High frequency>100MHz] )
kirchoff’s law Total voltage around a
loop is zero( KVL) Conductor Simple Microstrip
wire line

Ceramic
No net current build Capacitor Thin Film
SMD comp.
up at any node(KCL)
•If ε & μ =0, (c α ) i.e infinitely fast wave
Resistor Carbon
propagation of wave gives KVL and KCL Thin Film
SMD comp.
•As the physical dimension of circuit element & sub-circuit in a IC chip is very less
(even less than 1/10th of λ [ 30 cm in air at 1 GHz] ) , so finiteness of the speed of Inductor Wire Thin Film
light is not noticeable inside chip, so a full transmission line ( Microwave) for on- Wound SMD comp.
chip design and analysis is generally unnecessary. Kirchoff’s law is well suited for on-
chip design
•But for interfacing the RF signals in / out of the chip, we need connectors,
boards, cables etc. Where transmission-line effects cannot be ignored
 Comparison of Analog and RF/MW Comparison of MMIC/RFIC
1. On Performance Based

( Analog [Low frequency<100MHz] ) ( RF/MW [High frequency>100MHz] ) Parameter MMIC( Discrete) RFIC( integrated)
Development Cost Moderate Very high
A. Small signal AC equivalent circuit A. Small signal AC equivalent circuit
Modifications Relatively easy & inexpensive Expensive ,generally one or
analysis analysis with parasitic i.e. Good circuit more new mask
Modeling
BOM cost Low Depends on volume , die sized
B. Linearity B. Matching and process used
Mixing Technologies Optimum device technology can Limited scope
C. Stability C. Noise be used through out ( combined
GaAs, BJT, MOS)
D. Noise (on few cases) D. Stability
Parts Count High Low to very low
E. Linearity Size Small to medium Smallest
F. Sensitivity Weight Light Lightest

G. Dynamic range Cost of Using Additional Moderate Low

transistor
Matched transistor Difficult to implement Very good , used extensively

Basic of RFIC design RF CIRCUITS AND SYSTEMS - DESIGN ISSUES

1. Phase shift of the signal is significant over the extent of the component because it’s size is
comparable with the wavelength.
2. The reactance of the circuit must be accounted for, particularly those associated with the
parasitic of the active devices.
3. Circuit losses causes degradation of Q, reduction of frequency selectivity and noise
performance.

• Disciplines required in RF design
4. Noise especially arising from the circuit can be significant and it’s effect needs to be modeled.
5. Electromagnetic radiation capacitive coupling and substrate coupling significantly alter the
performance of the circuit.
6. Reflection issues, because circuit size is of the order of a wavelength.
7. Circuit design should take care to ensure reflections do not cause any loss of gain, power, or
failure of components.
8. Nonlinearity which causes distortion and unwanted frequency components is undesirable, but
it may become essential part of the circuit operation, as in mixing or local oscillators.

• Analog/RF design octagon

Noise Gate induced noise

Thermal agitation of channel charge cause fluctuation of channel potential. This couples
Significance :The significance of noise performance of a circuit is the limitation it places on the
capacitively with gate terminal, leading to gate noise
smallest input signals(MDS) the circuit can handle before the noise degrades the quality of output signal.
• this noise is negligible at low frequency, but can dominate at RF
• Thermal Noise
-Brownian motion of thermally agitated charge carriers - generated in every physical resistor

• δ ~ 4/3 in long device

- both drain and gate noise share a common origin and they
are correlated

Shot Noise
- pure reactive components generate no thermal noise
-Gaussian white process associated with the transfer of charge across an energy barrier

Thermal Noise in MOSFET - due to DC current through p-n junction, gate channel
Th most significant source of noise
Channel Noise:
Flicker noise in MOSFET
In2 = 4kTγgm
• γ ~1 at a zero VDS for long channel device, 2/3 at saturation, 2-3 for short channel transistor -random trapping of charge at oxide interface
- modeled as a voltage source in series with gate
 Noise figure Noise figure (cont..)

Noise figure (F) specifies the noise performance of a circuit or device

• Limitation : Noise figure is definable only when input source is resistive ------
important parameter on communication system as the source impedance in this
system is often resistive - NF is minimized by maximizing Rp
- Maximum power transform possible
•Definition : when Rs =Rp

• So condition for minimum noise figure

Noise factor (NF) = Noise Figure (F)= 10log10 NF •In most cases condition for power optimum and noise
does not coincide with maximum power
-Noise figure measures the SNR degradation as optimum resistance do not coincide ( challenge !!!) transfer
a signal pass through a system
• if a system has no noise the NF=1, F = 0dB Examples :
• if input signal contains no noise then SNRin =α
and NF = α ( even though the system has finite
noise ) : is it really possible!!

Noise figure (cont..) Noise figure (cont..)

Noise figure of Lossy circuit ..
Noise figure of cascaded stages .. •Passive circuits attenuates signal, contribute noise

For two stage case it can be shown

For m- stages

=>Noise factor= Loss

Cascade passive Filter &LNA

• NF of each stages is calculated with respect to the output impedance of previous stages

• The noise is contributed by each stage decreases as the gain preceding the stages increase
•That’s why the first stage of any system should have higher gain with low noise figure ( PRIME
CRITERION FOR LOW NOISE AMPLIFIER (LNA) DESIGN OF A RECEIVER)

Examples
V 2 nR s = 4kTR s Δf
LINEARITY ISSUES
i 2
n1 = 4kTγg d0 Δf
4kT
i2 nR D = Δf
R D

Output noise current due to source resistance = g 2 m V 2 ns = g 2 m .4kTR s Δf

4kT
Total Output noise current = g .4kTR s Δf + 4kTγg d0 Δf + Δf
2
m
RD
γg 1
NF = 1 + 2 d0 + 2
g mR s g mR sR D

sL
Vgs = Vns
R s + sL
{(R / ωL)2 + 1}γg d 0 1 + (R / ωL) 2
NF = 1 + + 2
g 2m R s g mRsR D
 Linearity Issues Cont… Linearity Issues Cont…

Method for Estimating Linearity Parameter from Device Parameter

Linearity Issues Cont…
Already we get for a nonlinear system

MOSFET current :
1 dB compression point

IIP3 value
g(Vo), g(V+), g(V-) are the Transconductance value, Where
V0 is the dc-bias voltage, V+ is slightly higher and V- is
slightly lower

Stability Analysis Sensitivity

Basic criteria:For good stable has no positive feedback loop, in general
the all pole must in right half s-plane.
s
CS -stage V out (s ) − g m r 0 (1 − ) g
= z p=
1
z= m
V in ( s ) s ,, r0 Cgd Cgd
1+
p
Cgd gives pole in right half plane, if Cgd 0 , then get good stability

CG -stage
Cds gives positive feed back, so stability reduce

• The backward-transmission(S12) is required to be small for good stability

•As real circuit are complex, proper analysis of transfer function is required and
compensation technique is used to obtain good stability (such as OPAMP)
 Dynamic Range
High Frequency Device modeling

Silicon Technologies

Bipolar BiCMOS MOS

Junction PMOS NMOS

Dielectric
Isolated
Isolated
BJTs
CMOS

WHY CMOS FOR RF-IC High Frequency Device modeling (contd.)

¾ Standard Digital CMOS is hardly the ideal Visualization of Process Flow
medium for RF ICs, because of :
¾ Lossy Silicon substrate CMOS BJT
¾ Large source/drain parasitics ƒ Symmetric behavior. ƒ Higher gm for same
bias. Protective Overcoat
¾ High device noise and ƒ Better linearity
(Higher signal swing). ƒ High fT.
¾ poor 1/f noise performance
ƒ Higher fT at sub- ƒ Low thermal and 1/f
¾ Series gate resistance micron feature size. noise, but input CVD Oxide
Metal-2
ƒ Better scaling current noise.
¾ But, properties. ƒ Lower DC offset .
via
Metal-1
¾ Device scaling …faster ƒ Low power (no gate ƒ No body effect.
contact
¾ CMOS fT (and fmax) ….range of 60GHz DC current). ƒ Lower overdrive
poly Gate oxide
¾ doubles roughly every 3 years. (Low VCE sat). FOX
¾ CMOS is cost effective n+ n+
¾ Both digital & analog block can be p-epi
¾ designed on same substrate
¾ High linearity; Low distortion
p-substrate
¾ Low power consumption
¾ On-chip realization of passive inductors
¾ and capacitors

RF CMOS MODELLING
“Standard” (digital oriented) MOS models do not allow for RF
Maximum unit power gain
frequency

Maximum Cut-
Cut-off frequency

Rpoly R Csub
Cgs Cgd Cds
•To calculate magnetic coupling between two adjacent metal line, interlayer capacitance ,
EMI between subcircuits & on-chip passive component (such as inductor and MIM In RF, Cgs ( whose effect negligible in low frequency analog) affects the matching with
capacitor) , the Maxwell EM equation is required ( Challenging issue !!!) successive blocks . Frequency dependence of Transconductance(gm )
 RF CMOS MODELLING
Long channel effect
ON-
ON- CHIP PASSIVE COMPONENT
1 W On-Chip inductor realization
I
d
= μ n C ox ( Vgs − V t ) 2
2 L
3 μn
™At RF frequencies, matching network consists of number
f
T
= ( V gs − V t ) of inductors. Therefore on-chip realization of inductors is
2 2 π L2
Sort channel effect
d v
important for RF IC design.
μ ε ε =
V = n
d y
d
ε
1 +
,
ε c ™ Three kind of inductors :
1 dv dv
Id = Q I WVd (y) I d (1 + . ) = W Q I ( y )μ n
εc dy dy ¾ ACTIVE INDUCTOR → More noisy, highly non-linear, High Q with large L
I =
μ n C W o x
(V − V ) 2 value possible , frequency dependent, higher power consumption.
d
− V t
V L
g s t
2 (1 + g s
)
ε cL
μ n C ox
¾ BOND WIRE INDUCTOR → Depends on curvature, High Q(~60), Typical
=
W
( V gs − V t ) 2 Vscl = μ n ε c
2[1 + θ ( V g s − V t )] L value : 1nH/mm, series resistance : 0.2 Ω/mm(1mm φ).
2 ( V gs − V t )
1+
εcL
−1 ¾ ON-
ON- CHIP SPIRAL INDUCTOR → Less Q (3-6), In CMOS process
g = W C V scl
m ox
2 ( V gs − V t ) maximum 10nH value possible with reasonable Q values, very small DC power
1+ ,
c.f Lee P-68,70 Cgc = Cox Ccb = Csi ε cL consumption….At very low (<0.5nH) L value → interconnect parasitics dominate…
C sbo C dbo
At high (>10nH) L values → Large area, Higher losses.
C jsb = C =
V jd B
V db 1/ 2 • fT independent of overdrive voltage (Vgs − Vt )
(1 + sb )1 / 2 (1 + )
ψ0 ψ0
• fT inversely proportional to L

Active Inductor Design

‰ ICs.
Coplanar Spiral Inductors
Key Issues :

Z(s) = == ™ Most Popular structure →

Coplanar Spiral Inductor
Z(s) = s L +R
Concerned properties ™ Shapes Used →
Bandwidth, Quality Factor (Q) and Noise Factor. Rectangular, Circular,
‰ Advantages over Spiral Inductors : Polygon
ƒ Much Less Chip Area ™ Disadvantages :
ƒ High Q factor( about 5 times) ¾ Lossy → Metallic ohmic loss, Substrate
ƒ Less parasitic effect losses, Eddy current loss
ƒ Better modeling and characterization . ¾ Poor Quality factor (Typically 3-6)
‰ Disadvantage: Bandwidth is Low , Higher Noise. ¾ Takes large area
¾ Noisy → Thermal noise of various
resistors (Metal, Eddy current,
Substrate)

Coplanar Spiral Inductor Design Multi Layer Inductors

¾ 2 or more layers combined in series
¾ Design Parameters: ¾ More electromagnetic coupling between
™ Edge to Edge distance d (Typically 100-200 um) two layers → higher L-value
™ Metal strip width w (Typically 10-15 um) ¾ Asymmetrical structure
™ No of turns (Typically 3-5) ¾ Modeling difficult (3-D effects)
™ Strip Separation t (Typically 1-3 um)
¾Technology Constraints:
™No of Metal Layers (Typically 3-5) Bond Wire Inductors
¾ Large Dia → High surface area → Low
™Metal Layer Thickness (or Metal Sheet Resistance)
Resistivity → Large Q.
™Substrate Resistivity ¾ No Conductive Surface beneath → No
¾Design Guide-Lines: Substrate/Eddy current losses.
¾ Typical Inductance : 1nH/mm.
™Hallow structure gives better Q ¾ No standard technology for Fab.
™Top metal layer used (Small substrate Cap, Low Metal Resistivity) ¾ Difficult Modeling.
™Pattern Ground Shield (reduces Eddy Current Loss) ¾ Coupled Bond Wires give higher L
™Self Resonance Frequency ( ω02 α [n*w*(d-w-t(n-1)]-1)> 5 * value.
Operating Frequency
 Pad & Bond Wire

PART – II
Transceiver Design

™Typical Bond Pad capacitance is of the

order of 300 – 600 fF.
™Shielding reduces the effect of loss
( due to Rsub).

Basic Transceiver Architecture Performance Measures

IF or Down Transmitter Receiver
LNA
baseband Converter

T/R
• Power efficiency • Sensitivity
Frequency
Synthesizer
Switch • Modulation accuracy • Selectivity
• Carrier leakage • Noise
IF or Up PA • Power consumption • Dynamic Range
baseband Converter
• Linearity
Simplified Diagram
• Power consumption

Complete Block Diagram

Standards
Transmitter Architecture
GSM Bluetooth Zigbee
Transmission TDMA & FDD FHSS(Frequency DSSS(Direct Sequence
scheme Hopping Spread Spread Spectrum) ‰ Modulation and upconversion
Sprectrum) are done in the same circuit
Frequency Band Tx : 890 – 915 MHz 2.4 GHz 2.4 GHz, 915 MHz, 868
Rx : 935 – 960 MHz MHz ‰ Simplicity lends it to high
degree of integration
Modulation scheme GMSK(Gaussian GFSK(Gaussian QPSK(Quadrature Phase
Minimum Shift Keying) Frequency Shift Keying) Shift Keying) or BPSK
depends on the freq band Direct Conversion Transmitter

Sensitivity -102 dBm -70 dBm for 0.1% BER -85 dBm (2.4GHz) or -92
dBm (915/868 MHz) for
packet error rate < 0.1%
0.8 – 20 W Maximum 100 mW, Minimum capability
Important drawback: Output of
Transmitted power
2.5mW or 1 mW 0.5mW, Maximum as the PA tends to shift the LO
depending on class allowed by local output as its spectrum lies
regulations around LO frequency.
Data Rate 270 KBPS 1 MBPS 250 KBPS, 40 KBPS or
20 KBPS ( depending on LO Pulling by PA
frequency band)
 Transmitter Architecture (contd.) Wide-band Transmitter Architecture

‰ LO pulling is avoided by
having the PA output
spectrum sufficiently away
from that of LO

Direct Conversion Tx with offset LO

‰ Quadrature modulation of I and

Q signals are done at a lower
frequency and thereafter the Ultra Wide-band( UWB) Transmitter
upconversion occur at higher
frequency.
‰ PA spectrum is away from both
the LO frequencies
Two step Transmitter

Receiver Architecture on Application Basis Architecture classification based on principle of

Single Band downconversion

‰Heterodyne architecture has

been the dominant choice for
many years.
‰The received signal is first
Multi-Band
downconverted to an Intermediate
Frequency (IF).
‰ Received signal is bandpass
filtered and downconverted at
progressively lower frequencies to
UWB achieve high selectivity.
‰ Stringent requirements on the
filters force the use of large
Heterodyne Architecture passive components and make it
difficult to integrate on a chip.
¾ Another option for multi-band
implementation is to use LNA tuned at
two different frequencies

Problem of Image
‰Images can be several
times larger than the
wanted signal mandating
an Image Rejection Ratio
(IRR) of at least -70 dB.
Problem of Image
‰Very high Q requirement
is usually placed on the
Image Reject Filter
High IRR or Facilitates
High IF
Image Rejection
Facilitates Channel
Low IF
Selection
Optimum Value of IF needs to be chosen
Use of image reject filter
Homodyne Receiver
Simple Homodyne or Direct Conversion Receiver
Quadrature Downconversion in DCR
‰ Simplicity lends it to
efficient on-chip
implementation
‰ Problem of image is not
there.
‰ To be more precise
“images” in this case comes
from the same channel and
hence are of comparable
magnitude as of the desired
signal. Hence IRR of around
-40 dB is typically sufficient.
 Demerits of DCR Image Reject Architectures

Special Image Reject

‰LO Leakage from LO to RF
port and subsequent self
mixing produces DC Offset
‰Offset voltages near DC
corrupts the signal and more
importantly may saturate the
LO Leakage to input
following stages
‰LO Leakage also generates
spurious radiations
‰Flicker Noise becomes more
prominent at low frequencies.
‰Even-order distortion
Even order Distortion
architectures were developed
to relax the required
performance of the filters
Image Rejection using
Single Sideband Mixing
Weaver
Architecture
‰ Image Rejection depends
on the matching between the
mixers and the LO I and Q
signals.
‰ For typical mismatch IRR is
limited to -40 dB.

From system level to component level specifications

Low IF architecture
Initial Guess

‰ Combines the advantages

of the heterodyne and Modify
Block Level Specs
homodyne architectures.
‰ Image rejection is deferred
till the IF stage and is done by
a filter with asymmetric
frequency response. System Level Specs
Low IF Architecture
‰ Signal and the image are
downconverted at positive and
negative frequencies
respectively or vice versa. Required System Requirement no
Level Specs Satisfied?
‰ The image is filtered out by
the polyphase filter. yes

Final Block
Image Rejection using Polyphase Filter Level Specs

From System level to

Component level specifications (contd.) Noise Figure of the Front-end

‰ Given
•SNRout Required = 14 dB
•Sensitivity Required( Pin,min) = -90 dBm
•Bandwidth = 2 MHz
‰ The required Noise Figure of the receiver front-end is calculated
Block Diagram of the Receiver System from the sensitivity eqn.

‰ Sensitivity of the Receiver

-90 = -174+ 10 log10(2x103) + NF + 14
Î NF = 7 dB
 Example- Gain and NF calculation
Gain, NF and IIP3 of cascaded stages
‰ Total Gain

Ap = A p1 × A p2 × L × A pk
‰ Total Noise Factor
NF2 − 1 NF3 − 1 N Fk − 1
NF=NF1 + + + ..... +
A p1 A p1 A p2 A p1 A p2 ...A p(k-1)
‰ Total IIP3

1 1 A A A A A ...A p(k-1)
= + p1 + p1 p2 + ..... + p1 p2
IIP3 IIP3,1 IIP3,2 IIP3,3 IIP3,k
Where NFi, Api and IIP3,i are respectively Noise Factor ,
Available Power Gain and input 3rd order intercept point of the
i-th stage

WHY ON-CHIP ?
¾ 4 P-words :
Price : Mass volume production reduces price
Package : Integration reduces No of total pin count
ON-CHIP GHz Performance : Improves except few cases
Power : On-chip components dissipate lesser power
CMOS LOW NOISE AMPLIFIER ¾ Challenges :
Poor quality of passive components (inductor etc.)
Device modeling at RF frequencies
Realizing good analog circuits in digital technology
Meeting stringent performance requirements in digital
environment. Substrate noise coupling is more critical in
mixed signal

LOW NOISE AMPLIFIERS Different structure of CMOS LNA

Characteristics :
ƒ First gain stage in receiver
ƒ Received signal very weak (~μV)
ƒ Gains usually moderate (10-20 dB
typical)
ƒ Noise Figure (NF) should be as low as
possible (<3 dB typical)
ƒ Linearity is also an issue
ƒ Reverse Isolation should be high
Design consideration :
ƒ Noise Figure: 2~3dB
ƒ Gain: 15~20dB
ƒ IIP3: ~ -10dBm
ƒ Input/output Impedance: 50 Ohm
ƒ Input/output Return Loss: -15dB
ƒ Reverse Isolation: >30dB
ƒ Stability Factor >1
All structures are narrow-band
¾ Capacitive input impedance.
¾ Lg cancels Capacitive term.
¾ A parallel RS (50 Ω) is added to
match input source R50.
¾ To reduce the effect of Zout (img)
Common source LNA ac equivalent model on tuning circuit, C value should
Disadvantage of this circuit : be large compared to Zout
¾Due to Rextra , the power divide by 2.
Corresponding circuit
¾NF ~1+ (γ/α) * Rextra/R50 , γ & α (=gm/gdo)
are device parameter. NF~3-4 dB.
¾Due to Cgd reverse isolation(S11) Bad.
¾Cgd affects stability due to presence of zero in
transfer function (Vout/Vin)
 Most popular LNA topology Bias &Device size
™ Noise and power are two important parameter to
™ Remedy ………
characterize device size and bias.
“ Cascode source degeneration common source” ¾ The channel noise & gate induced
Equation for choosing Input matching network Component ™ Two-port noise model
noise id2 & ig2 are main noise source in
vn I2 MOS
Noise-free
iS YS in V2
¾ Choosing of device (W/L) & Vgs : determine gm & Two-Port
Cgs value , then Ls and Lg can be found.
¾ Effect of channel resistance & gate resistance :
modify above equation (Fingering is done in layout to
reduce this value ).
¾ The parasitic of inductor must be considered for
calculating practical component values.
¾ Gate of M2 is ac ground, so Equation for choosing output matching network component
output cap due to Zout is Cgd2 ¾ Good L, Q is 2 –3, then get Rd, For optimum noise figure:
figure:
only….
only…. C value lesser. ¾ From Rd find-
find-out equivalent Ld
¾ As impedance looking to source by ASITIC with maximum
of M2 is 1/gm2 as a result Miller possible Q. then calculate C
cap effect gets reduced. ¾ Where Gs, Gc, Bc, Rn → noise parameters
from ω0, check whether C is
much larger(~10 times of Cgd)

Noise figure( cont’d) Noise (cont’d)

™ Minimum noise figure (Neglecting the gate resistance and ™Simplified form γ, δ, α → device geometry and scaling
dependent constants
inductor losses & without any power constraints):

Power constraint Without Power constraint

¾ Gopt= 20m mho( Gs) Cgs can be calculated from above Eq. Noise minimum Noise minimum
¾ Choose smallest possible length[ to make ωT(~1/L2) high]. ¾The FminP differ from Fmin about 0.5dB to 0.7 dB more(∞ <1)
¾ Then find out W, from the relation Cgs= 2/3 Cox. W*L.(in saturation)
¾But the FminP are more reliable one from practical circuit design point of view.
¾ This calculation gives a very high W value , which makes large power
consumption, ………therefore noise minima condition is not
preferable for choosing device geometry.
….. Analysis based on power constraint noise figure calculation : ¾It is difficult to achieve maximum gain, minimum power consumption ,
minimum noise figure & good input match at a single value of Wopt & bias (
Vgs)……we are now working to develop efficient algorithm for setting global
optimum for different constraints.
More complex form( considering all losses)

Differential LNA
Other LNA Structures
¾ The single ended LNA (especially for source degeneration topology), the
¾This is a common gate topology. the impedance
ground parasitic inductor is a crucial since degeneration inductor value is
looking from source end is 1/(gm+gm-bulk). This should be
small → parasitic dominates in operation
made 50ohm for matching (active matching).
¾ The ground inductor can be tuned by putting extra cap across ground line
¾The Ls cancels the Cgs value. inductor, but any cap in source line produces a negative resistance in input.
¾The noise figure is poor. This causes stability problem.

¾ Good linearity. ¾ Remedy → Differential structure

Common gate LNA structure
Complementary LNA structure
¾This is an inverting amplifier topology.
¾ Large gain {~(gm1+gm2)}.
¾Bias current reusable.
¾Relatively small Bias current for identical gain.
¾The noise figure is poor.
 INTER-STAGE MATCHING LNA 1 V Low Noise Amplifier
9 Provides better gain
9 Relatively low noise Figure
9 Provides 50 Ohm input/output impedance 9 Native MOSes used to facilitate low voltage
9 Minimum power dissipation operation
9 The input N/W consisting of LG and CGS is
tuned to 900 MHz.
9 The LC load is also tuned to 900 MHz.
9 Gate induced noise is included in simulation by
an equivalent resistor.

Performance Values in the typical

Parameters corner
• Provides a negative resistance &
extra inductance at I/P Supply Voltage 1 Volt
Bandwidth 825 - 975 MHz
• Matching condition changed
Voltage Gain 16.53 dB
Power Consumption 4.06 mW
Schematic Noise Figure 2.327 dB

Voltage Controlled Oscillators

™ Used for channel selection.

™ Frequency depends on Input Control Voltage.
™ Frequency change is made by tuning passive elements (e.g.
ON-CHIP GHz varactors in LC oscillators) or by changing current/voltage
OSCILLATORS supply (e.g. in ring oscillator).
™ Governing Equation is:

Fout = Kvco * Vcontrol

Here; Kvco ≡ VCO Gain (Hz/volt).
Vcontrol ≡ Input Control Voltage (volts).

VCO Specifications TYPES of OSCILLATORS

‰ Center Frequency; ωo (GHz) ‰ Oscillators are autonomous circuits that produce periodic
‰ Tuning Range (MHz) output without any periodic input.
‰ Tuning Sensitivity; KVCO (Hz/volt) ‰ Three main topologies and their Comparison:
‰ Spectral Purity or Phase Noise (dBc/Hz @ Hz offset)
‰ Power Consumption (mW) TYPE Principle On-chip? GHz ? PN
‰ Output Power (mW)
Ring Cascaded inverters YES YES POOR
‰ Harmonic Suppression (dBc)
‰ Load Pulling : Frequency changes with Load changes Relaxation Cap is charged and YES YES POOR
‰ Supply Pulling : Frequency change with VDD (Hz/volt) discharged
LC-Tuned LC resonance YES YES GOOD
(difficult)
 QVCO Architecture VCO Core: LC negative
Resistance Oscillator
I Common Mode Feedback
LC VCO Capacitive Cross-
Worse Phase coupling of PMOS pair
+ - + - + - + - Noise as The Complementary Cross-coupled VGS
VGS
compared to 900 structure is chosen as it V PMOSVDS
- + - + - + - + LC oscillator MHz provides more energy to
DS

LC VCO Q the tank as compared to

the NMOS only structure -2/gm -2/gm
Ring Oscillator for same current bias
Varactor
Cross-coupled 1V
-2/gm
Higher Q at this QVCO 1V
relatively higher VGS ≠ VDS VGS = VDS
I
frequency Frequency ‰ Requires
LC VCO Divider more inductors
‰ Lower power Q
consumption ‰ Inductors
1.8 GHz 900 MHz become bulky
‰ Lower Phase Noise at lower
frequency
Low area Cross Injection Binary weighted switched Cross-coupled
overhead Coupled Locked Native MOS NMOS 0.18 μm technology
capacitors
D Latch Divider ‰ Increases the tuning range ‰ Vth~ 80 mV 1 V Supply Voltage
while keeping KVCO low. ‰ Helps to combat Voltage
‰ Tuning becomes more linear headroom problem Threshold Voltage
~ 0.5 V.

VCO Core : Salient Features Frequency Divider

• Voltage headroom solution R Q+

– NMOS pair is replaced by Native MOS Q-
– PMOS pair is capacitively cross-coupled D+ D- gm
• Common mode feedback is required to keep the output DC levels
fixed. Clk+ Clk-
– The supply sensitivity of frequency decreases as the dc bias across the
D Flip-flop
varactor does not change with supply. Frequency Divider
‰ Provides quadrature signals at 900 MHz for input signal (clk) of 1.8 GHz.
• Bank of switched capacitors is used for discrete tuning ‰Self oscillation frequency of the Divider is designed to be 900 MHz
– Increases tuning range (150 MHz) keeping KVCO (~50 MHz/V) low. ‰Condition for self-oscillation: g m × R > 1
– Improves linearity of the frequency change with control voltage. ‰ Tail current source for the Flip-flops were removed to accommodate 1 V supply
• Consumes only 2.5 mW of power. ‰ Consumes 1 mW power.

Simulation results: Plots Comparison with other results

Our
Parameters [1] [2] [3]
work
Technology 0.25 μm 0.18 μm 0.18 μm 0.18μm
Supply (Volt) 2.5 1.8 1.5 1
Phase noise Tuning Range 0.667- 0.825–
Output waveform of VCO and QVCO 1.71–1.99 1.05–1.39
(GHz) 1.156 0.975
KVCO(MHz/V) -- -- -- 50
-143@ 3 -137@ 3 -124@ -136@ 3
Phase Noise
MHz MHz 600KHz MHz
KVDD(MHz/V) -- -- -- 6
Power (mW) 20 5.4 30 3.5
FOM (dBc/Hz) -185.5 -180.96 -- -180.1
2
⎛ Δf ⎞
Variation of frequency and KVDD(Δf/ΔVDD) F O M = S SSB ⎜ ⎟ PV C O / m W
Tuning curves ⎝ f0 ⎠
with supply voltage
 System simulation results Measurement Results
(VCO)(contd.)

PMOS Gate Output

Bias Power (dBm)
(mV)
0.329 -21.9
0.362 -23
0.411 -24
0.452 -27
0.519 -36
0.526 -60
Noise Figure IF output for 1 mV RF input
Output Power variation with bias Output spectrum and phase
noise measurement

MIXER

™Ideal Mixer → Multiply signals.

™Mixer is a Frequency translator circuit.

Acos(w1t) * Bcos(w2 t) = (AB/2)* [ cos(w1+w2)t + cos(w1-w2)t ]

up-conversion down-conversion

MIXERS

Block diagram representation of Mixer Basic Mixer operation and its MOS equivalent

Special considerations for Mixer Design Classification

™ Provides efficient frequency translation.
™ Low noise figure (10-13 dB).
™ A moderate conversion gain (8-15 dB).
™ Low LO coupling to RF Port (10-20 dB).
™ High linearity (-6 – 15 dBm, IIP3).
™ Suppression of LO feed-through to the IF port.
™ Provides good image rejection ( some times require to add
image rejection filter).
™ IF matching.
™ Low distortion.
™ Power consumption (3-5 mW) and Area consideration.
™ On the basis of operating mechanism :
a) Switching type – switch the RF signal path ON & OFF at
LO frequency.
b) Non linear type – use the non linear characteristic of
device.
™ On the basis of gain of a mixer :
a) Passive mixer – switch type, conversion gain less than one,
less noise.
b) Active Mixer – nonlinear type, conversion gain greater
than one, more noise.
 Different topologies of CMOS Active Mixer Different topologies (continued)…
1. Square law MOSFET Mixer 2. Single balanced mixer
¾ RF signal drives the gate while LO drives the source. ™ Output is balanced to RF signal.
¾ For long channel devices : ™ Exhibits superior performance.
™ Ideally generates inter-modulation terms.
id = β/2*(Vgs –VT)2
™ The inputs are entered at separate ports – gives high degree of isolation
= β/2*{VBIAS+[vRFcos(wRFt)-vLOcos(wLOt)]-VT}2 among RF, LO & IF.
¾ The useful term is the product of cos(wRFt) and cos(wLOt ™ Converts the RF voltage into a current through trans-conductance.
). All other terms are removed by filtering. ™ Performs multiplication in current domain.
¾ The output contains a dc part, RF and LO feed-through, and ™ Approximate expression of output current :
number of harmonics.
iout(t) = sgn [cos(wLOt)] * [ IDC + IRFcos(wRF)t ]
¾ Conversion gain = β/2*(VLO).
sgn(x) = 4/π[ sin(x) + (1/3)sin3(x) + (1/5) sin5(x) + …..]
¾ For low IF down-conversion, LC tuned output
network is replaced by RC network. ™ Actual current equation can be established on the basis of
single stage differential amplifier with time varying large LO in
in
Drawbacks : differential part and small ac RF signal in tail current part.
¾ High chances of LO to IF feed-through, poor port ™ Conversion gain α (2/π
(2/π )2
isolation between RF, LO & IF. ™ ADV: Differential output gives higher gain and more immunity
¾ For short channel device : id α (VGS –VT). So it can for RF to IF feed-
feed-through
not be used . ™ DIS-
DIS-ADV: High LO to IF feed-
feed-through, Large power
consumption compared to previous topology, noise figure increases.
increases.

Different topologies (continued)… Two Important Mixer

3. Double balanced Mixer
Gilbert Type Mixer
¾ Output is balanced to both RF and LO.
¾ Has high degree of LO-IF isolation. ™ Conversion gain = gmRL2/π
¾ The LO drive should be large enough, so that the differential pair behaves as switch.
¾ Two signals in double balanced mixer are connected in anti-parallel for LO signal Design issues
but in parallel for RF signal – LO terms sum to zero at output and RF is doubled.
iout(t)= 2IRF * sgn * [cos(wLOt)] * [cos(wRF)t ] ™ The gain and IIP3 are determined
• Actual current equation can be established on basis of single stage differential by tail current( Iss). The increase of
amplifier, with time varying large LO in upper part of differential pair and small tail current improves the
ac RF signal in lower part of differential part . performance, however the voltage
Conversion gain α (4/π
drop across load resistance drives
(4/π )2.
the RF transistor out of saturation.
‰ ADV: Gives higher port isolation among RF, LO & As a result conversion gain and
IF. Gives higher conversion gain. IIP3 suffers.
‰ DIS ADV: large power consumption, large noise ™ Increasing load resistance increases
figure. gain, but cannot be increased
indefinitely as the RF transistors
come out of saturation.

Even Harmonic Mixer

Low IF Receiver Architecture
I
1 MHz

Current reuse
+ -
0 1.7-1.9 GHz
850 – 950 MHz LNA gain stage
- + - +
- +
180
850 – 950 MHz
90
+ -
+ - + - - +
270
850 – 950 MHz
LO (VCO+Div2+Buffer)
DOUBLED BALANCED EVEN-HARMONIC MIXER PCB matching components

™ The circuit is a "three level multiplier", composed of two PCB 50 ohm Transmission line 1 MHz
Q
stages, a double-balanced switching cell and a differential
transconductance stage. Gilbert Cell
 Layout of the complete RF Front-End
(KGPLPRX)
System QVCO

FREQEUNCY
LNA

SYNTHESIZERS

LNA &Mixer
System

„ Total Die size ~2mmX2mm

„ System Die size ~ 1mmX1mm

Building blocks of frequency Synthesizer
¾ PLL based frequency synthesizer is a negative feedback system that locks
both phase & frequency
¾ Basic building blocks of PLL based frequency synthesizer are
¾ Phase Frequency Detector (PFD) Æ Sequential tri-state dual DFF PFD
¾ Charge Pump Æ Constant UP/DOWN Current sources with Switches
on Drain
¾ Loop filter Æ Passive 3rd order low pass filter
¾ Voltage Control Oscillator (VCO) Æ Low KVCO, low KVDD, low phase
noise LC VCO with on-chip inductor
¾ Programmable Integer N Frequency Divider Æ Divide by 2/3 pre-
scalar structure with both Current Mode Logic (CML) structure for high
frequency division and digital logic structure for low frequency division
Frequency Synthesizer
¾ Motivation-
¾ All frequencies in the band of interest from the reference frequency
¾ High degree of purity due to the ever decreasing channel spacing
¾ Low power consumption
¾ Low cost
¾ High integration
¾ Explosive growth in demand for wireless communication services
¾ Direct Analog/Digital Synthesis-
¾ Fine frequency resolutions and fast switching times
¾ Not suitable for high frequency and low phase noise synthesis
¾ Indirect PLL based Synthesis-
¾ Fine frequency resolutions and fast switching times
¾ Suitable for high frequency stability and accuracy, low phase noise and high frequency
(even in giga-hertz frequency range) synthesis
¾ Amenable to full integration on a standard CMOS technology

Block Diagram of frequency Linear PLL Model

Synthesizer
¾ Phase → Independent variable.
VCO Cap Control
¾ For phase variable → VCO is perfect integrator.
REFERENCEFR
(5 bit) ¾ Different blocks modeled as:
EQUENCY OUTPUT
CHARGE LOOP FREQUENCY ™ PFD → Difference Block
PFD
PUMP FILTER ™ Charge Pump → Constant gain, (Kcp
(Kcp))
™ Loop Filter → generic Transfer
VCO function F(s)
™ VCO → Integrator with constant gain,
(Kvco/s)
FREQUENCY
DIVIDER ™ Frequency Divider → Divider ratio
(N)

Channel Control (8 bit)

 PLL Large Signal Behavior Phase Frequency Detector

¾ > FREF; Down Exact PLL ¾ Gives difference between Reference and output phases.
locking is nonlinear ¾ Usually implemented digitally.
phenomena. ¾ Most widely used topology → Sequential tri-state dual DFF
¾ If FVCO/N output of PFD PFD.
will turn enable more often
than Up.
¾ Loop filter control voltage
→ goes down → FVCO
goes down.
¾ Typically; ts = 25/FREF.
ts : settling time.

Operation of Sequential PFD

Locking Behavior of PLL

Loop Filter
Charge Pump
¾ Gives infinite DC gain with passive filters → Needed for zero ¾ Usually a Low pass filter.
phase error. ¾ Provides a stabilizing zero for the loop (C2, R2).
¾ Consists of two or more Current sources, switched ON/OFF ¾ Determines loop’s transient behavior.
by PFD outputs. ¾ Active or passive implementation possible.
¾ Mismatches & Leakage in charge pump → Spurious ¾ Passive filter → No active device noise, easy on-chip
component in PLL output. implementation.
¾ Three main topologies: ¾ Filter order → decides spurious
™ Switch at Drain suppression (typically 2-3).
™ Switch at Source
™ Switch at Gate
¾ Filter Design parameters:

™ Loop Bandwidth → Decided by

¾ Switch on Source → Fastest, Lowest settling time requirements
mismatches, Minimum overshoots, ™ Phase margin → Decided by
maximum permissible overshoot Third order passive Loop Filter
easily scaleable.

VCO Programmable Divider

¾ Only block (except VCO) that operates
¾ VCO parameters, most relevant to Frequency Synthesizers: at RF frequency.
1. KVCO requirements → Should be linear ¾ Implementation is critical → Power
2. Phase Noise → Should meet the specifications hungry, high speed.
3. Settling time → Should be much higher than PLL loop ¾ Most popular Architecture → based on
band width Pre-scalar.
4. VCO isolation → Buffers should be added at the output ¾ Only pre-scalar operates at highest
frequency.
5. Power consumption → Should conform the system
requirements. ¾ Output Frequency = P*N + A
¾ Pre-scalar → Current Mode Logic
(CML)
¾ Details of VCO design has been discussed in previous
chapter……… ¾ CML → Constant current, No power
line spikes, Low power at GHz
frequencies. A CML DFF-AND gate
 (Divider cont’d) Simulation & Silicon Tested
¾ Prescalar architecture → Not modular
→ Complex Layout Results
¾ Architecture based on 2/3 divider cells: Parameter Simulation Result Results Tested on
fabricated chip
™ Programmable 2/3 divider cells are
Frequency range of operation 2.4 GHz – 2.4835 GHz 2.3964 GHz - 2.4788 GHz
cascaded.
™ For N cells, Division range : 2N –
(2N+1 - 1). No of channels 16 16

™ Highly regular structure. Channel spacing 5MHz 5MHz

2/3 Divider cell schematic VCO gain 60 MHz / V --
VCO current 2.5 mA --
Charge pump current 50uA --
Division ratio 480 – 495 480 – 495

Open loop unity gain 100 kHz --

frequency (PLL -3dB BW)
Phase margin 50 degree --
Total power consumption 9 mW 9mW
2 cascaded 2-3 cells in divide by 7 mode

Layout of Frequency Synthesizer Silicon Testing : PLL locking check

And Test Setup of the chip (Fref=5MHz).

Divider output
when no input is
given; Unlocked
condition

Divider output
when 5MHz input
is given; locked
Die area: 1812.4um x 1965.04um Snapshot of the PCB condition

Channel selection by Divider

Channel selection by Divider control in
control in locked condition
locked condition
There are 8 control bit is used to select a channel among the 16 channel over the
frequency range 2.40-2.48GHz .The divider ratio is changed with change of control bits
.Only 4 LSB bits are used for 16 channel selection, extra 4 MSB bits are added to select out
of band frequency. The test results are shown in the following table
Divider ratio:
1110,0000 (480)
4MSB+ 4 LSB divider VCO freq Ideal output as 5MHz
control bits(8) measured GHz reference
1110,1000 (488) 2.4426 2.44

1110,0000 (480) 2.3964 2.4

1110,1111 (495) 2.4788 2.475

1110,1100 (492) 2.4664 2.46 Divider ratio:

1110,1111 (495)
1110,0100 (484) 2.4194 2.42
¾ For first phase of testing, we taken the reference frequency from a signal generator,
which gives frequency variation from 4.992M-5.008MHz instead of fixed 5MHz, that’s
why the comparison table are slightly mismatched
 VCO centre frequency tuning Supply Voltage Variation and Operating Current

Conditions VDD Supply Current

I(VDD)
• There are 5 control bit is used to compensate the VCO center Minimum supply voltage for 1.40V 3.4mA
frequency variation of due to process. These are shown in the which the chip is functional
following table Maximum Supply voltage 2.5V 8.2mA
Cap_cntl bits(5) VCO freq Divider o/p
measured GHz frequency MHz checked
00000 2.6044 5.336 Normal Operating Condition 1.8V 5mA

00110 2.4404 5 Comparison of performance

• The frequency synthesizer consumes very less power which is lowest
00111 2.4148 4.448 reported till now for Integer-N frequency synthesizer in 2.45GHz Zigbee
application
• This structure gives low KVCO and KVDD
11111 1.9704 4.032 • The reference signal are given through a signal generator rather than from a
crystal oscillator , thus we expect better phase noise performance of the
frequency synthesizer by using crystal.
• Setting time measurement of FRS is on process

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