Professional Documents
Culture Documents
Version 1.0
February 2011
GNU Free Documentation License
Shakthi Kannan
shakthimaan@gmail.com
http://www.shakthimaan.com
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Dum Ka Biryani
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Makefile
target : prerequisites ...
recipe
...
...
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Makefile
objects = masala.o rice.o onion.o curd.o coriander.o meat.o
biryani : $(objects)
cc -o biryani $(objects)
masala.o : masala.h defs.h
rice.o : rice.h defs.h
onion.o : defs.h
curd.o : defs.h
coriander.o : defs.h
meat.o : defs.h
clean:
rm biryani $(objects)
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* Implicit rule
masala.o : masala.h
* Variable definition
objects = masala.o rice.o onion.o curd.o coriander.o meat.o
* Directive
ifeq ($(CC), gcc)
libs=$(libs for gcc)
else
libs=$(normal libs)
endif
* Comments
# This is a comment
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Default
* GNUMakefile
* makefile
* Makefile
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Default
* GNUMakefile
* makefile
* Makefile
$ make
$ make -f myMakefile
$ make --file=myMakefile
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* Syntax
include filenames...
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* Syntax
include filenames...
$ make
$ make -I
$ make --include-dir
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GNUmakefile
meat:
cc -c vegetables.c
%: force
@$(MAKE) -f Makefile $@
force: ;
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GNUmakefile
meat:
cc -c vegetables.c
%: force
@$(MAKE) -f Makefile $@
force: ;
$ make
$ make meat
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First phase
* Reads all makefiles
* Reads included makefiles
* Internalize variables, values, implicit and explicit rules
* Constructs dependency graph of targets and pre-requisites
* immediate: expansion in phase one
Second phase
* Determines which targets need to be re-built
* Invokes the necessary rules
* deferred: expansion in phase two
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Makefile
clean :
rm -f *.o
Wildcard expansion does not happen in variable definition
Makefile
objects = *.o
Use Wildcard function!
Makefile
objects = $(wildcard *.o)
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Automatic variables
$
all prerequisites
$@ target
$< first prerequisite
Makefile
coriander.o : coriander.c
cc -c $(CFLAGS) $^ -o $@
Makefile
masala.o : masala.c masala.h defs.h
cc -c $(CFLAGS) $< -o $@
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Makefile
LIST = masala rice onion
all:
for i in $(LIST); do \
echo $$i; \
done
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Makefile
LIST = masala rice onion
all:
for i in $(LIST); do \
echo $$i; \
done
$ make
masala
rice
onion
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$ make
$ make
Adding
Adding
Adding
Adding
Adding
mix
green chillies
ginger garlic paste
cinnamon, cardamom
fried onions
coriander and mint leaves
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Makefile
masala := chillies.o onions.o garlic.o ginger.o
biryani := $(masala:.o=.c)
Makefile
masala := chillies.o onions.o garlic.o ginger.o
biryani := $(masala:%.o=%.c)
* biryani is set to chillies.c onions.c garlic.c ginger.c
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Makefile
greeny = coriander
coriander = green coriander leaves
leaves := $($(greeny))
all:
@echo $(leaves)
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Makefile
greeny = coriander
coriander = green coriander leaves
leaves := $($(greeny))
all:
@echo $(leaves)
$ make
green coriander leaves
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Makefile
objects = masala.o rice.o onion.o curd.o
...
objects += coriander.o
Makefile
CFLAGS = $(includes) -O
...
CFLAGS += -pg
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Makefile
water := saffron water
leaves = mint leaves
undefine water
undefine leaves
Makefile
override undefine CFLAGS
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Makefile
target ... : variable-assignment
Makefile
prog : CFLAGS = -g
prog : masala.o rice.o onion.o
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()
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Makefile
libs for gcc = -lgnu
normal libs =
biryani : $(objects)
ifeq ($(CC), gcc)
libs=$(libs for gcc)
else
libs=$(normal libs)
endif
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Makefile
conditional-directive
text-if-true
else
text-if-false endif
Makefile
conditional-directive
text-if-one-is-true
endif
else conditional-directive
text-if-true
else
text-if-false endif
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* ifneq
ifneq ($(STRIP), strip)
* ifdef
ifdef $(LIBS)
* ifndef
ifndef $(CFLAGS)
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()
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Makefile
$(if condition,then-part[,else-part] )
$(or condition1[,condition2[,condition3...]] )
$(and condition1[,condition2[,condition3...]] )
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Makefile
$(foreach var,list,text )
Makefile
find files = $(wildcard $(dir)/*)
dirs := masala rice leaves
files := $(foreach dir, $(dirs), $(find files))
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Makefile
$(call variable,param,param,... )
Makefile
reverse = $(2) $(1)
make = $(call reverse,cook,mix)
make contains mix cook
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Makefile
LIST = $PATH
all:
@echo $(LIST)
@echo $(value LIST)
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Makefile
LIST = $PATH
all:
@echo $(LIST)
@echo $(value LIST)
$ make
ATH
/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin
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Makefile
$(origin variable )
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Makefile
$(flavor variable )
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Makefile
contents := $(shell cat onion.c)
Makefile
files := $(shell echo *.c)
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References
GNU Make:
http://www.gnu.org/software/make/
GNU Make Manual:
http://www.gnu.org/software/make/manual/
Dum Ka Biryani, Make for each other (sources):
http://www.shakthimaan.com/downloads.html#dum-ka-biryani-make-for-each-other
Symbols in LaTeX and HTML:
http://newton.ex.ac.uk/research/qsystems/people/sque/symbols/
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