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HFOUT
CH0+ + 16-bit FOUT0
PGA Multi-level HPF1 F2 F1 F0 FOUT1 NEG
CH0- –
ΔΣ ADC
REFIN/
OUT
2.4V
X LPF1 E-to-F
conversion
Reference
CH1+ + 16-bit
Multi-level HPF1 POR
CH1- – ΔΣ ADC MCLR
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ. Max Units Comment
Overall Measurement Accuracy
Energy Measurement Error E — 0.1 — % FOUT Channel 0 swings 1:500 range,
MCP3905 only (Note 1, Note 4)
— 0.1 — % FOUT Channel 0 swings 1:1000 range,
MCP3906 only (Note 1, Note 4)
No-Load Threshold/ NLT — 0.0015 — % FOUT Disabled when F2, F1, F0 = 0, 1, 1
Minimum Load Max (Note 5, Note 6)
Phase Delay Between — — 1/MCLK s HPF = 0 and 1, < 1 MCLK
Channels (Note 4, Note 6, Note 7)
AC Power Supply AC PSRR — 0.01 — % FOUT F2, F1, F0 = 0, 1, 1 (Note 3)
Rejection Ratio
(Output Frequency Variation)
DC Power Supply DC PSRR — 0.01 — % FOUT HPF = 1, Gain = 1 (Note 3)
Rejection Ratio
(Output Frequency Variation)
System Gain Error — 3 10 % FOUT Note 2, Note 5
ADC/PGA Specifications
Offset Error VOS — 2 5 mV Referred to Input
Gain Error Match — 0.5 — % FOUT Note 8
Internal Voltage Reference
Voltage — 2.4 — V
Tolerance — ±2 — %
Tempco — 15 — ppm/°C
Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz.
See Section 2.0 “Typical Performance Curves” for higher frequencies and increased dynamic range.
2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @
50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV.
4: Error applies down to 60° lead (PF = 0.5 capacitive) and 60° lag (PF = 0.5 inductive).
5: Refer to Section 4.0 “Device Overview” for complete description.
6: Specified by characterization, not production tested.
7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.
8: Gain error match is measured from CH0 G = 1 to any other gain setting.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 4.5V – 5.5V, AGND, DGND = 0V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +85 °C
Operating Temperature Range TA -40 — +125 °C Note
Storage Temperature Range TA -65 — +150 °C
Note: The MCP3905/06 operate over this extended temperature range, but with reduced performance. In any
case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,
AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ Max Units Comment
Frequency Output
FOUT0 and FOUT1 Pulse Width tFW — 275 — ms 984376 MCLK periods
(Logic-Low) (Note 1)
HFOUT Pulse Width tHW — 90 — ms 322160 MCLK periods
(Note 2)
FOUT0 and FOUT1 Pulse Period tFP Refer to Equation 4-1 s
HFOUT Pulse Period tHP Refer to Equation 4-2 s
FOUT0 to FOUT1 Falling-Edge Time tFS2 — 0.5 tFP —
FOUT0 to FOUT1 Min Separation tFS — 4/MCLK —
FOUT0 and FOUT1 Output High Voltage VOH 4.5 — — V IOH = 10 mA, DVDD = 5.0V
FOUT0 and FOUT1 Output Low Voltage VOL — — 0.5 V IOL = 10 mA, DVDD = 5.0V
HFOUT Output High Voltage VOH 4.0 — — V IOH = 5 mA, DVDD = 5.0V
HFOUT Output Low Voltage VOL — — 0.5 V IOL = 5 mA, DVDD = 5.0V
High-Level Input Voltage VIH 2.4 — — V DVDD = 5.0V
(All Digital Input Pins)
Low-Level Input Voltage VIL — — 0.85 V DVDD = 5.0V
(All Digital Input Pins)
Input Leakage Current — — ±3 µA VIN = 0, VIN = DVDD
Pin Capacitance — — 10 pF Note 3
Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.
2: If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP.
3: Specified by characterization, not production tested.
tFP
tFW
FOUT0
tFS
tFS2
FOUT1
tHW
HFOUT
tHP
NEG
FIGURE 1-1: Output Timings for Pulse Outputs and Negative Power Pin.
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
0.5 0.6
0.4 0.5
+85°C
Measurement Error
Measurement Error
0.3 0.4
0.2 0.3 +85°C
0.1 +25°C
0.2
0
0.1 +25°C
-0.1
-0.2 0
-40°C
-0.3 -0.1 -40°C
-0.4 -0.2
-0.5 -0.3
0.0000 0.0001 0.0010 0.0100 0.1000 0.0000 0.0001 0.0010 0.0100 0.1000
CH1 Vp-p Amplitude (V) CH1 Vp-p Amplitude (V)
0.5 0.7
+85°C 0.6
0.4
Measurement Error
0.5
Measurement Error
0.8 1
0.8
0.6 +85°C 0.6
Measurement Error
Measurement Error
0.5 0.5
0.4 0.4
Measurement Error
Measurement Error
0.5 0.5
0.4 0.4
+85°C
Measurement Error
0.3 0.3
Measurement Error
+85°C
0.2 0.2
0.1 +25°C 0.1 +25°C
0 0
-0.1 -0.1
-0.2 -0.2
- 40°C -40°C
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0.0001 0.0010 0.0100 0.1000 1.0000 0.0001 0.0010 0.0100 0.1000 1.0000
CH0 Vp-p Amplitude (V) CH1 Vp-p Amplitude (V)
0.5 4000
16384 Samples
0.4 3500 Mean = - 1.28 mV
0.3 PF = 0.5 3000 Std. dev = - 18.1 µV
Occurance
0.2 2500
% Error
0.1 2000
0 1500
-0.1 1000
-0.2 PF = 1.0 500
-0.3 0
-1.38E-03
-1.37E-03
-1.36E-03
-1.35E-03
-1.34E-03
-1.33E-03
-1.32E-03
-1.31E-03
-1.30E-03
-1.29E-03
-1.28E-03
-1.27E-03
-1.26E-03
-1.25E-03
-1.24E-03
-1.23E-03
-1.22E-03
-0.4
-0.5
45 50 55 60 65 70 75
Frequency (Hz) Bin (mV)
FIGURE 2-11: Measurement Error vs. FIGURE 2-14: Channel 0 Offset Error
Input Frequency. (DC Mode, HPF Off), G = 16.
3000 0.3
16384 Samples 0.2
2500 Mean = -1.57 mV
Measurement Error
Std. Dev = 52.5 µV 0.1 VDD=5.0V
Occurance
2000
0
1500
-0.1 VDD=4.5V
VDD=4.75V
1000 -0.2 VDD=5.25V
500 -0.3
VDD=5.5V
-0.4
0
-0.5
-1.75
-1.70
-1.65
-1.61
-1.56
-1.52
-1.47
-1.43
-1.38
FIGURE 2-12: Channel 0 Offset Error FIGURE 2-15: Measurement Error vs. VDD
(DC Mode, HPF off), G = 1. (G = 16).
1200 0.3
16384 Samples
1000 0.25
Mean = -1.64 mV
Measurement Error
600 0.1
0.05 VDD=5.0V
400
0
200 -0.05 VDD=5.25V
-0.1 VDD=5.5V
0
-0.15
-1.71
-1.69
-1.68
-1.67
-1.66
-1.65
-1.64
-1.63
-1.62
-1.60
-1.59
FIGURE 2-13: Channel 0 Offset Error FIGURE 2-16: Measurement Error vs. VDD,
(DC Mode, HPF off), G = 8. G = 16, External VREF .
0.3 0.3
Measurement Error
+25°C
0.1 0.1
+85°C
0 +25°C 0 - 40°C
-0.2 -0.2
-0.3 -0.3
0.0001 0.0010 0.0100 0.1000 1.0000 0.0000 0.0001 0.0010 0.0100 0.1000
CH0 Vp-p Amplitude (V) CH1 Vp-p Amplitude (V)
0.3
0.2 +85°C
Measurement Error
0.1 +25°C
0
-40°C
-0.1
-0.2
-0.3
0.0000 0.0001 0.0010 0.0100 0.1000
CH1 Vp-p Amplitude (V)
CH0+
MCP3905/06
+
CH0- –
PGA ΔΣ ADC HPF
FOUT0
X ..0101... FOUT1
ANALOG DIGITAL
HFOUT
LPF DTF
CH1+ +
CH1- –
ΔΣ ADC HPF
Frequency
Content
0 0 0 0 0
-40
TABLE 4-1: MCP3905 GAIN SELECTIONS
Maximum -60
G1 G0 CH0 Gain
CH0 Voltage -80
0 0 1 ±470 mV -100
0 1 2 ±235 mV
-120
1 0 8 ±60 mV 0 5 10 15 20 25 30
1 1 16 ±30 mV Frequency (kHz)
0V Time
NO PROPER
DEVICE RESET PULSE RESET
OUT OPERATION
MODE
TABLE 4-4: OUTPUT FREQUENCY CONSTANT HFC FOR HFOUT (VREF = 2.4V)
HFC (Hz) HFOUT Frequency (Hz) with
F2 F1 F0 HFC HFC (Hz)
(MCLK = 3.58 MHz) full-scale AC Inputs
0 0 0 64 x FC MCLK/215 109.25 27.21
0 0 1 32 x FC MCLK/215 109.25 27.21
0 1 0 16 x FC MCLK/215 109.25 27.21
0 1 1 2048 x FC MCLK/27 27968.75 6070.12
1 0 0 128 x FC MCLK/216 219.51 47.42
1 0 1 64 x FC MCLK/216 219.51 47.42
1 1 0 32 x FC MCLK/216 219.51 47.42
16
1 1 1 16 x FC MCLK/2 219.51 47.42
XXXXXXXXXXX MCP3905
XXXXXXXXXXX e3
I/SS^^
YYWWNNN 0739256
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
E1
1 2
b
NOTE 1
e
c
φ
A A2
A1 L1 L
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 24
Pitch e 0.65 BSC
Overall Height A – – 2.00
Molded Package Thickness A2 1.65 1.75 1.85
Standoff A1 0.05 – –
Overall Width E 7.40 7.80 8.20
Molded Package Width E1 5.00 5.30 5.60
Overall Length D 7.90 8.20 8.50
Foot Length L 0.55 0.75 0.95
Footprint L1 1.25 REF
Lead Thickness c 0.09 – 0.25
Foot Angle φ 0° 4° 8°
Lead Width b 0.22 – 0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-132B
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
12/08/06