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6 bits
5 bits
5 bits
5 bits
5 bits
op
rs
rt
rd
6 bits
5 bits
5 bits
16 bits
op
rs
rt
offset
6 bits
shamt funct
6 bits
26 bits
op
address
R-Format
I-Format
J-Format
Data
PC
Address
Instruction
memory
Instruction
Register #
Registers
Register #
ALU
Address
Data
memory
Register #
Data
Single Cycle
Multi-Cycle
Pipelined
Functional Elements
Combinational Elements
State
element
1
Clock cycle
Combinational logic
State
element
2
State
element
Combinational logic
State Elements
5 bits
5 bits
5 bits
W rite
re giste r
32 bits
R ead
data 1
32 bits
R ead
data 2
32 bits
Register file
W rite
da ta
W rite
Control signal
Port implementation:
Clock
Clock
Write
Read register
number 1
0
Register 0
Register 1
Register n 1
Register n
M
u
x
Read data 1
Register number
C
Register 0
n-to-1
decoder
n 1
Register 1
D
Read register
number 2
M
u
x
C
Register n 1
D
Read data 2
C
Register n
Register data
Verilog
Instruction
address
Add
PC
Instruction
Add Sum
Instruction
memory
PC
a. Instruction memory
b. Program counter
Read
address
c. Adder
Instruction
Instruction
memory
Datapath
ADD
4
PC
ADDR
Memory
RD
Instruction
5
Register
numbers
5
5
Data
Read
register 1
Read
data 1
Read
register 2
Registers
Write
register
Read
data 2
Write
data
Data
ALU control
Zero
ALU ALU
result
Instruction
Read
register 2
Registers
Write
register
Write
data
RegWrite
Read
register 1
Read
data 1
Zero
ALU ALU
result
Read
data 2
RegWrite
a. Registers
b. ALU
ALU operation
Datapath
Instruction
op
rs
rt
5
rd
shamt funct
Operation
RN1
RN2
WN
RD1
rs
Register File
ALU
WD
RD2
RegWrite
rt
Zero
MemWrite
Instruction
Address
Write
data
Read
data
Data
memory
Read
register 1
16
Sign
extend
32
MemWrite
Read
data 1
Read
register 2
Registers
Write
register
Read
data 2
Write
data
Zero
ALU ALU
result
16
Sign
extend
32
Read
data
Data
memory
MemRead
b. Sign-extension unit
Address
Write
data
RegWrite
MemRead
a. Data memory unit
ALU operation
Datapath
rs
WD of mem
takes in reg
from which data
is taken
Instruction
Add Sum
Branch target
Shift
left 2
3
Read
register 1
ALU operation
Read
data 1
Read
register 2
Registers
Write
register
Read
data
2
Write
data
RegWrite
16
Sign
extend
32
Datapath
ALU Zero
To branch
control logic
rs
rt
offset/immediate
16
PC +4 from
instruction
datapath
ADD
Operation
<<2
RN1
RN2
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
E
X
T
N
D
32
Data is either
from ALU (R-type)
or memory (load)
Instruction
32
16
rs
rd
rt
RN1
Operation
RN2
WN
RD1
rs
Register File
WD
ALU
Zero
rs+rt
DM remains unused.
rt
rd
RD2
RegWrite
16
E
X
T
N
D
32
M
U
X
rt
ALUSrc
MemWrite
MemtoReg
ADDR
Data
Memory
WD
MemRead
RD
M
U
X
Instruction
32
16
RN1
RN2
Operation
rt
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
E
X
T
N
D
32
M
U
X
ALUSrc
MemWrite
MemtoReg
ADDR
Data
Memory
RD
WD
MemRead
Since for writing, in R-Type rd is used and in LW/SW rt is used, a MUX is reqd there.
M
U
X
Instruction
32
16
Operation
RN1
RN2
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
E
X
T
N
D
32
M
U
X
ALUSrc
MemWrite
MemtoReg
ADDR
Data
Memory
WD
MemRead
RD
M
U
X
PC
Read
address
Instruction
Instruction
memory
Registers
Read
register 1
Read
Read
data
1
register 2
Read
Write
data 2
register
3
ALUSrc
M
u
x
RegWrite
MemWrite
MemtoReg
Write
data
16
ALU operation
Sign 32
extend
Zero
ALU ALU
result
Address
Read
data
Data
memory
Write
data
MemRead
M
u
x
PCSrc
M
u
x
Add
Add ALU
result
4
Shift
left 2
PC
Registers
Read
register 1
Read
Read
data 1
register 2
Read
address
Instruction
Instruction
memory
Write
register
Write
data
RegWrite
16
ALUSrc
Read
data 2
M
u
x
ALU operation
Zero
ALU ALU
result
MemtoReg
Address
Write
data
Sign
extend
MemWrite
Data
memory
32
MemRead
Read
data
M
u
x
ADD
M
U
X
ADD
ADD
PC
<<2
Instruction
ADDR
Instruction
Memory
RD
32
RN1
RN2
16
PCSrc
Operation
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
E
X
T
N
D
32
M
U
X
ALUSrc
MemWrite
ADDR
Data
Memory
WD
MemRead
MemtoReg
RD
M
U
X
Datapath Executing lw
ADD
M
U
X
ADD
ADD
PC
<<2
Instruction
ADDR
Instruction
Memory
RD
32
RN1
RN2
16
PCSrc
Operation
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
lw rt,offset(rs)
E
X
T
N
D
32
M
U
X
ALUSrc
MemWrite
ADDR
Data
Memory
WD
MemRead
MemtoReg
RD
M
U
X
Datapath Executing sw
ADD
M
U
X
ADD
ADD
PC
<<2
Instruction
ADDR
Instruction
Memory
RD
32
RN1
RN2
16
PCSrc
Operation
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
sw rt,offset(rs)
E
X
T
N
D
32
M
U
X
ALUSrc
MemWrite
ADDR
Data
Memory
WD
MemRead
MemtoReg
RD
M
U
X
ADD
M
U
X
ADD
ADD
PC
<<2
Instruction
ADDR
Instruction
Memory
RD
32
RN1
RN2
16
PCSrc
Operation
WN
RD1
Register File
ALU
Zero
WD
RD2
RegWrite
16
beq r1,r2,offset
E
X
T
N
D
32
M
U
X
ALUSrc
MemWrite
ADDR
Data
Memory
WD
MemRead
MemtoReg
RD
M
U
X