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// ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
//
// Watch Variables:
//
//
Voltage1[10]
Last 10 ADCRESULT0 values
//
Voltage2[10]
Last 10 ADCRESULT1 values
//
ConversionCount Current result number 0-9
//
LoopCount
Idle loop counter
//
//
//###########################################################################
//
// Original Author: D.F.
//
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################
#include "DSP28x_Project.h"
#define EPWM2_MAX_CMPB
#define EPWM2_MIN_CMPB
#define
#define
#define
#define
#define
1950
50
EALLOW;
#if (CPU_FRQ_150MHZ)
// Default - 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)
25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)
25.0 MHz
#endif
EDIS;
//
//
//
//
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
//
//
//
//
//
//
Initialize the PIE vector table with pointers to the shell Interrupt
Service Routines (ISR).
This will populate the entire table, even if the interrupt
is not used in this example. This is useful for debug purposes.
The shell ISR routines are found in DSP2833x_DefaultIsr.c.
This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
LoopCount = 0;
ConversionCount = 0;
// Configure ADC
AdcRegs.ADCMAXCONV.all = 0x0001;
//
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; //
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x2; //
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;//
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; //
// Assumes ePWM1 clock is already enabled
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL = 4;
t
EPwm1Regs.ETPS.bit.SOCAPRD = 1;
EPwm1Regs.CMPA.half.CMPA = 0x0080;
EPwm1Regs.TBPRD = 0xFFFF;
EPwm1Regs.TBCTL.bit.CTRMODE = 0;
in InitSysCtrl();
// Enable SOC on A group
// Select SOC from from CPMA on upcoun
// Generate pulse on 1st event
// Set compare A value
// Set period for ePWM1
// count up and start
}
}
interrupt void epwm1_isr(void)
{
// Update the CMPA and CMPB values
update_compare(&epwm1_info);
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
interrupt void epwm2_isr(void)
{
// Update the CMPA and CMPB values
update_compare(&epwm2_info);
// Clear INT flag for this timer
EPwm2Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
interrupt void epwm3_isr(void)
{
// Update the CMPA and CMPB values
update_compare(&epwm3_info);
// Clear INT flag for this timer
EPwm3Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBPHS.half.TBPHS = 0x0000;
EPwm1Regs.TBCTR = 0x0000;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;
// Setup shadow register load on
EPwm1Regs.CMPCTL.bit.SHDWAMODE =
EPwm1Regs.CMPCTL.bit.SHDWBMODE =
EPwm1Regs.CMPCTL.bit.LOADAMODE =
EPwm1Regs.CMPCTL.bit.LOADBMODE =
//
//
//
//
//
//
Count up
Set timer period
Disable phase loading
Phase is 0
Clear counter
Clock ratio to SYSCLKOUT
ZERO
CC_SHADOW;
CC_SHADOW;
CC_CTR_ZERO;
CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
ount
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;
ount
Values
// Select INT on Zero event
// Enable INT
// Generate INT on 3rd event
epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA;
epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB;
epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB;
}
void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD;
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm2Regs.TBPHS.half.TBPHS = 0x0000;
EPwm2Regs.TBCTR = 0x0000;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;
// Setup shadow register load on
EPwm2Regs.CMPCTL.bit.SHDWAMODE =
EPwm2Regs.CMPCTL.bit.SHDWBMODE =
EPwm2Regs.CMPCTL.bit.LOADAMODE =
EPwm2Regs.CMPCTL.bit.LOADBMODE =
//
//
//
//
//
//
Count up
Set timer period
Disable phase loading
Phase is 0
Clear counter
Clock ratio to SYSCLKOUT
ZERO
CC_SHADOW;
CC_SHADOW;
CC_CTR_ZERO;
CC_CTR_ZERO;
// Set actions
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
count
EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;
count
= &EPwm2Regs;
EPWM2_MAX_CMPA;
EPWM2_MIN_CMPA;
EPWM2_MAX_CMPB;
EPWM2_MIN_CMPB;
void InitEPwm3Example(void)
{
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD;
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm3Regs.TBPHS.half.TBPHS = 0x0000;
EPwm3Regs.TBCTR = 0x0000;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on
EPwm3Regs.CMPCTL.bit.SHDWAMODE =
EPwm3Regs.CMPCTL.bit.SHDWBMODE =
EPwm3Regs.CMPCTL.bit.LOADAMODE =
EPwm3Regs.CMPCTL.bit.LOADBMODE =
//
//
//
//
//
//
Count up
Set timer period
Disable phase loading
Phase is 0
Clear counter
Clock ratio to SYSCLKOUT
ZERO
CC_SHADOW;
CC_SHADOW;
CC_CTR_ZERO;
CC_CTR_ZERO;
EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE;
Values
// Select INT on Zero event
// Enable INT
// Generate INT on 3rd event
{
ConversionCount = 0;
}
else ConversionCount++;
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Reset SEQ1
// Clear INT SEQ1 bit
// Acknowledge interrupt to PIE
return;
}
void update_compare(EPWM_INFO *epwm_info)
{
// Every 10'th interrupt, change the CMPA/CMPB values
if(epwm_info->EPwmTimerIntCount == 10)
{
epwm_info->EPwmTimerIntCount = 0;
// If we were increasing CMPA, check to see if
// we reached the max value. If not, increase CMPA
// else, change directions and decrease CMPA
if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP)
{
/* if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMa
xCMPA)
{
epwm_info->EPwmRegHandle->CMPA.half.CMPA++;
}
else
{
epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN;
epwm_info->EPwmRegHandle->CMPA.half.CMPA--;
}
*/
epwm_info->EPwmRegHandle->CMPA.half.CMPA= AdcRegs.ADCRESULT1
>>4;
}
}
else
{
epwm_info->EPwmTimerIntCount++;
}
return;
}