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UCLA|EEM16/CSM51A|Winter2015

Prof.ManiSrivastava

Practice Problem Set #3


Problem #1

Please show your work. Just writing theanswer without show intermediate steps onthe way
tocomingupwiththeanswerwillgetzerocredit.

a.Convertthedecimalnumber59491intoahexadecimalnumber.

b.Represent59491asaBCDnumberusingtheminimumnumberofbits.

c.Represent59491asa2scomplementnumberusingtheminimumnumberofbits.

d.Represent59491asa2scomplementnumberusingtheminimumnumberofbits.

e.Represent59491asa1scomplementnumberusingtheminimumnumberofbits.

Problem #2:

Arithmetic operations on a digital computers are done using arithmetic modules that are
designed to represent inputs and outputs using the same number of bits. While this has the
nice property thatresult of one operation can be usedasinputforthenextone,itcreatesthe
problem of overflow and underflow, i.e. the output may be too large or too small to be
representable by the number of bits available. One way to combat thisis to makearithmetic
modules that do
saturation arithmetic instead of
modular arithmetic (wrap around)which the
arithmetic modules we discussed in the class do. In saturation arithmetic, theoutput values
are clamped to a maximum value in thecase of an overflow, and to a minimum value in the
case
of
underflow.
The
Wikipedia
article
on
this
topic
at
http://en.wikipedia.org/wiki/Saturation_arithmetic has an excellent description. While
properties like associativity and distributivity are no longer holdtrueinsaturationarithmetic,it
offers the tremendousadvantage that the results arenumericallyclosertoreality,e.g.adding
two large positive numbers may yield a negative number due to overflow in modular
arithmetic, but in thecase of saturated arithmetic would yieldthelargestpositivenumberthat
canberepresented.

Your task is to design an arithmetic module which takes as input two 8bit 2s complement
numbers DIN0 and DIN1, and a 1bit control signal CNTL, and outputs an 8bit t 2s
complement result DOUT suchthatwhenCNTLis0thenDOUTisthesaturatedsumof DIN0
and DIN1 (i.e. DIN0+DIN1 saturated), and when CNTL is 1 then DOUT is the saturated
subtraction of DIN1 from DIN0 (i.e. DIN0DIN1 saturated). You may use halfadders,
fulladders,NANDgates,andinverters.
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UCLA|EEM16/CSM51A|Winter2015

Prof.ManiSrivastava

Problem #3:
a. Draw the FSM for a multimodel counter with 3bit states 000, 001, 010, 111 and an
inputMsuchthat
If M=0, then the counter cycles through the states in binary order 000, 001, 010,
011,100,101,110,111,000
If M=1, then the counter cycles through the states in gray coded order 000, 001,
011,010,110,111,101,100,000
b. Implement the counter using D flipflops, NAND gates, and inverters only. Write
expressions for the next state logic and output logic, and show supporting steps (e.g.
Karnaugh maps if youusethem).Bothcorrectnessand efficiencyofimplementationwouldbe
considered during grading. Give the cost of your implementation, assuming that an ninput
NANDgatehasacostofn,anda1bitDflipflophasacostof10.
Note: For part (b), you might want to try out your solution in Logisim to make sure it works
correctly. If so, you are welcome to include printouts of Logisim schematics and Karnaugh
maps. However, please do things manually as otherwise you wouldhave a hard time in the
finals.

Problem #4:
a. You have to design a synchronous digital sequential system which has one input X and
output Z such that Z is asserted to be 1 whenever the input sequence 010 is observed, as
long as the input sequence 100 has never been seen. Draw a finite state machine (i.e. the
state diagram) for the system. Note thatfor30%reducedcredityoucouldinsteaddesignthe
systemasmorethanoneconcurrentfinitestatemachine.
b. Modifythe finitestatemachinesothatZisassertedtobe1whenevereitherofthefollowing
two input sequences are observed 01101+0 or011101+0,aslongastheinputsequence100
has never been seen. Here 1+ means one or more 1. Note thatfor30%reducedcredityou
couldinsteaddesignthesystemasmorethanoneconcurrentfinitestatemachine.
c. Implement the FSM of step (a) [or for extra credit,implement instead the FSM from step
(b)] using D flipflops, NAND gates, and inverters only. Write expressions for the next state
logic andoutputlogic,andshowsupportingsteps (e.g.Karnaughmapsifyouusethem).Give
the cost of your implementation, assuming that an ninput NAND gate hasa cost of n,anda
1bit D flipflop hasa cost of 10. Both correctness and efficiency of implementationwouldbe
consideredduringgrading.
Note: For part (c), you might want to try out your solution in Logisim to make sure it works
correctly. If so, you are welcome to include printouts of Logisim schematics and Karnaugh

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UCLA|EEM16/CSM51A|Winter2015

Prof.ManiSrivastava

maps. However, please do things manually as otherwise you wouldhave a hard time in the
finals.

Problem #5:
In the class we discussed D flipflops which at the clock edge read and stored the value
present at their data input pin. There are other types of flipflops that behave slightly
differently. Onesuch flipflopis calledthe T flipflop, whose behavioristhatattheclockedge
if theinputis1thenittogglesthestoredvalue (i.e. ifthestoredvaluewas0thenitischanged
to1,andviceversa),andiftheinputis0thenthestoredvalueisleftuntouched.
a. Derive the nextstateandoutput equations (in terms ofbooleanlogicoperatorsforand,or,
not,andxor)forthecircuitshownbelowthatismadeusingTflipflops.
b. Show the state table for the circuit, making sure to show all possible states thatthecircuit
canbein.
c. Draw the state diagram for the circuit, making sure to show all possible states that the
circuitcanbein.
d. Complete thetimingdiagram below by drawing the waveform forZassumingcurrentstate
rightaftert=0isS[0]=S[1]=0.
e. From the state diagram you would see that the circuit has an isolated state. What state is
that? This state should not occur in normal operation. What happens ifthecircuithappensto
start in this state? What circuit modifications can you make to prevent the system from ever
enteringthisillegalstateorcauseittoleavethisillegalstateonceentered?

Pleasefillthetimingdiagramforpart(d)here:

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UCLA|EEM16/CSM51A|Winter2015

Prof.ManiSrivastava

Problem #6:
Draw the state diagramof the following circuit with input x and outputs z0 and z1,andmade
using JK flips flops. The two statebits are qA and qB. These flipflops operate according to
thefollowingequation: Qnext = (J Q) (K Q) .

Problem #7:
Often time signals from realworld, such as audio, images, sensor data etc., are noisy and
need to be smoothed to remove noise. The goal of this problem is todesign a very simple
system to do this. Yoursystemreceivesan8bit2scomplementsigneddatasampleoninput
X on every clock cycle, and outputs on each clock cyclean8bit 2scomplementsigneddata
value Y such thatY[n] = 0.25X[n] + 0.5X[n1] + 0.25X[n2] where X[n] and Y[n] indicate the
nth input and outputdatasample. AssumethatthefirstvalidsamplethatyoureceiveonXis
forn=0,andthatallthepreviousX[n]forn<0were0.
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UCLA|EEM16/CSM51A|Winter2015

Prof.ManiSrivastava

Clearly show the steps in your design. Your design may use any standard combinational
combinational(simple gates, mux, demux,encoder,decoder,arithmeticfunctionsetc.,except
multipliers) or sequential modules (flipflop, registers,countersetc.)discussed inthelectures.
Noteagain:youdonothaveamultipliermoduleavailabletoyou.
Note: You might want to try out your solution inLogisimtomakesure itworkscorrectly.Ifso,
you are welcome to include printouts of Logisim schematics. However, please do things
manuallyasotherwiseyouwouldhaveahardtimeinthequizandfinals.

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