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XFP-10Gb-LR
10G XFP Optical Transceiver Module
Features
z
z
z
z
Duplex LC connector
No reference clock required
+3.3V power supply ,+1.8V optional
Applications
z
Symbol
Vcc3
Vcc1.8
TS
TOP
Min
-0.5
-0.5
-40
0
Typ
Max
4.0
2.5
85
70
Unit
V
V
C
C
Ref.
Max
70
3.45
1.95
Units
C
V
V
Ref.
Symbol
Top
Vcc3
Vcc2
Min
0
3.13
1.65
Typ
PAGE 1 OF 6
Parameter
Symbol
Min
Vcc3
Vcc2
Icc3
Icc2
P
3.13
1.65
Typ
Max
Unit
3.45
1.95
800
400
2.5
V
V
mA
mA
W
820
Vcc
GND+ 0.8
10
mV
V
V
us
850
mV
Note
Transmitter
Input differential impedance
Differential data input swing
Transmit Disable Voltage
Transmit Enable Voltage
Transmit Disable Assert Time
Rin
Vin,pp
VD
VEN
100
120
2.0
GND
Receiver
Differential data output
swing
Data output rise time
Data output fall time
LOS Fault
LOS Normal
Power Supply Rejection
Vout,pp
340
tr
tf
VLOS fault
VLOS norm
PSR
Vcc 0.5
GND
650
38
38
VccHOST
GND+0.5
See Note 3 below
ps
ps
V
V
2
2
3
3
4
Notes:
1. After internal AC coupling.
2. 20 80 %
3. Loss Of Signal is open collector to be pulled up with a 4.7k 10kohm resistor to 3.15 3.6V.
Logic 0 indicates normal operation; logic 1 indicates no signal detected.
4. Per Section 2.7.1. in the XFP MSA Specification.
Symbol
Min
Transmitter
ER
SSRmin
-6
1290
6
POFF
-30
Txj
Max
Unit
-1
1330
dBm
nm
dB
dB
30
dBm
RSENS
PMAX
Typ
-16
-11
+0.5
dBm
dBm
PAGE 2 OF 6
Ref.
C
Rrx
LOSD
LOSA
1270
1600
-14
-15
-25
1
nm
dB
dBm
dBm
dB
Pin Descriptions
Pin
Logic
Symbol
Name/Description
Ref.
GND
Module Ground
VEE5
LVTTL-I
Mod-Desel
Module De-select; When held low allows the module to , respond to 2-wire
serial interface commands
LVTTL-O
Interrupt
LVTTL-I
TX_DIS
VCC5
+5 Power Supply
GND
Module Ground
VCC3
VCC3
10
LVTTL-I
SCL
11
LVTTLI/O
SDA
12
LVTTL-O
Mod_Abs
13
LVTTL-O
Mod_NR
14
LVTTL-O
RX_LOS
GND
Module Ground
1
1
15
16
GND
Module Ground
17
CML-O
RD-
18
CML-O
RD+
19
GND
Module Ground
20
VCC2
21
P_Down/R
ST
LVTTL-I
Power Down; When high, places the module in the low power stand-by mode
and on the falling edge of P_Down initiates a module reset
Reset; The falling edge initiates a complete reset of the module including the
2-wire serial interface, equivalent to a power cycle.
22
VCC2
23
GND
24
PECL-I
RefCLK+
25
PECL-I
RefCLK-
Module Ground
Reference Clock non-inverted input, AC coupled on the host board Not
required
Reference Clock inverted input, AC coupled on the host board Not required
26
GND
Module Ground
27
GND
Module Ground
28
CML-I
TD-
29
CML-I
TD+
GND
Module Ground
30
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PAGE 3 OF 6
3
3
Notes:
1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector; should be pulled up with 4.7k 10k ohms on host board to a voltage
between 3.15Vand 3.6V.
3. A Reference Clock input is not required.
General Specifications
Parameter
Symbol
Min
Bit Rate
BR
9.95
BER
LMAX
Typ
Max
Units
Ref.
11.1
Gb/s
-12
10
10
2
km
Notes:
1. SONET OC-192 SR-1SDH STM I-64.1 ,10GBASE-LR/LW, 1200-SM-LL-L
2. Tested with a 231 1 PRBS
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PAGE 4 OF 6
As defined by the XFP MSA, 10Gb/s XFP transceivers provide digital diagnostic functions via
a 2-wire serial interface, which allows real-time access to the following operating parameters:
Transceiver temperature
Laser bias current
Transmitted optical power
Received optical power
Transceiver supply voltage
It also provides a sophisticated system of alarm and warning flags, which may be used to alert
end-users when particular operating parameters are outside of a factory-set normal range.
The operating and diagnostics information is monitored and reported by a Digital Diagnostics
Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial
interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated
by the host. The positive edge clocks data into the XFP transceiver into those segments of its
memory map that are not write-protected. The negative edge clocks data from the XFP
transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host
uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The
memories are organized as a series of 8-bit data words that can be addressed individually or
sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit
parameters, addressed from 000h to the maximum address of the memory.
4.7H
0.1f
22f
4.7H
0.1f
Host+1.8V
0.1f
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VCC3
22f
4.7H
0.1f
Optional Host
-5.2V 4.7H
0.1f
VCC2
22f
4.7H
XFP Connector
Host+3.3V
VCC5
XFP Module
VEE5
22f
PAGE 5 OF 6
Host Board
XFI Receiver
XFP Module
XFI Transmitter
RD+
CML
RD-
CML
XFI Receiver
XFI Transmitter
TD+
CML
TD-
CML
Reference Clock
XFI Connector
Mechanical Specifications
XFP transceivers are compliant with the dimensions defined by the XFP Multi-Sourcing
Agreement (MSA).
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PAGE 6 OF 6