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24,
NO.
2, APRIL 1989
241
Ahstruct -A 10-bit, S-Msample/s, two-step flash analog-to-digital converter (ADC) in 1.6-pm CMOS requires 54 kmil* and 350 mW. The fully
differential architecture is based on a resistor string and capacitor-array
structure. A sample-and-hold circuit (S/H) is internal to the architecture,
eliminating the timing requirements that get more severe with increasing
resolution. Monotonicity can be guaranteed with minimal component
matching and comparator offset cancellation. The exponential growth of
area and power with increasing resolution in flash converters makes 10-bit
resolution a brute-force and unfeasible solution. Subranging architectures use as few as 2* - 1 rather than 2 - 1 comparators for large
savings of area and power. Previous two-step architectures were limited by
op-amp gain and settling time requirements. This new architecture eliminates this potential error source by eliminating the op amp. The comparator is critical in the design of a high-speed ADC. By using simple
comparator stage models the optimum number of comparator stages for
the fastest response can be determined. A comparator gain stage uses a
diode-connected MOS transistor load to eliminate the need for commonmode feedback (CMFB) that adds complexity and uses area and power.
I. INTRODUCTION
HE rapidly growing field of digital video that includes image recognition and hgh-definition television has created the need for inexpensive, high-speed
( > 5 Msamples/s), and moderate-resolution (10 bit)
ADCs. The first video ADCs were expensive hybrids
and later 8-bit monolithic flash converters were made in a
bipolar technology. Now advanced CMOS processes are
able to reach video conversion rates [1]-[5]. Video ADCs
fall into the 8-10-bit resolution and 5-20-Msample/s
conversion ranges. Although 8-bit resolution is acceptable
for video at the consumer level, the next generation of
converters will need 10-bit resolution for high-definition
television because of its increased dynamic range and so
that digital signal processing can be applied at the studio
level. CMOS is preferred for its lower cost and so that in
242
111. HIGH-SPEED
ADC ARCHITECTURES:
MULTISTEP
CONVERTERS
The proposed solutions to the flash converter's drawbacks span a range of multistep converters that include
pipelined, subranging, and classical two-step converters.
The pipelined architecture uses several stages operating
concurrently to achieve a high overall throughput. The
subranging and classical two-step architecture use two
steps and trade a factor of 2 speed reduction for a large
area savings. However, previous pipelined and classical
two-step flash converters have been limited by a combination of op-amp gain and speed, area and power. The new
subrangmg architecture eliminates these problems.
A . Pipelined Architecture
yn
jsiH
rl+-I+-w
"
..
...
LSBs
Fig. 1. Subranging ADC using 2" resistors and two banks of 2"/2 - 1
comparators. MSB comparators determine which segment the input lies
in. Then switches connect the LSB comparators to the resistors in that
segment and the LSB's are determined.
input, and often the digital output code to latter stages for
the next conversion that increases the precision of the
previous result. This continues until the last stage where
the final precision is obtained. The latter stages can share
parts of previous stages, saving area and elimin.ating the
matching requirements between an ADC and a DAC or
two ADC's by using the same precision elements repeatedly. From this starting point specific subranging converter architectures can be described.
When the term "subranging converter" is used it generally refers to a converter of the form in Fig. 1. It consists
of 2" resistors and 2"/2 - 1 comparators, a switch bank,
and a S/H. Although two sets of comparators, latches, and
decoder/encoders are shown for simplicity, only one set is
needed. In the first step the comparators are switched to
points on the resistor string every 2"12 taps apart and the
most significant bits (MSB's) decision is made. When the
resistor interval where the input voltage lies is known, the
other 2"/2 - 1 comparators are switched to all taps in that
range to do the fine or LSB conversion.
For an n-bit ADC this implementation could use 2 " / 2 - 1
rather than 2" - 1 comparators. This represents a large
savings in area and power.
T h s architecture has been implemented at an 8-bit level
[4]. The limitations to extending it to 10 bits are that it
uses two banks of comparators (2"12 and 2"12 - 1) and
encoders. T h s would be a large increase in area and power
and it would require 1024 resistors. In this implementation
there are two resistor strings. One is for the MSB's and one
is for the LSB's. Poor matching between them will lead to
large differential nonlinearities.
C. Classical Two-step Flash ADC
B. Subranging Architectures
DOERNBERG
et
U/.
10-BIT
5-MSAMPLE/S
(a)
MSBs
243
LSBs
-LSB
ADC I
1
-
A
(b)
Fig. 3. Prototype subranging ADC block diagram Notice that there arc
no op amps. The timing is similar to that in Fig. 2(b). The ADCs and
DACs share components to eliminate matching requircments among
them.
TABLE I
CIRCUIT DESIGN
PROBLEMS ANI)
SOLlJrlONS
Multistage Cornparalor
244
MSB Converter
APRIL
1989
vr2
Un-1
Compare
24, NO. 2,
t(
ADCsettoCode11111
Sample
Encoder
32C
MSBs
16~+08C+ICf2Cf
i l l l l L
8C
16C
4C
l
2C
l
Vr,-
vrl7
I 1 1 I
.f
c::
y,
- +
Switches
set to
Code
B. MSB ADC
The DAC and MSB ADC are shown in Fig. 4. The
resistor string, 31 capacitors, 31 comparators, and a latch
bank and binary encoder form the MSB converter. Each
shaded capacitor is actually a binary-weighted capacitor
array that will be used in the second step for the subranging LSBs conversion. It has switches set so that it is just
one capacitor of value 32 C in the first step where it stores
the input voltage minus the comparator offset voltage.
The operation is common to most CMOS flash ADCs.
First, the feedback switch is closed around each comparator storing the comparator offset voltage on the capacitor.
At the same time the capacitor bottom-plate switch is in
the sample position storing the unknown input voltage
on the capacitor. Thus the comparator offset voltage is
canceled and does not cause an error. Next, the feedback
switches are opened and the bottom-plate switch is thrown
to the compare position.
The resulting comparator outputs are in a thermometer
code: ONES up to the comparator whose input is the
resistor-string tap voltage below the unknown input voltage, then ZEROS above the tap that is just below the input
voltage. The comparator outputs are then latched and
encoded to binary.
D. LSB ADC
The LSB ADC is made up of 31 ADC subsections, a
latch bank, and a binary encoder as shown in Fig. 5. The
latch bank, encoder, capacitors, and comparators in each
of the subsections are the same as those used in the MSB
ADC. By using 31, 1-bit output, ADC subsections, each
with its comparator set at 1 of the 31 possible thresholds
between the MSB transitions, a second-step flash decision
is made.
Each LSB ADC subsection consists of the 5-bit capacitor array and comparator, shown shaded, from the MSB
ADC. Thts configuration operates like the classical
McCreary charge-redistribution ADC [ 81. The array capacitors have stored the unknown input voltage and it is
compared to the 31 voltages between V,l and V,,. The
code that the switches are set to is the setting of the
capacitor bottom-plate switches and is the threshold of the
ADC subsection between V,, and Y2:
DOERNBERG
et
01.:
245
'~a
o/%of'::pj
Latch
Gain
"
1
2
Time (r)
(b)
Output 40
(3)
20
0
0
2 3 4
Time (T)
(4)
01 2345678910
Number of Stages
PToduct for eaih stage. (c) Time for an-n-st&e comparator to make a
decision. (Output reaches dotted line in Fig. 6(b).) Six stages is optimum but the curve is flat for three to ovcr ten stages.
V.
ERRORSOURCES
2-
- 2(fl-1)/2-N
(6)
_
uf?- 2(fl-1)/2-fl
R
= 2-(n+1)/2
@Jz"'
(7)
246
a@
( k ) 3 1= 0.683.
(9)
(3.24)2.2
2 In (3.24)
m=n+
In (2)
=n
+ 3.40.
(11)
G = A.
(14)
=-=-
G
r
(12)
VI. COMPARATOR
DESIGN
The comparator design is centered on meeting several
specifications. Comparator gain is usually about 2 as a
rule-of-thumb. This is so that it can amplify a voltage that
is less than 1/2 LSB up to a fraction of the supply voltage
that can then be stored in a latch. Here a gain of 1000 is
desired.
The errors from feedback-switch charge injection and
the offset voltage must be less than 1/2 LSB. The charge
injection errors are minimized by using a fully differential
arclutecture, by choosing a small feedback switch, and by
canceling any residual error as shown in Section VI-A-1.
The comparator offset voltage must be less than 1 LSB
to guarantee monotonicity. Tlus is aclueved by storing the
offset voltage on the sampling capacitor during the first
step described in Section IV-B.
The simplest comparator is a positive-feedback latch. It
has a gain that is the ratio Vo,,,/Vin and is et/. The
stage time constant is r , the reciprocal of the bandwidth.
At a time t = T the gain is e.
(15)
nG/
=-
GBW .
(16)
DOERNBERG
et d.
: 10-BIT S-MSAMPLL/S
247
INL
(a)
(LSBs)
-1
60r
m.
RESULTS
VII. EXPERIMENTAL
The ADC prototype was tested in two ways. First, the
INL and DNL were measured with a code density test
[12]. Second, an FFT was run on data collected from a
digitized sine wave and the SNR was computed. The
converter was running at a 5-Msample/s rate. A lowfrequency (50 Hz) input was used rather than the external
S/H needed for the charge-injection cancellation described in Section VI-A-l. compensation voltages were
applied to the resistor-string quarter-point taps for the
SNR test and some of the INL measurements to reduce
the loading effects.
A . Integral Nonlinearity
248
TABLE I1
PROTOTYPE
ADC PEMORMANCE
AND SPECIFICATIONS
Resolulion
Conversion Rate
Maximum DNL
Maximum INL (With comp.)
Maximum SNR (Wilh comp.)
10 bits
5 Msampleslscc
0.6 LSB
Technology
3.0 LSB
50 dB
I .6 pm CMOS
Input Capacitance
Power Dissipation
350 mW
54k mils
D. Die Photo
C ICornpl Digital
Fig. 9 is a die photo of the prototype chip. The horizontal rows in the center and right are for each comparator
and its associated capacitor array and switches. The vertical columns start on the left with the resistor string. To its
right is the interconnect from the resistor-string taps to the
comparator inputs for the MSB first decision and for the
analog multiplexer. In the middle are the capacitor bottom-plate switches. On the right are the capacitor arrays
and comparators. To the far right is the decoder/encoder,
digital logic, and buffers.
The prototype chip is 260 x 280 mil2 with an active area
of 54 kmi12. It was fabricated in a 1.6-pm double-metal
CMOS process.
VIII.
SUMMARY
Table I1 shows the ADCs measured performance characteristics and other key specifications. A 10-bit, 5-Msample/s A/D conversion in CMOS is now possible with a
new two-step flash archtecture based on a resistor string
and capacitor arrays. Key to the design was a three-stage
fully differential comparator.
ACKNOWLEDGMENT
B. Differential Nonlinearity
DOERNBERG
et ul.: ~ O - B I T~-MSAMPLE/S
T. Matsuura et al., An 8b 20MHz CMOS half-flash A/D converter, in ISSCC Tech. Pupers, Feb. 1988, pp. 220-221.
T. Shimizu. M. Hotta. K. Maio. and S. Ueda. A 10b 20 MHz
two-step parallel ADC with intemal S/H, in ISSCC Dig. Tech.
Pupers, Feb. 1988, pp. ??4-225.
A. G. F. Dingwall, Monllithc expandable 6 bit 20 MHz
CMOS/SOS A/D converter, IEEE J . Solid-Stute Circuits, vol.
SC-14, no. 6. DD. 926-932. Dec. 1979.
J. L. McCreaG, All-MOS ch:!ge
redistribution analog-to-digital
conversion techniques-Part 1, I E E E J . Solid-Stute Circuits, vol.
SC-10, no. 6, pp. 371-379, Dec. 1975.
S. H. Lewis, Video-rate analog-to-digital conversion using
pipelincd architectures, Ph.D. dissertation, Univ. of Calif., ERL
memo USB/ERL M87/90, pp. 88-94, Nov. 18, 1987.
T. Baji, A high-speed, high-precision comparator design for a
10-bit 15 MHz A/D converter, ERL, Univ. of Calif., Berkeley,
Memo. UCB/ERL M85/86, pp. 46-50, Aug. 7, 1985.
D. J. Allstot. A precision variable-supply CMOS comparator,
IEEE J . Solid-State Circuits, vol. SC-17, no. 6, pp. 1080-1087, Dec.
1982.
J. Doernbere. H.-S. Lee. and D. A. Hodees. Full-meed testing of
A/D converters. I E E E J . Solid-Stute fircuits, vol: SC-19, no. 6,
pp. 820-827, Dec. 1984.
249
Department of Electrical Engineering and Computer Sciences, University
of California, Berkeley, where he is now a Professor. His research
interests during this period have included bipolar and MOS circuit
design, electro-thermal interactions in integrated circuits. device modeling, telecommunications circuits, and analog-digital interfaces in VLSI
systems. He is the co-author of a college textbook on analog integrated
circuits. During year-long industrial leaves of absence from Berkeley. he
served as Project Manager for Telecommunications Filters at Intel Corporation, Santa Clara, CA, in 1977-1978, and as Director of CMOS
Design Engineering at Microlinear Corporation, San Jose, CA, in
1984-1985. At Berkeley he has held several administrative posts including Director of the Electronics Research Laboratory (1985-1986). and
Vice-chairman of the EECS Department for Computer Resources
(1988-1989).
Dr. Gray has been co-recipient of best-paper awards at the International Solid-state Circuits Conference, the European Solid-state Circuits
Conference, and was co-recipient of the IEEE R. W. G. Baker Prize in
1980, the IEEE Morris K. Liebmann award in 1983, and the IEEE
Circuits and Systems Society Achievement Award in 1987. He served as
editor of the IEEE JOURNAL
OF SOLID-STATE
CIRCUITSfrom 1977 through
1979, and as Program Chairman of the 1982 International Solid State
Circuits Conference. He currently serves as President of the IEEE SolidState Circuits Council.