All Digital Phase Locked Loop

(ADPLL)
In partial fulfillment of the requirements of the course
Advanced VLSI Design

Submitted
Dr. ANU GUPTA

Submitted By:
Suhas. B (2014H123167P)
Sureshkumar (2014H123165P)

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Table of Contents
....................................................................................................................................................... 1
List of figures ................................................................................................................................ 3
CHAPTER 1 ................................................................................................................................... 4
INTRODUCTION ............................................................................................................................ 4
All Digital Phase locked loop: ...................................................................................................... 4
Basic Block Diagram: ............................................................................................................... 4
CHAPTER 2 ................................................................................................................................... 6
ADPLL Architecture ...................................................................................................................... 6
Architecture of ADPLL: ................................................................................................................ 6
Design and Operation of jitter bounded ADPLL ........................................................................... 9
Innovation in design:.................................................................................................................... 9
Drawbacks of Design:................................................................................................................ 10
CHAPTER 3 ................................................................................................................................. 11
Simulation and Synthesis Results ............................................................................................. 11
Verilog Code :............................................................................................................................ 11
Simulation: ................................................................................................................................ 16
Synthesis:.................................................................................................................................. 18
Xilinx Synthesis (FPGA): ....................................................................................................... 18
RC Compiler (ASIC): .............................................................................................................. 21
Layout: ................................................................................................................................... 24
FPGA vs ASIC implementation comparision: ......................................................................... 25
Reports : ................................................................................................................................ 26
References .................................................................................................................................. 27

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List of figures
Figure 1 Basic Block diagram of PLL .............................................................................................. 4
Figure 2: Block diagram of Digital PLL ............................................................................................ 6
Figure 3: Digital Frequency Detector ............................................................................................... 7
Figure 4: SAR as loop filter ............................................................................................................. 7
Figure 5: Accumulator type DCO .................................................................................................... 8
Figure 6: Simulation for p=2 .......................................................................................................... 16
Figure 7: Simulation for p=4 .......................................................................................................... 16
Figure 8 : Simulation for p=8 ......................................................................................................... 17
Figure 9: Simulation for p=16 ........................................................................................................ 17
Figure 10: Layout of ADPLL .......................................................................................................... 24
Figure 11: Placement of cells ........................................................................................................ 25

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CHAPTER 1
INTRODUCTION
All Digital Phase locked loop:
Phase locked loop (PLL) is a very important clocking circuit for many digital systems such
as digital communication and microprocessor. It can be used for frequency synthesis and locking
the phase. Traditionally, the PLL is designed using analog techniques but with the increasing use
of SoC and deep sub-micron technology it takes a lot of effort to integrate an analog block to a
digital system. Furthermore, with the change of technology, the analog blocks need to be redesigned.
In contrast, all digital phase locked loop (ADPLL) uses the cell based design
approach, so it can be easily integrated into digital system. Also ADPLL has higher immunity for
switching noise, and process, voltage and temperature (PVT) variations.

Basic Block Diagram:

Figure 1 Basic Block diagram of PLL

The main components of PLL are

1.
2.
3.
4.

Oscillator
Phase Frequency Detector
Filter
Divider

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Oscillator:
It generates the desired frequency of the PLL. It can be a voltage controlled
oscillator (VCO) or a digitally controlled oscillator (DCO).
Phase Frequency Detector:
It produces a signal proportional to the phase difference between the incoming
signal and the VCO output signal.
Filter:
The output of the phase detector is filtered by a low-pass filter (LPF) and is fed to
the oscillator.
Divider:
Divider circuit divides the frequency of oscillator before it is fed to the phase
frequency detector for comparision with the incoming signal. By adjusting the value of the divider
we can change the frequency of the oscillator.

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CHAPTER 2
ADPLL Architecture
Architecture of ADPLL:
A Phase Locked Loop is a closed loop control system which is used for the purpose of
synchronization of the frequency and phase of a locally generated signal with that of an incoming
signal. There are basically three components in a PLL. The Phase and Frequency detector (PFD),
the loop filter and the Voltage Controlled Oscillator (VCO). The VCO is the heart of any PLL. The
mechanism by which this VCO operates decides the type of the PLL circuit being used. The analog
PLL or the Linear PLL has been in use since a long time. It basically uses a multiplier circuit for
serving the purpose of the PFD and a first order filter for the loop filter and a typical analog VCO.
Though the name Digital is present in the DPLL, its not exactly a complete Digital PLL. The All
Digital PLL makes an attempt at digitizing all the three components required for the operation of a
phase locked loop. The general structure of ADPLL is shown below in figure.

Figure 2: Block diagram of Digital PLL

All Digital Phase Detector:

The PD was the only component that was digitized long back. Its used in the Digital PLL.
Similar idea can be extended to the ADPLL. The three common implementations of the digital PD
are:
1. Exclusive-or (EXOR) Gate
2. Edge triggered JK Flip-Flop
3. Digital Phase-Frequency Detector

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The EXOR mechanism offers a simple yet reliable method of phase detection. One main
drawback of this mechanism is its lack of sensitivity to edges. Its a flat triggered mechanism. To
eliminate this drawback the edge triggered mechanism comes into picture. The edge triggered JK
mechanism is the most popular and effective one. It is sensitive to the edges and hence
instantaneous corrective action can be achieved. The incoming reference signal acts as one input
and the output of the Digital Controlled Oscillator (feedback of the PLL) acts as the other input.
This mechanism that has been used in the design of the current Jitter bounded ADPLL is shown
below in figure.

Figure 3: Digital Frequency Detector

All Digital Loop Filter :

In ADPLL implemented uses successive approximation register (SAR) as a loop filter.
Basically SAR used in ADPLL is same as SAR used ADC. Initially SAR generates the value 2N-1.
The input to the SAR is the control signal and up/down signal, according to the status of both the
signal SAR either increases or decreases the value of K.

Figure 4: SAR as loop filter

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Accumulator

type DCO

Figure 5: Accumulator type DCO

The DCO output is generated by successively adding the value of an integer K to itself at
the high frequency rate fs of a system clock. The accumulator type DCO is made use of in this
current design of ADPLL. The accumulator type DCO along with the edge triggered JK flip-flop
offer a powerful phase lock mechanism. The value at the output of the adder at time n is,
Output of latch = nk modulo 2N.
The DCO output is given by the most significant bit of the output of the latch, so that the
DCO output frequency is given by the formula,

In effect, this latch acts as a phase register, which indicates the phase of the DCO output
signal. As such, the above adder-latch arrangement constitutes a frequency generator which
operates at a fixed rate for given values of k and fs. In order to generate the desired frequency.
This adder-latch arrangement is operated in conjunction with a frequency comparator which
searches for a value of k that leads to p pulses of the DCO output during two successive rising
edges of the fq clock. For given values of fq and fs , it is possible to find at least one integer k
which leads to less than (p+1/2) and more than (p-1/2) DCO clock periods during a single cycle of
the q f clock, if the number of bits of the accumulator, N, satisfies the inequality

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Design and Operation of jitter bounded ADPLL

Design Specifications
Output frequency range of PLL; fmin - fmax = 1KHz 100 KHz
Limitations on jitter <= 10%
Therefore according to given constraints,

N = 16 bits and fs = 1 MHz

Operation:
The implementation of the Digital Phase-Locked Loop is shown in fig 2. Similarly, the
frequency fDCO is divided by p using a mod-p counter. The counter used is a down counter. The
counter is initialized to a pre-stored value in p-register respectively whenever the load signal is
asserted. The mod-p counter is basically counting the number of positive edges of fDCO that pass
between two successive positive edges of fREF. The count however might be less than or greater
than k depending on the jitter considerations. This is checked using the zero comparator provided
in the circuit.
If the number of edges counted is less than k then it asserts a high signal. Otherwise, it
asserts a low signal. The output of the zero comparator is provided to k-Register controller. kregister controller is basically a fsm that generates two output signals to drive the Successive
approximation register based on its two inputs received from the zero comparator and the phase
window comparator.
Successive approximation register is responsible for generating the value of k. The
successive approximation register is set at the mid-value i.e. only the msb is set. Depending on the
received inputs, the new value is set with setting and resetting of appropriate bits after required
comparisons. The k value is provided to the DCO. DCO used is basically an accumulator-type
DCO as shown in fig 2. One input is the k value and other input is the latched-output fed back to
the input. The MSB of the result produced is used as f DCO. The DCO and mod-p counter receive a
sync signal from k-register controller which is used to clear the DCO output and to load mod-p
counter with value from p-register.

Innovation in design:
It is difficult to write Verilog code which can be synthesised to count the number of f dco
pulses between two positive edges of fref signal. In order to accomplish this task a set of flag
registers were used. Using them as control signals in two always blocks, conditions were set/unset
in order to properly count the number of f dco pulses between two positive edges of f ref signal. Also
the phase comparator block was eliminated from the existing architecture so that chip area is
reduced without losing the performance much.

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Drawbacks of Design:
The designed ADPLL could generate frequencies in range 1KHz 100KHz only. To
generate further higher frequencies very high system frequency clock is to be used which causes
limitation in the critical delay path of the adder block in DCO.

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CHAPTER 3
Simulation and Synthesis Results
Verilog Code :
module ADPLL(fs,fq,fdco,p);
input fs,fq;
input [7:0]p;
output fdco;
wire [7:0]m_out;
wire [15:0]k;
DCO dco1(k,fs,fq,fdco);
divide_p dp1(fdco,fq,p,m_out);
zero_comp zc1(m_out,p,high,low);
k_register kr1(high,low,fq,ud,ctrl);
sar sar1(ud,ctrl,k,fq);
endmodule
/////////////////////////////////////////////////////////////////
module DCO(k,fs,sync,fdco);
input fs,sync;
output fdco;
input [15:0]k;
reg [15:0]latch_o;
wire [15:0]add_out;
reg count1 = 1'b1;
reg count2 = 1'b0;
assign add_out = latch_o + k;
always@(posedge count2, negedge sync)
begin
if(!sync)
count1 <= 1'b1;
else
begin
if(count2)
count1 <= 1'b0;
else
count1 <= 1'b1;
end
end
always@(posedge fs,posedge sync)
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begin
if(sync)
begin
if (count1)
begin
latch_o <= 16'h0000;
count2 <= 1'b1;
end
else
begin
latch_o <= add_out;
count2 <= 1'b0;
end
end
else
begin
latch_o <= add_out;
count2 <= 1'b0;
end
end
assign fdco = latch_o[15];
endmodule
///////////////////////////////////////////////////////
module divide_p(fdco,load,p,m_out);
input fdco,load;
input [7:0]p;
output reg [7:0]m_out;
reg [7:0]mout1;
reg count1;
reg count2 = 1'b0;
always@(posedge load,posedge count2)
begin
if(load)
begin
mout1 <= p;
if(count2)
count1 <= 1'b0;
else
count1 <= 1'b1;
end
else
begin
if(count2)
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count1 <= 1'b0;

else
count1 <= 1'b1;
end
end
always@(posedge fdco)
begin
if(count1 == 1'b1)
begin
m_out <= mout1 - 1'b1;
count2 <= 1'b1;
end
else
begin
m_out <= m_out - 1'b1;
count2 <= 1'b0;
end
end
endmodule
///////////////////////////////////////////////////////////
module zero_comp(m_out1,p,high,low);
input [7:0] m_out1;
input [7:0] p;
output high , low;
reg low1;
reg high1;
always @ (m_out1)
begin
if (m_out1>p)
begin
low1<=1;
high1<=0;
end
else if (m_out1<p)
begin
low1<=0;
high1<=1;
end
else
begin
high1<=0;
low1<=0;
end
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end
assign low=low1;
assign high=high1;
endmodule
///////////////////////////////////////////////////////////////
module k_register(high,low,fq,ud,ctrl);
input high,low,fq;
output reg ud,ctrl;
always@(posedge fq)
begin
if((high == 1'b1) && (low == 1'b0))
begin
ud <= 1'b1;
ctrl <= 1'b1;
end
else if((high == 1'b0) && (low == 1'b1))
begin
ud <= 1'b0;
ctrl <= 1'b1;
end
else if((high == 1'b0) && (low == 1'b0))
begin
ud <= 1'b0;
ctrl <= 1'b0;
end
end
endmodule
////////////////////////////////////////////////////////
module sar(ud,ctrl,k,fq);
input ud,ctrl,fq;
output [15:0]k;
reg [15:0]k1 = 16'h8000;
integer i = 15;
always@(posedge fq)
begin
if(ctrl)
begin
if(ud)
begin
k1[i] <= 1'b1;
k1[i-1] <= 1'b1;
end
else
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begin
k1[i] <= 1'b0;
k1[i-1] <= 1'b1;
end
i<=i-1;
end
//i=i-1;
end
assign k = k1;
endmodule

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Simulation:

Figure 6: Simulation for p=2

Figure 7: Simulation for p=4

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Figure 8 : Simulation for p=8

Figure 9: Simulation for p=16

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Synthesis:
The synthesis of ADPLL is done both in XILINX and RC Compiler. The synthesized RTL
diagrams are shown below.
Xilinx Synthesis (FPGA):
Top module:

DCO:

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Divide-p:

Zero-Comparator:

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K-register:

SAR:

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RC Compiler (ASIC):
In RC Compiler RTL level logic has been synthesized.
Top module:

Divide by p:

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K-register:

DCO:

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Zero Comparator:

SAR:

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Layout:
The layout of ADPLL is obtained from the Verilog netlist file using CADENCE SOC
Encounter tool. The layout is generated keeping the width and height ratio as 1 so that maximum
density can be achieved. Finally a density of 82% is obtained.

Figure 10: Layout of ADPLL

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Figure 11: Placement of cells

FPGA vs ASIC implementation comparision:

FPGA
LUT Implementation

Easily configurable

Area is not much concern

LUTs used = 218

ASIC
Standard Cell implementation

Once synthesized difficult to re-configure.

Area minimization is critical.

Standard cell blocks used = 419

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Reports :

LUT utilization:

Area:

Power:

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References
1. Digital Phase-Locked Loop with Jitter Bounded, Stephen Walters, Vol.36, No.7 , 1989.
2. Digital integrated circuit design, Rabaey.
3. Verilog modeling, S.Palnitkar.

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