CIRCUIT NOISE

379

it

+ vt

(a)

CIRCUIT NOISE
Noise is present in all electronic circuits. It is generated by
the random motion of electrons in a resistive material, by the
random generation and recombination of holes and electrons
in a semiconductor, and when holes and electrons diffuse
through a potential barrier. This article covers the fundamentals of noise from a circuit viewpoint. The principal sources
are described, circuit models are given, and methods for its
measurement are discussed. Noise models for the bipolar
junction transistor (BJT) and the field effect transistor (FET)
are given. The conditions for minimum noise in each are derived.
The notation for voltages and currents corresponds to
the following conventions: dc bias values are indicated by
an uppercase letter with uppercase subscripts, e.g., VDS, IC.
Instantaneous values of small-signal variables are indicated
by a lowercase letter with lowercase subscripts, e.g. vs, ic.
Mean squared values of small-signal variables are represented by a bar over the square of the variable, e.g., vs2,
ic2, where the bar indicates an arithmetic average of an
ensemble of functions. The root-mean-square (rms) value is
the square root of the mean squared value. Phasors are
indicated by an uppercase letter and lowercase subscripts
(e.g. Vs, Ic). Circuit symbols for independent sources are
circular, symbols for controlled sources have a diamond
shape, and symbols for noise sources are square. Voltage
sources have a  sign within the symbol, and current
sources have an arrow. In the numerical evaluation of noise
equations, Boltzmanns constant is k  1.38
1023 J/K
and the electronic charge is q  1.60
1019 C. The standard temperature is denoted by T0 and is taken to be T0 
290 K. For this value, 4kT0  1.60
1020 J and the
thermal voltage is VT  kT0 /q  25.0 mV.
THERMAL NOISE
Thermal noise, also called Johnson noise, is generated by the
random thermal motion of electrons in a resistive material. It
is present in all circuit elements containing resistance and is
independent of the composition of the resistance. It is modeled the same way in discrete-circuit resistors and in integrated circuit monolithic and thin film resistors. The phenomenon was discovered (or anticipated) by Schottky in 1928 and
first measured and evaluated by Johnson in the same year.
Shortly after its discovery, Nyquist used a thermodynamic argument to show that the mean squared open-circuit thermal
noise voltage across a resistor is given by
v2t = 4kTR  f

(1)

where k is Boltzmanns constant, T is the absolute temperature, R is the resistance, and f is the bandwidth in hertz

(b)

Figure 1. Thermal noise models of the resistor: (a) Thevenin model.

(b) Norton model.

over which the noise is measured. The corresponding mean

squared short-circuit thermal noise current is given by
i2t =

v2t
4kT  f
=
R2
R

(2)

The Thevenin and Norton noise models of a resistor are

given in Fig. 1. Because noise is random, the source polarities
are arbitrary. In general, the polarities must be labeled when
writing circuit equations that involve small-signal or phasor
voltages and currents. The mean squared noise is independent of the assumed polarities.
The crest factor of thermal noise is defined as the level
that is exceeded 0.01% of the time. To relate this to the rms
value, a statistical model for the amplitude distribution is required. It is common to use a Gaussian, or normal, probability
density function. For a Gaussian random variable, the probability that the instantaneous value exceeds four times the rms
value is approximately 0.01%. Thus the crest factor of thermal noise is approximately 4.
The spectral density of a noise source is defined as the
mean squared value of the source per unit bandwidth. It is
equal to the average power per unit bandwidth delivered by
the source to a normalized load resistance of 1 . In general,
the spectral density is a function of frequency. The voltage
and current spectral densities, respectively, for the thermal
noise generated by a resistor of value R are given by
Sv t ( f ) =

v2t
= 4kTR
f

(3)

Si ( f ) =

i2t
4kT
=
f
R

(4)

Because these are independent of frequency, thermal noise is

said to have a uniform or flat power distribution. It is sometimes called white noise by analogy to white light, which also
has a flat spectral density in the optical band.
In the frequency band from f 1 to f 2, the mean squared
open-circuit thermal noise voltage generated by any twoterminal network is given by

v2t = 4kT

f2

Re Z df

(5)

f1

where Z is the complex impedance of the network, Re Z is the

real part of Z, and f is the frequency in hertz. For f 2  f 1 

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

380

CIRCUIT NOISE

f and f small, the noise voltage divided by the square root

of the bandwidth is given by

v2t
= 4kT Re Z
f

NOISE RESISTANCE AND CONDUCTANCE

A mean-square noise voltage can be represented in terms of
an equivalent noise resistance Rn. Let vn2 be the mean-square
noise voltage in the band f. The noise resistance Rn is defined as the value of a resistor at the standard temperature
T0  290 K which generates the same noise voltage. It is
given by
v2n
4kTo  f

(7)

A mean-square noise current can be represented in terms

of an equivalent noise conductance Gn. Let in2 be the meansquare noise current in the band f. The noise conductance
Gn is defined as the value of a conductance at the standard
temperature which generates the same noise current. It is
given by
Gn =

i2n
4kTo  f

(8)

NOISE TEMPERATURE
The noise temperature Tn of a source is the temperature of
a resistor having a value equal to the output resistance of
the source that generates the same noise as the source. It is
given by
Tn =

v2ns
4kRS  f

(9)

2
is the mean squared open-circuit noise voltage genwhere vns
erated by the source in the band f, and RS is the real part of
the output impedance of the source. If the source noise is expressed as a current, the noise temperature is given by

Tn =

i2ns
4kGS  f

i2sh = 2qI  f

(6)

This equation defines what is called the thermal spot noise

voltage generated by the impedance. The units are read volts
per root hertz.

Rn =

eled by a parallel noise current source. The mean squared

shot noise current in the frequency band f is given by

(10)

where q is the electronic charge and I is the dc current flowing

through the device. This equation was derived by Shottky in
1928 and is known as the Shottky formula. The spectral density of shot noise is flat; thus shot noise is white noise. It
is commonly assumed that the amplitude distribution can be
modeled by a Gaussian distribution. Thus the relation between the crest factor and rms value for shot noise is the
same as it is for thermal noise.
FLICKER NOISE
The imperfect contact between two conducting materials
causes the conductivity to fluctuate in the presence of a dc
current. This phenomenon generates flicker noise, also called
contact noise. It occurs in any device where two conductors
are joined together, for example the contacts of switches, potentiometers, or relays. Flicker noise in BJTs occurs in the
base bias current. In FETs, it occurs in the drain bias current.
Flicker noise is modeled by a noise current source in parallel with the device. The mean squared flicker noise current in
the frequency band f is given by
i2f =

(12)

EXCESS NOISE
Flicker noise in resistors is referred to as excess noise. It is
caused by the variable contact between particles of the resistive material. Metal film resistors generate the least excess
noise, carbon composition resistors generate the most, and
carbon film resistors lie between the two. The mean squared
short-circuit excess noise current generated by a resistor R is
given by
i2ex =

2
f
Kf IDC
f

(13)

where IDC is the dc current through the resistor. The mean

squared open-circuit excess noise voltage across the resistor
is given by

SHOT NOISE
Shot noise is generated by the random emission of electrons
or by the random passage of electrons and holes across a potential barrier. The shot noise generated in a device is mod-

Kf I m  f
fn

where I is the dc current, n 1, Kf is the flicker noise coefficient, and m is the flicker noise exponent. The spectral density of flicker noise is inversely proportional to frequency. For
this reason, it is commonly referred to as 1/f noise.
Flicker noise in BJTs can increase significantly if the baseto-emitter junction is subjected to reverse breakdown. This
can be caused during power supply turn-on or by the application of too large an input voltage. A normally reverse-biased
diode in parallel with the base-to-emitter junction is often
used to prevent it.

2
ns

where i is the mean squared short-circuit noise current generated by the source in the band f, and GS is the real part
of the output admittance of the source.

(11)

v2ex =

2
K V2 f
R2S  f
Kf IDC
= f DC
f
f

where VDC  IDCR is the dc voltage across the resistor.

(14)

CIRCUIT NOISE

The noise index of a resistor in decibels is the value of 20

2 /V ) for one decade of frequency, where 2 is exlog ( vex
vex
DC
pressed in microvolts. An alternative definition of the noise
2 /I ) for one decade of freindex is the value of 20 log ( iex
DC
2 is expressed in microamperes. Given the
quency, where iex
2 in microvolts and the
noise index NI, the value of vex
2 in microamperes in the range from f to f are
value of iex
1
2
given by



v2ex

= 10

NI/20

VDC


i2ex = 10NI/20 IDC

ln( f 2 / f 1 )
ln 10

(15)

ln( f 2 / f 1 )
ln 10

(16)

BURST NOISE
Burst noise is caused by a metallic impurity in a pn junction
caused by a manufacturing defect. It is minimized by improved fabrication processes. When burst noise is amplified
and reproduced by a loudspeaker, it sounds like corn popping.
For this reason, it is also called popcorn noise. When viewed
on an oscilloscope, burst noise appears as fixed-amplitude
pulses of randomly varying width and repetition rate. The
rate can vary from less than one pulse per minute to several
hundred pulses per second. Typically, the amplitude of burst
noise is 2 to 100 times that of the background thermal noise.
NOISE BANDWIDTH
In making noise measurements, it is common to precede the
measuring voltmeter with a filter of known noise bandwidth.
The noise bandwidth of a filter is defined as the bandwidth of
an ideal filter that passes the same mean squared noise voltage, where the input signal is white noise. The filter and the
ideal filter are assumed to have the same gain.
The noise bandwidth B in hertz of a filter is given by
B=

1
A20

|A( f )|2 d f

(17)

where A( f) is the filter voltage-gain transfer function, A0 is

the maximum value of A( f), and f is the frequency in hertz.
Figure 2 graphically illustrates the concept of noise bandwidth for a low-pass filter and a band-pass filter. In each case,

Table 1. Noise Bandwidth B of Low-Pass Filters

Number
of poles

Slope
(dB/decade)

1
2
3
4
5

20
40
60
80
100

Low
pass

Butterworth







1.571f3
1.111f3
1.042f3
1.026f3
1.017f3

1.571f3
1.220f3
1.155f3
1.129f3
1.114f3

the actual filter response and the response of an ideal filter

having the same noise bandwidth are shown. For equal noise
bandwidths, the area under the actual filter curve must be
equal to the area under the ideal filter curve. This makes the
two indicated areas equal for the low-pass case. A similar interpretation holds for the band-pass case.
Two classes of low-pass filters are often used in measuring
noise. One has n real poles, all with the same frequency. The
other is a n-pole Butterworth filter. Table 1 gives the noise
bandwidth for each filter as a function of the number of poles
n for 1 n 5. For the real-pole filter, the noise bandwidth
is given as a function of both the pole frequency f 0 and the
upper 3 dB cutoff frequency f 3. For the Butterworth filter,
the noise bandwidth is given as a function of the upper 3
dB frequency. The table shows that the noise bandwidth approaches the 3 dB frequency as the number of poles is increased.
Band-pass filters are used in making spot noise measurements. The noise bandwidth of the filter must be small
enough so that the spectral density of the input noise is approximately constant over the bandwidth. The spot noise voltage is obtained by dividing the rms noise output voltage from
the filter by the square root of its noise bandwidth. Secondorder bandpass filters are commonly used for these measurements. The noise bandwidth of a second-order band-pass filter
having a resonance frequency f 0 and a quality factor Q is
given by
B=

f0
2Q

(18)

If f a and f b, respectively, are the lower and upper 3 dB frequencies of the filter, an alternative expression for the noise
bandwidth is

( f fa )
2 b

(19)

This expression is often used to approximate the noise bandwidth of unknown band-pass filters.
A second-order band-pass filter is often realized by a firstorder high-pass filter in cascade with a first-order low-pass
filter. The noise bandwidth is given by

A20
Equal
areas

Real Pole
1.571f0
0.785f0
0.589f0
0.491f0
0.420f0

B=
A(f)

381

A20
Band
pass

B=

( f + f2 )
2 1

(20)

0
B

Figure 2. The bandwidth of an ideal filter is equal to the noise bandwidth of a physical filter if the two filters have the same area beneath
their magnitude-squared response curves.

where f 1 is the pole frequency of the high-pass filter and f 2 is

the pole frequency of the low-pass filter. These frequencies
are not the 3 dB frequencies of the bandpass filter.
The noise bandwidth of any filter can be measured if a
white noise source and another filter with a known noise

382

CIRCUIT NOISE

bandwidth are available. With both filters driven simultaneously from the white noise source, the ratio of the noise bandwidths is equal to the square of the ratio of the output
voltages.
MEASURING NOISE
Noise is usually measured at an amplifier output, where the
voltage is the largest and easiest to measure. The output
noise is referred to the input by dividing by the gain. A filter
with a known noise bandwidth should precede the voltmeter
to limit the bandwidth. The measuring voltmeter should have
a bandwidth that is at least 10 times the filter bandwidth.
The voltmeter crest factor is the ratio of the peak input voltage to the full scale rms meter reading at which the internal
meter circuits overload. For a sine wave, the minimum voltmeter crest factor is 2. For noise measurements, a higher
crest factor is required. For Gaussian noise, a crest factor of
3 gives an error less than 1.5%. A crest factor of 4 gives an
error less than 0.5%. To minimize errors caused by overload
on noise peaks, measurements should be made on the lower
one-third to one-half of the voltmeter scale.
A true rms voltmeter is preferred over one that responds
to the average rectified value of the input voltage but has a
scale calibrated to read rms. When the latter type of voltmeter is used to measure noise, the reading will be low. For
Gaussian noise, the reading can be corrected by multiplying
the measured voltage by 1.13.

Real Signals
Let va(t) and vb(t) be two noise voltages having the mean
squared values va2 and vb2. Define the sum voltage vsum(t) 
va(t)  vb(t). The mean squared value of the sum is given by

v2sum = [va (t) + vb (t)]2

(21)

where
is the correlation coefficient defined by

va (t)v (t)
=  b
v2a v2b

v2sum = (Va + Vb )(Va + Vb )

= |Va |2 + 2 Re(VaVb ) + |Vb |2
 

= v2a + 2(Re ) v2a v2b + v2b

(23)

where is the complex correlation coefficient defined by

VaV
= r + ji =  b
v2a v2b

(24)

Equation (23) seems to imply that only the real part of

needs to be known. In general, it is necessary to know both
the real and imaginary parts. To illustrate this, consider the
sum Vsum  Vn  InZ, where Z is a complex impedance. The
mean squared sum is given by

v2sum = |Vn |2 + 2 Re(Vn In Z ) + |In Z|2

 
= v2n + 2(Re Z ) v2n i2n + i2n |Z|2

(25)

where the correlation coefficient is given by

Vn I
= r + ji =  n
v2n i2n

ADDITION OF NOISE SIGNALS

= v2a (t) + 2va (t)vb (t) + v2b (t)

 
= v2a + 2 v2a v2b + v2b

taken here to represent the rms value rather than the peak
value of the variable at that frequency. To illustrate the addition of noise phasors, let Va and Vb be the phasor representations of two noise voltages at a particular frequency. The sum
is given by Vsum  Va  Vb. The mean squared sum is calculated as follows:

(26)

For arbitrary Z, both r and i must be known to evaluate the

factor Re Z*.
Noise formulas derived by a phasor analysis of circuits containing complex impedances can be converted into formulas
for circuits containing real impedances, i.e. resistors, by setting to zero in the formulas the reactive, or imaginary, part
of all impedances and setting i  0 and r 
, where
is
real. However, the procedure cannot be done in reverse. For
this reason, noise formulas derived by a phasor analysis are
the more general form of the formulas.
Correlation Impedance and Admittance

(22)

The correlation coefficient can take on values in the range

1
1. For the case
 0, the voltages va(t) and vb(t)
are said to be statistically independent or uncorrelated.
Phasor Signals
It is often necessary to use phasor representations of noise
voltages and currents in writing equations for circuits containing capacitors and/or inductors. The mathematical basis
for this is involved and is omitted here. When a phasor representation is used, the ensemble average of the squared magnitude of the phasor represents the mean squared value of
the noise voltage or current in the band f centered on the
frequency of analysis. Thus the magnitude of the phasor is

The concepts of a correlation impedance Z and a correlation

admittance Y between a noise voltage Vn and a noise current
In are often used in the noise literature. These are defined by

Vn In
v2
Z = R + jX =
=  n
(27)
i2n
i2n

Vn In
i2

Y = G + jB =
=  n
(28)
v2n
v2n
It follows from these definitions that ZY  2.
vn in AMPLIFIER NOISE MODEL
A general noise model of an amplifier can be obtained by reflecting all internal noise sources to the input. In order for

CIRCUIT NOISE

Zs

Vs

Vts

Vn

Amplifier

Vi

In

383

Zs

Vo = AVi

(a)

Amplifier

Vn
+

+
Is

Ys

Its

In

Vi

Zi

Vo = AVi

Figure 3. The vnin noise model amplifier: (a) With Thevenin

source. (b) With Norton source.

(b)

the reflected sources to be independent of the source impedance, two noise sources are requireda series voltage source
and a shunt current source. In general, these sources are correlated. The amplifier noise model is described in this section.
The equivalent noise input voltage is derived for the case
where the source is represented by a Thevenin equivalent.
The equivalent noise input current is derived for the case
where the source is represented by a Norton equivalent. A
more general phasor analysis is used.
Thevenin Source
Figure 3(a) shows the amplifier model with a Thevenin input
source, where Vs is the source voltage, Zs  RS  jXS is the
source impedance, and Vts is the thermal noise voltage generated by the source. The output voltage is given by
Vo =

AZi
[Vs + (Vts + Vn + In Zs )]
Zs + Zi

(29)

where A is the loaded voltage gain and Zi is the input impedance. The equivalent noise input voltage Vni is defined as the
voltage in series with the amplifier input that generates the
same noise voltage at the output as all noise sources in the
circuit. Its value is given by the sum of the noise terms in
the parentheses in Eq. (29) and is independent of the amplifier input impedance.
The mean squared value of Vni is solved for as follows:

v2ni = (Vts + Vn + In Zs )(Vts + Vn + In Zs )

= VtsVts + VnVn + 2 Re(Vn In Zs ) + (In Zs )(In Zs )
 
= 4kTRS  f + v2n + 2(Re Zs ) v2n i2n + i2n |Zs |2
 
= 4kTRS  f + v2n + 2(r RS + i XS ) v2n i2n + i2n (R2S + XS2 )
(30)

where  r  ji is the correlation coefficient between Vn

and In and it is assumed that Vts is independent of both Vn
2
and In. For Zs very small, vni
vn2 and the correlation coeffi2
cient is not important. Similarly, for Zs very large, vni
in2
Zs2 and the correlation coefficient is again not important. Unless it can be assumed that  0, the vn in amplifier noise
model can be cumbersome for making noise calculations. For
0, it is often simpler to use the original circuit with its
internal noise sources.
With Vs  0 in Eq. (29), the mean squared noise voltage at
the amplifier output is given by



 AZi 2 
 4kTR  f
v2no = 
S
Zs + Zi 

 

+ v2n + 2(Re Zs ) v2n i2n + i2n |Zs |2

(31)

If Zs  0, this equation can be solved for vn2 to obtain

v2n =

v2no
|A|2

for

Zs = 0

(32)

If Zs is very large, in2 can be solved for to obtain


2
1
1  v2
i2n = 
+  no2
Zs
Zi |A|

for |Zs | large

(33)

These equations suggest methods for experimental determi2

nation of vn2 and in2. In measuring vno
, it is common to use a
filter with a known noise bandwidth preceding the voltmeter.
Norton Source
Figure 3(b) shows the amplifier model with a Norton input
source, where Is is the source current, Ys  GS  jBS is the

384

CIRCUIT NOISE

source admittance, and Its is the thermal noise current generated by the source. The output voltage is given by
A
Vo =
[Is + Its + VnYs + In ]
Ys + Yi

SNR =

i2ni = (Its + VnYs + In )(Its

+ VnYs + In )
+ (V Y )(V Y ) + 2 Re (V Y I ) + I I
= Its Its
n s
n s n
n n
n s
(35)
 
= 4kTGS  f + v2n |Ys |2 + 2(Re Ys ) v2n i2n + i2n
 
= 4kTGS  f + v2n (G2S + B2S ) + 2(r GS i BS ) v2n i2n + i2n

where  r  ji is given by Eq. (26).

SIGNAL-TO-NOISE RATIO
Thevenin Source
When the source is modeled by a Thevenin equivalent circuit
as in Fig. 3(a), the signal-to-noise ratio is given by

SNR =

v2ni

(36)

2
where vni
is given by Eq. (30). The SNR is often expressed
2
). The SNR is maximized by miniin decibels as 10 log(vs2 /vni
2
2
imizing vni. The source impedance that minimizes vni
can be
2
2
/dRS  0 and dvni
/dXS  0 and
obtained by setting dvni
solving for RS and XS. The solution for RS is negative. Because this is not realizable, RS  0 is the realizable solution
for the least noise. The source impedance which minimizes
2
vni
is given by

Zsm = Rsm + jXsm



v2
= 0 ji
n
i2n

(37)

Because minimum noise occurs for RS  0, it can be concluded that a resistor should never be connected in series
with a source at an amplifier input if noise performance is a
design criterion. Although the output impedance of a source
is usually fixed, the SNR can be improved by adding a reactance in series with the source that makes the total series
reactance equal to the imaginary part of Zsm. When this is the
2
case, vni
is given by

 
v2ni = 4kTRS  f + v2n (1 i2 ) + 2r RS v2n i2n + i2n R2S
 
= 4kTRS  f + v2n + 2r RS v2n i2n + i2n (R2S XS2 )

When the source is modeled by a Norton equivalent circuit as

in Fig. 3(b), the signal-to-noise ratio is given by

(34)

where A is the loaded voltage gain and Yi is the input admittance. The equivalent noise input current Ini is defined as the
current in parallel with the amplifier input that generates
the same noise voltage at the output as all noise sources in
the circuit. Its value is given by the sum of the terms in the
brackets in Eq. (34) with the exception of the Is.
The mean squared value of Ini is solved for as follows:

v2s

Norton Source

(38)

i2s
i2ni

(39)

2
is given by Eq. (35). The SNR is expressed in deciwhere ini
2
bels as 10 log(is2 /ini
). The source admittance that minimizes
2
2
2
ini
can be obtained by setting dini
/dGS  0 and dini
/dBS  0
and solving for GS and BS. The solution for GS is negative.
Because this is not realizable, GS  0 is the realizable solution
2
for the least noise. The source admittance that minimizes ini
is given by

Ysm = Gsm + jBsm



i2
= 0 + ji
n
v2n

(40)

Because minimum noise occurs for GS  0, it can be concluded that a resistor should never be connected in parallel
with a source at an amplifier input if noise performance is a
design criterion. Although the output admittance of a source
is usually fixed, the SNR can be improved by adding a susceptance in parallel with the source that makes the total parallel
susceptance equal to the imaginary part of Ysm. When this is
2
the case, ini
is given by

 
i2ni = 4kTGS  f + v2n G2S + 2r GS v2n i2n + i2n (1 i2 )
 
= 4kTGS  f + v2n (G2S B2sm ) + 2r GS v2n i2n + i2n

(41)

NOISE FACTOR AND NOISE FIGURE

Thevenin Source
The noise factor F of an amplifier is defined as the ratio
of its actual SNR to the SNR if the amplifier were noiseless.
When it is expressed in decibels, it is called the noise figure
and is given by NF  10 log F. It follows from Eq. (30) that
the noise factor for the amplifier model of Fig. 3(a) in which
the source is modeled by a Thevenin equivalent circuit is
given by

F=

v2ni
v2ts

=1+

 

v2n + 2(r RS + i XS ) v2n i2n + i2n (R2S + XS2 )
4kTRS  f
(42)

A noiseless amplifier has the noise factor F  1.

The value of Zs that minimizes F is called the optimum
source impedance and is denoted by Zso. It is obtained by setting dF/dRS  0 and dF/dXS  0 and solving for RS and XS.
The impedance is given by

Zso = Rso + jXso




v2
=
1 i2 ji
n
i2n

(43)

CIRCUIT NOISE

Note that the imaginary part of Zso is equal to the imaginary

part of Zsm that maximizes the signal-to-noise ratio. The corresponding minimum value of the noise factor is given by
 


v2n i2n 
r + 1 i2
(44)
Fo = 1 +
2kT  f
With the relations 1  i2  Rso in2 / vn2 and r  R in2 /
vn2, the minimum noise factor can be written
Fo = 1 +

i2n
[R + Rso ]
2kT  f

(45)

where R is the real part of the correlation impedance Z defined by Eq. (27). Let in2 be expressed in terms of the noise
conductance Gn, so that in2  4kT0Gnf. It follows that Fo can
be written in the alternate form
Fo = 1 + 2Gn

T0
[R + Rso ]
T

Gn
[(RS Rso )2 + (XS Xso )2 ]
Rns

(47)

(48)

Norton Source
For the amplifier model of Fig. 3(b) in which the source is
modeled by a Norton equivalent circuit, F is given by
 
v2n (G2S + B2S ) + 2(r GS i BS ) v2n i2n + i2n
i2ni
(49)
F=
=1+
4kTGS  f
i2
ts

The optimum source admittance Yso that minimizes F is obtained by setting dF/dGS  0 and dF/dBS  0 and solving for
GS and BS. The admittance that is obtained is equal to the
reciprocal of the optimum source impedance and is given by



i2
1
Yso =
= Gso + jBso =
1 i2 + ji
n
(50)
Zso
v2n
When Ys  Yso, F is given by Eq. (44). Note that the imaginary
part of Yso is equal to the imaginary part of Ysm that maximizes the signal-to-noise ratio.
With the relations 1  i2  Gso vn2 / in2 and r 
G vn2 / in2, Eq. (44) can be written
Fo = 1 +

e2n
(G + Gso )
2kT  f

Fo = 1 + 2Rn

T0
(G + Gso )
T

(52)

It is straightforward to show that the noise factor in Eq.

(49) can be expressed as a function of Fo as follows:
F = Fo +

v2n
[(GS Gso )2 + (BS Bso )2 ]
4kTGS  f

(53)

In this expression, let vn2 be expressed in terms of the noise

resistance Rn. Let the source noise be expressed in terms of
its noise conductance Gns, so that TGS  ToGns. It follows that
F can be written
F = Fo +

In this expression, let in2 be expressed in terms of the noise

conductance Gn. Let the source noise be expressed in terms of
its noise resistance Rns, so that TRS  T0Rns. It follows that F
can be written
F = Fo +

where G is the real part of the correlation admittance Y defined by Eq. (28). Let vn2 be expressed in terms of the noise
resistance Rn, so that vn2  4kT0Rnf. It follows that Fo can be
written in the alternative form

(46)

It is straightforward to show that the noise factor in Eq.

(42) can be expressed as a function of Fo as follows:
i2n
[(RS Rso )2 + (XS Xso )2 ]
F = Fo +
4kTRS  f

385

Rn
[(GS Gso )2 + (BS Bso )2 ]
Gns

The noise factor can be a misleading specification. If an

attempt is made to minimize F by adding resistors either in
series or in parallel with the source at the input of an amplifier, the SNR is always decreased. This is referred to as the
noise factor fallacy or the noise figure fallacy. Confusion can
be avoided if low-noise amplifiers are designed to maximize
the SNR. This is accomplished by minimizing the equivalent
noise input voltage referred to the source.

NOISE IN MULTISTAGE AMPLIFIERS

Figure 4 shows the first two stages of a multistage amplifier
having N stages. The input impedance to each stage is modeled by a resistor. Each output circuit is modeled by a Norton
equivalent circuit consisting of a parallel current source and
resistor. The equivalent noise input voltage for each stage is
shown as a series voltage source preceding that stage. For
the jth stage, it is given by vnij  vnj  injRo(j1).
The short-circuit output current from the jth stage can be
written ioj  Gmjvij(oc), where vij(oc) is the open-circuit input
voltage and Gmj is the transconductance gain from the opencircuit input voltage to the short-circuit output current.
This transconductance is given by Gmj  gmjRij /(Ro(j1) 
Rij), where gm is the ratio of the short-circuit output current
to the actual or loaded input voltage. The open-circuit voltage gain of the jth stage is given by GmjRoj. For the overall
circuit, the voltage gain is given by K  Gm1Ro1Gm2Ro2
   GmNRoN RL.
It is straightforward to show that the output voltage is
given by


v + in2 Ro1
vn3 + in3 Ro2
vo = K vs + vn1 + in1 RS + n2
+
Gm1 Ro1
Gm1 Ro1 Gm2 Ro2
+ +

(51)

(54)

vnN + inN Ro(N1)

Gm1 Ro1 Gm2 Ro2 Gm(N1) Ro(N1)

(55)

386

CIRCUIT NOISE

RS

vs

vni1
+

vni2
+

Ri1

i01

R01

+
R01

i01

R01

RL

v0

Figure 4. Model used to calculate the equivalent input

noise voltage of a multistage amplifier.

Amplifier 1

The equivalent noise input voltage vni is given by the sum of

all terms in the brackets in this equation except the vs term.
It is given by

vn2
vn3
+
+
Gm1 Ro1
Gm1 Ro1 Gm2 Ro2
i
in3
+ in1 RS + n2 +
+
Gm1
Gm1 Ro1 Gm2

vni = vn1 +

(56)

It can be seen that the vn noise of any stage following the

first stage is divided by the open-circuit voltage gain of the
first stage. If this gain is sufficiently high, the vn noise of all
stages after the first stage can be neglected. This also minimizes the in noise of all stages after the second stage. The in
noise of the second stage is divided by Gm1. Unless Gm1 is
large, the only way to minimize the in2 term is to use a second
stage that exhibits a low in noise. For a single bipolar transistor, Gm gm  IC /VT, where IC is the collector bias current
and VT is the thermal voltage. For IC  1 mA and VT  25
mV, gm  0.04. For field effect devices, the gm is usually lower.
Therefore, minimization of the in2 noise can be difficult to
achieve by maximizing Gm1.
NOISE REDUCTION WITH PARALLEL DEVICES
A method that can be used to reduce the noise generated in
an amplifier input stage is to realize that stage with several
active devices in parallel, e.g. parallel BJTs or parallel FETs.
Figure 5 shows the diagram of an amplifier input stage having N identical devices in parallel. For simplicity, only the
first two are shown. The noise source Vts models the thermal

Zs

Vs

Vts

Vn1

In1

Amplifier 1

Zi

I01

I0(sc)

Z0

noise generated by the source resistance RS  Re Zs. Each

amplifier stage is modeled by the vn in amplifier noise model
having an input impedance Zi. The output circuit is modeled
by a Norton equivalent circuit consisting of a parallel current
source and impedance. The short-circuit output current from
the jth stage can be written Ioj  gmVij, where gm is the transconductance and Vij is the input voltage for that stage.
The short-circuit output current from the circuit can be
written




N

Vs + Vts 
Zi

Io(sc) = gm N Zs 
+
In j
N
Zs
j=1

N


j=1

Zi
Vn j

Zi
Zi + Zs 
N1

Zi
Zs 
N


N1




Vnk

Zi
k=1
Zi + Zs 
N 1 k= j
(57)

To define the equivalent noise input voltage, the expression

multiplying Vs must be factored from the outer brackets in
this equation. All remaining terms with the exception of the
Vs term then represent Vni. When this is done and the expression for Vni is converted into a mean-square sum, a significant
2
simplification occurs. The final expression for vni
is
v2ni = 4kTRS  f +

 
v2n
+ 2(Re Zs ) v2n i2n + Ni2n |Zs |2
N

(58)

where is the correlation coefficient between Vn and In for

any one of the N identical stages.
2
If Zs  0, Eq. (58) reduces to vni
 vn2 /N. In this case, the
noise can theoretically be reduced to any desired level if N is
2
made large enough. For Zs 0, Eq. (58) predicts that vni

for N 0 or N . Thus there is a value of N that mini2

mizes the noise. It is solved for by setting dvni
/dN  0 and
solving for N. It is given by


2
1

vn
N=
(59)
|Zs | i2n

Amplifier 2

Vn2

This expression shows that N decreases as Zs increases. It

follows that the noise cannot be reduced by paralleling input
devices if the source impedance is too large.

In2

Amplifier 2

Zi

I02

Z0

NOISE REDUCTION WITH AN INPUT TRANSFORMER

Figure 5. Model used to calculate the equivalent input noise voltage

of paralleled amplifier stages.

A transformer at the input of an amplifier may improve its

noise performance. Figure 6(a) shows a signal source connected to an amplifier through a transformer with a turns
ratio 1 : n. Resistors R1 and R2, respectively, represent the

CIRCUIT NOISE

Transformer
Zs

++

Vs

Amplifier

1:n
R1

387

R2
Zi

v0

(a)
n2 (Zs + R1) + R2

nVs

vt1

vn

+
+

Amplifier

in

+
Zi

v0

Figure 6. (a) Model used to calculate the equivalent input

noise voltage of a transformer coupled amplifier. (b) Equivalent circuit.

(b)

primary and the secondary winding resistances. Figure 6(b)

shows the equivalent circuit seen by the amplifier input with
all noise sources shown. The source Vt1 represents the thermal noise generated by the effective source resistance n2
(RS  R1)  R2, where RS  Re Zs. By analogy to Eq. (29), the
amplifier output voltage is given by

Vo =

AZi
n2 (Zs + R1 ) + R2 + Zi

(60)

In this case, the magnitude of the effective source impedance

seen by the amplifier is n2 Zs  vn2 / in2. The transformer
also minimizes the noise factor, but it is not equal to the optimum noise factor Fo unless and Zs are real.
If the source resistance is small, the transformer winding
resistance can be a significant contributor to the thermal
noise at the amplifier input. For this reason, a transformer
can result in a decreased SNR compared to the case without
the transformer.

{nVs + Vt1 + Vn + In [n2 (Zs + R1 ) + R2 ]}

The equivalent noise input voltage referred to the source
is obtained by factoring the turns ratio n from the braces in
Eq. (60) and retaining all terms except the Vs term. The expression obtained can be converted into a mean-square sum
to obtain



v2
R
v2nis = 4kT RS + R1 + 22  f + n2
n
n
 
!  
R
+ 2 Re Zs + R1 + 22
v2n i2n
n

2

R 
+ n2 i2n Zs + R1 + 22 
n

(61)

v2nis

The current in a pn junction diode consists of two componentsthe forward diffusion current IF and the reverse saturation current IS. The total current is given by I  IF  IS.
The forward diffusion current is a function of the diode voltage V and is given by IF  IS exp(V/ VT), where  is the emission coefficient and VT is the thermal voltage. (For discrete
silicon diodes  2, whereas for integrated circuit diodes
 1.) Both IF and IS generate uncorrelated shot noise. The
total mean squared noise is given by
i2n = 2q(IF + IS )  f = 2q(I + 2IS )  f 2qI  f

where is the correlation coefficient between Vn and In.

Because the series resistance of a transformer winding is
proportional to the number of turns in the winding, it follows
that R2 /R1 n. This makes it difficult to determine the value
2
of n which minimizes vnis
. In the case that Zs  R1  R2 /n2,
2
the expression for vnis
is given approximately by
 
v2
4kTRS  f + n2 + 2(Re Zs ) v2n i2n + n2 i2n |Zs |2
n

JUNCTION DIODE NOISE MODEL

(64)

where the approximation holds for a foward biased diode for

which I  IS. Figure 7(a) shows the diode noise model. In Fig.

(62)

in

in

rd vn

This is minimized when n2 is given by



2
1
2

vn
n =
|Zs | i2n

(a)

(63)

(b)

Figure 7. (a) The noise model of a diode. (b) Small-signal model with
the diode replaced with its small-signal resistance.

388

CIRCUIT NOISE

7(b), the diode is replaced by its small-signal resistance rd 

VT /(I  IS) VT /I.
At low frequencies, the diode exhibits flicker noise. When
this is included, the total mean squared noise current is
given by
i2n = 2qI  f +

Kf I  f
f

(66)
(67)

where VT  kT/q is the thermal voltage, IE is the emitter bias

current VCB is the collector-to-base bias voltage, and VA is the
Early voltage. The collector, emitter, and base bias currents
are related by
(68)

where
=

1+

re

ifb

ro

ie
+

vt2

ishc

io

R2
v2

Figure 8. Small-signal T-model of the BJT with all noise sources.

in IC is modeled by ishc. In the band f, these have the mean

squared values
v2t1 = 4kTR1  f,

The principal noise sources in a BJT are thermal noise in the

base spreading resistance, shot noise and flicker noise in the
base bias current, and shot noise in the collector bias current.
Figure 8(a) shows the small-signal T model of the BJT with
the collector node grounded and all noise sources shown. The
short-circuit collector output current is labeled ic(sc). The circuit contains two signal sources: one connects to the base (v1
and R1) and the other to the emitter (v2 and R2). With v2  0,
the circuit models a commonemitter (CE) amplifier. With
v1  0, it models a commonbase (CB) amplifier.
In the figure, rx is the base spreading resistance, is the
emitter-to-collector current gain, re is the intrinsic emitter resistance, and ro is the collector-to-emitter resistance. The latter two are given by

IC = IE = IB

ishb

C ic ( sc )

E
v1

BJT Noise Model

VCB + VA
IC

(65)

NOISE IN BIPOLAR JUNCTION TRANSISTORS

ro =

vt1 +

ie

ib

R1

where it is assumed that I  IS. A plot of in2 versus f for a

constant f exhibits a slope of 10 dB/decade for very low
frequencies and a slope of zero for higher frequencies. The
two terms in Eq. (65) are equal at the frequency where the
noise current is up 3 dB from its high-frequency limit. This
frequency is called the flicker noise corner frequency.
Diodes are often used as noise sources in circuits. Specially
processed zener diodes are fabricated as solid-state noise diodes. The noise mechanism in these is called avalanche noise,
and it is associated with the diode reverse breakdown current.
For a given breakdown current, avalanche noise is much
greater than the shot noise in the same current.

V
re = T
IE

i2shb = 2qIB  f,

v2tx = 4kTrx  f,
i2fb =

K f IB  f
f

v2t2 = 4kTR2  f
(70)

i2shc = 2qIC  f

Equivalent Noise Input Voltage

Looking to the left in Fig. 8 into the branch where the current i b is labeled, the Thevenin equivalent circuit consists of
the voltage v1  vnb in series with the resistance R1  rx,
where vnb is given by
vnb = vt1 + vtx + (ishb + ifb )(R1 + rx )

(72)

Looking down into the branch where the current i e is labeled,

the Thevenin equivalent circuit consists of the voltage v2 
vne in series with the resistor R2, where une is given by
vne = vt2 + (i0 + ishc ishb ifb )R2

(73)

The current i e can be solved for from the loop equation

(v1 + vnb ) (v2 + vne ) =

ie
(R + rx ) + ie (re + R2 )
1+ 1

(74)

to obtain
ie =

(v1 + vnb ) (v2 + vne )

(R1 + rx )/(1 + ) + re + R2

(75)

It follows that the short-circuit collector output current is

given by
ic(sc) = i0 + ishc + ie

(69)

(71)

= i0 + ishc + Gm (v1 + vnb v2 vne )

(76)

where Gm is the effective transconductance given by

The noise sources vt1, vtx, and vt2, respectively, model the thermal noise in R1, rx, and R2. The shot noise and flicker noise,
respectively, in IB are modeled by ishb and by ifb. The shot noise

Gm =

rie + R2

(77)

CIRCUIT NOISE

and rie is the resistance given by

rie =

389

When the BJT is biased at IC(opt), let the equivalent noise

2
input voltage be denoted by vni(min)
. Its given by

R1 + r x
+ re
1+


1+
v2ni(min) = 4kT (R1 + rx + R2 )  f 
1+ 1

(78)

(85)

With these definitions, Eq. (76) can be written


ic(sc) = Gm

i + ishc
v1 v2 + vnb vne + 0
Gm

!
(79)

The collector output resistance is given by

ric =

r0 + rie  R2
1 G m R2

The terms in the parentheses in

the equivalent noise input voltage vni.
that the collector-to-emitter resistance
so that the current io can be neglected.
given by

(80)
Eq. (79) represent
It will be assumed
ro is large enough
It follows that vni is

vni = vt1 + vtx vt2 + (ishb + ifb )(R1 + rx + R2 )



R1 + rx + R2 VT
+
+ ishc

IC

"
v2ni

(81)

This has the mean squared value

v2ni = 4kT (R1 + rx + R2 )  f



K I f
(R1 + rx + R2 )2
+ 2qIB  f + f B
f

2
R1 + rx + R2 VT
+
+ 2qIC  f

IC

For minimum noise, this equation shows that the series resistance in the external base and emitter circuits should be minimized and that the BJT should have a small rx and a high .
2
Although vni(min)
decreases as increases, the sensitivity is
not great for the range of for most BJTs. For example, as
2
decreases by 0.32 dB.
increases from 100 to 1000, vni(min)
Superbeta transistors have a in the range 1000
2
10,000. As increases from 1000 to 10,000, vni(min)
decreases
by only 0.096 dB. It can be concluded that only a slight improvement in noise performance can be expected by using
higher- BJTs when the device is biased at IC(opt).
2
If IC IC(opt), then vni
can be written

(82)

v2ni(min)

0.5(IC /IC(opt) + IC(opt)/IC ) 1

1+

1+ 1+

2
This equation shows that a plot of vni
versus log(IC /IC(opt))
would exhibit even symmetry about the value IC /IC(opt)  1.
2
This means, for example, that vni
is the same for IC  IC(opt) /2
2
as for IC  2IC(opt). In addition, the sensitivity of vni
to changes
in IC decreases as increases. For example, at IC  IC(opt) /2
2
2
and IC  2IC(opt), vni
is greater than vni(min)
by 0.097 dB for 
100, by 0.033 dB for  1000, and by 0.010 dB for 
10,000.

The above analysis shows that the noise performance of the

CE amplifier is the same as that of the CB amplifier. This
assumes that the noise generated by the stages driven from
the collector can be neglected. Let the second stage be modeled by a vn in amplifier noise model having the noise sources
2
vn2 and in2 and the correlation coefficient
2. Let vni
be the new
noise equivalent input voltage. Following Eq. (56), this is
given by

Optimum Bias Current

Except at low frequencies, the flicker noise term in Eq. (82)
2
can be neglected. When this is done, vni
can be written

v2ni = 4kT (R1 + rx + R2 )  f

(83)

2
It can be seen that vni
if IC 0 or if IC . It follows
2
that there is a value of IC that minimizes vni
. This current is
called the optimum collector bias current, and it is denoted
2
by IC(opt). It is obtained by setting dvni
/dIC  0 and solving for
IC. It is given by

IC(opt) =

VT


R1 + r x + R2
1+

(86)

Comparison of CE and CB Stages

This expression gives the mean squared equivalent noise input voltage for both the CE and the CB amplifier. The SNR
2
for either amplifier is given by SNR  vi2 /vni
, where vi2 is the
mean squared value of v1 for the CE amplifier and the mean
squared value of v2 for the CB amplifier.

I
+ 2q C  f (R1 + rx + R2 )2


2
R1 + rx + R2 VT
+
+ 2qIC  f

IC

(84)

v2ni 

v2
= v2ni + 2n22 + 22
Gm ric

 
v2n2 i2n2
G2m ric

i2n2
G2m

(87)

where ric is the collector output resistance of the first stage.

It follows from this equation that the noise contributed by the
second stage is the lowest for the first-stage configuration
that exhibits the largest Gm.
For a CE first stage, let R1  RS and R2  0, where RS is
the source resistance. For a CB first stage, let R1  0 and
R2  RS. The ratio of the Gms for these two configurations is
Gm(CE)
Gm(CB)

rx /(1 + ) + re + RS
(RS + rx )/(1 + ) + re

(88)

RS  0, the ratio is unity. In this case, the noise performance

of the two amplifiers is the same. For RS large, the ratio approaches 1  , so that the effect of the second-stage noise on
the CB amplifier is greater than for the CE amplifier. There-

390

CIRCUIT NOISE

C
rx

vn
+

where vn and in are given by



i
V
vn = vtx + ishb + ifb + shc rx + ishc T

IC

C
vn
+

in

in

in = ishb + ifb +

(a)

(b)

Figure 9. The vnin noise models of the BJT. (a) First model. (b)
Second model.

First Model. There are two formulations for vn2 and in2 for
the BJT, which differ by the placement of rx in the model. For
the first, Eq. (81) can be written
vni = vt1 vt2 + vn + in (R1 + rx + R2 )

(89)

(97)

i2n = 2qIB  f +

2qI
Kf IB
 f + 2C  f
f

(99)

In this case, ishb, ifb, and ishc appear in the expressions for both
vn and in. The correlation coefficient is given by

"
K f IB  f
1
rx
2qIB  f +
=  
f
v2n i2n

!
I
rx VT
+
(100)
+2q C  f

IC
The second form of the vn in BJT noise model is shown in Fig.
9(b). The first form has the simpler equations.

where vn and in are given by

vn = vtx + ishc

VT
IC

in = ishb + ifb +

ishc

(90)
(91)

These expressions can be converted into mean squared sums

to obtain
v2n = 4kTrx  f + 2kT
i2n = 2qIB  f +

ishc

These expressions can be converted into mean squared sums

to obtain


K I f
r2x
v2n = 4kTrx  f + 2qIB  f + f B
f
(98)

2
rx VT
+
+ 2qIC  f

IC

fore, the CE amplifier is the preferred topology for low-noise

applications when the source resistance is not small.
Two BJT vn in Noise Models

(96)

VT
f
IC

2qI
Kf IB
 f + 2C  f
f

(92)
(93)

Flicker Noise Corner Frequency. The expression for in2 in

each form of the BJT vn in noise model is the same. The equations predict that a plot of in2 versus frequency would exhibit
a slope of 10 dB/decade at low frequencies and a slope of
zero at higher frequencies. The flicker noise corner frequency
is the frequency at which in2 is up 3 dB from its higherfrequency value. This is the frequency for which the middle
term in Eqs. (93) and (99) is equal to the sum of the first and
last terms.
CommonCollector Stage. Figure 10 shows the circuit diagram of a commoncollector (CC) amplifer with its output
connected to the input of a second stage that is modeled with
the vn vn amplifer noise model. For simplicity, the bias

Because ishc appears in the expressions for both vn and in, the
correlation coefficient is not zero. It is given by

2kT f
 
v2n i2n

(94)

The first form of the vn in BJT noise model is shown in Fig.

9(a). The asterisk indicates that the base spreading resistance r*x is considered to be a noiseless resistor. Its noise is
included in the expression for vn2.

rx

vt1

vtx
ishc

ishb+ifb

ie

R1
v1

it2

R2

Amplifier

vn2

in2

ii2

vi2

Ri2

vo = Avi2

Second Model. For the second formulation, Eq. (81) can be

written
vni = vt1 vt2 + vn + in (R1 + R2 )

(95)

Figure 10. Circuit for calculating the equivalent noise input voltage
of an amplifier preceded by a BJT commoncollector stage.

CIRCUIT NOISE

sources are not shown. The resistor rx and all BJT noise
sources are shown external to the BJT. The source it2 models
the thermal noise current in R2. The voltage across Ri2 is proportional to the short-circuit current through Ri2, that is, the
current ii2 evaluated with Ri2  0. It is given by

ii2(sc) = ie (ishb + ifb ) + ishc + it2 +

=

Q2

Rs

Gm
[v + vt1 + vtx + (ishb + ifb )(R1 + rx ) + vn2] (101)
1
v
(ishb + ifb ) + ishc + it2 + n2 + in2
R2

This can be converted into a mean squared sum to obtain


2
R1 + r x
= 4kT (R1 + rx ) f +
1+
R
 2

  
+
r
R
R + rx
x
1
+ re
1+ 1
+ 22 v2n2 i2n2
1+
R2


Kf IB  f
[(R1 + rx ) re ]2
+ 2qIB  f +
f


2
4kT f
R1 + r x
+ re
+ 2qIC  f +
+ i2n2
R2
1+

ic2(sc)
Q1

vn2
+ in2
R2

where Gm is given by Eq. (77) with R2  0. It follows that the

equivalent noise input voltage is given by



vni = vt1 + vtx + vn2 1 +

G m R2



+
(i + it2 + in2 )
+ (ishb + ifb ) R1 + rx
Gm
Gm shc
(102)

v2ni

ic1(sc)

v2n2

(103)

where
2 is the correlation coefficient between vn2 and in2.
It can be seen from Eq. (103) that the vn2 noise is increased
by the CC stage. The in2 noise is decreased if R1  rx / 
re /. The noise voltage generated by the base shot and flicker
noise currents can be canceled if re  (R1  rx). For R2 
2VT /IC, the thermal noise generated by R2 can be neglected
compared to the shot noise in IC.
BJT Differential Amplifier
Figure 11 shows the circuit diagram of a BJT differential amplifier. For simplicity, the bias sources are not shown. It is
assumed that the BJTs are matched and biased at equal currents. The emitter resistors labeled R2 are included for completeness. For lowest noise, these should be omitted. The
source int models the noise current generated by the tail current source, and the resistor rt models its output resistance.
For minimum noise output from the differential amplifier,
the output signal must be proportional to the differential
short-circuit output current iod(sc)  ic1(sc)  ic2(sc). The subtraction cancels the common-mode output noise generated by the
tail current int. Although a current-mirror active load can be
used to realize the subtraction, the lowest-noise performance
is obtained with a resistive load. With a resistive load on each
collector, a second differential amplifier is required to subtract the output signals. The analysis presented here assumes
that the circuit output is taken differentially. In addition, it
is assumed that rt is large enough so that it can be approxi-

vs1

391

Rs
R2

R2
va

vs2

rt

int

Figure 11. Circuit for calculating the equivalent noise input voltage
of a BJT differential amplifier.

mated by an open circuit. This is equivalent to the assumption of a high common-mode rejection ratio.
The simplest method to calculate the equivalent noise input voltage of the differential amplifier is to exploit symmetry
by resolving all sources into their differential and commonmode components. The common-mode components are all canceled when the output is taken differentially. Therefore, only
the differential components are required. When the sources
are replaced by their differential components, the node labeled va in Fig. 11 can be grounded. This decouples the differential amplifier into two CE stages.
Consider the effect of the base shot noise currents. For Q1,
ishb1 is replaced with i shb1  (ishb1 ishb2)/2. For Q2, ishb2 is replaced
by i shb2  (ishb2  ishb1)/2. The differential short-circuit collector
output current iod(sc)  ic1(sc)  ic2(sc) is proportional to i shb1  i shb2 
ishb1  ishb2. If ishb1 and ishb2 are not correlated, it follows that
2
2
2
iod(sc)
contains a term that is proportional to ishb1
 ishb2
. Be2
2
cause ishb1
 ishb2
, the base current shot noise is increased by
3 dB over that in a CE amplifier. Likewise, the thermal noise
of the base spreading resistance, the thermal noise of R1 and
R2, the base current flicker noise, and the collector current
shot noise are increased by 3 dB over those of a CE amplifier.
The mean squared noise input voltage of the differential am2
2
, where vni
is given by Eq. (82). Above
plifier is given by 2vni
the flicker noise frequency band, the noise is minimized when
each BJT is biased at a collector current given by Eq. (84).
BJT at High Frequencies
Figure 12 shows the high-frequency T model of the BJT with
the emitter grounded and the base driven by a voltage source
having the output impedance Zs  RS  jXS. The base-to-emitter capacitance and the collector-to-base capacitance are
given by
c =
c =

F IC
VT

(104)
cjc0

(1 + VCB / C )m c

(105)

where F is the forward transit time of the base-to-emitter

junction, cjco is the zero-bias junction capacitance of the base-

392

CIRCUIT NOISE

B
Vts

rx

Vtx

The noise factor is given by

Ie

Ib

C Ic (sc)

Ishb

re

Zs

ro

Ie

+
Vs

F=

v2ni

(109)

4kTRS  f

If it is assumed that c  c and that 2c2 re2  2, the

2
values of XS and IC can be solved for to minimize vni
. These
2
2
are obtained by setting dvni /dXS  0 and dvni /dIC  0 and
solving the equations simultaneously. It is straightforward to
show that XS and IC are given by

Ishc

Io

XS = F (RS + rx ) 
1+

Figure 12. Small-signal T-model of the commonemitter amplifier

used to calculate the equivalent noise input voltage at high frequencies.

IC =
to-collector junction, C is the built-in potential, and mc is the
junction exponential factor. All noise sources are shown in
the circuit except the base flicker noise current, which can be
neglected at high frequencies.
If the current I0 through r0 is neglected, it is straightforward to show that the short-circuit collector output current is
given by

!
I
(106)
Ic(sc) = Gm Vs + Vts + Vtx + Ishb (Zs + rx ) + shc
Gm

(110)

VT

(RS + rx )(1 + 2 F2 )
1+

(111)

2
The corresponding expressions for vni
(min) and F are


1+

= 4kT (RS + rx ) f 
1+ 1
 

1+
rx
F = 1+

RS
1+ 1

v2ni(min)

(112)

(113)

where Gm is given by

Gm = 

+ jc re

1
+ jre cT (Zs + rx ) + re
1+

NOISE IN FEEDBACK AMPLIFIERS

(107)

SeriesShunt Amplifier

and cT  c  c. The equivalent noise input voltage is given

by the sum of the terms in the brackets in Eq. (106) with the
Vs term omitted. It has a mean squared value given by

v2ni = 4kT (RS + rx ) f + 2qIB  f [(RS + rx )2 + XS2 ]

"
2
RS + r x
2qIC  f
+ 2
+
r
(1

X
c
)
e
T
S
+ 2 c2 r2e
1+

2 
XS
+ re cT (RS + rx )
+
1+

(108)

Figure 13(a) shows the simplified diagram of a seriesshunt

feedback amplifier with a BJT input stage. The bias sources
and networks are omitted for simplicity. If the loop gain is
sufficiently high, the voltage gain is approximately the reciprocal of the feedback ratio and is given by vo /vs 1  RF /RE.
The circuit in Fig. 13(b) can be used to solve for the equivalent noise input voltage. The figure shows the BJT with its
collector connected to signal ground and the circuit seen looking out of the emitter replaced by a Thevenin equivalent circuit with respect to vo. The equivalent noise input voltage is
modeled by the source vni. If flicker noise is neglected, the

ic (sc)
vo

RS

RS
vs

RF

vs

vni
+

RE RF

RE
+

Figure 13. (a) Seriesshunt feedback

amplifier with a BJT input stage. (b)
Equivalent circuit of the input stage used
to calculate the equivalent noise input
voltage.

(a)
(b)

vo

RE
RE + RF

CIRCUIT NOISE

393

ic (sc)

RF
vni
+

vo
is
is

RS RF

vo
RF

R2

RS
R2
(b)
(a)
Figure 14. (a) Shuntshunt feedback amplifier with a BJT input stage. (b) Equivalent circuit
of the input stage used to calculate the equivalent noise input voltage.

2
value of vni
is obtained from Eq. (83) with R2 replaced with
RE RF. It is given by

v2ni = 4kT (R1 + rx + RE RF )  f

IC
 f (R1 + rx + RE RF )2

2

R1 + rx + RE RF VT
+
+ 2qIC  f

IC
+ 2q

(114)

For minimum noise, RERF should be small compared to R1 

rx and the BJT should be biased at IC(opt). The resistance
RERF cannot be zero, because the amplifier gain is set by the
ratio of RF to RE.

2
flicker noise is neglected, vni
is given by Eq. (83) with R1 re2
placed with RSRF). It follows that ini
is given by


r x + R2
4kT  f
1+
i2ni =
RS RF
RS RF
2

r x + R2
+ 2qIB  f 1 +
(116)
RS RF

!2

1
rx + R2 VT
1
+
+
+ 2qIC  f

RS RF

IC

The noise is minimized by making R2 small and by making

RF large compared to RS. In addition, the BJT should be
biased at IC(opt).
NOISE IN FIELD EFFECT TRANSISTORS

ShuntShunt Amplifier
Figure 14(a) shows the simplified diagram of a shuntshunt
feedback amplifier with a BJT input stage. The bias sources
and networks are omitted for simplicity. The signal source is
represented by the current source is in parallel with the resistor RS. If the loop gain is sufficiently high, the transresistance
gain is given by vo /is RF.
The circuit in Fig. 14(b) can be used to evaluate the input
stage noise. The figure shows the BJT with its collector connected to signal around and the circuit seen looking out of the
base replaced by a Norton equivalent circuit with respect to
is and vo. The equivalent noise input voltage is modeled by the
source vni. The short-circuit collector current ic(sc). is given by


R R
ic(sc) = Gm is (Rs RF ) + v0 S F + vni
RF

(115)

where Gm is given by Eq. (77) with R1 replaced with RSRF.

Because the signal source is a current as opposed to a voltage, the noise-equivalent input current ini in parallel with is
must be calculated. This is obtained by factoring the coefficient of is from Eq. (115) and retaining only the term involving vni. It follows that ini is given by ini  vni /(RSRF). When

General Noise Model

The principal noise sources in the FET are thermal noise and
flicker noise generated in the channel. If the gate bias current
in the junction FET (JFET) is not negligible, the shot noise
generated by it must also be included. Flicker noise in a MOSFET is usually larger than in a JFET because the MOSFET
is a surface device in which the fluctuating occupancy of traps
in the oxide modulate the conducting surface channel all
along the channel. The relations between the flicker noise in
a MOSFET and its geometry and bias conditions depend on
the fabrication process. In most cases, the flicker noise, when
referred to the input, is independent of the bias voltage and
current and is inversely proportional to the product of the
active gate area and the gate oxide capacitance per unit area.
Because the JFET has less flicker noise, it is usually preferred over the MOSFET in low-noise applications at low frequencies.
Figure 15 shows the MOSFET small-signal T model with
the drain node grounded and all noise sources shown. The
bulk lead is shown connected to signal ground. A simple modification to the noise equations for this connection can be made
to obtain the equations for the case where the bulk is connected to the source. The equations so obtained also apply to

394

CIRCUIT NOISE
id
is1
R1

vt1
+

v1

D id (sc)

is2
B

G
ig ig = 0

1
gm

ishg

is1

gmb
is2

is

v2t1 = 4kTR1  f,
rds

ifd

itd

i2td
i0

vt2 +

R2

v2

Figure 15. Small-signal T-model of the FET with all noise sources.

the JFET. The small-signal transconductances and drain-tosource resistance are given by


gm = 2 K(1 + VDS )ID 2 KID
(117)
gmb = gm
rds =

(119)

where K is the transconductance parameter,  is the channel

length modulation factor, VDS is the drain-to-source bias voltage, and ID is the drain bias current. For the JFET, the transconductance parameter is given by K  IDSS /VP2 , where IDSS is
the drain-to-source saturation current and VP is the pinchoff
voltage. For the MOSFET, K is given by K  0CoxW/2L,
where 0 is the average carrier mobility in the channel, Cox is
the gate oxide capacitance per unit area, W is the effective
channel width, and L is the effective channel length.
The parameter  is referred to here as the transconductance ratio. It is the ratio of the bulk transconductance gmb to
the transconductance gm and is given by

= 
2 + VSB

(121)

i2shg = 2qIG  f

(122)

i2fd =

Kf ID  f
f L2Cox

for the MOSFET

(123)

i2fd =

Kf ID  f
f

for the JFET

(124)

2
It follows from the equation for itd
that the mean squared
thermal noise current generated in the channel is the same
as the thermal noise current generated by a resistor of value
1.5/gm.
Looking to the left in Fig. 15 into the branch where the
current i g is labeled, the Thevenin equivalent circuit consists
of the voltage v1  vng in series with the resistance R1, where
vng is given by

vng = vt1 + ishgR1

(118)

VDS + 1/
ID

gm
 f,
= 4kT
1.5

v2t2 = 4kTR2  f

The source ifd represents flicker noise generated in the drain.

Its mean squared values are

is

channel and the shot noise generated in the gate bias current.
The latter is zero for the MOSFET. The mean squared values
of these sources are

(120)

where is the body threshold parameter,  is the surface

potential, and VSB is the source-to-body bias voltage. Any
equation derived from the circuit of Fig. 15 can be converted
into a corresponding equation for the case where the body is
connected to the source simply by setting   0 in the equation. The T model for the JFET is the same as the T model
for the MOSFET with   0.
In Fig. 15, the short-circuit drain output current is labeled
id(sc). There are two signal sources in the circuit: one connects
to the gate (v1 and R1) and the other to the source (v2 and
R2). With v2  0, the circuit models a commonsource (CS)
amplifier. With v1  0, it models a commongate (CG) amplifier. The sources vt1 and vt2, respectively, represent the thermal noise generated by R1 and R2. The sources itd and ishg,
respectively, represent the thermal noise generated in the

(125)

Looking up into the branch where the current i s is labeled,

the Thevenin equivalent circuit has the open-circuit voltage
and output resistance
vis =

v1 + vng
1+

(126)

ris =

1
(1 + )gm

(127)

Looking down into the branch where the current i s is labeled,

the Thevenin equivalent circuit consists of the voltage v2 
vns in series with the resistor R2, where vns is given by
vns = vt2 + (itd + ifd + i0 ishg )R2

(128)

It follows that
id = is =

vis (v2 + vns )

ris + R2

(129)

The short-circuit drain current is given by

id(sc) = itd + ifd + i0 + id

vis (v2 + vns )
r + R2
is

v1 + vng
v2 vns
= itd + ifd + i0 + Gm
1+
= itd + ifd + i0 +

(130)

where Gm is the effective transconductance given by

Gm =

1
ris + R2

(131)

CIRCUIT NOISE

Equivalent Noise Input Voltage in

a Junction Field Effect Transistor

The drain output resistance is given by

rid =

rds + ris R2

1 G m R2

(132)

Equivalent Noise Input Voltage in a

MetalOxideSemiconductor Field Effect Transistor
Unless   0, the equivalent noise input voltage for the MOSFET is not the same if it is reflected to the gate as it is if it
is reflected to the source. If it is reflected to the gate, it is
obtained from Eq. (130) by factoring out Gm /(1  ), setting
ishg  0, and retaining all remaining terms except v1  v2. It
will be assumed that the drain-to-source resistance rds is large
enough so that the current i0 can be neglected. It follows that
vni is given by
vni = vt1 vt2 (1 + ) +

itd + ifd
gm

(133)

This has the mean squared value

Kf
4kT
v2ni = 4kT[R1 + R2 (1 + )2 ]  f + 
f +
f
4K f L2Cox
3 KID
(134)
where   0 for the case where the bulk is connected to the
source.
For minimum noise in the MOSFET, it can be concluded
from Eq. (134) that the series resistance in the external gate
and source circuits should be minimized and the MOSFET
should have a high transconductance parameter K and a low
2
flicker noise coefficient Kf . The component of vni
due to the
channel thermal noise is proportional to 1/ ID. This decreases by 1.5 dB each time ID is doubled.
vn in Noise Model for a MetalOxideSemiconductor
Field Effect Transistor
For the MOSFET vn in noise model, the mean squared values
of vn and in are given by
Kf
4kT
v2n = 
f +
f
4K
f
L2Cox
3 KID

(135)

i2n = 0

(136)

Figure 16(a) shows the MOSFET model.

vn

vn

in

(a)

395

(b)

Figure 16. The vnin noise models of the FET: (a) MOSFET model.
(b) JFET model.

The equivalent noise input voltage for the JFET is obtained

from Eq. (130), setting   0, factoring out Gm, and retaining
all terms except v1  v2. It will be assumed that the drain-tosource resistance rds is large enough so that the current i0 can
2
be neglected. It follows that vni
is given by

Kf
4kT
f
v2ni = 4kT (R1 + R2 )  f + 2qIG  f + 
f +
4K f
3 KID
(137)
where IG is the gate bias current. This current is commonly
assumed to be zero when the gate-to-channel junction is reverse biased. For a high source impedance, the effect of the
gate current on the noise might not be negligible. In particular, attention must be paid to the variation of the gate current
with drain-to-gate voltage. In general, the gate current increases with drain-to-gate voltage. Some devices exhibit a
threshold effect such that the gate current increases rapidly
when the drain-to-gate voltage exceeds some value. The
drain-to-gate voltage at which this occurs is called the IG
breakpoint. It is typically in the range of 8 V to 40 V. The
JFET noise is minimized in the same way that the MOSFET
noise is reduced.
vn in Noise Model for a Junction Field Effect Transistor
For the JFET vn in noise model, the mean squared values of
vn and in are given by
Kf
4kT
f
v2n = 
f +
4K f
3 KID

(138)

i2n = 2qIG  f

(139)

It is common to assume that ishg is independent of both itd and

ifd. Thus the correlation coefficient between vn and in is zero.
Figure 16(b) shows the vn in JFET model.
Flicker Noise Corner Frequency
It can be seen from Eq. (135) for the MOSFET and Eq. (138)
for the JFET that a plot of vn2 versus frequency would exhibit a slope of 10 dB/decade at low frequencies and a slope
of zero at higher frequencies. The flicker noise corner frequency f f is defined as the frequency at which vn2 is up to 3
dB from its higher-frequency value. For the MOSFET, this is
the frequency for which the two terms in Eq. (135) are equal.
For the JFET, it is the frequency for which the two terms in
Eq. (138) are equal.
Field-Effect-Transistor Differential Amplifier
It has been shown in a preceding section that the BJT noise
is 3 dB higher in the differential amplifier than in the CE
amplifier. The same comparison holds between the FET differential amplifier and the CS amplifier. This assumes that
the signal output from the differential amplifier is taken differentially. Otherwise, the common-mode noise generated by
the tail current bias supply is not canceled.

396

CIRCUIT NOISE

M2
+

vn2
vn1
+

vs

M2

vn2
io

io

vn1

vo

M1

M1

vs

vo

V
(a)

(b)
V

2ID
+

vn2

M2
io

vs

vo

vn3

M3

vn1

M1

vn1
+

vs

Figure 17. MOSFET circuits for example

noise calculations.

vn4

vn2

M4

V
(c)

vo

M2

(d)

Examples of Low-Frequency Noise in

MetalOxideSemiconductor Field Effect Transistors
The equivalent noise input voltage at low frequencies is determined in this subsection for four example MOSFET circuits.
It is assumed that the frequency is low enough so that the
dominant component of the noise is flicker noise. It is
straightforward to modify the results for the higher-frequency
case where the dominant component of the noise is thermal
noise or for the more general case where both thermal noise
and flicker noise are included. The circuits are shown in Fig.
17. The analysis assumes that each transistor is operated in
the saturation region and that the noise sources are uncorrelated. Because the MOSFET exhibits no current noise, the
output resistance of the signal source is omitted with no loss
in generality.
CommonSource Amplifier with Enhancement-Mode Load.
Figure 17(a) shows a single-channel NMOS enhancementmode commonsource (CS) amplifier with an active NMOS
enhancement-mode load. It is assumed that the two MOSFETs have matched model parameters and are biased at the
same current. With v0  0, the short-circuit output current
can be written
io(sc) = gm1 (vs + vn1 ) gm2 vn2

io

M1

(140)

The equivalent noise input voltage is obtained by factoring

gm1 from the expression and retaining all terms except the vs
term. It has the mean squared value

v2ni

v2n1

gm2
gm1

2
v2n2

(141)

When the low-frequency approximation is used for vn2 in Eq.

2
(135), the expression for vni
reduces to

v2ni

Kf  f
=
2 W L f
2nCox
1 1

"
1+

L1
L2

2 
(142)

The value of L1 that minimizes this is L1  L2. The noise can

be reduced further by increasing W1 and L2. The noise is independent of W2.
CommonSource Amplifier with Depletion-Mode Load. Figure 17(b) shows a single-channel NMOS enhancement-mode
CS amplifier with an active NMOS depletion-mode load. It is
assumed that the two MOSFETs are biased at the same current. With vo  0, the expression for io(sc) is the same as for
the circuit of Fig. 17(a). Therefore, the expression for vni is the
same. However, the two MOSFETs cannot be assumed to

CIRCUIT NOISE

have the same flicker noise coefficient. The low-frequency ex2

pression for vni
is

v2ni =

Kf1  f
2 W L f
2nCox
1 1

"
1+

Kf2
Kf1

L1
L2

2 
(143)

The value of L1 that minimizes this is L1  L2Kf1 /Kf2. The

noise can be reduced further by increasing W1 and L2. The
noise is independent of W2.
Complementary MetalOxideSemiconductor Amplifier.
Figure 17(c) shows a pushpull complementary MOSFET
(CMOS) amplifier. It is assumed that the two MOSFETs are
biased at the same current. With vo  0, the short-circuit output current is given by
io(sc) = gm1 (vs + vn1 ) + gm2 (vs + vn2 )

(144)

The equivalent noise input voltage is obtained by factoring

gm1  gm2 from the equation and retaining all terms except
the vs term. It has the mean squared value

v2ni =

g2m1 v2n1 + g2m2 v2n2

(gm1 + gm2 )2

(145)

In order for the quiescent output voltage to be midway between the rail voltages, the circuit is commonly designed
with gm1  gm2. When this is true and the low-frequency ap2
proximation is used for vn2 in Eq. (135), vni
can be written
v2ni =

1
2

Kf1  f
Kf2  f
+
2 W L f
2
2nCox
2
pCoxW2 L2 f
1 1


(146)

The noise can be decreased by increasing the size of both

transistors. For gm1 gm2, a technique for further reducing
2
vni
is to increase L for the MOSFET for which Kf /o is the
largest.
Differential Amplifier with Active Load
Figure 17(d) shows a differential amplifier with a currentmirror active load. It is assumed that M1 and M3 have
matched model parameters and similarly for M2 and M4. In
addition, it is assumed that all four transistors are biased at
the same current so that gm1  gm3 and gm2  gm4. Because the
noise generated by the tail source is a common-mode signal,
it is canceled at the output by the current-mirror load and is
not modeled in the circuit. The differential input voltage is
given by vid  vs  vn1  vn3. The component of the shortcircuit output current due to vid is io(sc)  gm1vid. To solve for
the component of io(sc) due to vn2 and vn4, the sources vs, vn1,
and vn3 are set to zero. This forces M4 to have zero drain signal
current. Thus the gate of M4 is a signal ground and io(sc) 
gm2(vn2  vn4). The total short-circuit output current is
given by
io(sc) = gm1 (vs + vn1 vn3 ) + gm2 (vn2 vn4 )

(147)

397

The equivalent noise input voltage is obtained by factoring

gm1 from this equation and retaining all terms except the vs
term. The mean squared value is

v2ni = v2n1 + v2n3 +

gm2
gm1

2
(v2n2 + v2n4 )

(148)

When the low-frequency approximation is used for vn2 in Eq.

2
(135), vni
can be written
"
 2 
Kf2 L1
Kf1  f
(149)
1
+
v2ni =
2 W L f
pCox
Kf1 L2
1 1
The noise can be reduced by increasing W1 and L2 and by making L1  L2Kf1 /Kf2. The expression is independent of W2.
COMPARISON OF THE BIPOLAR JUNCTION TRANSISTOR
AND THE FIELD EFFECT TRANSISTOR
An exact comparison of the BJT and the FET is impossible,
in general, because the noise performance of each is so dependent on device parameters and bias currents. The FET exhibits only vn noise, whereas the BJT exhibits both vn and in
noise. For a low source resistance, the BJTs vn noise is its
dominant noise. In this case, the BJT usually has lower noise
than the FET. For a high source resistance, the BJTs in noise
can cause it to exhibit more noise than the FET. This assumes
that the BJT bias current remains fixed as the source resistance is increased. If the BJT is biased for minimum noise,
the collector bias current must be decreased as the source resistance is increased. In this case, the FET may not be the
better choice device for the lowest noise. However, a very
small bias current is a disadvantage when the amplifier slew
rate, for example an op amp, is a design consideration. For
this reason, the FET may be preferable when the source resistance is high and a low bias current is a disadvantage.
The above considerations neglect flicker noise effects.
Flicker noise is so device-dependent that it is difficult to reach
general conclusions. However, the FET usually exhibits more
flicker noise at low frequencies than the BJT. In a JFET not
selected for low flicker noise, the flicker noise corner frequency can be as high as several kilohertz. In MOSFETs, it
can be even higher.
OPERATIONAL AMPLIFIER NOISE
Op amp noise models are variations of the vn in amplifier
noise model. The general noise model puts a noise voltage
source and a noise current source at each input to the op amp.
Thus four noise sources are required. In general, the sources
are correlated. However, the correlation between the two
sources on one input and the two sources on the other input
would be expected to be weak and might be neglected. The
general noise model is given in Fig. 18(a).
Because the op amp responds only to the differential input
voltage, the two noise voltage sources in the general model
can be replaced by a single noise voltage source in either op
amp input lead. Figure 18(b) shows the modified model,
where the source is input in the noninverting input lead and
vn  vn1  vn2. In general, vn in this circuit is correlated to
both in1 and in2.

398

CIRCUIT STABILITY

in1

vn1

Figure 18. Noise models of the op amp.

vn2

in1

vn
+

in

in2

in2

(a)

An even simpler noise model can be obtained if the two

noise current sources are replaced by a single differential
noise current source as shown in Fig. 18(c). This model is not
as accurate as the other two. In making calculations that use
specified noise data on op amps, it is important to use the
noise model for which the data apply.

vn

(b)

(c)

CIRCUIT OSCILLATORS. See HARMONIC OSCILLATORS,

CIRCUITS.

CIRCUITS, ANALOG PROCESSING. See ANALOG PROCESSING CIRCUITS.

CIRCUITS, ASYNCHRONOUS. See ASYNCHRONOUS

LOGIC DESIGN.

CIRCUITS, BOOTSTRAP. See BOOTSTRAP CIRCUITS.

CIRCUITS, CONPARATORS. See COMPARATOR CIR-

BIBLIOGRAPHY
W. R. Bennett, Methods of solving noise problems, Proc. IRE, 44: 609
638, 1956.
J. R. Pierce, Physical sources of noise, Proc. IRE, 44: 601608, 1956.
H. Rothe and W. Dahlke, Theory of noisy fourpoles, Proc. IRE, 44:
811818, 1956.
H. A. Haus, Representation of noise in linear twoports, Proc. IRE, 48:
6974, 1960.
H. Fukui, The noise performance of microwave transistors, IEEE
Trans. Electron Devices, ED-13: 329341, 1966.
A. van der Ziel, Noise: Sources, Characterization, Measurement, Englewood Cliffs, NJ: Prentice-Hall, 1970.
A. Van der Ziel, Noise in solid-state devices and lasers, Proc. IEEE,
58: 11781206, 1970.
C. A. Liechti, Microwave field-effect transistors1976, IEEE Trans.
Microw. Theory Tech., MTT-24: 279300, 1976.
M. S. Gupta (ed.), Electrical Noise: Fundamentals & Sources, New
York: IEEE Press, 1977.
J. C. Bertails, Low frequency noise considerations for MOS amplifier
design, IEEE J. Solid-State Circuits, SC-14: 773776, 1979.
H. Fukui, Low-Noise Microwave Transistors & Amplifiers, New York:
IEEE Press, 1981.
Y. Netzer, The design of low-noise amplifiers, Proc. IEEE, 69: 1981.
P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., New York:
Cambridge Univ. Press, 1989.
H. W. Ott, Noise Reduction Techniques in Electronic Systems, 2nd ed.,
New York: Wiley, 1988.
M. Steyaert, Z. Y. Chang, and W. Sansen, Low-noise monolithic amplifier design: bipolar versus CMOS, Analog Integrated Circuits
Signal Process., 1: 919, 1991.
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, New York: Wiley, 1993.
C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System
Design, New York: Wiley, 1993.
W. M. Leach, Jr., Fundamentals of low-noise analog circuit design,
Proc. IEEE, 82: 15151538, 1994.

W. MARSHALL LEACH, JR.

Georgia Institute of Technology

CUITS.

CIRCUITS, COUNTERS. See COUNTING CIRCUITS.

CIRCUITS, DELAY. See DELAY CIRCUITS.
CIRCUITS, DIFFERENTIAL. See DIFFERENTIAL AMPLIFIERS.

CIRCUITS, DIFFERENTIATING. See DIFFERENTIATING

CIRCUITS.

CIRCUITS, HYSTERESIS IN. See HYSTERESIS IN CIRCUITS.

CIRCUITS,
CIRCUITS,
CIRCUITS,
CIRCUITS,

MAGNETIC. See MAGNETIC CIRCUITS.

MIXER. See MIXER CIRCUITS.
NAND. See NAND CIRCUITS.
NONLINEAR. See NONLINEAR CIRCUIT SYN-

THESIS USING INTEGRATED CIRCUITS.

CIRCUITS, NONLINEAR DYNAMIC PHENOMENA. See NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS.

CIRCUITS, NOR. See NOR CIRCUITS.
CIRCUITS, PERIODIC NONLINEAR. See PERIODIC
NONLINEAR CIRCUITS.

CIRCUITS, SAMPLE AND HOLD. See SAMPLE AND

HOLD CIRCUITS.

CIRCUITS, SUMMING. See SUMMING CIRCUITS.

422

LINEAR NETWORK ELEMENTS

LINEAR NETWORK ELEMENTS

Within the limits of circuit model approximation the operating conditions for each component of an electrical network
are identified univocally by the currents and the voltages at
their terminals. The voltages and currents of each component
are linked by relations that depend only on their physical constitution. Such relations are not, however, capable of determining the actual operating conditions of the individual
componentsthat is, the values the voltages and currents assume when a component is put in a given circuit. This indetermination disappears if one takes into account the fact that,
again within the circuit model approximation, each component of the electrical network interacts with the other components through the currents and the voltages at their terminals. More precisely, one may say that the operating
conditions of each component, and thus of the whole circuit,
are the result of two distinct requirements: that the component should behave in a manner compatible with the nature
of the other components of the network, as they are connected, and that its behavior, in turn, should be compatible
with its specific nature.
While the interaction of the single component with the rest
of the circuit is regulated by Kirchhoff s laws and is dealt
with in TIME-DOMAIN CIRCUIT ANALYSIS and NETWORK EQUATIONS, the specific nature of each single component is manifested through particular relations imposed between the voltages and the currents at their terminals. These are the
constitutive relations and are the subject of this article.
This distinction, which is fully justified at the conceptual
level and is also used in practice, cannot, of course, be interpreted in an absolute manner. One cannot speak of electrical
networks without referring to the nature of their components,
just as one cannot deal with circuit components without considering that they are inserted in a network. Thus a certain
overlapping of topics in this article and the others mentioned
is inevitable. What is substantially different in them is the
viewpoint from which these topics are considered.
As long as there is more than one, there can be any number of terminals in a circuit component. For the sake of simplicity, we will begin by speaking of components with only
two terminals, also called one-ports. The one-port operation
is characterized by a single current and a single voltage, and

its constitutive relation expresses the link between them. The

extension to components with more than two terminals does
not raise any question of principle.
Even if the definitions of voltage and current for one-ports
are deemed to be known by the reader of this article, it is
useful to recall them briefly so as to be clear as to the limits
within which they can be introduced. The limits are in fact
those of the validity of the circuit model. When one speaks
of electric currents in the theory of circuits, one is, in effect,
committing a venial linguistic sin. One should more rightly
use the term intensity of electric current. To be clear, let us
suppose that within a region of space there are carriers of
electric charges with assigned number of charge particles per
unit volume N (numerical density) and velocities for each type
of particle. For simplicitys sake, let us assume that each carrier has the same charge q, the numerical density N is uniform, and all the charges have the same average velocity u.
Now let us consider a plane surface S0 and ask ourselves what
amount of charge Q flows through it in a given direction
during the time interval t. One may easily recognize that
Q is equal to the amount of charge in the volume enclosed
by the oblique cylinder with base S0 and height utcos (see
Fig. 1), that is,
Q = (qNu) tS0 cos

(1)

where is the angle that the direction of motion of the

charges forms with the normal n to the surface S0, oriented
in one of the two possible directions, and u is the module of
the velocity u. The amount of charge passing through the surface per unit time, which is known as the electric current intensity, is thus equal to
i = Q/ t = (qNu)S0 cos

(2)

In the SI system the unit of the electric charge is the coulomb

(C) and that of electric current intensity is the ampere (A): 1
C
1 A  1 s.
Introducing the current density vector field J
qNu,
which describes the motion of the charges and the vector
S0
S0n
, where n
is the unit vector of the normal n, we may
write i
J  S0 (with the dot we indicate the scalar product).
Thus the intensity of the electric current appears as the flux
of the current density vector field through a given surface in
a given direction. This definition can be easily extended to the

u
S0

ut
ut cos

Figure 1. The particles flowing through S0 during the time t are

all those contained in the oblique cylinder of height utcos and base
S0.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

LINEAR NETWORK ELEMENTS

ia
Terminal a

Limiting
surface l

423

Analogous considerations can be developed for the voltage

between the two terminals of the component. In this case too,
it is necessary to choose a direction, from a to b, for example,
and a particular path along which to integrate the tangent
component of electric field E. By definition, the voltage v is
the line integral of E along a path (Fig. 2), going from terminal a to terminal b lying outside the limiting surface of the
component,


v = E dll
(4)

Terminal b

ib

Figure 2. A one-port may be schematized as a box enclosed by the

limiting surface l interacting with the rest of the circuit only through
the two terminals a and b.

case where all the variables change in the time, the numerical
density is not uniform, the average velocity is not the same
for all the carriers, which themselves may not carry the same
amount of charge, and the surface S may be of any kind. In
general we have the expression



S
iS (t) =
J dS
(3)
S

and hence the electric current intensity iS(t) flowing through

a given surface S in an assigned directionor more simply
the electric currentis the flux, instant by instant, of the current density field J through the surface S according to the
preselected direction.
In the light of these considerations, the fact that the operation of a circuit component with two terminals may be characterized by a single electric current requires a more precise
explanation. We can consider a generic component with two
terminals as a box enclosed by a limiting surface l. The component can interact with the outside only through two perfectly conducting regions of l that we will suppose to be tiny
and call terminals (see Fig. 2). The rest of the limiting surface
consists of a perfectly insulating material. Therefore it is always possible to define at least two current intensities involving the component itself: that flowing through the surface at
terminal a with the normal oriented on the inlet side of l,
for example, ia; and that flowing through the surface at terminal b with the normal oriented on the outlet side, ib. The component we are analyzing can be considered a one-port only if
ia
ib.
This seemingly banal property is never, in fact, truly verified in a component, unless it is not operating under strictly
steady-state conditionsthat is, when the electrical variables
are constant in time. In such conditions, in fact, ia
ib is
assured by Maxwell equations (for more details see Ref. 1),
which establish that in steady state the flux of the electric
current density field J through any closed surface must be
zero. In a dynamic operation, that is, when the electrical variables vary with the time, such a condition can only be approximate: The slower the current variation in the time, the closer
the approximation. This problem will be examined in greater
detail later in the article.

In the SI system the unit of the electrical voltage is the volt

(V). Thus v represents the work that would be done by the
electric field to carry a positive unit charge from a to b along
the path considered. For such work to be unique the line
integral of the field E will obviously have to be independent
of the path; that is, the field E must be conservative. This is
rigorously ensured by Maxwells equations only in steadystate (for details see again Ref. 1). In this case the line integral of the electric field does not depend on the path chosen
but only on the ends, and it may be represented by the difference between the values that a new function, the electrical
potential, assumes at a and b. Thus we should use different
terminology for stationary and dynamic operations. It would
be better to speak of potential difference between the terminals in the case of steady-states and would be better to speak
of voltage, stating along which path, for dynamic operations.
Once again, in a dynamic operation, the fact that the behavior
of the component may be characterized by a single voltage
is merely an approximation, the more so when the electrical
variables change slowly. From such considerations it is evident that one can speak of one-ports only if the voltage across
the terminals may be expressed as a difference of potential or
may be approximated through it. This problem, too, will be
dealt with more fully later in this article. For the sake of linguistic simplicity, we will use the terms voltage and current
without further specification, with the considerations that
have been outlined being implicitly assumed.
There still remains the problem of choosing the reference
directions for the currents and voltages: It is not possible to
assign unambiguously the constitutive relations of a one-port
without first identifying them.
The voltage reference direction is usually indicated by the
signs  and  near the terminals: The  sign indicates the
starting point and the  sign the ending of the path for the
line integral of the electric field. The reference direction for
the current is usually indicated with an arrow placed on one
of the two terminals. Referring to the generic one-port we
have already spoken of, one may see that two alternative
choices exist, which are represented in Fig. 3. Suppose that a
+

+
(a)

(b)

Figure 3. Two possible conventions for the reference directions of

the current and voltage of a one-port: (a) normal convention and (b)
source convention, v
v.

424

LINEAR NETWORK ELEMENTS

current reference direction is chosen. Then the voltage reference direction can be chosen with either the  sign or the 
sign at the terminal where the current arrow enters. In the
first case [Fig. 3(a)], one speaks of the normal convention and
this is the one to which we shall implicitly refer, unless otherwise specified.
In technical language the same term is used to indicate
both the physical object concretely characterized by a certain
constitutive law and the ideal component that we find in circuit layouts. Naturally, in the first case the constitutive law
is intended as an approximation sufficient to describe the behavior of the component in a certain set of conditions. In the
second case, it is an exact law that fully describes the behavior of an ideal component extrapolated from the real one.
Even if this ambiguity of language does not cause any confusion, since the limits within which the model is intended to
operate are always very clear, in general one prefers to call
the ideal component the circuit element.
This article focuses essentially on the ideal components of
an electrical network. Nonetheless, we shall not fail to refer
to the physical objects to whose characteristic they approximate, both when they are elementary components (e.g., as
for example resistors) and when they are the result of a more
complex aggregation of other elementary components (e.g.,
operational amplifiers or controlled sources).
The relationship between real and ideal components may
be interpreted from two opposite viewpoints. One may think
of starting from a real component by identifying the approximate constitutive lawperhaps experimentallyand then,
by extrapolation, building the corresponding ideal component. Alternatively, it is possible to imagine a determined
constitutive lawof which perhaps one feels the need for a
particular applicationand attribute an ideal component to
it and then, if possible, build a real component suitably approximate to it in behavior. From the historical viewpoint,
one may clearly say that both paths have been trodden: the
former for the components we have previously called elementary and the latter for more complex ones. We, too, for didactic reason will adopt the possibility of introducing diverse
components from the two distinct viewpoints, beginning naturally with elementary components.
A first and fundamental classification of one-ports divides
them into linear and nonlinear. Obviously a linear one-port is
one whose constitutive relation is of the linear type. In this
article we will limit ourselves to linear elements only, while
nonlinear ones are dealt with in NONLINEAR NETWORK ELEMENTS.
A second classification of one-ports that it is convenient to
introduce is that distinguishing nondynamic or resistive
one-ports from dynamic one-ports. The former are those characterized by an algebraic link between the voltage and the
current. If, for example, the current is the independent variable (the control variable), the constitutive relation of the oneport will be of type v
v(i). If v(i) is single-valued, one speaks
of current controlled one-ports. However, one can also express
the constitutive relation as
(v). If (v) is single-valued,
one speaks of voltage-controlled one-ports. In general, a oneport is both voltage- and current-controlled if its constitutive
relation is invertible.
The linear resistors are nondynamic one-ports that are
characterized by a linear algebraic constitutive relation between the voltage and current. They can both be described by

v = Ri

and i = Gv

(5)

where R and G are two constant parameters called, respectively, resistance and conductance. They are linked by the relation R
1/G. The symbol of the linear resistor is illustrated
in Fig. 4(a). In the SI system, electrical resistance is measured in ohms (; 1 
1 V/1 A) and conductance is measured in siemens (S; 1 S
1/1 ). There are, however, cases
where inversion is not possiblefor example, if the constitutive relation v
v(i) is nonlinear and v(i) is not strictly increasing. In such cases the nature of the one-port imposes
one of two descriptions and one then says that one-ports are
intrinsically current- or voltage-controlled.
There are nondynamic one-ports that impose the time behavior of the voltage at their terminals independent of the
current circulating therein, v
e(t). These are the independent voltage sources. Likewise, current-independent sources
impose the time behavior of current circulating therein independent of voltage, i
j(t). The symbol for voltage- and current-independent sources are, respectively, shown in Figs.
4(b) and 4(c).
Dynamic one-ports, instead, are characterized by a more
complex relation between voltage and current: The derivative
of one of the two electric variables is present. Such one-ports,
when present, introduce ordinary differential equations in the
circuit equations, notably enlarging the behavioral complexity
of the electric network (for more details see NETWORK EQUATIONS).
Elementary dynamic one-ports are the capacitor, whose operation is described by the differential equation
i=C

dv
dt

(6)

and the inductor, whose operation is described by the differential equation

v=L

di
dt

(7)

The parameters C and L are two constants that are, respectively, known as capacity and inductance. In the SI system,
capacity is measured in farads (F) and inductance is measured in henries (H). The symbols for linear capacitors and
linear inductors are illustrated, respectively, in Figs. 5(a)
and 5(b).
A third classification divides one-ports into active and passive. One-ports unable to supply more electric energy than
they have previously absorbed belong to the second category.
Let us first consider nondynamic one-ports. From the definitions of voltage and current previously given, it is obvious

(a)

i
e(t)

i
j(t)

(b)

(c)

Figure 4. Symbols for (a) linear resistor, (b) independent voltage

source, and (c) independent current source.

LINEAR NETWORK ELEMENTS

+
i

(a)

(b)

Figure 5. Symbols for (a) linear time-invariant inductors and (b) linear time-invariant capacitors.

that the product p
iv is, instant by instant, the electrical

power flowing in the one-port. In fact, v is the work needed to
carry a positive charge from one terminal to the other inside
the element, while i is the amount of electric charge transported per unit time through the one-port. In particular, if
the normal convention is assumed, p
iv represents the work
per unit time done by the electric field on the charges: It is
equal to the electrical energy per unit time absorbed by the
one-port. Thus we call it electric power absorbed by the oneport. If this power is always positive, obviously the one-port
is only able to absorb electric energy and thus, as previously
defined, is passive. If operating conditions exist wherein the
power absorbed is negative, the nondynamic one-port is said
to be active. In the SI system, electrical power is measured in
watts (W) and the electrical energy is measured in joules (J),
1 J
1 W  1 s.
In the case of nondynamic one-ports the property of passivity has a simple verification on the characteristic curve. Since
the constitutive relation of a resistive one-port is described by
an algebraic relation between voltage and current, it can be
represented on a cartesian plane (i,v). In particular, for linear
resistors the representative curve will be a straight line passing through the origin, inclined with respect to the axis of the
currents at an angle  so that R
tan [Fig. 6(a)]. Thus in
the plane (i,v) the characteristic curve always develops in the
first and third quadrants if the resistance is positive. In the
first quadrant a positive voltage corresponds to a positive current, while in the third quadrant a negative voltage corresponds to a negative current, so that the power absorbed is
always positive or at most equal to zero. If the one-port characteristic curve has points in the second or fourth quadrants
(recall that the convention assumed is the normal one), operating conditions exist in which the power absorbed is negative and thus corresponds to positive supplied energy and the
one-port is said to be active. This happens, for example, for
voltage- and current-independent sources [Fig. 6(b)].

In conclusion a resistor is passive if we have vi  0 for any

pair (v, i) (we are assuming the normal convention for the
reference directions of the current and the voltage). If such is
not the case, the resistor is active. The resistor is said to be
strictly passive if vi
0 only for the case i
0 and v
0, and
so a linear resistor with R 0 is strictly passive. As we will
see later there are also one-ports that absorb zero-power for
any pair of (v, i). Unlike voltage and current sources, a linear
resistor with negative resistance always absorbs a negative
power, except for the case v
0 and i
0 where the absorbed
power is zero. To stress this property we could introduce the
concept of strictly active one-port. However, we have to note
that physical devices whose characteristic curve always lies
in the second and fourth quadrant of the (v, i) plane do not
exist.
For dynamic one-ports, too, p
iv represents the electrical
power absorbed. In this case, however, the definition of passivitywhich remains the same as previously statedhas
more complex implications. The fact is that a dynamic oneport is generally able to store electrical energy for a certain
interval of time and supply it later. Consider, for example, a
capacitor of positive capacity C [its characteristic is represented by Eq. (6)] and integrate the power absorbed p on the
interval (t0,t). In this way we calculate the electric energy absorbed by the capacitor in the interval (t0,t), which is given by

w(t0 , t) =

E0

(a)

(b)

Figure 6. (a) Characteristic curve of a linear resistor; (b) characteristic curve of an independent voltage source.

p( ) d =
t0

t0

d
d

Cv2 
2

d
(8)

Such energy is positive (and therefore effectively absorbed) if

v2(t) v2(t0), whereas it is negative (and thus corresponds to
energy effectively supplied by the one-port) if v2(t)  v2(t0). If
at the initial instant v(t0)
0, the energy w(t0,t) is certainly
positive. All these considerations lead to the following conclusions: The capacitor is able to absorb or supply electrical energy; at each instant the level of energy stored is equal to
Cv2(t)/2; the energy that can be supplied at any given instant
is never greater than that stored previously if C 0. In other
words, the capacitor with C 0 is passive because

p( ) d 0

(9)

for each instant of time t.

Analogous considerations can be developed for the inductor
with positive L. Then we have

w(t0 , t) =

1
1
= Cv2 (t) Cv2 (t0 )
2
2

v

425

p( ) d =
t0

t0

d
d

Li2 
2

d =

1 2
1
Li (t) Li2 (t0 )
2
2
(10)

The amount of energy stored by an inductor at any instant is

proportional to the square of the current circulating therein
at that instant. Here too passivity is assured by the condition
L 0 and so Eq. (9) is valid.
An immediate consequence of what has been said is that
the constitutive laws of the dynamic one-ports are not sufficient in themselves to univocally predict their behavior starting from an instant t0: It is necessary to know the level of
energy stored at that instant. In other words, one needs to

426

LINEAR NETWORK ELEMENTS

know an initial condition, which for the capacitor is the voltage value at t
t0 and for the inductor is the current value
at t
t0.
In conclusion, as regards classification we should recall
that a one-port is said to be time-invariant, whether resistive
or dynamic, if the parameters of its constitutive relation do
not vary in the time.
In this article first we will describe the linear resistive oneports and then the main properties of linear resistive elements with more than two terminals that are of notable importance in the circuit theory and applications. Then we will
study in detail the capacitor and inductor. We shall conclude
by describing the behavior of mutually coupled circuits.
RESISTIVE ONE-PORTS
In this section we will introduce different resistive one-ports
by briefly describing their concrete structure and discussing
the properties implicit in their characteristic laws. Let us begin with linear resistor one-ports operating in the steadystate condition, which in a certain way can be considered typical. As we shall see many of the things we will say are also
true when the resistors operate in nonstationary conditions.
We will then illustrate the ideal voltage source, the ideal current source, the short circuit, the open circuit, the nullator,
and the norator.
The Linear Resistor
Materialsusually metalsexist in which, for a suitable
range of parameters, the current density field J is, at every
instant and throughout the material, directly proportional to
the electrical field E according to the equation
E
J = E

(11)

where  is the electric conducibility of the material, which is

measured in siemens/meter (S/m) in the SI system. Equation
(11), which is called the local Ohms law, can also be rewritten
as E
J, where  is the electrical resistivity of the material
that in the SI system is measured in ohm  meter (  m).
The fact that some materials, called in fact ohmic materials, verify Ohms law has a very subtle significance that we
will try and examine, even if only from the qualitative point
of view. From its definition it is evident that current density
is directly proportional to the average velocity of the charge
carriers. On the other hand, the electric field is directly proportional to the force exercised on the carriers themselves.
Therefore, Ohms law affirms that the velocity is directly proportional to the force, in apparent contradiction with the laws
of dynamics that require that the force is directly proportional
to the acceleration. In effect, the contradiction is only apparent since in Newtons law the body is assumed to be completely free to move in the surrounding space under the action
of the force. Obviously the charge carriers in an ohmic conductor are not completely free to move! The crystal lattice
which constitutes the material body in which the carriers are
forced to move offers some obstacle to the charge movement.
Ohms law, indeed, allows us to determine what type of obstacle there is. Let us, in fact, suppose that the overall effect of
the motionless charges constituting the lattice is equivalent
to a friction directly proportional to the velocity. The overall

force acting on the charges will then be qE  kv, given that

the friction is opposed to the action of the electric field. If a
steady state is achieved, the charge velocity remains constant
and the acceleration is therefore nil. Then we will have
E kv
v
0 = qE

(12)

and so v
qE/k as prescribed by Ohms law. This model of

conduction in ohmic materials is known as Drudes model,
and what we have explained only qualitatively can be further
considered at a quantitative level. We are principally interested in underlining the fact that the verification of Ohms
law requires rather particular conditions. It is not surprising
therefore that there are conducting materials that do not satisfy this law, and that ohmic materials themselves are such
only in determined conditions. For example, the resistivity of
a material does not remain constant when the material temperature varies, as we will see later.
Let us now consider a cylindrical conductor of uniform
cross section S and length l [Fig. 7(a)], crossed by a steadystate current density field J that we will suppose to be uniform, directed parallel to the cylinder axis. A uniform electric
field will be associated to it. Integrating Eq. (11) between two
points a and b on the extreme surfaces of the cylinder along
any path connecting them within the cylinder, we obtain


i
(13)
vab = E dll = /J = l = Ri
S

where vab is the voltage and i
JS is the intensity of the

electric current flowing across any section of the conductor
cylinder. The orientation of the normal to the generic section,
indispensable in calculating the current, has been chosen in
agreement with the orientation of path . Factor R
l/S is
called the electric resistance of the conductor tract, and Eq. (13)
is Ohms law applied globally.
This result may easily be generalized to any conductor
form involving a charge flux constant in time, in conditions
where all the charge carriers start from one end and arrive at
the other end of the conductor tract. Two perfectly conducting
electrodesthat is, 
0constrain the electric potential to
be uniform at the tract ends [Fig. 7(b)]; we will call them terminal a and terminal b. Even without knowing the actual distribution of the current density J inside the body, we can certainly affirm that all the field lines must start from and meet

Sk
J

b
(a)

(b)

Figure 7. (a) Cylindrical resistor with uniform cross section; (b) cylindrical resistor with a varying cross section in which an elementary
flux tube is represented. The terminals are perfect conducting electrodes.

LINEAR NETWORK ELEMENTS

427

metal, in Taylor series with initial point T0 and stopping it at

the second term. So one obtains




d
1
(T ) 1 +
 (T T )
(T ) =
(16)
0
0
(T0 ) dT T

107
106
Copper
105
10

-cm

Coefficient (T0)
[1/ (T0)] (d /dT)T0 is called the material

temperature coefficient at T
T0, or resistor temperature coefficient (RTC), because it is also found in the dependence on
the temperature of the resistance R,

103
Graphite

100

178

102

R(T ) = R(T0 )[1 + (T0 )(T T0 )]

101
1000

316
562
Temperature (K)

Figure 8. Resistivity versus temperature for two conducting materials (in both axes, logarithmic scales have been used).

at the terminals a and b. Let us consider a flux tube of J

having an elementary cross section Sk that is, an elementary tube on whose side vector field J is tangent. Integrating
Ohms law [Eq. (11)], as before, along the median of the elementary flux tube, one has


vab =

k

E dll =

Sk Jk
dl = ik
Sk

k

dl
Sk

(14)

because the intensity of the current ik along the elementary

flux tube is, by definition, constant. Taking ik from Eq. (14)
and summing on all elementary flux tubes of the conductor
tractthat is, on kone obtains

i=


k

ik =  

vab

k
k

v
= ab

R
dl
Sk

(15)

which is the constitutive relation [Eq. (5)] of a linear resistor

with R
kk ( /Sk) dl.
As we have already observed, the fact that a one-port has
a type (5) constitutive relation requires the verification of
quite strict conditions and that the movement of the charges
in the component itself is regulated by particular laws. Therefore, it is not surprising that a real resistor behaves as such
only in a determined range of parameters that characterize
its physical conditions.
A physical condition that regulates the behavior of a resistor, for example, is the temperature. In fact, the resistivity of
a material generally depends on the temperature. Figure 8
shows the typical resistivity performance as a function of the
temperature for two materials, copper and graphite. As can
be seen, the resistivity can increase or decrease with the
change in temperature. Even with the same material, these
two behaviors can be encountered at different temperature
ranges.
For changes in temperature that are not too wide, it is possible to take into account such dependence by developing the
function (T), where T indicates the temperature of the

(17)

The fact that R depends on the temperature has an important

consequence that we wish to examine in greater detail. As we
know, a resistor with resistance R crossed by an electric current i for a time interval t absorbs an electric energy equal
to Ri2t. This energy is all transformed into heat, according
to Joules well-known law. As a consequence of this phenomenon, the temperature of the resistor tends to increase and so
the resistance tends to vary. The result, therefore, is an indirect dependence of R on i that modifies the characteristic of
the one-port itself. In effect, however, the resistor soon
reaches a steady-state temperature that can easily be determined by a simple energy balance. The temperature reached
will be that at which the power dissipated in the resistor is
exactly equal to the quantity of heat per unit time transferred
by the resistor to the surrounding ambient, which depends on
the temperature difference between the resistor body and the
environment. Once the temperature is stabilized, the value of
R stabilizes, even if at a different value from that initially
held. It follows that for every resistor, in addition to the value
of its resistance and the precision with which it is guaranteed,
the maximum value of the currentor the power Ri2 for
which the resistance value is guaranteed must also be given.
For these reasons, resistors are generally classified on the basis of the power they are capable of dissipating without the
resistance value exceeding the limits of precision guaranteed,
or the limit at which the resistor itself deteriorates irreversibly. Naturally, to allow a resistor to dissipate greater power,
while maintaining its temperature within acceptable limits,
the simplest way is to increase the exchange surface with the
surrounding ambient, so as to increase the quantity of heat
lost per unit time. On the other hand, larger surfaces involve
greater volumes and so, generally, the size of a resistor is an
index to its capacity to dissipate power.
Another factor that can affect the size of the resistor is
the operating voltage for which it is built. This is particularly
significant with resistors designed for high voltages. So far we
have implicitly assumed that the resistor is embedded in an
insulating medium so that the motion of the electric charges
must develop only within the resistor itself. In effect, any insulating medium behaves as such only if the force due to the
electric field acting on the charges present therein (we are
thinking about the molecular and atomic structures) does not
exceed determined limits. With very high values of the electric field the insulator loses its characteristics, the passage of
the charges is no longer impeded, and a discharge develops
inside it. The breakdown field above which the discharge develops depends significantly on the physicochemical conditions in the insulating medium (composition, temperature,
etc.); for example, the breakdown electric field for the air is

428

LINEAR NETWORK ELEMENTS

about 25 kV/cm in normal conditions. Consequently, the dimensions of the resistor must be such as to guarantee that,
for the voltages for which it is designed, the breakdown field
cannot be exceeded at any point in the insulator. As we have
said, this factor is particularly important for high-voltage resistors.
In general, all these characteristics depend on the way in
which the resistor is built. From this viewpoint, resistors can
be broadly classified as wirewound, foil, thin film, thick film,
and bulk resistors. The specific characteristics for each of
these classes depend, of course, on the different technologies
used in their production and will not be dealt with further in
this article. There are numerous handbooks that deal with
these matters in detail (see, for example, Ref. 2).
Another useful classification is that which divides resistors
into two classes: fixed resistors and potentiometers. In the
former there are low-power resistors (typically from 0.05 W
to 2 W) high-power resistors, high-ohmic resistors, and chip
resistors. For some types of sufficiently low power resistors,
and thus small size, it is usual to indicate the resistance and
its relative tolerance with a colored band code whose key is
given in the manuals. However, the second class includes all
variable resistors that, according to the way in which their
variability is obtained, can be divided into rotary control,
slide control and preset potentiometers. For further details
one should again consult Ref. 2.
On the other hand, the same words used to identify the
different classes of resistors already give an idea of how they
are built. In each of them, then, one varies between three
available parametersthe resistivity  (and hence the material), the length l, and the cross section Sto obtain the resistance values desired.
In conclusion, it is worth recalling that in this section we
have described the operation of resistors when the voltage
and current are in steady state, that is, we have described the
so-called direct current (dc) operation. As we shall see, many
of the things we have said are also true when the resistor
does not operate in steady state.
Short-Circuit and Open-Circuit One-Ports
As we have seen, resistor constitutive relation (5) is represented on the plane (i,v) by a straight line passing through
the origin inclined to the current axis at an angle  so that
R
tan [Fig. 6(a)]. Thus, as R varies, the straight line will
be more or less inclined on the i axis. Two limit cases immediately come to mind: one in which the angle  is zero and the
other in which it is equal to /2.
In the first case, R
0 and the voltage of the one-port will
always be zero for any current flowing in it, that is,
v=0

for any i

(18)

Such a one-port is called short circuit. Its symbol is illustrated

in Fig. 9(a); and, in theory, it can be realized with a perfect
conductor, namely, a conductor with infinite conducibility
(that is, with zero resistivity). We may imagine the connections between different one-ports in a circuit as being of this
nature. In reality, of course, a real conductor can at most approximate such behavior, and the shorter the conductor tract,
the closer the approximation will be. This also justifies its
being called a short-circuit one-port.

i
v=0

i=0

+
v

i=0

v=0

(a)

(b)

(c)

(d)

Figure 9. Symbols for (a) short circuits, (b) open circuits, (c) nullators, and (d) norators.

The other case, R
, corresponds to that in which the

electric conducibility of the conductor is equal to zero. In such
an event, in contrast, for any voltage at the one-port terminals, the current crossing the one-port is always zero, that is,
i=0

for any v

(19)

Such a one-port can be realized by placing an ideal insulator

between the terminals. For this reason the one-port is called
open circuit and its symbol is represented in Fig. 9(b). The
electrical power absorbed by the short-circuit and open-circuit
one-ports is always zero. For this reason we call them zeropower one-ports.
Ideal Voltage and Current Sources
Starting from the characteristic of a short circuit, let us imagine moving its characteristic curve parallel to itself, for example, in the direction of the positive voltages. Let E0 be the
value at which the straight line parallel to the axis of the
currents so obtained intersects the axis of the voltages. The
one-port having such a characteristic could be described as
follows: For any value of the current flowing in it, the voltage
at the terminals is always equal to E0. Such a characteristic
must develop in the first and second quadrants of the plane
(i,v) [Fig. 6(b)]. Because we have assumed the normal convention on the one-port, when the operating point lies in the second quadrant, the electric power absorbed by the one-port is
negative and therefore the one-port supplies electric energy.
For this reason the one-port so identified is called a source. It
is to be noted that, contrary to that which happens in the
resistor with positive resistance, where the positive charge
movement is always from the higher potential terminal to the
lower (so the power absorbed is always positive), in this oneport when the operating point lies in the second or fourth
quadrant the positive charges move from the lower potential
terminal to the higher, against the force exercised by the electric field. Thus, it is evident that such a one-port must be the
site of more complex phenomena, wherein forces of a nature
other than that produced by the electric field come into play
(for example, such forces in a battery are of a chemical nature
and of an electrodynamic nature in a dynamo).
More generally, an ideal voltage source can impose a voltage variable in the time with a known waveform and independent of the current that circulates within; that is,
v = e(t)

for any i

(20)

The symbol used to indicate an ideal voltage source is shown

in Fig. 4(b).
The characteristic of an ideal voltage source can only approximate that of a real source. In fact, it is implicit in the

LINEAR NETWORK ELEMENTS

characteristic of an ideal voltage source that it can supply as

great a power as one wants, to infinite limit when the current
is infinite. Naturally a real source cannot possess such a property. If the current circulating in the source becomes too high,
the voltage will not remain equal to the value assumed when
the current is zero (open-circuit voltage), but will fall until it
tends to zero and change sign for a finite current value (shortcircuit current). The simplest way to represent a real voltage
source is to consider an ideal voltage source, with the voltage
intensity equal to the open-circuit voltage of the real source,
in series with a resistor that takes into account the effects
due to the internal resistance of the real source. This real
voltage source model tends to the ideal one when the internal
resistance tends to zero.
Similarly, starting from an open-circuit one-port, one can
deduce a new ideal one-port in which a current with an assigned waveform circulates irrespective of the voltage between the terminals,
i = j(t)

for any v

(21)

Such a one-port, for which considerations analogous to those

relative to the ideal voltage source can be developed, is called
an ideal current source and its symbol is shown in Fig. 4(c).
Naturally it may be better not to use the normal convention
for source one-ports, but rather the other [Fig. 2(b)], which
for this reason we call source convention.
Nullators and Norators
Let us complete this overall view of resistive one-ports by introducing another two ideal one-ports whose characteristics
are in fact pathological. Their use, which may not be clear
at first sight, lies in the fact that they allow models of complex
components to be built, as the following examples illustrate.
The first is the nullator which is an ideal one-port, whose
symbol is given in Fig. 9(c), defined by the constitutive equations
i = 0,

v=0

(22)

This, unlike the short-circuit one-port, imposes a zero voltage

with a zero current. With such a one-port, one can make two
nodes of a circuit have the same potential without changing
the distribution of the currents. The electric power absorbed
by a nullator is zero; in fact, in the plane (i, v) the characteristic of the nullator is reduced to a point, the origin of the axes.
This is another example of zero-power one-port.
The other one-port, whose symbol is shown in Fig. 9(d), is
the norator. It is an ideal one-port that on the contrary imposes no constraint on the voltage and the current: The voltage and the current can assume any value whatsoever. In
other words, the characteristic of norators is the whole (v, i)
plane and hence its pathology is complementary to that of
nullators. The norator, unlike an open circuit, allows any current to flow, whatever the voltage. With a similar one-port it
is possible to connect different parts of a circuit without altering the voltage distribution. The electric power absorbed by a
norator is not usually zero and can even be negative. Thus
the norator is an active element.

429

LINEAR RESISTIVE ELEMENTS WITH

MORE THAN TWO TERMINALS
As we have already said, the components of an electrical circuit can have more than two terminals. An element with terminals is called an n-pole and is characterized by n currents
and n(n  1) voltages if the order in each pair of nodes is
taken into account. In agreement with Kirchhoff s laws, only
(n  1) currents and (n  1) voltages are independent (see
NETWORK EQUATIONS). The operation of an n-pole can be conditioned by the topology of the circuit into which it is inserted;
the most significant example is that of a 2m-pole connected to
m circuits, each of which can be considered as a one-port. In
this case the current entering from a given terminal is equal
to the current exiting from the other terminal. Let us call
each pair of terminals having this property a port and call the
element operating in this way m-port. There are also 2m-poles
that operate intrinsically as m-ports because of their physical
constitution. As for the one-ports, we could classify n-poles
and m-ports into linear and nonlinear, into nondynamic or
resistive and dynamic, into active and passive, and into timeinvariant and time-variant.
If an n-pole does not function as an n/2-port, either because of its internal physical structure or because n is odd, it
can still be described by an (n  1)-port through its descriptive variables after having chosen an arbitrary common terminal (see NETWORK EQUATIONS). For example, let us consider
a 3-pole. To identify a set of independent voltages and currents one may choose an arbitrary reference terminal, for instance the terminal labeled 3, and consider the currents of
the other two terminals i1 and i2 and the voltages v1 and v2
between these two terminals and the reference terminal 3.
To current i1 and voltage v1 we can associate a port whose
terminals are those labeled 1 and 3, and to current i2 and
voltage v2 we can associate a port whose terminals are those
labeled 2 and 3: the terminal labeled 3 is in common to
the two ports. In this way it is possible to characterize the 3pole as a 2-port. However, the general theory of linear n-poles
and linear m-ports is dealt with in MULTIPOLE AND MULTIPORT
ANALYSIS, whereas NONLINEAR NETWORK ELEMENTS considers
nonlinear resistive elements with more than two terminals
that are of special interest in circuit applications. Here we
will limit ourselves to describing the basic linear resistive
two-ports that are of notable importance in the theory of circuits and in the building of complex models, beginning with
linear controlled sources.
Linear Controlled Sources
Linear controlled sources are two-ports in which one of the
variablesvoltage or currentat one of the two ports is directly proportional to one of the variables of the other port.
Considering all the possible combinations one has the elements which follows.
The voltage-controlled voltage source is a linear two-port
defined by the constitutive equations [the symbol is shown in
Fig. 10(a)]
i1 = 0,

v2 = v1

(23)

where is a constant called the voltage transfer ratio. Port 1

is equivalent to an open circuit and port 2 is equivalent to a

430

LINEAR NETWORK ELEMENTS

i1 = 0

i2

i1
+

v1

v1

+
v2

+
+

v1 = 0

ri1

v1

(b)
i2

i1
+

gv1

v2

(a)
i1 = 0

i2

v2

i2

+
v1 = 0

+
i1

(c)

v2

(d)

Figure 10. Symbols for the linear controlled sources.

voltage source that imposes a voltage linearly dependent on

the voltage at port 1 and independent of the current i2.
The current-controlled voltage source is a two-port defined
by the constitutive equation [whose symbol is shown in Fig.
10(b)]
v1 = 0,

v2 = ri1

The Gyrator
(24)

where r is a constant called transresistance. Port 1 is equivalent to a short circuit and port 2 is equivalent to a voltage
source that imposes a voltage linearly dependent on the current circulating at port 1 and independent of the current i2.
The voltage-controlled current source is a two-port defined
by the constitutive equations [whose symbol is given in Fig.
10(c)]
i1 = 0,

i2 = gv1

(25)

where g is a constant called transconductance. Port 1 is equivalent to an open circuit and port 2 is equivalent to a current
source that imposes a current linearly dependent on the voltage at port 1 and independent of the voltage v2.
Finally, the current-controlled current source is a linear
two-port defined by the constitutive equations [whose symbol
is illustrated in Fig. 10(d)]
v1 = 0,

i2 = i1

It can easily be shown that, by connecting a current-controlled voltage source in cascade to a voltage-controlled current source, we obtain a current-controlled current source
with a transfer ratio given by
rg. However, if one connects
a voltage-controlled current source to a current-controlled
voltage source, we obtain a voltage-controlled voltage source
with a transfer ratio given by
rg.
Even if the controlled sources are to be imagined as ideal
components, so as to simplify the circuit representation of
more complex components, such as linear models of transistors (see NONLINEAR NETWORKS ELEMENTS), it is also true that
by using the operational amplifier itself it is possible to realize components whose constitutive relations approximate satisfactorily to the various controlled sources. Thus these elements are often used in real circuits to obtain particular
effects. For example, it is possible to connect two two-ports by
means of a voltage-controlled source so that the operating of
the first is not affected by the presence of the second. This
separation technique is an important tool in the designing of
electronic circuits.
To complete the picture of linear and resistive two-ports,
let us introduce another three two-ports: the gyrator, the
ideal transformer, and the operational amplifier. Thus we will
have all the elements needed to realize two-ports with any
link between their electrical variables.

(26)

where is a constant called the current transfer ratio. Port 1

is equivalent to a short circuit and port 2 is equivalent to a
current source that imposes a current linearly dependent on
the current circulating at port 1 and independent of the voltage v2.
One should note that the electric power absorbed by the
controlled sources is always equal to p
v2i2, because port 1
never absorbs power. This power can be negative, so the controlled sources are active two-ports. Controlled sources are
also nonreciprocal two-ports, that is, the two ports considered,
one as an input and the other as an output, do not behave in
the same manner. For fuller consideration of this question
refer to NETWORK THEOREMS.

The gyrator is a linear resistive two-port, whose operation is

described by the equations
i1 = Gv2 ,

i2 = Gv1

(27)

where the constant G is called the gyration conductance. The

symbol is shown in Fig. 11(a). The electric power absorbed by
the gyrator is zero in any operating condition, so it is a globally passive two-port that neither dissipates nor stores energy. Even if globally passive, the nonamplification of voltages and currents is not verified for this two-port. For
example, if one considers a gyrator with port 1 connected to
an ideal voltage source and port 2 connected to a short circuit,
the current in the voltage source is zero, while the current in
the short circuit is different from zero. Consequently, even
if the gyrator is globally passive, it must be constituted by
active elements.
The gyrator is an antireciprocal two-port, which is a particular case of nonreciprocity. This strong property is the basis
of the most important property of a gyrator, which can be

G
i1

i2

i1

n:1

i2

v1

v2

v1

v2

(a)

(b)

Figure 11. Symbols for (a) gyrators and (b) ideal transformers.

LINEAR NETWORK ELEMENTS

Esat

i1

i2

i1

v1

v2

n:1 i2

C v1

v2

+
vi

i+

vo
Slope
A100,000

io
+
vi

vi
Esat

(a)
(a)

431

(b)

(b)

Figure 12. (a) A gyrator terminated at the output with a capacitor;

(b) an ideal transformer terminated at the output with a resistor.

illustrated by means of the circuit in Fig. 12(a). Port 2 is connected to a linear time-invariant capacitor C. In this case, one
has
v1 =

C dv2
C di
i2
=
= 2 1
G
G dt
G dt

(28)

Therefore when a gyrator is connected to a time-invariant linear capacitor of capacity C, the inlet port behaves as a linear
time-invariant inductor of inductance C/G2. Thus the gyrator
allows inductor one-ports to be realized starting from capacitors. It is also possible to realize a capacitor from an inductor
by using a gyrator.
The following properties may also easily be demonstrated:
If a gyrator is connected to a linear resistor of resistance R,
the equivalent one-port behaves like a linear resistor of resistance 1/(RG2); if the gyrator is connected to a voltage (current)-controlled resistorfor example, a diode tunnelthe
equivalent one-port then behaves as if it were a current (voltage)-controlled resistor. Because of these characteristics, it is
called a gyrator.
There are on the market components that approximate to
the operation of a gyrator. A gyrator can also be made from
two voltage-controlled current sources with transconductance
G, as illustrated in Fig. 13(a).
The Ideal Transformer
The ideal transformer is a linear resistive two-port whose operation is defined by the equations
v1 = nv2 ,

i2 = ni1

(29)

Figure 14. (a) Symbols for the biased operational amplifier; (b)
transfer characteristic curve.

where the constant n is the transformation ratio. The symbol

for the ideal transformer is illustrated in Fig. 11(b). The electric power absorbed by the ideal transformer is equal to zero
whatever the operating condition. Therefore like the gyrator
it is a globally passive two-port that neither dissipates nor
stores energy. For this two-port too, the nonamplification of
the voltages and currents does not apply, even if it is globally
passive. Unlike controlled linear sources and gyrators, the
ideal transformer is a reciprocal two-port.
One of the most important properties of the transformer
can be illustrated by considering the circuit shown in Fig.
12(b), where a transformer port is connected to a linear resistor with resistance R. In this case we have
v1 = nv2 = nRi2 = n2 Ri1

(30)

Thus, when a transformer is connected to a linear resistor of

resistance R, the equivalent one-port behaves like a linear
resistor of resistance n2R and therefore the transformer
allows the resistance of the resistor to be changed. It is also
easy to show the following properties: When a transformer
is connected to a linear inductor with inductance L (a linear
capacitor of capacity C), the equivalent one-port behaves like
an inductor of inductance n2L (a capacitor with capacity
C/n2).
An ideal transformer can be realized by means of a current-controlled current source and a voltage-controlled voltage source as shown in Fig. 13(b). It, too, is the fundamental
element in representing a real transformer realized with two
coupled circuits; and, in turn, a real transformer, under certain operating conditions, approximates to the operation of an
ideal one.
The Ideal Operational Amplifier

i1

i2

+
v1

Gv1

i1

i2

v2

v1

v2

ni1

The ideal operational amplifier is an extremely complex semiconductor component. In use at low frequencies it behaves
like a nonlinear resistive element with four terminals, whose
operation may be described by the approximated relations
[the symbol is shown in Fig. 14(a)]

i = I ,
Gv2

(a)

nv2

(b)

Figure 13. Realization (a) of a gyrator and (b) of an ideal transformer by using linear controlled sources.

i+ = I+

Esat ,
vo = f (vi ) =
Avi ,

Esat ,

vi (Esat/A)
(Esat /A) vi (Esat/A)
vi (Esat /A)

(31)

where I and I are the so-called input polarization currents,

Esat is the maximum absolute value of the output voltage vu,
and A is the so-called open-loop voltage gain. It should be

432

LINEAR NETWORK ELEMENTS

+ E
+
vi

i+

+
FD

ii = 0

+ E

vi = 0

vo

io
+

io

the circuit into which the amplifier is inserted. Thus, the operational amplifier is an active two-port.
If the operational amplifier in the circuit into which it is
inserted functions in the linear regionthat is, the output
voltage satisfies the relation Esat  vo  Esat then the
characteristic relations are

vo

ii = 0,

vi = 0

(33)

(a)

(b)

Figure 15. (a) Typical biasing scheme for the operational amplifier;
(b) equivalent circuit of an ideal operational amplifier in the linear
region.

noted that the transfer characteristic f(vi) of this approximate

model is piecewise linear and has three segments: a linear
tract and two saturation tracts [see Fig. 14(b)].
The device known as an operational amplifier that we can
buy in any electronics shop has at least five terminals [Fig.
15(a)]. To function as an operational amplifier, as described
by characteristic Eq. (31), it must be biased with two equal
constant voltage sources, as indicated in Fig. 15(a). The component, thus polarized, is shown by means of the symbol illustrated in Fig. 14(a) and its operation is described by Eq. (31).
The polarization voltage is typically 15 V. Besides the five
terminals shown in Fig. 15(a), other terminals are added to
the device to allow it to be controlled.
Currents I and I do not normally exceed values of the
order of 0.1 mA. For example, for A741, I and I are of the
order of 0.1 mA, while for A740, they are of the order of 0.1
nA. Typically the open-loop voltage gain A is 105 and the saturation voltage Esat is 2 V less than the polarization voltage of
the operational amplifier.
Many operational amplifiers are produced with integrated
circuits using bipolar transistors as base elements (bipolar
technology). For example, the A741 contains about a dozen
bipolar transistors. In very large scale integration (VLSI) circuits, operational amplifiers are made with a different technology, known as CMOS technology. For further information
the reader is referred to OPERATIONAL AMPLIFIERS and Ref. 3.
Because of the typical values of I, I, and A, the precision
is only slightly diminished if one assumes I
I
0 and
A
. This simplified assumption is the basis of the ideal
operational amplifier model defined by the characteristic
equations

Consequently, the linear model of the ideal amplifier may be

thought of as a two-port consisting of a nullator and a norator, as illustrated in Fig. 15(b): The input port of the linear
operational amplifier behaves as if it were a nullatorthat
is, both current and voltage are zerowhile the output port
behaves as if it were a norator, since the current and voltage
can be of any value whatsoever. The linear model of the operational amplifier is a non reciprocal and active two-port.
By using linear operational amplifiers, one can realize all
possible kinds of controlled sources. Let us consider the twoport shown in Fig. 16 consisting of an ideal operational amplifier and two linear resistors. One assumes that the outlet
voltage of the operational amplifier is, in absolute value,
lower than the saturation voltage. In this operating condition
it is possible to use the linear model described by Eqs. (33).
Applying Kirchhoff s laws and using the characteristic equations of the elements, one obtains
Ra i1 + v2 = 0,

Rb i 2 + v 1 = 0

(34)

If the resistor of resistance Rb is a short circuitthat is,

Rb
0then from Eqs. (34) one obtains
v1 = 0,

v2 = Ra i1

(35)

Characteristic equations [Eq. (35)] are those for a currentcontrolled voltage source: r
Ra is the transresistance of
the source (the sign for the transresistance may be changed
by inverting the terminals of a port).
If the resistor of conductance Ga
1/Ra is an open circuitthat is, Ga
0then from Eqs. (34) one obtains
i1 = 0,

i2 = v1 /Rb

(36)

Characteristic equations [Eq. (36)] are those for a voltagecontrolled current source and the transconductance is g

1/Rb (as for the transresistance, the sign of the transconductance can be changed by inverting the terminals of a port).

i = 0

Ra

i+ = 0
vo = Esat sgn(vi ),

vi = 0

vi = 0,

Esat < vo < +Esat

(saturation region)
(linear region)
(32)

Therefore, the ideal operational amplifier is an element that

functions intrinsically as a two-port. The current in the input
port ii
i
i is zero, and that at the output port is independent of the input voltage vi: The output port behaves as if it
were a voltage source controlled by the input voltage. The
electric power absorbed by the ideal operational amplifier is
given by p
iovo. It may be positive or negative, according to

i1
+

i2
+

v1
Rb

v2

Figure 16. Basic circuit to realize controlled sources.

LINEAR NETWORK ELEMENTS

DYNAMIC ONE-PORTS
Previously we have introduced the two fundamental dynamic
one-ports: the capacitor and the inductor and we have done
so by hypothesising the existence of a mathematical model
type (6) for the capacitor and type (7) for the inductor. In effect, however, a deeper examination shows that dynamic oneports present different problems and their existence will now
be demonstrated.
For the electric field in a dynamic regime we have



E dll =

d
dt

S=
B dS
S

d
dt

(37)

for every closed line , where B is the magnetic field and S

is any open surface that has  as contour, oriented in
agreement with the right-hand rule. Equation (37) is Faradays induction law. For fuller information consult Ref. 1. The
surface integral represents the flux of the magnetic field
through the surface S. This flux does not depend on the particular surface S we are considering because the flux of the
magnetic field through any closed surface is always equal to
zero. It depends only on the magnetic field and on the contour
. For these reasons the quantity  is called the magnetic
flux linked with .
Therefore, as the electric field in a dynamic regime is not
conservative, the voltage between the two one-port terminals
must no longer be independent of the path chosen to calculate it. One should remember that the voltage of a one-port is
the line integral of the electric field along a determined path
that connects the two terminals. Because of the presence of
the time-varying magnetic field the voltage depends on the
predetermined path . In such conditions it is the idea of the
constitutive relation itself that loses significance, since it is
no longer possible to identify a single voltage to be associated
to the two terminals. Naturally, one can always define the
voltage at the terminals by making a particular choice of the
integration path. However, such a choice cannot be satisfactory since it would give a much more limited meaning to
Kirchhoff s second law.
In the same way, in a dynamic regime, one cannot associate a single current to the two terminals of the component.

v1

v2

Even if we admit that the element is embedded in a nonconductor medium, as in fact it is, and that it may interact with
the rest of the network only through its terminals, nothing
will assure that the current entering one of them will be equal
to that exiting from the other, instant by instant. In fact, we
have



dQ
S=
 J dS
dt


(38)

1

E t dl

E t dl =

d
dt

12

(39)

(a)

E
E
S
S= 
dS
 J dS

 t

v1 v2 =

or

where  is any closed surface whatsoever,  is the dielectric

constant of the medium (which is assumed to be linear, isotropic, and time-invariant), and Q(t) is the electric charge
that is within  at time t; the generic surface element dS is
oriented to the outside. The first equation in Eq. (38) is the
well-known electric charge conservation law and the second
is derived by using the Gauss law (for fuller information consult Ref. 1). Therefore the flux of the current density field J
through any closed surface is not zero, but is equal to the
minus of the time derivative of the electric charge contained
in it. As a consequence the current entering the terminal can
be different from that exiting from the other terminal at every
instant, because there can be an increase or reduction of the
total charge stored in the component. In the dynamic operation, in fact, it is no longer the vector field J but the vector
field (J  
E/
t) that has to be conservative with respect to
the flux.
It would seem that in a dynamic operation the very basis
on which the theory of circuits is founded collapses, and indeed it does. Of course to limit ourselves to this simple observation is to be superficial. It is better to ask whether conditions exist under which a single voltage and a single current
can be associated to a component with an acceptable error. To
answer this it is necessary to consider the problem more fully.
Referring to Fig. 17(a) we can affirm that the path integrals of the electric field E between points a and b along two
lines 1 and 2 differ by the flux of field
B/
t through any
surface that has the closed line 12
1 2 as its contour:

ia

433

Nonadmissible
line

b
ib
(b)

Figure 17. (a) The voltages v1 and v2 differ

by the time derivative of the magnetic flux
linked with 1 2; (b) the currents ia and
ib differ by the time derivative of the total
electric charge contained in the limiting
surface l.

434

LINEAR NETWORK ELEMENTS

As long as the voltages v1 and v2 differ by a negligible amount,

there must be









d




|v| =  E t dl  
B n dS
(40)
dt

S
where is any line going from a to b that does not pierce the
limit surface l. The surface S is open and it has as its contour a closed line given by the union of and any line 0 lying
on the limit surface of the element and joining a to b [Fig.
17(a)]. In effect, it would be exaggerated to require that this
condition be verified for any line , and it would not correspond to real needs. In fact, our real aim is to define univocally a voltage at the terminals of the one-port so as to be
able to write the Kirchhoff equations for the network into
which the one-port is inserted. The lines that we require to
satisfy Eq. (40) are therefore lines that have the same length
as the longest characteristic length of the one-port itself. For
simplicity of language we will henceforth call these lines admissible lines to distinguish them from nonadmissible lines
of the type shown qualitatively in Fig. 17(a) and that form a
great number of turns.
As regards the currents, current ia entering at terminal a
can differ from that exiting at terminal b by an amount equal
to the flux of field 
E/
t through a closed surface, which, at
most, can be the same as the limit surface l enclosing the
entire component and thereby cutting the terminals at two
distinct points a and b [Fig. 17(b)]:



d
E ) dS
S
ia ib =
 (E
(41)
dt 
l

It follows that for our needs it must be




 





d
  dQ 



 
l 


J
S
E
S
|i| = 
dS 
 (E ) dS  = 

 dt 
  dt 
Sa

where is the magnetic permeability of the medium (which

is assumed to be linear, isotropic, and time-invariant) and S
is any open surface that has  as its contour. If we have






d





 (B

B/) dll  
E ) dS
S
(E
(44)



dt

S


S

E
,
Ec

b=

B
,
Bc

x=

r
,
Lc

t
Tc

(46)

where Ec, Bc, Lc, and Tc are the respective reference variables,
for the moment all arbitrary, for the electric field, the magnetic field, position vector r, and the time t. With the introduction of these new variables, Eqs. (40) and (44) assume the
forms














  d
S
(47)
e

dx
b

dS
x
S



 d
x
x













  d
S
(48)
b

dx
e

dS
x
S



x
d
x
where the dimensionless parameters and are defined as
=

cBc
,
Ec

Lc
cTc

(49)

and c
1/  is the propagation velocity of the light in the

medium.
At this point it is convenient to transform the dimensional
analysis in a proper scaling, not by choosing reference variables arbitrarily but by choosing them so that we have



 





  d



x
S
(50)
e

dx
b

dS
x
S

  d
x
x


 





  d


Sx 
b dx  
e dS
(51)

 d

x
S
x

where i is the current flowing through terminal a and Sa is

any open surface cutting only this terminal.
To render condition (42) in a form analogous to condition
(40), let us consider the other fundamental Maxwell law, the
MaxwellAmpere law (for fuller information consult Ref. 1)







d
B/) dll =
S+
E ) dS
S
(B
J dS
(E
(43)
dt

S
S

e=

(42)

for each closed line  which links the component, then



J
S
B/) dll
iS =
dS = (B

der of magnitude, so it is opportune, first, to render the variables concerned dimensionless. This is easily done by introducing the new dimensionless variables:

(45)

and Eq. (42) is satisfied.

In this way we must investigate the conditions given by
(40) and (44). These relations require a comparison of the or-

where the symbol indicates equal in order of magnitude.

In this way, the conditions in Eqs. (47) and (48) are respectively reduced to
 1

(52)

1

(53)

Naturally this result is always possible if the reference variables are chosen equal to the orders of magnitude of the relative variables in the regions of the space concerned. For example, to have the same order of magnitude for e and
e/
! it is
sufficient to choose Tc equal to the characteristic time of the
dynamics of the system. Thus, for dynamics of sinusoidal type
with frequency f it is sufficient to set T
1/f. From what has
been said previously, concerning admissible lines, it is clear
that for Lc we need to choose the characteristic length of the
element being examined.
At this point, parameters and , which the adimenstionalization has very naturally underlined, assume a particular
significance. It is noted that time and space enter only into
parameter , together with velocity c, which is a characteristic constant of the electromagnetic propagation phenomena.
By defining the characteristic wavelength of the electromagnetic field, c
cTc, we can say that is the ratio between
the characteristic length of the element and the wavelength,

LINEAR NETWORK ELEMENTS

Lc / c. Parameter can tell us whether the effects of the

electric field or those of the magnetic field prevail. More precisely, introducing the energy densities associated to the reference fields Ec and Bc and to the reference dielectric constant c and magnetic permeability c, we have
Wm =

1 B2c
,
2 c

We =

1
c Ec2
2

(54)

435

ia = i
+

l
Conducting
plates

Dielectric

and we can say that

2 =

Wm
We

(55)
b

If we could retain independent of , we could immediately

conclude that for a sufficiently small , Eqs. (52) and (53) are
both verified and that the error made by associating a single
voltage and a single current to a two-terminal element is, in
fact, on the order of . In reality, however, depends on ;
and when the latter tends to zero, it varies in a way that
requires investigation. If we imagine of varying by varying
the characteristic time of the dynamics Tc, we will have
0 for Tc and for Tc 0. In other words,
0
corresponds to the steady-state.
It is evident that, for the same element, the reference
fields Ec and Bc must of necessity be different if the rapidity
of the dynamics under consideration is different. Thus we can
distinguish between three fundamental cases: (1) when
tends to zero tends to zero like ; (2) when tends to zero
diverges like 1/; and (3) when tends to zero tends to a
finite value 0 0.
The Capacitor ( Tends to Zero as for 0). In these
conditions, Eq. (52) and hence (40) certainly hold for sufficiently small . This means that if we limit ourselves to considering only admissible lines, the line integral of the electric
field is with good approximation (the error goes to zero as
for 0) independent of the integration path. In other
words, the electric field is conservative with a good approximation. We note the fact that tends to zero like implies
that in the steady-state limit (
0) the reference magnetic
field and so also the field B is zero, while the corresponding
electric field is not zero. The annulment of B in the steadystate limit leads to the annulment of the current density J.
Thus, one concludes that the component under examination
must contain a material that blocks the passage of the electric
current. In other words, a layer of insulating material must
have been interposed between the two terminals a and b, as
illustrated in Fig. 18. Evidently this component corresponds
to the idea we have of a capacitor. A capacitor, in fact, consists of a pair of conducting plates from which two wires, the
terminals, are brought out. The plates may be of any shape
whatsoever, and they are separated by some dielectric material. Furthermore, we assume that the plates and the wires
are perfect conductors and that the dielectric is a perfect insulator.
Apparently we can say nothing about condition (42) because is proportional to for small values. In effect, however, in this case the total charge stored in the component is
zero, instant by instant, on the order of . In fact, the electric
field, which we have already said can be considered conservative on the order of , can be represented by a scalar electric

ib

Figure 18. Sketch of a capacitor: It consists of two conducting plates

separated by a dielectric.

potential. In this case the electric potential is the solution of

the Laplace equation within the dielectric because in an insulating material it is not possible to have free electric charge
(see, for example, Ref. 1). The boundary conditions for such a
problem are given by the electric potentials on the two conducting plates of the capacitor and, thus, at each instant, by
the differences between the potentials themselves and by the
regularity conditions at infinity. Here we are assuming that
there is no direct interaction with any other elements that
might be present. In this hypothesis, as we know, the solution
to the Laplace problem is, at each instant, unique (see again
Ref. 1) and so is the same as that of the steady-state problem.
In other words the dynamics of the electric field can be seen,
at each instant, as a succession of steady-state fields and the
time enters into the equation only as a parameter. In this
situation the charges on the two conducting plates can only
be equal in absolute value and opposite in sign, at each instant, and so the total charge must be zero (since the system
is insulated, it is assumed that it is initially not charged).
Thus, from Eq. (41) we have ia
ib. In conclusion, the condition ia
ib
i must be considered to be verified with the
same approximation as that by which the electric field can be
held to be conservative.
Once we have defined the limits within which it is possible
to associate a single voltage and a single current to the component being examined, we may ask ourselves which constitutive relation the element itself must respect. According to the
charge conservation law, the current is equal to the time derivative of the total charge Q deposited on the electrode toward which the reference arrow for the current direction
points:
i=

dQ
dt

(56)

Charge Q is, in turn, directly proportional to the electric field,

which is itself directly proportional to the voltage and so
Q = Cv

(57)

where the constant C is the capacitance of the capacitor (positive if the normal convention is assumed). Substituting Eq.
(57) into Eq. (56) we get Eq. (6).

436

LINEAR NETWORK ELEMENTS

As examples we recall that the capacitance of a parallelplate capacitor is C
 S/d, where S is the surface area of
the capacitor plates, d is the distance between them, and the
capacitance of a cylindrical capacitor is C
2l /ln(r2 /r1),
where l is the length and r1 and r2 are the radii of the internal
and external cylinders.
The Inductor ( Diverges Like 1/ for 0)
The case of the inductor can be dealt with in similar way. In
this case, Eq. (53) and hence (42) are verified for a sufficiently
small , and so it is possible to identify a single current i for
the element we are examining. It is to be noted that, as long
as diverges like 1/ for 0, it is necessary for the electric
field to be zero in the steady-state limit, while the magnetic
field and hence the current density field are not zero. Moreover, as the electric field in the steady-state limit regime must
be zero, the material has to be a perfect conductor, otherwise
it would not be possible to have an electric current without
an electric field. This means that in the component we are
examining there is a perfect conducting wire joining the two
terminals, as illustrated in Fig. 19. Thus, the element we are
examining corresponds to our idea of an inductor.
However, Eq. (52) and hence (40) are not necessarily satisfied in these conditions. In effect, nothing more can be said
unless one fixes how the conducting wire develops inside the
element. An inductor is made by winding many turns of conducting wire in the form of a coil and bringing the two ends
out at some distance from the coil. Let us consider line ,
obtained by closing line e shown in Fig. 19, which is completely outside the element, with a line i developing wholly
within the conducting wire. The line integral of the electric
field along  coincides with the voltage along e, since the
electric field in the conductor is zero. On the other hand, from
Eq. (37) we get



d
d
(58)
v e =
B n dS =
dt
dt
S
where  is the flux linked with . But  can be decomposed
into the sum of two terms, which corresponds to a suitable
choice for surface S. The first contribution, which we will
call i, is the flux linked with a line obtained by closing i

b
Figure 19. Sketch of an inductor: It is made by winding many turns
of conducting wire.

with a line that s that develops on the limit surface of the

element and joins the two terminals. The second, which we
will call e, is the flux linked with the line obtained by closing
e again with line s. Then we have
v e =

d
dt

di
dt


(59)

By varying e, the voltage ve varies because e varies,

whereas i does not vary. If at this point we hypothesize that
the coil ending in a and b within the component develops by
forming a large number of turns, we have
i e

(60)

and thus ve will in practice be independent of the external

line e. In this way we have achieved our purpose of defining
a single voltage for the element we are examining, the approximation being closer as the number of turns is increased.
This voltage coincides with the line integral of the electric
field along e, provided that such a line is wholly outside the
limit surface of the component itself and that, naturally, it is
admissible in the way we have previously specified.
We must now determine the constitutive equation of this
one-port. The flux i is directly proportional to the magnetic
field, which is, at each instant, directly proportional to the
current i flowing in the coil; that is,
i = Li

(61)

where the constant L is the self-induction coefficient of the

inductor (positive if the normal convention is assumed). At
this point, by utilizing Eq. (60) from Eqs. (59) and (61) we
deduce Eq. (7).
An an example we recall that the self-induction of a long
solenoid of length l, cross section S, and with N turns is given
by L
(N2S)/l.
The Resistor in Dynamic Operation
( Tends to 0 0 for 0)
In this case, Eqs. (52) and (53) are satisfied for sufficiently
small , and so it is possible to associate a single voltage and
a single current to the component being examined. It is to be
noted that as long as tends to 0 0 for 0, both the
electric and the magnetic fields do not go to zero in the
steady-state limit (
0). This means that there is a link
between a and b within the one-port that develops entirely
within a conductor material (J 0) with a finite conducibility
(E 0), as shown in Fig. 20. Two wires which we take to be
perfect conductors go from the terminals a and b to the ends
of a bar of ohmic material with infinite conducibility. Thus
this component is a resistor.
At this point one must deduce the constitutive relation of
the element under examination. Since the current i is directly
proportional to J, which in turn is directly proportional to E
according to Ohms local law (11), which in turn is directly
proportional to the voltage v, one deduces Eq. (5), where R is
the resistance of the resistor.

LINEAR NETWORK ELEMENTS

The value of R is not necessarily the same that one would

obtain in the steady-state limit. One can demonstrate that if
(see, for example, Ref. 1)
d = D  Tc

(62)

where D is the characteristic transverse length of the conductor material, then the field J has with good approximation
the same spatial distribution as in the steady state and so R
assumes the same value given by Eq. (15). Otherwise R depends on Tc or, likewise, on the characteristic frequency of the
dynamics. Parameter !d is called the characteristic diffusion
time. By introducing the penetration depth
Tc /(),
Eq. (62) can be written as
D

(63)

If condition (63) is not verified, most of the current flows in

the vicinity of the surface of the bar in a layer of thickness .
For example, the penetration depth for copper is equal to 2
mm at f
100 Hz.
The three limit cases that we have analyzed have led us to
consider three ideal one-ports: the capacitor, the inductor,
and the resistor. Naturally, in practice, such components are
never ideal, so it follows that the behavior that we have described can be present in the same component at the same
time. If, for example, the inductor wire is not a perfect conductor, as is the case in reality, Eq. (7) is modified. Because
of the finite conducibility, the behavior of the resistor is added
to that of the inductor and the constitutive equation becomes
v = Rpi + L

di
dt

(64)

where Rp is the resistance of the wire in the steady-state

limit. Equation (64) can also be thought of as the constitutive
equation of a more complex one-port consisting of the series
of an ideal inductor with an ideal resistor.
In general, an inductor consists of a large number of turns
concentrated in a limited volume, and so every turn will be in
close contact with other turns. Electrical contact between the
coils is avoided by means of an insulating varnish covering
the wire. The arrangement just described reminds us that of

i
+

+
+

Cp

Rd

(a)

(b)

Figure 21. (a) Equivalent circuit of a real inductor; (b) equivalent

circuit of a real capacitor.

the capacitor (the conducting plates are the turns, and the
dielectric is the insulating varnish) and leads us to consider
an overall capacity of the entire element, equivalent to the
effect of all the capacities between the individual turns. One
concludes that an equivalent and more refined circuit for a
real inductor is that shown in Fig. 21(a), where, of course,
both Rp and Cp are very small if the inductor is well-built.
A similar situation may be found in a wire-wound resistor.
Here too, the numerous turns needed to obtain the required
resistance cause the one-port to behave like an inductor.
When such an effect is not wanted, particular arrangements
are adopted to reduce the flux linked with the many windings
in the resistor. For example, one may wind not a single wire,
but one bent back on itself so that linked flux is practically
zero. Such resistors are called anti-inductive. In the same way
we have to consider that in the case of the capacitor the dielectric cannot be perfect. In such cases a conduction current
density field is added to the current density field 
E/
t in the
dielectric. Consequently, a more realistic equivalent circuit of
a real capacitor will be that shown in Fig. 21(b), where Rd
(dispersion resistance) will normally have to be very high. Although it may seem strange, for capacitors too it is sometimes
necessary to consider an inductor in series with it. This is due
to the fact that in some types of construction, the plates are
made by rolling two layers of conducting material with the
dielectric sandwiched between. The turns so formed make
it necessary to introduce a parasite inductance in the equivalent circuit.
MUTUALLY COUPLED CIRCUITS

Ohmic material

Rp

437

Figure 20. Sketch of a resistor: Two wires of perfect conductor connect the two terminals a and b to the ends of an ohmic material.

If a coil of the type described in Fig. 19an inductor thereforeis placed in the immediate vicinity of another analogous element, the flux linked with each of them will depend
on both the current that circulates in the first coil and that
which circulates in the second. We are, therefore in the presence of an intrinsic two-port that we will call mutually coupled circuits. Mutually coupled circuits are widely used in
communication circuits, in measuring instruments, and in
power systems. Transformers used in power networks that
transmit and distribute electric energy are coupled circuits.
Electric motors and generators can also be modeled by timevarying coupled circuits. We will limit ourselves to describing
the more simple, but nonetheless significant, case in which
there are two coils and the reciprocal coupling does not vary
in time.

438

LINEAR NETWORK ELEMENTS

Let us consider two coils wound on a toroidal-shaped magnetic iron (typically ferrite or special steel thin plates), as
shown in Fig. 22(a). The coils are constituted, respectively, of
N1 and N2 turns of wire coated with insulating varnish. If
approximation (60) is valid for both the coils, one can write
v1 =

d1
,
dt

v2 =

If we define the average fluxes of self- and mutual induction

21m

d2
dt

L1 i1
,
N1
M i
= 21 1 ,
N2

11m =

(65)

M12 i2
,
N1
L i
= 22
N2

(67)

2d = 22m 12m

(68)

12m =
22m

we can affirm that

where 1 and 2 are, respectively, the magnetic field fluxes
linked with coils 1 and 2 produced by currents i1 and i2 circulating in the two coils (the electrical conducibility of the two
wires is considered infinite).
To determine the relation between the two fluxes and the
two currents it is necessary to make some approximations. In
the limit 1 it is possible to ignore the effects due to the
displacement current. Let us assume also that the toroidal
loop is made of an ideal magnetic material, in which we can
ignore the effects due to nonlinear phenomena, such as saturation and magnetic hysteresis. Finally, we can also assume
that the effects of the eddy currents induced in the toroidal
loop because of the time variation of the magnetic field are
negligible (a magnetic iron material is usually an electric conductor). With these hypotheses, since the superimposition of
the effects is valid and the only sources of the magnetic field
are the currents circulating in the two coils, we may affirm
that the relation between fluxes and the currents must be
algebraic and, moreover, linear:
1 = L1 i1 + M12i2 ,

2 = M21 i1 + L2 i2

(66)

where L1, L2, M12, and M21 are four constants in time, independent of currents i1 and i2. The term L1i1 is the flux linked with
the first coil when the current i2 in the second coil is zero,
and L2i2 is the flux linked with the second coil when current
i1 in the first coil is zero. Therefore the coefficients L1 and L2
are, respectively, the self-induction coefficients of coils 1 and
2. The coefficients M12 and M21 are called the mutual induction coefficients: M12 represents the flux of the magnetic field
linked with coil 1 produced by a unitary current circulating
in coil 2 when i1 0, while M21 represents the flux of the
magnetic field linked with coil 2 produced by a unitary current circulating in coil 1 when i2 0.

>> 0

i1

i2

+
v1

N1

N2

(a)

i1
+

v2

v1

i2
+

L1

L2 v2

(b)

Figure 22. (a) Sketch of two coupled circuits; (b) circuital symbol for
two coupled circuits.

1d = 11m 21m ,

are the average dispersion fluxes at coils 1 and 2, respectively. In practice if the coupling is perfect, one can expect
1d and 2d to be zero. In other words, one may expect a current circulating in the first coil to produce, on average, the
same linked flux per coil in both the first and the second coils.
It can be easily demonstrated that this condition gives
L1 L2 = M12M21

(69)

For the mutual fluxes of magnetic fields and currents, one can
demonstrate a property of reciprocity analogous to that valid
for voltages and currents in resistive circuits. Consider the
case where i1 0 and i2 0: Current i1 in coil 1 may be
considered as the cause, and flux M21i1 linked with coil 2
may be considered as the effect. In the same way, let us consider the case in which i1 0 and i2 0: Current i2 may be
considered as the cause, and the flux M12i2 linked with coil 1
may be considered the effect. It is possible to show (see, for
example, Ref. 1), by using the equations for the steady-state
magnetic field, that the ratio between cause and effect in the
two coupled circuits with i1 0 is equal to the ratio between
cause and effect in the two coupled circuits with i2 0 and so
M12 = M21 = M

(70)

Combining Eqs. (65), (66) and (70), we obtain the constitutive

relations of mutually coupled circuits:
v1 = L1

di1
di
+M 2,
dt
dt

v2 = M

di
di1
+ L2 2
dt
dt

(71)

(These equations are not valid if the self- and mutual inductances are time-varying.) Two coupled circuits constitute a dynamic two-port: The values of the two voltages, v1 and v2, at
a generic instant do not depend only on the values of the two
currents at that instant, but also on the values that they assume in the neighborhood of that instant.
The self-induction coefficients are positive if we assume
the normal convention on both the ports. Instead, the mutual
induction coefficient can be positive or negative, according to
the reference chosen for the direction of the currents. For example, with the choice made in Fig. 22(a), the sign for M is
positive. Figure 22(b) reports the circuit symbol for two coupled circuits. The two terminals are countersigned for the reference direction of the currents that make M positive. If the
references for the direction of the two currents are both in
agreement or both in disagreement with the countersigns,
then M must be considered positive.

LINEAR NETWORK ELEMENTS

The Energy Properties of Coupled Circuits

The electric power absorbed by two coupled circuits is given
by
p(t) = i1 v1 + i2 v2 =

dWm
dt

(72)

where
Wm (i1 , i2 ) = 12 L1 i21 + Mi1 i2 + 12 L2 i22

(73)

Thus it is impossible to obtain a coupling coefficient greater

than one. When k 0, M 0, and there is no interaction
between the two inductors.
Consider the other limit casethat is, k 1. In this
case, as we have already seen, the coupling is perfect. It is
evident that a transformer, which in general is required to
furnish the most efficient energy transfer between the two
coils, must be designed and built as near as possible to the
perfect coupling conditions. Let us observe that when the coupling is perfect the energy stored is given by
Wm (i1 , i2 ) =

On the other hand it can be demonstrated that

Wm (i1 , i2 ) =

B2 /2) dv 0
(B

(74)

where is the permeability of the medium. Therefore,

Wm(i1,i2) L1i12 /2 Mi1i2 L2i22 /2 represents the energy stored
in the component and it is a quadratic form, which is positive
defined. Energy W(t0,t) which the coupled circuits absorb in
the time interval (t0,t) is given by
W (t0 , t) = Wm [i1 (t), i2 (t)] Wm [i1 (t0 ), i2 (t0 )]

(75)

As in the case of the inductor, the energy absorbed in the time

interval (t0,t) depends only on the values that the stored energy Wm(i1,i2) assumes at the extremities of the interval and
therefore depends only on the initial and final values of the
two currents i1 and i2, and not on their history. For example,
if the values of currents at instant t are equal to the values
they assume at instant t0, then the energy absorbed by the
component in the interval considered is zero, irrespective of
the waveform of the currents in the interval (t0,t). One notes
that if M12 M21 were not true, it would not be possible to
express the power absorbed as the time derivative of a quadratic function of currents only and so the energy absorbed
would also depend on the time history of the currents.
Coupled circuits store the electric energy that they absorb
in the form of magnetic field energy. The energy stored can be
recovered, even completely so, in the form of electric energy in
the circuit into which they are inserted. However, the electric
energy that can be supplied cannot be greater than that previously absorbed due to the fact that the energy stored is positive-defined. Therefore coupled circuits are passive and conservative two-ports.

1
M
L i +
i
2 1 1 L1 2

2

(78)

and can therefore be annulled, even with i1 0, i2 0 if the

condition i1 (M/L1)i2 holds. As long as this happens, the
magnetic field produced by the two currents must be zero at
every point in the space; that is, the field produced by current
i1 must cancel the field due to current i2 at every point, which
is a further justification for the expression perfect coupling.
Condition M2 L1L2 is, naturally, a limit condition that
can be approached by using, for example, a torus of ferromagnetic material with very high permeability ( 0). When
this condition holds, the lines of the magnetic field are practically confined in the magnetic material. The torus behaves as
if it was a flux tube for the magnetic field because the normal
component of B at the limit surface of the toroidal core is
practically zero and so the field in the surrounding medium
is much weaker. (The analogy with the current field that
flows in a conductor with electric conducibility much greater
than that of the surrounding space, in which it is embedded,
springs to mind.)
If the two coils are made so as to be described as two long
solenoids of length land thus to be schematized as tracts of
length of two infinite solenoidfor the coefficients L1 and L2
we have the following approximate expressions:
L1 =

N 21 S
,
l

L2 =

N 22 S
l

(79)

It is also assumed that the two cylindrical solenoids have the

same cross-section S. When the coupling is perfect the mutual
induction coefficient M is given by
M=

Perfect Coupling

439

N1 N2 S
l

(80)

The mutual induction coefficient is often expressed by the

coupling coefficient k as a function of the self-induction coefficients with the relation

From characteristic Eqs. (71), in the case of perfect coupling,

we obtain

M
k=
L1 L2

L
v1
= 1
v2
M

(76)

Because the energy stored in the two coupled circuits is positive-defined and the two self-induction coefficients are both
positive, the coupling coefficient must verify the inequality
|k| 1

(77)

(81)

which is, in fact, the relation between the voltages of an ideal

transformer with transformation ratio
n=

L1
M

(82)

440

LINEAR NETWORK ELEMENTS

i1 n:1

i1
iL

+
v1

L1

i2

L1

i1
+

v2

v1

n:1

i2
+

L*1

v2

(a)

(b)

FINAL CONSIDERATIONS

Figure 23. (a) Equivalent circuit of a perfect coupling; (b) equivalent

circuit of a nonperfect coupling.

From this it is easy to show that a perfect coupling is equivalent to a two-port consisting of an ideal transformer and an
inductor as illustrated in Fig. 23(a). In fact we have
v1 = L1

diL
d
i
= L1
i + 2
dt
dt 1
n

= L1

di
di1
+M 2
dt
dt

(83)

From the relations in Eqs. (79), (80) and (82) we obtain that
for a transformer with perfect coupling the transformation ratio is approximately given by
n=

ability, r (/0) 1. In such condition, indeed, L1 0

and k2 1. Moreover, within the limit r we have L*1
and so the magnetized current circulating in the inductor
of inductance L*1 must tend to zero and in consequence the
equivalent circuit in Fig. 23(b) is reduced to the single ideal
transformer.

N1
N2

(84)

Equivalent Circuit of a Nonperfect Coupling

The condition of the perfect coupling, as we have seen, is only
an ideal limit condition to which one may approach. In reality, toroidal magnetic material does not provide a perfect flux
tube and so the coupling coefficient, in absolute value, is less
than one, even if a little less. We can show, however, that
even with a nonperfect coupling it is possible to have an
equivalent circuit that uses the ideal transformer. In fact, for
any L1, L2, and M, with M2 L1L2, it is always possible to
decompose L1 (or L2) into the form
L1 = L1 + L1

(85)

In the introductory paragraphs to this article we stressed the

fact that the currents and voltages that concern a circuit in a
given operating condition are the result of two distinct requirements: that each component in the network should behave in a manner compatible with its own naturethe constitutive relationand that such behavior should be compatible
with the interaction imposed by the rest of the circuit. In this
article we have been concerned with the former aspect and
have shown that within the limit 0, not only for resistive
elements, but also for dynamic ones, such constitutive relations are reduced to relations between the voltages and currents at the terminals of the elements in question.
Interaction with the remaining part of the network is subject to two very simple laws, Kirchhoff s law for currents and
Kirchhoff s law for voltages. These laws are discussed in detail in NETWORK EQUATIONS and TIME DOMAIN CIRCUIT ANALYSIS.
In concluding this article we may show that, always in relation to the hypothesis 1, Kirchhoff s laws too are deducible from the Maxwell equations for the electromagnetic field.
Kirchhoff s law for voltages, which states that in a mesh
the algebraic sum of the voltages is equal to zero, is in reality
a direct consequence of the fact that a one-port, or more generally a couple of terminals of an n-pole, is inserted in every
branch of the mesh. The voltage between two terminals of any
circuit component is in fact, in the limit 1, independent
of the path (obviously we refer only to admissible paths) and
is therefore the same, whether if it is calculated along the
line a or along b c as in the example shown in Fig. 24).
In this light Kirchhoff s second law simply expresses


va + vb + vc =

where
L1 L2 = M 2

E dll =

d
dt

S
B dS
=0

(88)

S

(86)

and
L1 = L1

M2
>0
L2

Capacitor

(87)
Re

c
c
ge
lta
Vo urce
so

These considerations justify the equivalent circuit of a nonperfect coupling illustrated in Fig. 23(b). The inductance L1
is related to the dispersed fluxes. It describes the contribution
of the flux linked with the first coil due to the lines of magnetic field that are not linked with the other coil; for k2 1,
L1 0. L*1 is said to be the magnetization inductance, and
it takes account of the common flux at both the coils.
It is interesting to observe that a transformer designed and
produced to obtain the best performances possible tends to be
an ideal transformer. In fact, for the coupling to be perfect
it is necessary for the two coils to be strictly wound on a nucleus of ferromagnetic material with a high relative perme-

r b
isto

ib

Re

e
sis

ie

tor

Node
1

ia

a
a

u
Ind

cto

Figure 24. Sketch of an electrical circuit composed of two resistors,

a generator, an inductor, and a capacitor.

LIQUID CRYSTAL DISPLAY

where a b c and va, vb, and vc are, respectively, the

voltages across the inductor, the resistor (b), and the voltage
source with the reference directions in agreement with the
orientation of a, b, and c. In fact the time derivative of the
magnetic field flux linked with the mesh can always be ignored provided that does not pierce the limit surfaces and
the currents vary slowly in the time, which certainly holds
true in the limit 1.
Kirchhoff s law for currents is also deducible from Maxwell
equations, in the limit 1. In fact the algebraic sum of the
currents in a nodefor example, the node labeled 1 in Fig.
24can differ from zero only if, in accordance with the charge
conservation law, on the node itself there is an increase or a
reduction of the electric charge Q1:



dQ1
S=
(89)
ia + ib + ie =  J dS
dt
1
where 1 is the node surface. Outside the one-ports, the electric field is quasi-conservative and thus can be expressed by
a scalar potential. In these conditions the behavior of the field
is the same as that which there would be in rigorously static
conditions, so the charge accumulated on the node is negligible, given its smallness. In consequence we still have
dQ1 /dt 0, provided that the voltages vary very slowly in
time, which is certainly so in the limit 1.
Referring to Fig. 24, where a simple circuit is illustrated
by putting the spaces occupied by the single components in
evidence, we note that in the circuit model the space can always be subdivided into parts, in each of which a simplified
model of the electromagnetic field can be considered. In the
region a, where there is an inductor, the model is that of the
quasi-stationary magnetic field: In Maxwell equations the
density of the displacement current (E/t) is ignored but
not B/t ( as 1/ for 0). In the region d, where
there is a capacitor, the model is that of the quasi-stationary
electric field: In Maxwells equations, B/t is ignored but not
E/t ( 0 as for 0). Finally, in the regions b, c,
and e where there are, respectively, a generator and two resistors, both the terms B/t and (E/t) are ignored and the
model is that of the quasi-stationary current field ( 0
0 for 0). In all these models the two fields E and B are
separated, and so, if the boundary conditionsthat is, the
voltages or currents at the terminals of the one-portsare
assigned, then the equations for each of them can be resolved
independently and univocally. It is this which makes it possible to express the constitutive equations as relations between
voltage and current. Then outside the components the electric
field must verify the condition E dl 0 for each admissible closed line that does not pierce the limit surfaces, and
the current density field must verify the condition

J
dS 0 for every closed surface that does not cut the limit
surfaces. These equations express, respectively, the Kirchhoff
law for the voltages and the Kirchhoff law for the currents.
As a consequence, the boundary conditions of single oneportsthat is, the voltages and currents at their terminals
are subject to the two Kirchhoff laws. Note that the Kirchhoff
laws are rigorously exact in steady state.
This way of interpreting circuit models allows us on the
one hand to recognize the limitswhich today we are approaching nearer and nearer as studied in electromagnetic
compatibilityand on the other to observe its enormous sim-

441

plifying possibilities: The solution of a circuit, even the simplest (such as that shown in Fig. 24), in terms of the electromagnetic field would be practically impossible.
BIBLIOGRAPHY
1. R. M. Fano et al., Electromagnetic Fields, Energy, and Forces, New
York: Wiley, 1960.
2. W.-K. Chen (ed.), Circuits and Filters Handbook, Cleveland and
Boca Raton, FL: CRC Press and Piscataway, NJ: IEEE Press,
1995.
3. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 4th ed., New
York: Oxford Univ. Press, 1997.
Reading List
L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits, New York: McGraw-Hill, 1987.

LUCIANO DE MENNA
GIOVANNI MIANO
University of Naples Federico II

LINE CODING. See INFORMATION THEORY OF MODULATION

CODES AND WAVEFORMS.

LINE ECHO CANCELLATION. See ECHO CANCELLATION

FOR SPEECH SIGNALS.

LINKED LISTS. See LIST PROCESSING.

TIME-DOMAIN NETWORK ANALYSIS

219

TIME-DOMAIN NETWORK ANALYSIS

Time-domain analysis of nonlinear networks is a complicated
process composed of several steps. To avoid inaccuracies and
possible confusion, this article covers all such steps, starting
with a few definitions. Standard network elements are reviewed in the section entitled Basic Concepts and Definitions in a form suitable for network formulations. The section entitled Kirchhoff s Laws briefly summarizes
Kirchhoff s laws and introduces the concept of cuts, needed
later in state variables. The section entitled Nodal and Loop
Equations repeats nodal and loop equations, a concept
taught in every course of network analysis. The two methods
are suitable for hand solutions, but are not sufficiently general for computer applications.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

220

TIME-DOMAIN NETWORK ANALYSIS

Network equations are normally solved by triangular decomposition, a method which may not be known to the reader.
A very brief summary is provided in the section entitled Solutions of Network Equations, along with the Newton
Raphson method, used for solution of nonlinear equations.
The section entitled Graphs covers basic concepts of graph
theory, to the extent needed later for the various methods of
collecting the network equations. One such method, state
variables, is covered in the section entitled State Variables.
It is still used for theoretical studies but is not suitable for
computer applications, and we explain the difficulties. A more
general method, the tableau, is explained in the section entitled Tableau. It keeps as many equations as possible, and it
pays the price by leading to very large systems. The method
is useful only if a complicated sparse matrix solver is available. The best method to write network equations is the modified nodal. It is covered in the section entitled Modified
Nodal Formulation, to an extent sufficient for understanding. References will help the reader in further studies.
Time-domain solutions are done by methods which replace
derivatives by special expressions. The subject is divided into
two parts. The section entitled Simple Integration Methods
explains three simpler methods, where various problems can
be easily explained. Although they are simple, they are extensively used in commercial simulators and are quite practical.
More advanced integration formulas are covered in the section entitled Advanced Integration Methods, where we concentrate on the modern backward differentiation formulas.
With these preliminary steps we are in the position to explain time-domain solutions. The subject is divided into two
parts. The section entitled Linear Networks deals with the
integration of linear algebraic differential equations and derives simple formulas which are easy to use. The section entitled Nonlinear Networks explains integration methods for
nonlinear networks. It points out that nonlinear capacitors
and inductors must be described by their charge and flux
equations, and it shows how to formulate the Newton
Raphson iteration procedure.
Recent advances in semiconductor technology made it possible to use transistors as switches. They are reliable and fast
and opened completely new areas. The section entitled
Switched Networks introduces the reader to the problem of
switched networks and offers a simple solution how to analyze switched networks in time domain.
The bibliography at the end of this article lists publications
for additional study.

be described for the purposes of network analysis by a collection of these basic elements.
Node is a point where two or more elements are electrically
connected together. If the node can be accessed from the outside, then it is called the terminal.
With these basic definitions we can turn our attention to
the concept of voltage and current.
Voltage is electrical force which is applied across some
element and which drives the flow of electrons through the
element. The simplest source of voltage is a battery with its
and terminal. If any electrical element is connected to
these two terminals, some amount of electrons will flow
through the element and this flow is called the current. The
definition of current direction was introduced long before the
existence of electrons was discovered, and the accepted positive direction of current in network analysis is opposite to the
flow of electrons: from the more positive point (or from ) to
a less positive point (or to ). For general voltages within the
network we will use the letter V, and for currents flowing in
the network we will use the letter I.
Ideal voltage source is a fundamental element in network
analysis, and its symbol is in Fig. 1. Positive direction of cur-

i
i
+

+
E

V0

j
j
j
j
Voltage source Current source Conductor Capacitor
and resistor
i

I0

j
Inductor

I
I1
j

m
Current-controlled
current source

Voltage-controlled
current source

I2

+
I

BASIC CONCEPTS AND DEFINITIONS

Solutions of networks require unified notation for which we
need the necessary definitions. Most of them are known to the
reader, but some definitions and expressions may somewhat
differ. To start we define the concept of ground, node, and
electrical element.
Ground usually refers to our earth, but for network analysis it is the chassis or the metal construction into which the
electric network is built.
Electrical element is any product functioning in the network. The simplest elements will be defined in this section.
The function of most electronic devices, like transistors, can

Current-controlled
voltage source

Voltage-controlled
voltage source
I

j
m
Operational amplifier

M
i

L1

L2

I1

I2

Transformer

Figure 1. Elements and their symbols.

TIME-DOMAIN NETWORK ANALYSIS

rent is always from the to the sign, and this applies to

the voltage source as well. If in the application the current
actually flows the other way, it is assigned the minus sign.
This unified way of defining currents is maintained throughout. It is advantageous to distinguish the voltage supplied by
the voltage source from the general voltages in the network,
and we will use the letter E. Considering nodal voltages with
respect to ground, the voltage source properties are described
by
Vi V j = E

(2)

In our considerations we will always assume that the resistor

does not change with time. It may change with the current
flowing through it or with the voltage across it, and in such a
case the resistor is nonlinear. If the value of R is independent
of all external influences, then the resistor is linear. In practice, some nonlinearity is always present, but very often we
take advantage of the linearity assumption because it greatly
simplifies all mathematical steps.
Capacitor is one of two fundamental elements whose behavior depends on the derivative with respect to time. It is
usually denoted by the letter C. We will skip many details
and only state here that it can hold a charge, usually denoted
by the letter Q. The current flowing through the capacitor is
defined by
I=

dQ(V )
dt

(3)

If the capacitor is linear, the expression simplifies to

I =C

dVi (t) dV j (t)

dt

The capacitance is measured in farads. In Fig. 1, V0 is the

initial voltage on the capacitor.
Inductor is the other element whose behavior depends on
the derivative with respect to time. It is usually denoted by
the letter L, and its symbol is in Fig. 1. If a current flows
through the inductor, a flux is formed and the voltage
across the inductor is defined by
Vi V j =

d
(I)
dt

(5)

(1)

An ideal voltage source theoretically maintains its voltage

across its terminals no matter what other elements are connected to it. This should be true even if it is a short circuit,
an impossible situation. All actual voltage sources have a resistance in series, called the internal resistance. If E 0, the
ideal voltage source behaves as a short circuit.
Ideal current source is another fundamental source. Its
symbol is in Fig. 1. Similarly as in the case of the voltage
source, this element theoretically maintains its current no
matter what is connected to it. This should theoretically be
valid even for an open circuit, another impossible case. Every
practical current source will have an internal resistor in parallel to it. Similarly to the above, it is advantageous to distinguish in writing the current delivered by the current source
from the other currents in the network. We will use the letter
J. If J 0, then the element becomes an open circuit.
Resistor is the most common element. It is usually denoted
by the letter R, and its resistance is measured in ohms. Inverted value of the resistance is called the conductance. It is
usually denoted by the letter G 1/R and is measured in
siemens. The symbol for the resistor is in Fig. 1. For the purposes of network analysis, it is convenient to consider nodal
voltages, measured with respect to ground. The current
through the resistor is expressed in terms of nodal voltages
by the equation
I = G(Vi V j )

221

(4)

In Fig. 1, I0 is the initial current flowing through the inductor.

If the inductor is linear, then its inductance is measured in
henry and Eq. (5) simplifies to
Vi V j = L

dI(t)
dt

(6)

Dependent sources form another set of important elements.

Altogether we have four dependent sources:
Voltage-controlled current source (VC) measures a voltage
somewhere in the network and adjusts the current at some
other terminals. Its symbol is in Fig. 1, and in terms of nodal
voltages its performance is expressed by the equation
I = g(Vi V j )

(7)

The constant g is called the transconductance, is measured in

siemens, and the current flows from the terminal k to terminal m. Note that if the difference of the voltages is zero, the
current will be zero and the source part will become an open
circuit.
Current-controlled current source (CC) measures the current flowing through the short circuit between terminals i and
j and delivers a current flowing from terminal k to terminal
m. Its performance is expressed by
I2 = I1

(8)

where is a dimensionless constant.

Voltage-controlled voltage source (VV) measures a voltage
between terminals i and j and forms a voltage source between
terminals k and m. In terms of nodal voltages, its performance is expressed by
Vk Vm = (Vi V j )

(9)

where , the amplification factor, is a dimensionless constant.

Current-controlled voltage source (CV) measures a current
between i and j and delivers voltage between terminals k and
m. In terms of nodal voltages, its performance is expresed by
the equation
Vk Vm = rI

(10)

where r is the transresistance measured in ohms. In the

above explanations we assumed that the conversion coefficients g, r, , and are constants. They may depend on voltage or current and in such case they will be nonlinear functions of the controlling variable.
Many more elements can be defined, but the above are fundamental and all other elements can somehow be referred to

222

TIME-DOMAIN NETWORK ANALYSIS

these ones. It is convenient, however, to introduce two more

ideal elements.
Operational amplifier (OP) is a voltage-controlled voltage
source with an infinitely large gain . Its symbol is given in
Fig. 1. Often the terminal m is internally grounded and then
the symbol has only the terminal k, with the line starting
from the tip of the triangle. Using Eq. (9), first divide the
equation by and then let . This results in Vi Vj
0, or Vi Vj. In other words, when analyzing a network with
an ideal operational amplifier, then instead of performing
similar operations as just described, we simply let both input
terminals have the same voltage with respect to ground.
Transformer in its technically realizable form is an element made of two (or more) closely placed inductors, sometimes constructed on a ferromagnetic core. If only two linear
inductors are present, then the transformer is described by
two equations

dI1
dI
+M 2
dt
dt
dI2
dI1
+ L2
Vk Vm = M
dt
dt
Vi V j = L1

(11)

where L1 and L2 are the primary and secondary inductors and

M is the mutual inductance. For additional information the
reader is referred to any introductory book on network theoryfor instance, Ref. 1.
KIRCHHOFFS LAWS
For a systematic writing of equations we need Kirchhoff s
laws and some additional rules.
The first rule states that a current is positive when it flows
away from a node. This is in addition to the previous rule that
positive current flows from to . Thus if we consider the
independent voltage source from Fig. 1, in the equations the
current at the sign will be taken as positive, while the current flowing into the node will be taken as negative.
Kirchhoff discovered two fundamental laws: one for currents, KCL, and one for voltages, KVL.
KCL states that the sum of currents flowing away from
any node is equal to zero. This means that some currents will
flow from the node (and have positive signs), while others will
flow to the node (and have negative signs).
KVL states that the sum of voltages around any closed loop
is equal to zero.
KCL has yet another definition which we will need later.
Assume that we pull two sections of a network apart and consider only the wires which connect them. If we take the currents flowing in the connecting wires from left to right as positive and the others as negative, then this form of KCL states
that the sum of currents in these wires will be zero. Rather
unfortunately, those who introduced this theory gave it the
name cut. The cut is of course only in our mind, nothing is
changed in the network.
We will explain these laws in more detail in the following
sections, but some additional notation has to be understood.
In the section entitled Basic Concepts and Definitions we
stated that if the capacitor is linear, then its current is the
derivative of the voltage across it with respect to time,
multiplied by the constant C. The dual was stated for a linear
inductor. As will be explained later, analysis of nonlinear net-

works is always done by repeated solutions of linearized approximations. It is thus advantageous to study first linear
networks, which we will do here.
Linear networks can be looked upon from many points of
view. We can seek time-domain solutions, like in nonlinear
networks. In addition, we can apply frequency-domain analysis and find absolute value and phase for a sinusoidal input
signal in steady state. To give the reader an easy reference to
subjects in other chapters, we will introduce a special symbol
for the derivative:
s

d
dt

(12)

If the network is linear, then s is also the Laplace transform

operator, used in frequency domain analysis. In time domain
it is the symbol for the derivative. Consider a linear capacitor
for which I sC(Vi Vj). In frequency domain the operator s
will be attached to the constant C. In time domain it will be
attached to the voltages, to indicate their derivatives. With
these introductory explanations we can now turn to the methods for setting up network equations.
NODAL AND LOOP EQUATIONS
Nodal and loop equations are the simplest methods to write
network equations. They are the subject of every fundamental
course on network analysis. The methods are not general and
are suitable only for hand calculations and small networks.
We will start with the more important nodal formulation
which is based on KCL.
Consider the network in Fig. 2. The bottom line represents
ground. The voltages V1 and V2 are nodal voltages, measured
with respect to ground. The network has all elements which
can be used in nodal analysis without some additional steps.
They are the current source, capacitor, conductance, and the
voltage-controlled current source, VC. Note that in nodal formulation it is advantageous to work with conductances and
not with resistances.
When writing the sum of currents for any node, we do not
know anything about the voltages and we are free to think
that this particular node is the most positive one. This means
that all currents through passive elements must flow away
from the node under consideration. Using the rules about the
signs of currents we write for node 1
G1V1 + sC(V1 V2 ) J = 0
and for node 2
sC(V1 V2 ) + G2V2 g(V1 V2 ) = 0

V2

V1
C
G1
J

G2
g(V1 V2)

Figure 2. Network for nodal analysis.

TIME-DOMAIN NETWORK ANALYSIS

In mathematics we normally place known values on the right

and collect terms multiplied by the same variable. This leads
to

EG

(G1 + sC)V1 sCV2 = J

223

1/R

JR

(sC g)V1 + (G2 + sC + g)V2 = 0

Figure 4. TheveninNorton theorem.

Equations describing linear networks can be always put into

matrix form:

(G1 + sC)
(sC g)

sC
(G2 + sC + g)


  
V1
J
=
0
V2

If we assign unit value to each element except g 2, the

matrix reduces to

1+s
2 s




s
V1
J
=
3 + s V2
0

It is solved by any available method. If we were interested in

the output, the result would be V2 J(2 s)/(3 2s). For
frequency-domain analysis we substitute s j and let J
1. Repeating for a number of frequencies will provide frequency-domain response of the network. In time domain the
operator s will be replaced by a numerical expression representing the derivative.
Loop equations are based on KVL. It is a method which
can be used only for planar networks: We must be able to
draw the network on a paper without any element crossing
another element. The concept of ground is not needed in this
formulation. The network in Fig. 3 contains all elements
which can be used in this formulation without additional
steps. In the figure we indicated fictitious loop currents, circulating in each loop. Note that through the resistor R2 flow two
currents in opposite directions. When writing the sum of voltages around the loop, we consider its circulating current as
positive. This leads to the equation

right and collecting terms we obtain

(R1 + R2 )I1 R2 I2 = E
(R2 + r)I1 + (R2 + sL r)I2 = 0
In matrix form this is


(R1 + R2 )
(R2 + r)

Suppose now that we would like to analyze the first network

by the loop method and the second by the nodal method. It is
not possible directly and we must apply some transformations
before we can proceed.
The TheveninNorton transformation states that a voltage
source with a resistor in series can be transformed into a current source with the same resistor in parallel. As far as the
other parts of the network are concerned, there will be no
difference. The transformation is schematically shown in Fig.
4. The sources are coupled by a law which looks like Ohms
law, but applies to the sources:
E = RJ

where our assigned current flows through the source from

to and thus its contribution must be taken negatively. For
the second loop we will consider I2 as positive and we write
the sum of voltages
R2 (I2 I1 ) + sLI2 + r(I1 I2 ) = 0
The current through CV flows from to and thus the voltage it contributes is taken as positive. Transferring E to the

V1

+
I1

R2

I2

r(I1 I2)

Figure 3. Network for loop analysis.

R1

or J = GE

(13)

As indicated in Fig. 4, we can go with the transformation in

either direction.
As an example, we will transform the current sources in
Fig. 2 into voltage sources. The transformed network is in
Fig. 5. To proceed, we must express the dependent source in
terms of the unknown current, V1 V2 I/sC. Afterwards
we must find the voltage V2 as a sum of the voltages delivered
by the dependent source plus the voltage across the resistor
R2. The result is, of course, the same as before, but we had to
go through a number of additional steps. Similar problems




E
I1
=
0
I2

Selecting r 2 and assigning unit values to all other elements reduces the equation to





2
1
I1
E
=
1 1 + s I2
0

R1 I1 + R2 (I1 I2 ) E = 0

R1

R2
(R2 + sL r)

JR1

V2
R2

+
gR2(V1 V2)

Figure 5. The network in Fig. 2, transformed for loop analysis.

224

TIME-DOMAIN NETWORK ANALYSIS

would be with the transformation of network in Fig. 3 for

analysis by the nodal method. It can be seen that the transformations make the whole process fairly complicated and unsuitable for computerized programming. Other methods had
to be invented: the state variables, the tableau, and the modified nodal formulations. To proceed with their explanations
we will need some fundamental concepts of the graph theory,
but before that we discuss methods for the solution of systems
of equations. Details of the various transformations can be
found in Ref. 1.
SOLUTIONS OF NETWORK EQUATIONS
Only the smallest networks can be solved by hand; all practical networks must be solved by computer, and this leads us
to the methods used in such solutions.
Equations describing linear networks are expressed in the
form of a matrix equation
TX = W

(14)

Here T is the system matrix, X are the system variables, in

most cases voltages and/or currents, and W denotes the
sources. Our examples in Figs. 2 and 3 were brought to this
final matrix form.
Networks with up to 1000 nodes are almost always solved
by a process called LU or triangular decomposition. Many
books describe this process, and the reader is referred to other
sourcesfor instance, Refs. 25. However, because we will be
referring to it in the following, at least some general concepts
will be given.
Suppose that we manage to decompose the matrix T into
the product of two matrices, T LU where the matrix L is
lower triangular, with all the entries above the main diagonal
being zero. The U matrix has all entries below the main diagonal zero and, in addition, all entries on the main diagonal
are units. The system in Eq. (15) is rewritten as
LUX = W

(15)

Suppose that we now introduce a new definition,

UX = Z

f 1 (x1 , x2 ) = 0
f 2 (x1 , x2 ) = 0

(16)

(17)

Because the matrix is triangular, a simple process, called forward substitution, can be used to find Z. Once this is known,
we go back to Eq. (16) and find X by a similarly simple process, called back substitution. The important point of this process is that the decomposition into the LU matrices costs
n3 /3 multiplication/division operations, while the forwardback substitution costs only n2 operations, n being the size of
the matrix. If the right-hand side changes, only new forward
and back substitution is needed, and the LU decomposed matrix is re-used.
Almost all larger networks have system matrices with
many zeros, and a special processing, called sparse matrix decomposition, can be used. Computer codes may be fairly com-

(18)

Expand each equation into a Taylor series about the point

x1 x1 and x2 x2. The expansion is

f1
x1 +
x1
f
f 2 (x1 , x2 ) + 2 x1 +
x1

f 1 (x1 , x2 ) +

f1
x2 + higher terms = 0
x2
f2
x2 + higher terms = 0
x2

(19)

If we neglect the higher terms, we can rewrite these equations as

f1
x1 +
x1
f2
x1 +
x1

f1
x2 = f 1 (x1 , x3 )
x2
f2
x2 = f 2 (x1 , x2 )
x2

(20)

This is a set of linear equations which can be written in matrix form:

x1

This cannot be solved yet, but inserting into Eq. (15) we can
write
LZ = W

plex, but sparse matrix solutions are done with a cost approximately proportional to n and not n3. In fact, the discovery of
sparse matrix processing made it possible to write practical
programs for the analysis of quite large networks.
All network solutions eventually reduce to the solution of
a system of linear equations. In frequency domain, s is substituted by j and programming is in complex. In time domain,
the derivatives are replaced by an approximation which
changes the system of algebraic and differential equations
into a system of algebraic equations only.
Nonlinear networks are solved by a method leading to a
repeated solution of linear approximations. The method is
known as the NewtonRaphson iteration, and we will explain it with a set of two equations in two unknowns:

x1

f1




x2
x1 = f 1 (x1 , x2 )
f 2 x2
f 2 (x1 , x2 )
x2

(21)

The matrix on the left is called the Jacobian; we will denote

it by the letter M, the vector of unknowns by X, and the
right-hand side by f,
X = f
MX
Since we neglected higher terms, this is not a final solution.
We denote the kth step with the superscript k and rewrite the
process as two equations:

X k = f k
Mk X
Xk
Xk+1 = Xk + X

(22)

In the first one we apply LU decomposition to the matrix and

find X. The second equation finds new X, closer to the correct solution. With it we go back to the first equation, and so
on. If the process converges, the xi will eventually become
very small and we stop the iteration.

TIME-DOMAIN NETWORK ANALYSIS

GRAPHS

C3

Network formulations suitable for computer applications require at least a few graph concepts, and we devote this section
to the subject (2).
Graph theory attempts to extract basic properties of a network without giving any details about the network elements.
An element is replaced by a line in which the assumed direction of the current is indicted by an arrow. For passive elements we are free to select this direction. Sources have their
current directions given by the previous rules, and the arrow
must agree with them: For the voltage source the arrow will
go from to , for the current source it will be the direction
indicated at the current source symbol.
Consider the graph in Fig. 6 representing some network
with six elements, replaced by directed graphs. Nodes are indicated by numbers in circles. For nodes 1, 2, and 3 we write
three KCL equations:

I1 + I4 + I6 = 0
I2 I4 + I5 = 0
I3 I5 I6 = 0
They can be written in matrix form:

0
0

0
1
0

0
0
1

1
1
0

0
1
1

I1

I2

1
0

I3
0 = 0
I4

1
0
I
5
I6

225

6
C2
C1

Figure 7. Graph with a tree.

To work with another formulation method, the state variables, we need additional graph concepts of the tree and cotree. Consider Fig. 7, where we have used the same graph but
where we selected a tree, indicated by bold lines. A tree is
such a selection of lines of the graph which connects all nodes
but which does not close a loop. Directions of the arrows are
again arbitrary, except for lines representing sources. The
thin lines represent the co-tree. The figure also shows three
cuts, Ci. Each cut goes through only one line of the tree and
as many lines of the co-tree as necessary to separate the network into two parts. If we sum the currents in these cuts
but taking the direction of the tree line as positive, we end up
with the following set of equations, written in the sequence of
the cuts Ci:

I1 I5 + I6 = 0
I2 I4 I5 + I6 = 0
I3 I4 I5 = 0

or

In matrix form
AI = 0

(23)

The matrix A is called the incidence matrix. It also couples

nodal voltages, Vn, to the voltages across the elements, Vb, by
the equation
Vb = AT Vn

0
0

0
1
0

0
0
1

0
1
1

1
1
1

(24)

where the superscript T denotes the transpose of A. Equations (23) and (24) will be needed to explain the tableau formulation.

I1

I2

1
0

I3
1 = 0
I4

0
0
I
5
I6

or briefly
QI = 0
In selecting the tree we used the following sequence of rules:

2
1

Figure 6. Graph for incidence matrix.

1. Assign orientations to all lines.

2. Select a tree.
3. Assign consecutive integers starting from 1 to the lines
of the tree and continue numbering the lines of the cotree.
If we follow these three steps, it will always be true that the
matrix Q will have in the left partition a unit matrix, followed
by a partition describing directions of the co-tree:
Q = [1 | Qc ]

226

TIME-DOMAIN NETWORK ANALYSIS

Similarly as in the case of the incidence matrix, tree (subscript t) and co-tree (subscript c) voltages and currents can be
related by means of the Qc matrix:
It = Qc Ic
Vc =

QTc Vt

L7

(25)

G4

(26)

C3

+
C2

E1

Complete derivations of these equations can be found in Ref.

2. We will need Eqs. (25) and (26) when we speak about the
state variable formulation.

C6

G5

STATE VARIABLES
Historically, state variables were the first method used to
write equations for larger networks. The idea was to reduce
the system to a set of first-order differential equations. Over
the years, many attempts were made to write a general analysis program based on state variables, but none of them succeeded. As a result, this method can be used for relatively
small networks, mostly for manual solution. It is useful for
theoretical studies, and it is still applied in some disciplines.
A system of first-order differential equations can be written in matrix form as
X = AX + BW

(27)

On the left is the derivative of the X vector, composed of voltages and currents, and W describes the sources. This equation
is usually accompanied by another matrix equation for the
outputs:
Y = CX + DW

7
1

3
3
2

6
5

Figure 8. Example for state variables.

The last four columns create the matrix Qc. In the next step
we take Eqs. (25) and (26) and put them into one matrix equation:

(28)

In our explanations we will use only Eq. (27). The graph theory and the Q matrix which were explained in the previous
section related tree and co-tree voltages and currents by
means of Eqs. (25) and (26). Importance of the equations lies
in the fact that independent variables are tree voltages and
co-tree currents. Because in (27) we need the derivatives, consider the expression I C[dV(t)/dt]. It indicates that we
should retain capacitor voltages as independent variables,
which is helped by taking capacitors into the tree. Dually,
derivatives of currents appear in V L[dI(t)/dt]. The derivatives should be retained, which is helped by placing inductors
into the co-tree. In practical networks we often experience situations where capacitors form a loop and thus not all can be
taken into the tree. A dual situation may also happen with
the inductors.
Independent voltage sources also require special attention:
Their voltages are known and thus cannot be considered as
dependent variables. This means that the voltage sources
graph lines must be taken into the tree. Dually, current
sources must be taken into the co-tree.
We will demonstrate some of the problems on the small
network and its graph in Fig. 8. Only two capacitors can be
taken into the tree, and the inductor is in the co-tree. Using
the graph we set up the Q matrix as explained in the previous
section:

1 0 0
1
0
0 0

Q = 0 1 0 1
1
1 0
0 0 1
0 1 1 1

0
QTc

Qc
0




It
Vt
=
Ic
Vc

Writing the matrix and inserting into the column vectors expressions describing properties of the elements we obtain one
matrix equation:

0
0

0
0

0
0
0
1
1
1
0

0
0
0
0
1
1
1

1
1
0
0
0
0
0

0
1
1
0
0
0
0

0
1
1
0
0
0
0

0
E1
I1

0
V2 sC2V2
V sC V
1
3 3 3

0 G4V4 = V4

0 G5V5 V5

0 sC6V6 V6
0
I7
sL7 I7

As an intermediate step we must eliminate all variables except V2, V3, and I7, namely, the tree voltages and co-tree currents. After a number of steps which we omit, we get the preliminary result

C2 + C6
C
6
0

dV2 /dt
0

0 dV3 /dt
L7
dI7 /dt

G5
G4 G5
G5
G5
=
0
1

C6
C3 + C6
0

G4 E
V2
0

1 V3 + 0
0
0
I7

This is still not the state variable form, because there is a

matrix on the left. Our matrix happens to be nonsingular and
could be inverted to get the form Eq. (27). In many situations
the matrix on the left turns out to be singular and additional

TIME-DOMAIN NETWORK ANALYSIS

eliminations are necessary. Our example did not have any dependent sources. If present, they contribute with algebraic
equations which must also be eliminated. As can be seen,
state variable formulation creates so many problems that it
was effectively abandoned in computer applications. Its usefulness seems to be in theoretical studies of relatively small
problems. We do not recommend its use, but we felt that some
explanations are necessary. Details on state variables can be
found in many booksfor instance, in Refs. 6 and 7.

1
1

0
1

Y b V b + Z b I b = Wb

(29)

To show that this is true, for instance, for the voltage source
defined by Vb E, select Yb 1, Zb 0, and Wb E. Four
terminal networks, like the dependent sources, are represented by two equations and their graphs must have two
graph lines: one for the input and one for the output. The
reader should test validity of these statements for all networks in Fig. 1. Details can be found in Ref. 2.
Equations (23), (24), and (29) can be collected into one matrix equation:

Yb
0

AT
Vb
0

0 Ib = Wb
0
Vn
0

0
Zb
A

(30)

This is the tableau formulation. Note how simple it is to write

it once we have set up the incidence matrix.

V2

V3

0 1

V4

R2
sC3

0
1
1

I1

J1

I2

I3

I4

Vn1
Vn2

Figure 10. Tableau matrix equation for example in Fig. 9.

We will use one example to indicate how the system matrix

is set up. Consider the network in Fig. 9 with its graph. The
incidence matrix is



1 1
1 0
A=
0 0 1 1
The network has four branch voltages, Vb, four branch currents, Ib, and two nodal voltages, Vn. The elements are described by the equations I1 J1, V2 R2I2, V3 sC3V3, and
V4 G4V4. The system will have the size 10. Filling the entries we obtain the tableau matrix shown in Fig. 10. The matrix has 100 entries, but only 21 are nonzero and only three
would be real numbers. Had we used nodal formulation, the
network would be described by two equations only. This
clearly shows that the tableau is useful only on computers
and only if an appropriate sparse matrix solver is available.
MODIFIED NODAL FORMULATION
Modified nodal formulation (9) is the method used in practically all modern simulators. It is based on nodal formulation
to which additional equations are added as needed. Recall
from the section entitled Solutions of Network Equations
that only four elements can be used in nodal formulation directly: current source, capacitor, conductor, and voltage-controlled current source (VC). Also recall that TheveninNorton
transformations can help, but the steps become very difficult
for programming.
To clarify the ideas consider the network in Fig. 11 but
think of the inductor as replaced by the current which flows

V1

1
1

This method is more modern than state variables (8), but it

still has problems. In some way it does exactly the opposite
to the state variables: Instead of eliminating as many equations as possible, the tableau retains all of them. This would
not be a good idea, except for the fact that the equations are
very sparse and sparse matrix methods can be used. Recall
that the price of sparse matrices processing is approximately
proportional to n instead of n3, as is the case for full matrices.
However, the sparse matrix solver turns out to be very complex. Unless the reader has access to a solver for tableau, we
suggest not to use this method, but we explain at least its
principles.
In the section on graphs we introduced the concept of the
incidence matrix A, with Eqs. (23) and (24). To complete network description, we need a general expression suitable for
any element. It turns out that this is possible by writing

1
0

G4

TABLEAU

227

IL

V1

V2
L

C3
R2

G4

J1

Figure 11. First example for modified nodal formulation.

Figure 9. Example for tableau.

228

TIME-DOMAIN NETWORK ANALYSIS

V2
V1

IE

C
V3
IOP

Figure 12. Second example for modified nodal formulation.

through it. Using KCL for node 1 we write

GV1 + IL J = 0
Since the current IL flows away from node 1, it is taken positive. At node 2 it must be taken negative and KCL for this
node leads to
IL + sCV2 = 0
So far we have two equations and three unknowns. The set
must be completed with an equation describing properties of
the inductor:
V1 V2 sLIL = 0
The three equations

0
1

can be put into a matrix form:

0
1
J
V1

sC
1 V2 = 0
IL
1 sL
0

The two networks introduced the principles we use: First we

replace all elements which cannot be taken into nodal formulation by their currents and write KCL. Then we append
equations describing properties of the elements. Let us return
to the voltage source. In a general case Vi Vj E and this
must be added to the previous set of equations. In addition,
the current flowing through the voltage source must also be
added at node i and subtracted at node j. This is symbolically
summarized in the stamp shown in Fig. 13. On the left the
rows are marked by i and j. They correspond to the nodes
where the currents are added or subtracted. Above the stamp
the letters i and j are subscripts of the nodal voltages which
multiply the columns. The units appearing in the stamp are
thus multiplied by either a voltage or a current, also indicated
above the stamp. Following similar considerations we can derive stamps for all the elements introduced in the section
entitled Basic Concepts and Definitions. They are collected
in Fig. 13.
The starting matrix is always the nodal matrix; its size is
n, the number of ungrounded nodes. Afterwards additional
row(s) and column(s) are added one by one, as we keep adding
the various elements. This was actually done when we considered the network in Fig. 12. First we added the row and column for the voltage source, and afterwards we added to this
already increased matrix the row and column for the operational amplifier.
A reader wishing to learn more about this formulation is
referred to Refs. 1 and 2.
SIMPLE INTEGRATION METHODS

(31)

This is the modified nodal formulation. Since multiplication

by s represents the derivative with respect to time, our steps
resulted in a system with one algebraic and two differential
equations.
Consider next the network in Fig. 12. It has one voltage
source and one operational amplifier, elements which cannot
be taken into nodal formulation. Similarly as above we first
replace them with their currents, as shown, and apply KCL
to the three ungrounded nodes:

G(V1 V2 ) + IE = 0
GV1 + (G + sC)V2 sCV3 = 0
sCV2 + sCV3 + IOP = 0
To this set we append equations describing properties of the
two elements. For the voltage source V1 E. For the operational amplifier we know that the two input terminals are at
the same potential. Since one of them is grounded, the second
will be at zero potential and V2 0. Adding these equations
to the above set we get in matrix form

G
G
0
1 0
0
V1
G G + sC sC 0 0 0
V

0
V = 0
sC
sC
0
1
(32)

0
0
0 0 II E
1
IOP
0
1
0
0 0
0

Methods for integration of differential equations were developed much earlier than programs for simulation, and first attempts of computerized network simulations were directed to
the use of known integration procedures. State variables were
developed because integration of first-order differential equations was available in the RungeKutta routines. When problems were encountered, new methods for integration were developed.
The majority of integration methods are polynomial approximations of various orders. In this section we will consider three simplest formulas for numerical integration: the
forward Euler, the backward Euler, and the trapezoidal (2).
They are practical methods, used in commercial simulation
packages.
Consider a given differential equation
x = f (x, t)

(33)

where x replaces dx/dt for simplicity. Let the initial value

x0 be known at t 0. The derivative x0 can be evaluated by
inserting into Eq. (33). The simplest formula to predict the
value x1 at t h can be derived by inspecting Fig. 14:
x1 = x0 + hx0

(34)

All terms on the right are available: The formula is explicit

and belongs to the class of predictors. Its name is forward
Euler. Another formula, the backward Euler, makes the estimate differently:
x1 = x0 + hx1

(35)

TIME-DOMAIN NETWORK ANALYSIS

1
1

r.h.s.

r.h.s.
i

Current source

r.h.s.

Voltage source
i

sC

sC

CE0

sC

sC

CE0

Conductor

r.h.s.

i
i

k m

i
j
g g
k
m g g

sL

LJ0

k m

1
1

k m

k m

i
j
k
m

1
1
r

1 1

VV

I1 I2
1
1

i
j
k
m

1 1

1 1
k m

1
1

i
j
k
m

CC
j

Resistor

i
j
k
m

VC
i

Inductor
j

Capacitor
i

1 1

i
i
j
k
m

1
1
1 1

CV

Operational amplifier

k m

I1
1
1

I2

1
1
1 1
sL1 sM
1 1 sM sL2
Transformer

Because the right side contains the unknown derivative at

t h, this formula is implicit and belongs to the class of correctors. It would seem that Eq. (34) is better, because it is
simpler. Actually, Eq. (35) is much better, but Eq. (34) has its
use as well. It can be applied at the beginning of every step
to predict the new point x1. The information is then used in
Eq. (33) to find an approximation to x1, which in turn can be
inserted into Eq. (35). Repeating several times between Eq.
(33) and Eq. (35) we eventually come to a situation when x1,
substituted into Eq. (33), provides x1 which we already had.

Figure 13. Stamps for the networks in

Fig. 1.

The iterations have converged and the process can be repeated for another step to find x2, and so on. Both Euler formulas match the first derivative and we say that their order
of integration is one.
If we take the sum of Eq. (33) and Eq. (34), we get another
corrector, called trapezoidal:
x1 = x0 +

h 
(x + x0 )
2 1

(36)

Its order of integration is two.

Properties of integration methods are generally studied on
the simplest differential equation (2,10)

x1 x0
x0

x = x

(37)

x(t) = x0 et

(38)

x(t1)

x0

t0

229

x1

t1 t0

x(t)

t1

Figure 14. Approximations for forward Euler formula.

Its exact solution is

The constant can be real or complex. Using simple steps (2),

it is possible to derive for the three formulas important stabil-

;
;;;
;;
;
;;;;;;
230

TIME-DOMAIN NETWORK ANALYSIS

Figure 15. Stability properties of integration formulas. (1) Forward

Euler, stable inside; (2) backward Euler, stable outside; (3) trapezoidal, stable in the left half-plane.

ity properties, summarized in Fig. 15. Areas indicated by

hatching indicate unstable regions of each formula. Let
have negative real part, which means that x(t) in Eq. (38) will
tend to zero for large t, irrespective of what is its imaginary
part.
The left unit circle refers to the forward Euler formula. If
the product h can be plotted inside this circle, then application of the formula will give results which will tend to zero
for a large number of steps, similarly as the exact solution.
However, if the point falls outside the unit circle, the results
by the formula will incorrectly grow with the number of steps.
The consequence is that for large absolute value of we must
choose a small step size h to get the point into the unit circle.
Stability, however, does not yet mean accuracy. For that the
product h must fall close to the origin of axes in the figure.
The outside of the right unit circle corresponds to the backward Euler formula and its stable region. It shows that for
the negative real part of the solution will be always in the
stable region, no matter how large a step we take. Again, for
accuracy the point should be close to the origin.
The vertical axis is the border between stable and unstable
regions of the trapezoidal formula. If the real part of is negative, both exact solution and results by the formula will tend
to zero for large t. The opposite will be true for the positive
real part, which is again correct. This is called absolute stability. There exists a proof by Dahlquist that no higher-order
formula can be absolutely stable.

we still need to pull the desired poles close to the origin, but
the large i will not bother us. Their responses will not be
traced, but we in fact do not want them, because their rapid
changes do not contribute to the useful function of the network. The BDF formulas behave (roughly speaking) similarly
to the backward Euler method (2).
Assume that we have the solution xn at the instant tn, as
well as a number of previous solutions xni at instants tni, as
sketched in Fig. 16 with three previous solutions. A new step
h reaches the instant tn1 where we wish to find the solution.
For our explanation we will assume equal integration steps,
with BDF formulas collected in Table 1. They are actually
polynomials passing through known points and extrapolated
to the next time instant. The formulas are used as follows. At
the beginning n 0, we know the initial value x0 and we
select h. The zero-order predictor from Table 1 estimates the
value of xn1 x1. With this and the previous point we can
use the corrector of order 1. It is, in fact, the already known
backward Euler formula.
We have now two possibilities. Either we use always only
two last points and in a sequence of steps apply the first-order
predictor or corrector. The other possibility is to take more of
the already known solutions and use a predictor corrector
pair of higher order.
Equal steps are not very practical, although in some cases
they are used. If we permit a change of the step in every new
evaluation, then the BDF formulas change, as summarized in
Table 2. The values zk in Table 2 are expressed by
zk =

tn+1 tn+1k
h

(39)

If we use higher-order formulas, zk must be saved simultaneously with the previous solutions.
The step size influences accuracy and for correct integration we must estimate the error. This is where the importance
of the predictorcorrector pair of the same order comes into
the picture. It was shown in Refs. 12 and 13 that the error is
expressed by

E=

h(xpred
xcor
n+1 )
n+1
a0 (tn+1 tn+1k )

hD
a0 T

(40)

Predictor

ADVANCED INTEGRATION METHODS

Integration methods can be self-starting or can use a number
of previous solutions. Self-starting are, for instance, the
RungeKutta formulas. If previous solutions are used, the
formulas are generally known as multistep. Many such methods are available, but the only ones used these days are the
backward differentiation formulas (BDF) (2,10,11).
If the network is linear and has parasitic elements, then
its responses will be a weighted sum of functions Eq. (38) with
very different i. Such systems are called stiff. Should we integrate such a system with the forward Euler method, every
multiplied by h must be pulled into the unit circle to preserve
stability of integration. If we use the backward Euler method,

Corrector

hz3
hz2

h
tn 2

tn

tn 1

tn + 1

Figure 16. Estimating error from predictor and corrector results.

TIME-DOMAIN NETWORK ANALYSIS

231

Table 1. BDF Formulas, Equal Steps

Order

Predictors

Correctors

xn1 xn

xn1 2xn xn1

xn1 3xn 3xn1 xn2

xn1

1 3
1
xn1 2xn xn1
h 2
2

xn1 4xn 6xn1 4xn2 xn3

xn1

1 11
3
1
xn1 3xn xn1 xn2
h 6
2
3

where k is the number of points taken into consideration, and

D and T are shown in Fig. 16. The coefficient a0 is the coefficient multiplying xn1 in the corrector formula. If the error is
large, we reduce the step size. There exist advanced methods
on how to adjust the step, all beyond the scope of this contribution, but in many cases the step is simply halved and the
process tried again. One can similarly increase the step if the
error turns out to be smaller than permitted.
Most commercial packages use only the Euler formulas
and the trapezoidal rule, and some also use the second-order
BDF formula. Higher-order integration turns out to be efficient only if nonlinearities have several continuous derivatives. Since most transistor models have only the first derivative continuous, there would be no advantage in switching to
orders higher than two (14).

xn1 0
1
xn1 (xn1 xn)
h

is the frequency of interest. The program for LU decomposition must be in complex arithmetic, and the resulting solution
variables are complex as well. Absolute value or phase can be
obtained from such complex values. Repeating for a number
of frequencies, we get the frequency-domain response.
Time-domain solutions are more complicated, but still simple enough when considering backward Euler or trapezoidal
formulas. Recall that multiplication by s represents the derivative and write
GXn+1 + CXn+1 = Wn+1

Xn+1 =

1
(X
Xn )
h n+1

Inserting into Eq. (41) provides (2)



1
1
G + C Xn+1 = CXn + Wn+1
h
h

Predictors

Correctors

xn1 xn

xn1 0

a1 z2 /(z2 1)
a2 1/(1 z2)

a0 1
a1 1
1
xn1 (a0 xn1 a1 xn)
h

xn1 a1 xn a2 xn1
2

D (z3 z2)(1 z2 z3 z2 z3)

a1 z2 z3(z3 z2)/D
a2 z3(1 z3)/D
a3 z2(z2 1)/D
xn1 a1 xn a2 xn1 a3 xn2

(42)

(43)

On the left is the same matrix as we had before, with s replaced by 1/h. On the right, the C matrix is multiplied by the
previous result, Xn, and added to the vector of the sources,
evaluated at the next time instant. Now suppose that we keep
the step size fixed during the whole integration. In such a
case the matrix on the left does not change and all we need
is one LU decomposition for the entire time-domain calcula-

Table 2. BDF Formulas, Variable Steps

Order

(41)

We added the subscript n 1 to indicate integration steps.

In Eq. (41), G are all entries of the matrix not multiplied by
s, and C are all entries multiplied by s. The backward Euler
formula can be similarly expressed by

LINEAR NETWORKS
Linear networks offer a large number of possibilities how to
study them. They can be analyzed in frequency domain and
time domain, network functions can be derived, and poles and
zeros can be calculated.
Since our modified nodal formulation was explained on linear networks, it is worth mentioning how simple frequency
domain analysis is. In frequency domain we calculate how a
sinusoidal input signal would be transferred through the network after all transients have died out. Suppose that we have
the equations in matrix form, similarly as in the section entitled Nodal Formulation. Once we have the equations in matrix form, all we do is insert a unit value for the source E or
J and substitute in the matrix s by j, where 2f and f

D z2 (z2 1)
a0 (z 22 1)/D
a1 z 22 /D
a2 1/D
1
xn1 (a0 xn1 a1 xn a2 xn1)
h

232

TIME-DOMAIN NETWORK ANALYSIS

tion. In each step we prepare a new right-hand side and find

Xn1 by forward and back substitution. For the example in
Fig. 11 this system would be

0
1

0
C/h
1

V1,n+1
1

1 V2,n+1
IL,n+1
L/h

= 0
0

F Vb
F
F
=
=+
Vi
Vb Vi
Vb

0
V1,n
Jn+1

0 V2,n + 0
IL,n
0
L/h

0
C/h
0

Using the same steps as above, we can derive an expression

for the trapezoidal formula (2):

G+

The dots indicate possible presence of other elements. To prepare the Jacobian, we differentiate with respect to Vi and Vj.
Using the chain rule we obtain




2
2
C Xn+1 = G C Xn + Wn+1 + Wn
h
h

(44)

NONLINEAR NETWORKS
Nonlinearities introduce major difficulties. The concepts of
frequency-domain response, amplitude, phase, poles, or zeros
do not exist. What remains is (1) a dc solution when no signal
is applied and (2) a time-domain solution. Both are obtained
by iterations.
Dc solutions find the operating point, which are nodal voltages and currents in the absence of a signal. It is a situation
to which the network stabilizes after the power is turned on
and no signal is applied. The operating point is found by first
short-circuiting all inductors and open-circuiting (removing)
all capacitors and then solving the resulting algebraic system.
This is not without problems. In transistor networks we may
have nodes connected to the rest of the network through capacitors only. Removal of capacitors will result in a node without connection to the other parts of the network, and in such
a case the solution routines fail. Some kind of preprocessing
may be needed to remove such nodes from the equations.
Once this has been done, we have an algebraic system of
equations which can be solved by NewtonRaphson iteration
(see the section entitled Solutions of Network Equations).
In linear networks we were able to write first the modified
nodal equations and then put them into matrix form. This is
not possible when nonlinear elements are present. Consider a
nonlinear element connected between points i and j. Its current, which we denote as Ib, flows from i to j and is the function of the voltage across it, Vb:
Ib = F(Vb )

F
F Vb
F
=
=
V j
Vb V j
Vb
Contribution to the Jacobian will be in columns and rows i
and j:




. . . + F/Vb . . . F/Vb
Jacobian :
. . . F/Vb . . . + F/Vb



. . . + F(Vb )
Right-hand side :
. . . F(Vb )
For additional understanding consider Fig. 17 with two linear
and one nonlinear conductor. Using nodal formulation we
take the sums of currents at each node:

f 1 = G1V1 + Ib J = 0
f 2 = Ib + G2V2 = 0
The expressions are already in the form needed for iteration,
with zero on the right, see Eq. (18). The NewtonRaphson
equation will have the form

G1 + F/Vb
F/Vb

F/Vb
G2 + F/Vb




V1
V2




G1V1 + F (Vb ) J
=
F (Vb ) + G2V2

The minus sign in front of the right-hand side comes from Eq.
(22). Had we used a linear conductance G3 instead of the nonlinearity, it would appear in the same positions as the derivatives. We are coming to a very important conclusion: The derivative appears in the Jacobian in the same position as if
the element was linear. All the stamps we derived for linear
elements are also valid for the Jacobian.
Returning to Fig. 17, let Ib Vb3, J 1, and G1 G2 1.
Then Ib /Vb 3V b2 with Vb V1 V2. The NewtonRaphson

In terms of modified nodal formulation the branch voltage is

expressed by

Ib
V1

F(Vb)
V2

Vb = Vi V j
In nodal equations the current will be added at node i and
subtracted at j,

G1

G2

Equation for node i :

. . . + F (Vi V j )

Equation for node j :

. . . F (Vi V j )

Figure 17. Resistive network with one nonlinear element.

TIME-DOMAIN NETWORK ANALYSIS

V1

V2
G

0.1V1

V1,0

233

dc

R
C1

2V

C2

Figure 19. Network with Dirac impulse of current.

Figure 18. Network with nonlinear capacitor.

SWITCHED NETWORKS
equation will be

3(V1 V2 )2
1 + 3(V1 V2 )2




V1
V2



V1 + (V1 V2 )3 J
=
V2 (V1 V2 )3

For iteration we must select some initial estimates on the

voltagesfor instance, V1 1 and V2 0.5.
Nonlinear memory elements must be defined by the flux,
(Ib), for the inductor and by the charge, Q(Vb), for the capacitor. Simulation uses their derivatives with respect to time:

Q(Vb )
t

(Ib )
VL =
t
IC =

(45)

and these derivatives are replaced by their approximations:

for equal steps those from Table 1, for variable steps those
from Table 2. Consider the network in Fig. 18 with a nonlinear capacitor defined by Q 0.1V 13 and an initial voltage
V1,0 2V. Writing nodal equations for both nodes

Q
+ G(V1 V2 ) = 0
t
V
f 2 = G(V1 V2 ) + C 2 = 0
t

f1 =

Suppose we use the backward Euler formula. This changes

the equations to

f1 =

0.1V 31 0.1V 31,0

h

+ G(V1 V2 ) = 0

V2 V2,0
=0
f 2 = G(V1 V2 ) + C
h

(46)

The Jacobian is prepared by differentiating with respect to

V1 and V2. This will lead to the following NewtonRaphson
equation:

G + 0.3V 21 /h
G






f1
G
V1
=
G + C/h V2
f2

In modern electronics, semiconductor devices can be used as

reliable switches of voltage or current. This had led to the
development of many methods where switched networks are
used. In communications switched capacitor networks have
been used successfully over the past two decades. In power
engineering, classical power supplies were replaced by
switched networks.
Simulation of networks with switches presents new challenges, not known before. Switching may be performed by a
clock with switching instants known precisely in advance. In
power engineering, diodes or transistors may be used as
switches. Their switching instants depend on the system voltages or currents and change with time.
Detailed analysis of switching networks by classical simulators is difficult. Not only does the topology change, but the
instants of switching change as well and have to be found
with sufficient precision.
Modeling of switches can take various forms. Exact semiconductor models can be used, but then simulations are
lengthy. The other possibility is to replace switches by open
and short circuits, but this also presents problems. In this
section we will explain what must be done if ideal switches
are used.
Consider the network in Fig. 19, with the switch connected
to the source. The capacitor C1 is charged to the voltage of the
voltage source, say V1. The other node has a voltage V2 V1.
If we transfer the switch to the right, then we have a situation that at the same node is voltage V1 from the left capacitor
and V2 from the right capacitora situation of inconsistent
initial conditions. The voltages are equalized instantaneously
by a Dirac impulse of current. A Dirac impulse is a strange
impulse having zero duration and infinite amplitude, but finite area. Another case of inconsistent initial conditions is in
Fig. 20. Let the switch be on the left side for some time. Since
we have a dc source, a linearly growing current will flow upwards through the inductor. If we suddenly transfer the
switch to the right, we will have a single loop with some current in the left inductor and zero current in the right induc-

1 + 3(V1 V2 )2
3(V1 V2 )2

dc
+

where on the right we insert Eq. (46). Had we used higherorder integration, then in the Jacobian the terms divided by
h would be multiplied by the corrector coefficient a0 (see Table
2). Additional details can be found in Refs. 2, 15, and 16.

L2
L1

Figure 20. Network with Dirac impulse of voltage.

234

TIME-DOMAIN NETWORK ANALYSIS

tor. The currents are instantaneously equalized by a Dirac

impulse of voltage.
In network simulations the question is: What will be the
voltages (in Fig. 19) or the currents (in Fig. 20) immediately
after switching? The solution of the problem turns out to be
very simple (17). All we have to do is use backward Euler
integration formula, make a one-step h forward, and get the
solution. Next use it as initial conditions for a step back, with
negative h, to the instant of switching. The solution will provide the correct initial conditions after switching. Afterwards,
integration is done as described in the previous section.

PERIODIC STEADY STATE

If a network is turned on from a quiescent state, there is always a certain period of time when transients take place. The
same is true if we suddenly apply a signal. If the signal is a
simple sine wave and the network is linear, the transients
will eventually die out and the output will be the same sine
wave, amplified or attenuated and with a different phase
shift. In linear networks, this type of steady state is easily
calculated using frequency domain methods.
If the network has nonlinearities and the signal is still a
simple sine wave, the output will be composed of some transients, of the signal and its harmonics. In steady state the
signal will be distorted. Because of the nonlinearity, classical
frequency domain methods cannot be applied.
Networks with periodic steady state are quite common and
designers need to know the behavior in steady state. Computer solution seems to be easy: use a periodic input signal
and integrate for a sufficiently long time until all the transients have died out. Unfortunately, this may be a very expensive proposition, and it is thus no surprise that attempts
have been made to somehow speed up the process to reach
the steady state by other means.
Two fundamental types of methods are available: one is
based on integration, the other on the use of frequency domain methods. We will explain the principles of both methods
without going into any details. References will direct the
reader to additional information.
To start integration, we need an initial vector of voltages
and currents, x(0). If nothing more is known, we can start
with a zero vector. Let us integrate over the period T of the
periodic input signal and get the solution x(T). At this point
we can form an error vector
E(x) = x (T ) x (0)
which, at steady state, must be a zero vector. To solve the
problem by NewtonRaphson iteration, we would have to calculate the Jacobian, which is a fairly complicated process.
Moreover, the first solution may not result in a zero vector
and the process may have to be repeated. More about this
method can be found in Refs. 18 and 19.
Another method, based on integration and not requiring
the knowledge of the derivatives, was invented by Skelboe
(20,21). The principle is as follows: integrate over a number
of periods, save the vectors x(0), x(T), . . . x(nT), and apply
a special algorithm to project the result to the steady state.
Similarly as above, the projection may not be satisfactory in
the first run, and the process may have to be repeated several
times with new integrations over n periods.

IL

IN

+
Linear

+
VL

VN

Figure 21. Linear network with one nonlinear resistor.

Methods based on frequency domain solutions completely

avoid calculation of the transients; they are usually referred
to as harmonic balance methods. We will explain the principle
with the help of Fig. 21, composed of some linear network and
one nonlinear resistor. Normally the linear and nonlinear
part would be connected. In the figure we separated them and
applied two sources VN VL. We also indicated the currents
IN and IL. If these two equal voltage sources are such that the
two currents IL IN, then we have a situation in which a
direct connection of the nonlinearity to the linear network
will not result in any change.
The trick of separating the two parts by the voltage
sources has the advantage that we can apply harmonic frequencies f, 2f, . . . nf to the linear network one by one (superposition principle applies) and get the currents by frequency domain methods. This will provide a vector of currents
I L = [IL,1 , IL,2 , . . . IL,n ]T
Next, we apply the same voltages to the nonlinear part, but
first convert them to time domain by using Fast Fourier
Transform (FFT). This will give us the possibility to calculate
the current through the nonlinearity as a time-domain function. Using the inverse FFT we decompose this current into
frequency-domain components:
I N = [IN,1 , IN,2 , . . . IN,n ]T
We can now create an error vector
E = IL IN
and using some iterative process try to reduce this vector to
a zero vector. Additional details can be found in Ref. 22.
Many modifications of the above methods have been published. For further study we recommend Ref. 23. It is a book
devoted to the steady-state problem and has numerous additional references on this subject. In addition, Refs. 24 and 25
may be of interest; they are books dealing with the general
problem of circuit simulation.
BIBLIOGRAPHY
1. J. Vlach, Basic Network Theory with Computer Applications, New
York: Van Nostrand Reinhold, 1992.
2. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis
and Design, 2nd ed., New York: Van Nostrand Reinhold, 1994.
3. G. E. Forsythe, M. A. Malcolm, and C. B. Moler, Computer Methods for Mathematical Computations, Englewood Cliffs, NJ: Prentice-Hall, 1977.
4. G. Dahlquist and A. Bjorck, Numerical Methods, Englewood
Cliffs, NJ: Prentice-Hall, 1974.
5. D. Kahaner, C. Moler, and S. Nash, Numerical Methods and Software, Englewood Cliffs, NJ: Prentice-Hall, 1989.

TIME MEASUREMENT

235

6. R. A. Rohrer, Circuit Theory: An Introduction to the State Variable

Approach, New York: McGraw-Hill, 1970.

TIME HOPPING MODULATION. See SPREAD SPEC-

7. P. M. DeRusso, R. J. Roy, and C. M. Close, State Variables for

Engineers, New York: Wiley, 1965.

TIME INTERVAL METERS. See FREQUENCY AND TIME IN-

8. G. D. Hachtel, R. K. Brayton, and F. G. Gustavson, The sparse

tableau approach to network analysis and design, IEEE Trans.
Circuits Syst., CT-18: 101113, 1971.
9. C. W. Ho, A. E. Ruehli, and P. A. Brennan, The modified nodal
approach to network analysis, IEEE Trans. Circuits Syst., CAS22: 504509, 1975.
10. G. Dahlquist, A special stability problem for linear multistep
methods, BIT, 3: 2743, 1963.
11. C. W. Gear, Numerical Initial Value Problems in Ordinary Differential Equations, Englewood Cliffs, NJ: Prentice-Hall, 1971.
12. R. K. Brayton, Error estimates for the variable-step backward
differentiation methods, IBM Research Report RC 6205, September 1976.
13. R. K. Brayton, F. G. Gustavson, and G. D. Hachtel, A new efficient algorithm for solving differential-algebraic systems using
implicit backward differentiation formulas, Proc. IEEE, 60: 98
108, 1972.
14. I. N. Hajj and S. Skelboe, Time domain analysis of nonlinear systems with finite number of continuous derivatives, IEEE Trans.
Circuits Syst., CAS-26: 297303, 1979.
15. C. W. Gear, Simultaneous numerical solution of differential-algebraic equations, IEEE Trans. Circuit Theory, CT-18: 8995, 1971.
16. W. M. G. Van Bokhoven, Linear implicit differentiation formulas
of variable step and order, IEEE Trans. Circuits Syst. CAS-22:
109113, 1975.
17. J. Vlach, J. Wojciechowski, and A. Opal, Analysis of nonlinear
networks with inconsistent initial conditions, IEEE Trans. Circuits Syst. I, 42: 1995, 195200.
18. T. J. Aprille and T. N. Trick, Steady state analysis of nonlinear
circuits with periodic inputs, Proc. IEEE, 60 (1): 108114, 1972.
19. F. R. Colon and T. N. Trick, Fast periodic steady state analysis
for large signal electronic circuits, IEEE J. Solid State Circ., 8
(4): 260269, 1973.
20. S. Skelboe, Computation of the periodic steady state response of
nonlinear networks by extrapolation methods, IEEE Trans. Circuits Syst., CAS-27: 161175, 1980.
21. S. Skelboe, Conditions for quadratic convergence of quick periodic
steady state methods, IEEE Trans. Circuits Syst., CAS-28 (4):
234239, 1982.
22. M. S. Nakhla and J. Vlach, A piecewise harmonic balance technique for determination of periodic response of nonlinear systems, IEEE Trans. Circuits Syst., CAS-23 (2): 8591, 1976.
23. K. S. Kundert, J. K. White, and A. Sangiovanni-Vincentelli,
Steady-State Methods for Simulating Analog and Microwave Circuits, Norwell, MA: Kluwer, 1990.
24. J. Ogrodzki, Circuit Simulation Methods and Algorithms, Boca
Raton, FL: CRC Press, 1994.
25. L. T. Pillage, R. A. Rohrer, and Ch. Visweswariah, Electronic Circuit and System Simulation Methods, New York: McGraw-Hill,
1995.

JIRI VLACH
University of Waterloo

TIME-DOMAIN REFLECTOMETERS. See REFLECTOMETERS, TIME-DOMAIN.

TIME-FREQUENCY ANALYSIS. See FREQUENCY MODULATION.

TRUM COMMUNICATION.
TERVAL METERS.

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

95

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

In this article the most important aspects of electrical circuits
operating in a sinusoidal steady state, also known by practitioners as alternating current circuits, will be explored. In
this section a brief historical introduction is followed by a
mathematical overview of sinusoids and phasors.
HISTORICAL NOTES
Today, alternating current (ac) circuits are the standard for
electric power production, transmission, distribution, and
consumption. The advantage of ac versus direct current (dc)
systems became evident toward the end of the nineteenth century, when a number of theoretical and technical results were
converted to practical machines, making long-distance power
transmission feasible and economical. Most of these inventions are still in use: alternators, transformers, and asynchronous motors are the standard energy-to-energy conversion
mechanisms in the modern world. At the same time the first
experiments with electromagnetic waves (discovered by H.
Hertz in 1887) underlined the importance of the study of ac
systems and resonant circuits, and led the way to modern
communications and electronics.
Important historical milestones are the invention of the
transformer, asynchronous motor, and the (theoretical) definition of the rotating vector (alternatively called a phasor) formalism. The work of Faraday and Ruhmkorff provided the
basis for the invention of the transformer. The first practical
open-core ac transformer was introduced by Gaulard at the
1884 Worlds Fair in Turin, Italy. Thanks to the theoretical
work of Ferraris, who defined the power factor for ac circuits,
and definitely proved the high performance of the transformer, ac systems could be used for long-distance power
transmission. The design of the first transformer was improved in the following year by Deri, Blathy, and Zipernowsky, with a closed-core design. The 1885 Budapest fair was lit
by an array of 75 of these transformers. In the same years
Ferraris and Tesla independently investigated the application
of the rotating magnetic field to the design of ac asynchronous
motors, patented by Tesla in 1888. A complete ac system powered by a hydroelectric plant 176 km away was demonstrated
in 1891 in Frankfurt, Germany. The definitive victory for ac
systems occurred in 1892, with the decision to adopt the alternators designed by Tesla and built by Westinghouse for
the Niagara Falls power plant.
Finding steady state solutions in ac systems was a difficult
task. J. C. Maxwell contributed by providing a general solution of his equations for an ac circuit. Even with Maxwells
simplifications, solving for a particular problem still involved
the use of differential methods, not yet well known to the
practical engineer. The solution to this problem came with T.
Blakesley in 1885. His rotating vector method was the starting point for the subsequent theory developed by C. P.
Steinmetz, which was published in 1893 (1) and 1898 (2).
SINUSOIDS AND PHASORS
Sinusoids are periodic functions known from trigonometry:
u1 (t) = u01 cos(1t + 1 )
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

(1)

96

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

Any sinusoid is characterized by a triplet of parameters: amplitude u01 and angular frequency 1, both positive by convention, and (initial) phase 1, defined less an integer multiple of
2. The positiveness of u01 and 1 does not limit the generality
of the definition in Eq. (1). In fact, the change in sign of u01
corresponds to the addition of to 1, while the change in
sign of 1 is equivalent to the change of sign of 1.
Two other parameters are commonly used as alternatives
to 1: frequency f 1 1 /(2) and period T1 1/f 1. Moreover,
the effective value ueff
1 of sinusoid u1(t)

ueff
1 =

lim

(t 2 t 1 )

1
t2 t1

t2

t1

u
[u01 cos(1t + 1 )]2 dt = 01
2

[u1ej 1t]

1t
u01

(2)

u01cos( 1t + 1)

where j is the imaginary unit, the complex number u1

u01 exp( j1) is the phasor of the sinusoid, u01, coincident with
the amplitude of the sinusoid, is its modulus, and [ ] denotes
the real part of the complex quantity between [ ]. Analogously, [ ] denotes the imaginary part. The second expression in Eq. (3) allows one to interpret sinusoids from a geometrical point of view. A sinusoid with angular frequency 1
and phasor u1 may be regarded as the projection on the real
axis of a point moving along a circumference with angular
velocity 1 (see Fig. 1). The circumference is centered on the
origin of the complex plane: the modulus u01 of the phasor
determines its radius, while the phase 1 determines the position of the point on the circumference in t 0.
Subclasses of Sinusoids With The Same Angular Frequency
Consider the subset of sinusoids characterized by the same
angular frequency, hereinafter denoted by symbol , which
will be called -subclass. Each sinusoid of an -subclass is
distinguishable from other sinusoids of the same subclass by
its specific phasor value. Some examples of sinusoids and corresponding phasors are shown in Table 1.

u01

may be used in place of u01. Since the integrand is periodic

with period T1 /2, this result does not change if the integration
range (t2 t1) is coincident with any integer multiple of
T1 /2.
Recalling trigonometry and complex number mathematics,
the expression of u1(t) in Eq. (1) may assume the alternative
forms:

u01 cos(1 ) cos(1t) u01 sin(1 ) sin(1t)

u01 (t) = [u1 exp( j1t)]
(3)

(1/2)u exp( j t) + (1/2)(u ) exp( j t)

1

[u1ej 1t]

1t + 1

Figure 1. Geometrical relations between phasors and corresponding

sinusoids in time domain.

subclass and with phasor u1 u2:

u1 (t) + u2 (t) = [u1 exp( j t)]

+ [u2 exp( j t)]

= [(u1 + u2 ) exp( j t)]

(5)

Property. The set of the time derivatives of all sinusoids of

any -subclass is equivalent to the subclass itself. More exactly, the derivative of a sinusoid of an -subclass and with
phasor u1 is again a sinusoid of the same subclass and with
phasor j u1.
Proof. Consider a generic sinusoid and its time derivative:

u1 (t) = 12 [u1 exp( j t)

+ u1 exp( j t)]

du1 (t)
= 12 [ j u
1 exp( j t)
j u
1 exp( j t)]

dt

(6)

Property. According to Eqs. (4) and (5) each -subclass of

sinusoids or, equivalently, the corresponding set of phasors,
constitutes a two-dimensional linear space.

Comparing the derivative with the sinusoid itself proves the

property.

Proof. A sinusoid u1(t) of a -subclass and phasor u1,

multiplied by any real number , is again a sinusoid of the
same subclass with phasor u1:

Table 1. Some Examples of Sinusoids and Related Phasors

u1 (t) = [u1 exp( j t)]

= [(u1 ) exp( j t)]

(4)

while the sum of any pair of sinusoids u1(t) and u2(t) of an subclass and with phasors u1 and u2 is a sinusoid of the same

Sinusoid uk (t)
15
10
3
8

cos( t /4)
cos( t /2)
sin( t)
cos( t /6)

Phasor uk
15
10
3
8

exp( j/4)
exp(j/2)
exp(j/2)
exp( j5/6)

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

97

Table 2. Terminology Used in Comparing Two Sinusoids and Their Phasors

1 2
2 1 2
1 2 /2

1 2
2 1 2
1 2 /2

u1 and u2 are in phase

u1 anticipates u2
u1 anticipates in quadrate u2

Analogously the integral of a sinusoid of a -subclass is

once more a sinusoid of the same subclass and with phasor
u1 /( j ), if the arbitrary integration constant is zero.
A set of phasors of the same -subclass may be represented
in the complex plane. This representation, called a phasor diagram, is convenient in qualitative and quantitative analysis.
An ad hoc terminology is commonly used when phasors (and/
or the corresponding sinusoids) are compared in the complex
plane; Table 2 reports such terminology for two sinusoids
with phasors u1 u01 exp( j1) and u2 u02 exp( j2). Note
that phases 1 and 2 must be defined so that 1 2 ,
by choosing suitably the arbitrary integer multiples of 2 of
the two phases.
PHASOR DOMAIN ANALYSIS OF CIRCUITS IN SINUSOIDAL
STEADY STATE
In this section the phasor domain method will be applied to
analyze a circuit operating in a sinusoidal steady state. A linear dynamic circuit operates in a sinusoidal steady state
(SSS), that is, all voltages and currents of the circuit vary
versus time as sinusoids of the same -subclass (4), if the
following conditions are met:
1. The circuit is built using linear, resistive, and time invariant elements with any number of terminals, sinusoidal independent sources all with the same fixed angular frequency , linear and time invariant capacitors,
inductors, and coupled inductors.
2. The circuit is asymptotically stable, that is, all the natural complex frequencies sk k jk (k 1, 2, . . ., n)
of the circuit are in the left side of the complex plane
[i.e., k 0, (k 1, 2, . . ., n)] (4).
3. The circuit has been left running with no external intervention (e.g., switch commutation) for a time interval
t such that t 1/k, (k 1, 2, . . ., n).
Under the above circumstances the transient effects due to
initial conditions vanish, because the circuit is asymptotically
stable, all voltages and currents are sinusoids versus time. In
conclusion, by substituting sinusoids and their derivatives
with the respective phasors, the time domain linear differential equations with forcing sinusoids of the same -subclass
are transformed into complex-domain algebraic equations.
Topological Relations in Phasor Domain
The time domain Kirchhoff s laws (see NETWORK EQUATIONS)
are translated in SSS into the phasor domain (4): they are
again homogeneous linear algebraic relations with the same
real and constant coefficients. Table 3 shows phasor domain

u1 and u2 are in opposition

u1 delays u2
u1 delays in quadrate u2

laws, when the incidence matrix A and a fundamental mesh

matrix B are employed: vectors v(t) and i(t) group the sinusoidal branch voltages and currents, and vectors v (t) and (t)
group the sinusoidal node voltages and mesh currents, while
vectors v, i, v, and group the respective phasors.
Constitutive Relations In Phasor Domain
The constitutive relations, also known as branch or element
relations, are introduced, in the phasor domain, by using the
voltage and current reference directions (defined in LINEAR
NETWORK ELEMENTS) for independent voltage and current
sources: the corresponding source voltage or current phasor is
introduced, while the respective current or voltage remains
unconstrained in the phasor domain (see Table 4): source voltages and currents are characterized by the symbol .
Linear resistive elements are defined, in the phasor domain, by algebraic, constant coefficient relations identical to
those used in the time domain (see Table 5). Table 6 shows
the constitutive relations of simple dynamical elements (see
LINEAR NETWORK ELEMENTS): they display the imaginary factor
j, which replaces the time domain derivative d/dt, denoted
hereinafter by (see Eq. 6).
Sparse Tableau Analysis in Phasor Domain
A circuit operating in SSS is now analyzed, by using the same
methods presented for general analyses (see NETWORK EQUATIONS). For the sake of brevity only the sparse tableau method
will be discussed. To this end, consider Kirchhoff s laws and
constitutive relations in phasor domain:

AT

Im,m
0n1,m
H v0 + j H
v1

0n1,n1
0m,n1

0m,m
0m
v

A
v = 0n1
i0
i1
H + j H

i
u

where n and m are the number of nodes and branches in the

graph; A is the (n 1) m incidence matrix; Hv0, Hv1, Hi0,
and Hi1 are m m block diagonal matrices grouping the parameters of constitutive relations, Im,m is the identity m m
matrix, 0m, 0n1 are vectors of null elements, and 0m,m, 0m,n1,
0n1,m, 0n1,n1 are matrices of null elements; subscripts denote
in the right-hand side groups the phadimensions. Vector u
sors of source voltages and currents, while the unknowns of
the system are the phasors of node voltages, branch voltages,
and currents. Note that the elements of matrices Hv0 j Hv1
and Hi0 j Hi1 either are adimensional or have the physical
dimensions of voltage-to-current or current-to-voltage.

Table 3. Formulations of Kirchhoff s Laws in Phasor Domain

KVL
KCL

(7)

Time Domain

Phasor Domain

Time Domain

Phasor Domain

v(t) A Tv(t)
Ai(t) 0

v A Tv
A 0

Bv(t) 0
i(t) B T(t)

Bv 0
B T

98

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

Table 4. Constitutive Relations of Independent Sources in Phasor Domain
Voltage Source

Current Source

Time Domain
v(t) [v exp( jt jv )]

Phasor Domain

Time Domain

Phasor Domain

v v v exp( jv )

i(t) [ exp( jt ji )]

exp( ji )

Impedance and Admittance

The phasor domain representation of sinusoidal voltages and
currents suggests, for any one-port element, the introduction
of impedance and admittance, which have the same role as,
respectively, resistance and conductance in dc circuits (see
LINEAR NETWORK ELEMENTS). For the fixed value , impedance
z( j ) and admittance y( j ) are complex numbers defined by
the quotient of voltage-to-current and of current-to-voltage
phasors, respectively:
z( j )
= r()
+ jx()
=

v
i

y( j )
= g()
+ jb()
=

i
v

(8)

In Eq. (8) both impedance and admittance have been decomposed into real and imaginary parts: r( ) is called resistance,
x( ) is reactance, g( ) is conductance, and b( ) is susceptance,
as shown in Fig. 2. Impedance and admittance are not at all
phasors, since they do not represent sinusoids; they may be
considered as phasor-to-phasor operators. For this reason
their symbol is not barred.
Impedance and admittance of one-port subnetworks (i.e.,
built connecting simple one-port elements) may be calculated
using the same rules given for two-terminal resistors (see
TIME DOMAIN CIRCUIT ANALYSIS). For instance, the impedance
z( j ) and admittance y( j ) 1/z( j ) of series and parallel
connections of two one-port elements are:

Series:

z( j )
= z1 ( j )
+ z2 ( j )

Parallel:

y( j )
= y1 ( j )
+ y2 ( j )

2 ( j )

y1 ( j )y
y1 ( j + y2 ( j )

z ( j )z
2 ( j )

z( j )
= 1
z1 ( j )
+ z2 ( j )

(9)
y( j )
=

where z1( j ) 1/y1( j ) and z2( j ) 1/y2( j ) are the impedances of the connected one-ports (see LINEAR NETWORK ELEMENTS).

For instance, consider a dynamical one-port subnetwork

formed by connecting, in parallel, a resistor with value
500/3 and a capacitance with value 20 F operating in
SSS characterized by 300 rad s1: admittance y and impedance z are obtained as:

1
+ j 300 20 106 S =
500/3

500

500
1
j
z= =

y
6
6

y=

3
3
+j
500
500

Time Domain

Phasor Domain

Representations of Dynamical Two-Port Elements

in the Phasor Domain
The six representations of two-ports (see LINEAR NETWORK ELEMENTS), if they exist, are valid also for two-ports in the phasor
domain. Consider, as an example, the current and voltagecontrolled representations:
  
 
z11 ( j )
v1

z12 ( j )

i1
=
z21 ( j )
v2

z22 ( j )

i2

(10)
 
i1

y12 ( j )

v1
y11 ( j )
=
y21 ( j )

y22 ( j )

v2
i2
The four elements of both matrices are, in general, complex
because they depend on the imaginary number j . The impedance and admittance matrices Z( j ) and Y( j ) substitute the
real resistance and conductance matrices R and G proper of
dc circuits. The same considerations hold also for the other
four representations of two-ports.
Generalization of dc Analysis Methods and Properties
to ac Circuits
All the following topics, introduced for linear resistive circuits, are easily generalized to the phasor domain [see LINEAR

Table 5. Constitutive Relations of Linear Resistive Elements in Phasor Domain

Element

Element

Short circuit

v(t) 0

v 0

Open circuit

Resistor

v(t) ri(t)

v r

Nullor

CCVS

v1(t) 0
v2(t) rmi1(t)

v1 0
v2 rm1

CCCS

v1(t) 0
i2(t) i1(t)

Ideal transformer

v1(t) nv2(t)
i1(t) i2(t)/n

Time Domain

Phasor Domain

i(t) 0
v1(t) 0
i1(t) 0

0
v1 0
1 0

VCCS

i1(t) 0
i2(t) gmv1(t)

1 0
2 gmv1

v1 0
2 1

VCVS

i1(t) 0
v2(t) v1(t)

1 0
v2 v1

v1 nv2
1 2 /n

Gyrator

v1(t) i2(t)/gm
i1(t) gmv2(t)

v1 2 /gm
1 gmv2

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

99

Table 6. Constitutive Relations of Dynamical Elements in Phasor Domain

Elements

Time Domain

Phasor Domain

Capacitor
Inductor

i(t) Cv (t)
v(t) Li(t)
v1(t) L1i1(t) Mi2(t)
v2(t) Mi1(t) L2i2(t)

j Cv
v j L
v1 j L11 j M2
v2 j M1 j L22

Coupled inductors

NETWORK ELEMENTS;

NETWORK EQUATIONS; see also (3) or (4) for

classical methods]:

(Fig. 3):
p(t) = v0 cos(t
+ v )i0 cos(t
+ i )

Reciprocal and nonreciprocal two-ports

Thevenin and Norton models of one-port elements and respective theorems
Superposition theorem
Nodal analysis and modified nodal analysis
Loop and cut set analysis
Current and voltage partition rules

= (v0 i0 /2) cos(v i ) + (v0 i0 /2) cos(2t

+ v + i )

The constant term v0i0 cos(v i)/2 has an absolute value

less than or equal to the amplitude v0i0 /2 of the sinusoidal
term. In particular, the constant term coincides with this amplitude in the case of resistors and is null in the case of capacitors and inductors, according to:

Resistor:
Capacitor:
Inductor:

First and second Millmann theorems

Y and Y transformations
POWER IN SINUSOIDAL STEADY STATE
To evaluate the electrical power exchanged in linear dynamic
circuits operating in SSS, the sinusoidal behavior of any
branch voltage and current must be taken into account.

(11)

p(t) = [(ri20 )/2][1 + cos(2t

+ 2v )]
2
+ 2v + /2)
p(t) = [(Cv
0 )/2] cos(2t
+ 2v /2)
p(t) = [(Li
20 )/2] cos(2t

(12)

Recall that the sum of instantaneous powers absorbed by all

the K elements (including possible multiport elements) of a
circuit is zero.
K


pk (t) = 0

(13)

k=1

Instantaneous Power in One-Port Elements

Let v(t) v0 cos( t v) and i(t) i0 cos( t i) be the
voltage and current of a one-port element or any port of a
multiport element operating in SSS; the instantaneous power
p(t) v(t)i(t) absorbed by this element is composed of a constant term plus a sinusoidal term with angular frequency 2

Active Power and Power Factor

Instantaneous power p(t) is somewhat inconvenient and does
not have much practical use. Other definitions dealing with
power are often preferred.
Definition. In generic dynamic situations, active power P is
defined as the average of instantaneous power p(t) over a time

[ z]
jx()

Note that in Eq. (13), pk(t) is negative for independent sources

delivering power.

z( )

[ z]

r( )

p(t)

(a)

[ y]
g( )

[ y]

jb( )
i(t)

v(t)

(b)
Figure 2. Real and imaginary parts of (a) impedance and (b) admittance.

Figure 3. Instantaneous power of a generic one-port element.

100

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

interval long enough:

P=

1
t2 t1

t2

p(t)dt

t1

for (t2 t1 )

(14)

In SSS active power P assumes a compact and popular form

since it coincides with the constant term appearing in Eq.
(11):


Introducing the impedance z or the admittance y of the

one-port, and their real and imaginary parts in Eq. (8), two
different and popular expressions of complex power are obtained:

P = 12 zii = P + j[P] = (1/2)ri20 + j(1/2)xi20

P = 12 y v v = P + j[P] = (1/2)gv20 j(1/2)bv20

(19)

(15)

The introduction of the complex power is justified by the following theorem:

/2 or (t2 t1) T
/2 (where is an arbitrary
with (t2 t1) T
/2.
integer) because p(t) is periodic with period T

Complex Power Theorem. The sum of complex powers over

all K elements of a circuit is null:

P=

1
t2 t1

t2

t1

p(t) dt = (v0 i0 /2) cos(v i )

Active Power Theorem. Recalling the power theorem in

Eq. (13), and averaging both sides of the equation that fixes
at zero the sum of instantaneous powers, one obtains that the
sum of active powers over all the K elements of a circuit is
zero:
K


Pk = 0

(16)

k=1

K


Pk = 0

(20)

k=1

Proof. With reference to Table 3, Kirchhoff s laws may be

written as: Ai 0 or, equivalently, Ai* 0 and v ATv.
Computing the scalar product of v and i*, one obtains:
K


Pk = 12 v T0i 0 = 12 [ATv 0 ]Ti 0 = 12 v 0 [Aii 0 ] = 0

(21)

k=1

Definition. For a given one-port element, the factor

cos() cos(v i), appearing in Eq. (15), is called power
factor, where v i coincides with the phase of the
impedance of the one-port defined in Eq. (8). By using the
definition in Eq. (2) and Eq. (15), active power P exchanged
through a port is equal to the popular formula:

From the above proof, since the sum of active powers over all
elements of a circuit coincides with the real part of the sum
of complex powers, it is again proved that the sum of active
powers equals zero [see Eq. (16)].

P = veff ieff cos()

Definition. The modulus of complex power is called apparent

power and is symbolized as A:

(17)

Other equivalent expressions for active power are often used:

the first is equal to one-half the voltage amplitude v times the
component ic i0 cos() of current i in phase with
v, while the second is equal to one-half the current amplitude
i times the component vc v0 cos() of voltage v in phase
with i: P v0ic /2 and P vci0 /2.
In practice, active power is a measure of the absorbed or
delivered electrical energy in a unit time interval (see POWER
MEASUREMENT).
Complex Power
A definition, whose significance will be clarified later, is now
introduced, relating to a quantity that depends upon the
product of the voltage phasor with the conjugate of that of the
current. A priori this product does not have a physical meaning, since it is an unspecified operation in phasor theory [see
Eqs. (46)].
Definition. The complex power P in one-port elements is defined as one-half the product of the voltage phasor v and the
conjugate of the current phasor i*:

P = (1/2)vi = [P] + j[P]

= (v0 i0 /2) cos(v i ) + j(v0 i0 /2) sin(v i )

(18)

Note that the real part of complex power [P] coincides with
the active power in Eq. (15), while the imaginary part [P]
will be discussed later on.

A = |P| =

P2 + Q2 = (v0 i0 /2)

(22)

In general, the sum of all apparent powers extended to all

elements of a circuit is not null.
Reactive Power
The focus will now be on the imaginary part of complex
power [P] in Eqs. (18) and (19).
Definition. The imaginary part of complex power [P], denoted by Q
Q = [P] = (v0 i0 /2) sin(v i )

(23)

is called reactive power.

By observing the factor sin(v i) in Eq. (23), reactive power
Q appears to be positive, if the voltage anticipates the current
(resistive-inductive one-port), and negative otherwise (obviously Q 0 if voltage and current are in phase). The resulting
sign of Q is only a convention, universally accepted, due to
the introduction of the conjugate of the current phasor in Eq.
(18). If complex power were defined as (1/2)v*i, its imaginary
part would change sign. Reactive power Q in a capacitor or in
an inductor has a strong relation with the maximum value of
the instantaneous energy w(t) stored in the element during
one whole period.

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

Property. Reactive power Q and the maximum wM of w(t) are

related by:

Q = 12 bv20 = 12 Cv
20
Capacitor:
Q = w
M
wM = max[w(t)] = 12 Cv20
t

(24)
Q = 12 xi20 = 12 Li
20
Inductor:
Q = w
M
wM = max[w(t)] = 12 Li20
t

The above physical interpretation of reactive power does not

at all hold for other elements. Reactive power in a resistor is
always zero, because sin(v i) 0, while in an independent voltage or current source Q may be different from zero,
even if these elements are resistive. This result is explained
by considering that in independent sources the current or the
voltage is unconstrained.
Reactive Power Theorem. The sum of reactive powers over
all K elements of a SSS circuit is zero.
K


Qk = 0

Active, Reactive, and Complex Power in Two-Ports

Consider now the complex power absorbed by a two-port in
the case that representation matrix Z exists. The complex
power P absorbed by a two-port element has the complex quadratic form:

 T  
i 1
v1
=
v2
i 2

1
2 [i 1 i1 z11

1
2

 T 
z11
i 1
z21
i 2

i 1 i2 z12

i 2 i1 z21

P = 12 {(rm rm )[i 1 i2 ]} = 0 Q = rm [i 1 i2 ]

(28)

where rm is the gyration transresistance. The result in Eq.

(28) shows why the first port of a gyrator with the second port
closed on a capacitor (which absorbs negative reactive power)
is equivalent to an inductor (which absorbs positive reactive
power).
NETWORK FUNCTIONS

Proof. The sum of all reactive powers coincides with the

imaginary part of the sum of all complex powers. The latter
is zero because of Eq. (20).

1
2

Both active power P and reactive power Q in the four controlled sources and in the nullor may have any value in (,
) (see LINEAR NETWORK ELEMENTS and Table 5). Indeed,
these five two-port elements are characterized by having the
voltage and/or current of the output port unconstrained.
In an ideal transformer P and Q are both zero independently of the rest of the circuit. In fact, the instantaneous
power is null and the ideal transformer is reciprocal.
Compute the reactive power absorbed by a gyrator (see Table 5). In general, it may have any value, even if the instantaneous power absorbed is always zero, since the gyrator is
antireciprocal. This apparent paradox may be verified by
applying Eq. (27) to the impedance matrix of a gyrator.

(25)

k=1

P=

101

z12
z22

 
i1
i2

(26)

i 2 i2 z22 ]

where T denotes transposition.

Equating the real and imaginary parts of the two sides of
Eq. (26), the active and reactive power are obtained.

P = 12 {r11 i201 + r22 i202 + (r12 + r21 )[i 1 i2 ] + (x21 x12 )[i 1 i2 ]}


Q = 12 {x11 i201 + x22 i202 + (r12 r21 )[i 1 i2 ] +(x21 + x12 )[i 1 i2 ]}


(27)
Similar formulas hold for the other representations of twoports.
The form of the underbraced terms (r12 r21)[i*1 i 2] and
(x21 x12)[i*1 i 2] in Eq. (27) denotes the following properties.
Property. A two-port with a pure imaginary impedance and/
or admittance matrix does not absorb or deliver active power
if and only if it is reciprocal (i.e., x12 x21).
Property. A two-port with a pure real impedance and/or admittance matrix does not absorb or deliver reactive power if
and only if it is reciprocal (i.e., r12 r21).

The previous sections considered circuits operating in SSS

with a fixed angular frequency . Now consider the properties
of these circuits by considering the angular frequency as an
arbitrary variable of the problem. Toward this aim it is necessary to introduce the network functions of a circuit in SSS (4).
Definition of Network Functions
Set at zero the value of any sinusoidal source voltage and
current in the circuit except the source voltage or current,
generically denoted by u(t), which is considered to be an input
variable of the circuit. Any sinusoidal branch voltage or current, generically denoted by y(t), may be chosen as output
variable.
Definition. A network function is the quotient of the output
phasor y of y(t) by the input phasor u of u(t).
Circuit linearity causes the above quotient to depend only on
the angular frequency of the source, and not on its phasor
u; so j is the argument of the network function since it appears in the constitutive relations of any dynamical element.
Obviously since, in general, a circuit may have more independent sources (inputs) and many branch voltages or currents
that may be considered as output, several different network
functions may be defined in any dynamic circuit. In a general
situation, it is possible to define network functions as the quotient of the generalized phasors y and u of the complex exponential functions y(t) [y exp(st)] and u(t) [u exp(st)],
characterized by complex frequency s j. Equivalently,
network functions may be defined as the quotient of the Laplace transforms of the same quantities (see FREQUENCYDOMAIN CIRCUIT ANALYSIS). In these cases the network function
is a complex valued function F(s) of the complex variable s:
F(s) results to be the quotient of two polynomials with real
coefficients. This property can be shown by considering the
solution of the linear system in Eq. (7) obtained using the
Kramer rule: the denominator of F(s) coincides with the deter-

102

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

minant of the matrix of the system, while the numerator coincides with the determinant of a suitable submatrix, less possible common factors that cancel out. The roots of the
numerator polynomial are the zeroes of the network function,
while the roots of the denominator are the poles. Zeroes and
poles may be real or complex conjugate pairs: their values
characterize, less a constant factor, the network function and,
in particular, its behavior along the imaginary axis (see the
section titled Logarithmic Scales and Bode Plots and the subsection titled Factorization of Network Functions, later in this
article). If F(s) is evaluated along the imaginary axis, that is,
for s j, the network function F( j) defined in SSS is obtained.
Classes of Network Functions
In any network function in SSS the output phasor y may be
any branch current or voltage, and the input phasor u may
be any source voltage or current. Any network function may
then be seen either as the admittance or impedance of a composite one-port element, or as an off-diagonal element of the
impedance, admittance, or hybrid matrix [see Eq. (10)] of a
two-port subnetwork extracted from the circuit (see LINEAR
NETWORK ELEMENTS). One may then define the following
classes of network functions:
Impedance Function. The quotient of the voltage phasor
v of a current source by the current phasor of the source
itself (see Fig. 4a)
Admittance Function. The quotient of the current phasor i of a voltage source by the voltage phasor v of the
source itself (see Fig. 4b)
Transimpedance Function. The quotient of any voltage
phasor by any source current phasor
Transadmittance Function. The quotient of any current
phasor by any source voltage phasor
Voltage Gain Function. The quotient of any voltage phasor by any source voltage phasor
Current Gain Function. The quotient of any current phasor by any source current phasor

+
^

Remaining
subnetwork

(a)

i
v^

Remaining
subnetwork

(b)
Figure 4. Definition of immitance functions: (a) impedance and (b)
admittance.

Impedance and admittance functions are jointly called immittance functions, from the contraction of the terms impedance
and admittance. The last four network functions in the above
list are called transfer functions, because the input and output are related to two different branches of the circuit.
Magnitude and Phase of Network Functions
In SSS, network functions are, in general, complex valued
functions of the imaginary variable j, that is, any network
function may be written as F( j). Using complex number
mathematics, it is possible to derive from network function
F( j), two real-valued functions: magnitude F( j) and
phase F() F( j). It is possible to better examine these
real-valued functions by splitting the numerator N(s) and the
denominator D(s) of F(s) into even and odd parts:
N(s) = N2 (s2 ) + sN1 (s2 )

D(s) = D2 (s2 ) + sD1 (s2 )

(29)

where N2(s2) and D2(s2) contain the even terms of polynomials

N(s) and D(s), while sN1(s2) and sD1(s2) contain the odd terms.
By substituting s j, one can decompose both numerator
and denominator into real and imaginary parts:
F ( j) =

N (2 ) + jN1 (2 )
N( j)
= 2
D( j)
D2 (2 ) + jD1 (2 )

(30)

The magnitude F( j) is an even function of :

|F ( j)| =

[N ( )]
2

[D2

(2 )]2

+ [N1 (2 )]2
+ [D1 (2 )]2

(31)

It is often preferable to use the squared magnitude F( j)2

because it is rational in 2. For this reason it is used to solve
approximation problems in filter design (see FILTER APPROXIMATION METHODS; ANALOG FILTERS).
The phase function F() may be computed using the numerator and denominator of the network function:
F () = \F ( j) = \N( j) \D( j)

(32)

defined less an arbitrary integer multiple of 2. The phase

function is odd symmetric, F( j) F(j), with respect
to , because the substitution j j causes the change of
sign of the imaginary parts of N( j) and D( j). In general,
the phase function F() is continuous in , except in correspondence of pure imaginary conjugates zeroes or poles,
where phase has a k discontinuity, where k is the multiplicity of the zeroes or poles, including possible poles or zeroes
in the origin.
Phase of the Immittance of One-Port Elements
The phase of an immittance function is important in classifying one-port elements; to this end the terminology reported in
Table 7 and illustrated in Fig. 5 is used.
Properties. It may be easily seen that any one-port subnetwork containing only resistors and inductors is resistive-inductive for any value of , because this subnetwork absorbs
nonnegative reactive power for any . Analogously, any oneport will be resistive-capacitive if it is built using only capacitors and resistors. Subnetworks containing resistors, capaci-

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

103

Table 7. Phases of Immittances and Related Classification

One-Port Element Class
Inductive
Resistive-inductive
Resistive
Resistive-capacitive
Capacitive

Phase

Comment

z( j) y( j) /2
0 z( j) y( j) /2
z( j) y( j) 0
0 z( j) y( j) /2
z( j) y( j) /2

v anticipates in quadrate
v anticipates
v and are in phase
anticipates v
anticipates in quadrate v

tors, and inductors will be, in general, resistive-capacitive in

some frequency intervals and resistive-inductive in others.
The series and parallel resonators are of this type (see the
section titled Resonance, later in this article).
Factorization of Network Functions
Since any network function is rational, it may be factorized
in order to evidence poles and zeroes.

F( j) = h ( j) 0

Kzr
!




k zc
!
[1 + j/z ]
[1 + j/(qz z ) + ( j/z )2 ]


=1

=1

K pr

[1 + j/ p ]

=1

Definition. When the degree of numerator and the degree of

denominator are not equal, the network function has a zero
or pole at infinity. Introducing the integer parameter as
the difference in degree,

Complex conjugate zeroes

Real zeroes



k pc
!

(33)

[1 + j/(q p p ) + ( j/ p )2 ]

=1



Real poles

Complex conjugate poles

Where h is the real constant factor and 0 is the number of

zeroes in the origin if 0 0 or the number of poles in the
origin if 0 0. Kzr and Kpr are the number of real zeroes and
poles, excluding those in the origin, while Kzc and Kpc are the
number of complex conjugate zero and pole pairs. Parameters
z and p are the th real zero and pole, z and p are

[z]

Inductive

the modulus of the th pair of complex conjugate zeroes and

poles. Parameters qz and qp of the th pair of complex conjugate zeroes and poles are strictly related to the phase of
complex conjugate poles or zeroes: q 1/[2 sin( /2)],
where is the phase of the complex zero or pole with positive
imaginary part. This formula shows that the q parameter
has, for complex conjugate pairs of poles or zeroes, an absolute value greater than 0.5.

= 0 + K pr + 2K pc Kzr 2Kzc

(34)

it may be easily seen that

> 0 : F ( j) 0 of order if
< 0 : F ( j) of order | if
= 0: no zeroes or poles of F( j) at infinity
LOGARITHMIC SCALES AND BODE PLOTS
Often the magnitude and phase of a network function are
most easily analyzed if logarithmic scales and logarithmic
quantities are adopted. In particular, plots are usually more
readable, the numbers involved in practical calculations are
more manageable, and the magnitude function may be easily
decomposed in simple addends.
Logarithmic Scale for Angular Frequency

Resistive-inductive

Resistive
[z]

Resistive-capacitive
Capacitive

Figure 5. Impedances in complex plane.

In the practical analysis of network functions it is often necessary to evaluate the magnitude or phase of the function in
many different values of , differing by several orders of magnitude. In this case, if a linear scale for is used to represent
magnitude and phase of a function, the resulting plot may be
quite unreadabletoo compressed for small values of , and
too expanded for high values. To avoid the problems mentioned above, a logarithmic transform of the axis is adopted:
the angular frequency is normalized with respect to 0
2f 0 and the base 10 logarithm is introduced:
log(/0 ) = log( f / f 0 )

(35)

With the above scale a decade is a unit length interval of the

logarithmic quantity just defined, that is, an interval where
, and analogously f, vary by a factor of 10.

104

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

Logarithmic Scale for Magnitude Functions

The magnitude F( j) or the squared magnitude of a network
function may have values differing by several orders of magnitude, even for small variations of . If a linear scale was
used, the magnitude plots of some network functions would
be poorly readable. To overcome this problem a logarithmic
transform is used: the magnitude of the network function
F( j) is substituted by the attenuation F(). When (trans)impedance or (trans)admittance functions are considered,
they must be normalized with respect to a conventional resistance. The base unit is called decibel (dB):
F () = 20 log(1/|F ( j)|) = 20 log(|F ( j)|)

(36)

Depending on the application, it is possible to use, instead of

the attenuation F() in dB, the gain defined as the negative
of the attenuation.
Definitions. The diagram obtained by representing the attenuation F() (or the gain in dB) on the y-axis and
log(/0) on the x-axis is called the magnitude Bode plot. The
phase Bode plot F() is obtained by representing the phase
on the y-axis with the usual linear scale and log(/0) on the
x-axis.
Decomposition of Attenuation (Gain) and Phase Functions
From complex number mathematics it is known that the modulus of the product or quotient of two complex numbers is
equal to the product or quotient of their moduli. For this reason the factorization of a network function, shown in Eq. (33),
is appropriate also for the corresponding magnitude F( j).
If the attenuation or gain of F( j) is considered and logarithmic scales are introduced, the factorization of the magnitude of a network function is transformed into a sum or difference of terms. Each term is the attenuation or gain of a factor
of the numerator or denominator polynomials of the network
function in Eq. (33), and carries information regarding a single real zero or pole, or a complex conjugate pair of zeroes or
poles, respectively. Thus it is possible to obtain the Bode plot
of the attenuation or gain as the addition of the simple plots
relating to each single term. For the attenuation:

F () = 10 log[|F ( j)|2 ] = 10 log(h2 ) 0 10 log(2 ) +

10

Kzr


log[1 + (/z )2 ] +

=1

10

Kzc


log[(1 (/z )2 )2 + (/(qz wz ))2 ] +

=1

+ 10

K pr


(37)

log[1 + (/ p )2 ] +

=1

+ 10

K pc


log[(1 (/ p )2 )2 + (/(q p p ))2 ]

=1

The plots of a single first- or second-degree factor, both of the

numerator and denominator of the network function, are
called elementary Bode plots.
The phase of the product or quotient of two complex numbers is equal, respectively, to the sum or difference of the
phase of the single factors. In this case it is not necessary to

use a logarithmic scale, as for magnitude, to expand the

phase as a sum of terms. If the numerator and denominator
polynomials of a network function F( j) are decomposed into
the first- and second-degree factors, the following property is
obtained:
Property. The phase F( j) of a network function is equal
to the sum (for the numerator factors) and the difference (for
the denominator factors) of the phases of the single first- and
second-degree factors:

F () = \F ( j) = 0 /2 +

=1

\(1 + j/z ) +

 
K pr
/(qz z )

\(1 + j/ p ) +
1 (/z )2
=1
=1
"

K pc

p p )

\ 1 + j 1 /(q
(38)
j(/ p )2
=1

Kzc


"

Kzr


1+ j

If in Eq. (33) h is negative, a constant contribute of must

be added to phase in Eq. (38).
RESONANCE
Resonance is a very important phenomenon in many fields
of physics. Resonant circuits have played a relevant role in
communication systems since their origin. They are of series
and parallel type and may be divided into ideal and nonideal
types (4).
Ideal Resonators
Ideal resonators are composed by the series or parallel connection of a capacitor and an inductor. Their immitance functions are:

Ideal series resonator


"
1
z( j) = 0 + jx() = j L
C
Ideal parallel resonator
"

1
y( j) = 0 + jb() = j C
L

(39)

Both reactance x() and susceptance b() are monotone increasing with respect to in (, ). When 0
1/ LC, called resonance angular frequency, both x() and
b() are null because the reactance and susceptance of capacitor and inductor cancel out. In other words, at resonance the
series resonator is equivalent to a short circuit and the parallel resonator to an open circuit. Analogously, frequency f 0
0 /(2) is called resonance frequency.
For 0 and 0 the resonators are equivalent to a
single element:

1
for  0
C
z( j) = jx()  jL for 0
z( j) = jx()  j

1
for  0
L
y( j) = jb()  jC for 0
y( j) = jb()  j

The previous results can be revisited in time domain.

(40)

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

In the ideal series resonator, the voltage over the capacitor vc(t) and the voltage over the inductor vl(t) coincide instant-by-instant less the sign: vc(t) vl(t), while the corresponding currents ic(t) and il(t) are coincident.
In the ideal parallel resonator, the current through the capacitor ic(t) and the current through the inductor il(t) coincide
instant-by-instant less the sign: ic(t) il(t), while the corresponding voltages vc(t) and vl(t) are coincident.
So, voltage over a series resonator and current in a parallel
resonator are zero, and instantaneous power p(t) exchanged
with the rest of the circuit is zero. Consequently, the sum of
the energies stored in the capacitor and in the inductor is
constant. Therefore, the exchange of instantaneous power
takes place only between the inductor and the capacitor inside the ideal resonator.

105

In lossy resonators the resonance angular frequency 0

1/ LC is again introduced as in the ideal case, although the
physical meaning is somewhat different: 0 is the angular
frequency at which the admittance or impedance are pure
real and coincide with that due to the embedded resistor:
y( j0) 1/r for the series resonator and z( j0) r for the
parallel one. For distant from 0 the approximated formulas
in Eq. (40) also hold for lossy resonators. So, the effect of the
added resistor is relevant only when is close to 0.
Rewrite y( j) and z( j) in Eq. (41) by introducing the normalized angular frequency /0 and by normalizing them
with respect to resistance r; one obtains the normalized immittances Fs( j) and Fp( j):

1
1 + jQs ( 1/)
1
Fp ( j0 ) = z( j0 )/r =
1 + jQp ( 1/)
Fs ( j0 ) = ry( j0 ) =

Lossy Resonators
Since the model of an ideal resonator is equivalent, at the
resonance frequency, to an ideal short circuit or open circuit,
a more realistic model might be needed in many situations.
For instance, if a sinusoidal voltage source, with angular frequency 0, is connected to an ideal series resonator with resonance frequency equal to 0, the model of the circuit is inconsistent in SSS. This model becomes consistent if the resonator
is assumed to be nonideal, that is, with a very small, but nonzero impedance at 0.
The nonideal model of a series/parallel resonator may be
characterized by a series/parallel resistor added to the corresponding ideal model (Fig. 6) and it is called a lossy series/
parallel resonator. In the series case a very small resistance
r value is chosen, while in the parallel case a small conductance 1/r is chosen, and so a large resistance value is used.
For any the nonideal model is not equivalent to a short or
open circuit. The admittance of lossy series resonator and the
impedance of lossy parallel resonator may be easily analyzed:

1
y( j) =
r + jL + 1/( jC)
1
z( j) =
1/r + jC + 1/( jL)

(42)

Factors Qs and Qp in Eq. (42) are defined as Qs r0 /r and

Qp r/r0 with r0 L/C. For the series resonators Qs is also
equal to the absolute value of the quotient of inductor or capacitor impedance, at 0, by the resistance of the resistor:
Qs (0L)/r 1/(0Cr). For the parallel resonator Qp is also
equal to the absolute value of the quotient of the capacitor or
inductor admittance, at 0, by the conductance of the resistor:
Qp 0Cr r/(0L).
The energy exchange of a lossy resonator with the remaining part of the circuit is not zero as in the ideal case.
However, if the Q factor is high, the energy dissipated inside
the resonator during each whole period 2/0 is a small fraction of the total energy stored in the capacitor and inductor.
Normalized Immittance of Lossy Resonators

(41)

The expressions in Eq. (42) of the normalized admittance

Fs( j) and the normalized impedance Fp( j) are equivalent.
Then, for both resonators, the unique normalized immittance
function F( j) is introduced:
F ( j) =

1
1 + jQ( 1/)

(43)

where Q may be either Qs or Qp.

The maximum value of the magnitude F( j) of F( j) in
Eq. (43) occurs for 1, where the imaginary part jQ(
1/) is zero. So, the magnitude function is bell-shaped.

Property. By substituting 1/ in Eq. (43), note that any

pair of values F( j) and F( j/) satisfies the relation
(a)

F( j) = F ( j/) = [F ( j/)]

C

(44)

(b)
Figure 6. Lossy (a) series and (b) parallel resonators.

So, in complex plane each pair of points F( j) and F( j/) is

symmetric with respect to the real axis, since they have the
same real part, but opposite imaginary part. This property is,
in general, regarded as geometric symmetry.

106

NETWORK ANALYSIS, SINUSOIDAL STEADY STATE

The Nyquist plot of F( j) (see NYQUIST CRITERION, DIAis a complete circle (Fig. 7) with the
segment 0 } 1 on the real axis as a diameter; for increasing
from 0 to point F( j) describes the circle clockwise, starting and ending in the origin.

F( j )

GRAMS, AND STABILITY)

1
2

Magnitude and Phase Functions of Lossy Resonators

Consider the magnitude F( j) and phase F( j) of lossy
resonators. The geometric symmetry of F( j) implies that
F( j) is geometrically even symmetric, while F( j) is geometrically odd symmetric, with respect to resonance frequency
1. For increasing values of Q factor this geometric even
or odd symmetry tends, respectively, to arithmetic even or
odd symmetry for values of close to resonance. If the Bode
plots are drawn by adopting a logarithmic scale for on the
abscissa, the previous geometric symmetries become arithmetic symmetries.
Consider now the normalized frequencies 1 and 2
marked in Fig. 7. The geometric symmetry states that
12 1. By means of a simple inspection of Nyquist plot,
both 1 and 2 satisfy the relations [F( j)] [F( j)]
and F( j) 1/ 2, that is,
1 1/1 = 1/Q 2 1/2 = 1/Q

F( j )

(45)

4
0

By subtracting the first equation from the second one, one obtains:

[ F( j )]

2
Figure 8. Plots of magnitude and phase of normalized immittance of
lossy resonators.

lossy resonators is bell-shaped and it is called band-pass

(Fig. 8).
Property. The phase Bode plot of F( j) in Fig. 8 depends on
Q factor of resonator:

\F ( j) = arctan[Q( 1/)]


"

d\F ( j)
1 d\F ( j)
= 2Q Q =
d

"

[ F( j )]

1/2

(46)

The difference 2 1 (2 1)/0 is the so-called relative bandwidth of lossy resonators and so Eq. (46) shows that
factor Q is a measure of the selectivity of the immittance magnitude of lossy resonators. Higher Q factors correspond to a
narrower relative band 2 1, and to resonators closer to
the ideal case. The magnitude of the immittance function of

Property. The normalized frequencies 1 and 2 1/1 satisfy the following relations:
2 + 1/1 1/2 1 = 2/Q 2 1 = 1/Q

1 0 2

=1

d

(47)
=1

The phase decreases from /2 to /2, it is null in 1, and

it has a derivative in 1 with absolute value for
Q . A higher selectivity of magnitude function corresponds to a phase function with higher slope. Note that the Q
factor coincides with the parameter q introduced in the second-order terms derived from the factorization of network
functions in Eq. (33).

BIBLIOGRAPHY

Figure 7. Nyquist plot of normalized immittance of lossy resonators.

1. C. P. Steinmetz, Complex quantities and their use in electrical

engineering, Proc. Int. Electr. Congr., Chicago, 1893, pp. 3374.

NETWORK ANALYSIS USING LINEARIZATION

2. C. P. Steinmetz, Theory and Calculation of Alternating Current
Phenomena, New York: W. J. Johnston Co., 1898.
3. M. E. Van Valkenburg, Network Analysis, Englewood Cliffs, NJ:
Prentice-Hall, 1955.
4. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.

AMEDEO PREMOLI
GIANCARLO STORTI-GAJANI
Politecnico di Milano

NETWORK ANALYSIS, TIME-DOMAIN. See TIMEDOMAIN NETWORK ANALYSIS.

107

FREQUENCY-DOMAIN CIRCUIT ANALYSIS

When a designer is examining the behavior of an electrical circuit, the rst thing to do, as in the case of any other
physical system, is to write down a suitable set of equations
describing the existing links between the involved physical variables, which are, in this case, voltages and currents.
Generally, these equations arise from Kirchhoffs voltage
and current laws and from the branch relations which describe circuit components.
If there are dynamic components (i.e., described by
branch relations where time derivatives of voltages and/or
currents are present), then the circuit is governed by a system of mixed algebraic and integrodifferential equations.
The solution of such a system may be carried out using time
as the independent variable and evaluating the wanted
voltages and/or currents by numerical or analytical integration techniques. In this case the analysis is said to be
performed in the time domain.
A completely different approach may be followed
for linear time-invariant circuits. By using suitable
transformationsthat is, Laplace transform or Fourier
transformthe original integrodifferential equations,
which are linear with constant coefcients, are reduced
to algebraic equations, where the original time functions
are substituted by complex-valued functions of a complex
variable s = + j in the case of Laplace transform, or simply j in the case of Fourier transform. Then the system
of linear algebraic equations is solved for the new transformed functions. Finally, an inverse transformation recovers the requested voltages or currents as functions of
time. When following this procedure, the analysis is said
to be performed in the frequency domain or, alternatively,
in the s-domain when an explicit reference to the Laplace
transform is preferred.
The frequency-domain approach offers several advantages over the direct solution of time-domain circuit equations:

1. The solution is reduced to algebra and is greatly simplied by the extensive use of tables.
2. The conditions of energy storage elements within the
circuit at the time when the input signal is applied
(i.e., the initial conditions) become part of circuit
equations and hence are automatically accounted for.
3. There is no need to evaluate initial conditions at
t = 0+, as in the case of time-domain analysis, when a
jump discontinuity occurs at t = 0. Only their values
immediately before the beginning of the transient
(i.e., at t = 0) are required.
4. The sinusoidal steady-state behavior of a linear circuit may be easily analyzed by resorting to network
functions dened in terms of Laplace transforms.
5. Frequency-domain analysis provides a deeper insight in the behavior of linear circuits. For example,
it is possible to effectively compute sensitivities, to
give stability conditions, to establish necessary and
sufcient conditions for the realization of one-port
and multiport networks, and so on.

6. Many design techniques are based on the description

of the circuit behavior in the frequency domain, via
network functions. The knowledge of these functions
is of paramount importance in designing feedback
amplier, one-ports, multiports, active and passive
lters, equalizers, oscillators, and so on.
7. Frequency-domain formulation allows an effective
description of transmission lines, which would otherwise require partial differential equation in the time
domain.
8. Frequency-domain formulation allows model simplication techniques not possible in the time domain.
In what follows, we rst describe the different methods developed to write circuit equations in the frequencydomain. Then we introduce the concept of network function
and its fundamental properties. As a third step, the use of
two-sided Laplace and Fourier transforms in circuit analysis is illustrated. Finally, a Section on the applications of
frequency-domain analysis with some examples completes
the manuscript.
FREQUENCY-DOMAIN CIRCUIT EQUATIONS
This section starts introducing the one-sided Laplace
transform and a number of its properties, relevant to circuit analysis. A complete discussion of this topic may be
found in Refs. 1 and 2. Successively, we will illustrate the
use of Laplace transform to write frequency-domain circuit
equations for lumped, linear, time-invariant circuits. The
case of distributed circuits will be considered at the end of
the paper.
The One-Sided LaplaceTransform
Given a function of time f(t) dened for all t 0, its onesided Laplace transform is dened as

where s = + j is a complex variable, called the complex

frequency. Note that in Eq. (1) the lower limit of integration
equals 0, to include functions which have a discontinuity
or an impulse at t = 0.
Equation (1) establishes a correspondence between the
time function f(t) dened for all t 0 and its Laplace transform F(s). This fact ensures that the solution coming from
the frequency-domain approach is identical to the one obtainable by operating in the time domain.
The integral which denes the Laplace transformation
exists under mild conditions on the function f(t), generally
met for the signals used in engineering. A sufcient condition is that f(t) is exponentially boundedthat is, |f(t)|
Mect for some constant M > 0 and some constant c, for all
t > 0 (or only for t greater than some t0 ).
The greatest lower bound + of the values of for which
the Laplace integral (1) exists is called abscissa of convergence. It can be shown that the Laplace integral denes an
analytic function within the half-plane of convergence >
+.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Frequency-Domain Circuit Analysis

Extensive tables of transform pairs have been built (see

Refs. 3 and 4) by using the denition given in Eq. (1). Examples of Laplace transforms of elementary functions are
reported in Table 1. Some of the main properties of onesided Laplace transform, relevant in circuit analysis, are
shown in Table 2. For proofs and a complete collection of
these properties, see Refs. 1 and 2.
The inverse transform, which gives f(t) from its Laplace
transform F(s), is denoted by L1 [F(s)] and is expressed by

In many practical situations, the inverse transform may

be simply obtained by resorting to a partial-fraction expansion of the original function. Then, the inverse transforms of the elementary fractions are found by inspection,
resorting to tables of Laplace transforms.
Tableau Equations
We start by considering the time-domain tableau equations for a lumped, linear time-invariant circuit (5, 6). The
(nodal) tableau equations are

ditions. In matrix form we have

0
0
T (s)W(s)
AT
1
0
M
s
0


+ M 1
0
=
0
U s (s) + U 0

A
0
N 0s + N 1



E(s)
V (s)
I(s)


(9)

where matrix T is constituted by elements which are either

real constants or real polynomials of degree 1 and W is the
vector of output variables.
Other forms of the tableau equations are possible if reference is made to fundamental cut-sets or fundamental
loops of the connected digraph associated to the considered circuit. These forms of the tableau equations are not
considered here, and the interested reader is referred to
Ref. 6, pp. 715717.
As a concluding remark, let us consider tableau equations 68 in more detail. Equations (6) and (7) may be obtained from Eqs. (3) and (4) by a simple substitution of
time functions with their Laplace transforms: They may
be viewed as Kirchhoff s current and voltage laws in the
frequency domain. Equation (8) contains the frequencydomain branch equations. They are listed in the fourth
column of Table 3, for the components shown in Fig. 1(a),
while in the third column the corresponding time-domain
equations are shown for comparison.
Impedance and Admittance. Consider a two-terminal element, with zero initial conditions. Let us choose associated
reference directions for input current and terminal voltage,
(e.g., see Fig. 1(a)) and denote their transforms by I(s) and
V(s), respectively. The ratio

where i is the vector of branch currents, v is the vector of

branch voltages, and e is the vector of nodal voltages with
respect to a datum node. Equations (3) and (4) are the matrix formulation of Kirchhoffs current and voltage laws:
A is the (n 1) b reduced incidence matrix, n being the
number of nodes and b the number of branches; the superscript T denotes transposition. The branch equations are
given (in matrix form) by Eq. (5): M0 , M1 , N0 , N1 are b b
matrices with real constant elements; D is the differentiation operator d/dt and us (t) is the vector of independent
sources.
The application of Laplace transform to both sides of
Eqs. 35, taking into account the properties shown in Table 2, gives the (nodal) tableau equations in the frequency
domain

where I(s), V(s), and E(s), are vectors of transformed branch

currents, branch voltages, and node-to-datum voltages, respectively. Us (s) is the vector of transformed independent
sources and U0 = M0 v(0) + N0 i(0) is the vector of initial con-

is called the impedance of the two-terminal element. The

reciprocal of the impedance

is referred to as the admittance of the two-terminal element. In the frequency domain, impedance and admittance
play the same role as resistance and conductance in Ohms
laws, respectively. Table 4 gives impedances and admittances of resistors, capacitors, and inductors.
Writing Circuit Equations by Inspection. Taking into account Eqs. (10) and (11), one can easily verify that the
circuits shown in Fig. 1(b) are governed by the algebraic
frequency-domain equations reported in the fourth column
of Table 3. These circuits are called the equivalent circuits
in the frequency domain for resistors, capacitors, inductors,
and coupled inductors.
As a consequence, the frequency-domain equations of
any circuit may be written directly, avoiding the preliminary step of writing time-domain equations. In fact, it is
sufcient to apply the same analysis methods used for resistive circuits (see Ref. 6, Chapter 5; and Ref. 7, Chapter 4) to a frequency-domain equivalent circuit, hereafter
called the transformed circuit, obtained by replacing each

Frequency-Domain Circuit Analysis

Table 1. Elementary One-Sided Laplace Trasform Pairs

Type

Laplace Trasform F (s) = [ f (t)]

(t)

Impulse function

u(t)

Unit step function

Time Function f (t)

1
s
1
s2
1
s+a
0

Ramp

t
eat

Exponential

eat sin 0 t

Damped sine

eat cos 0 t

Damped cosine

(s + a)2 + 02
s+a
(s + a)2 + 02
Table 2. Main Properties of One-Sided Laplace Transform

Property

Transform Pair

Linearity
Time differentiation
Time integration
Time shift
Frequency shift
Initial-value theorem
Final-value theorem

limt

L[a1 f 1 (t) + a2 f 2 (t)] = a1 F1 (s) + a2 F2 (s)

 df 
= sF (s) f (0 )
L
dtt
 1
L 0 f ()d = F (s)
s
L[ f (t t0 )u(t t0 )] = et0 s F (s), t0 > 0
L[es0 t f (t)] = F (s s0 )
+
f (0 ) = limt 0+ f (t) = lims sF (s)
f (t) = lims 0 sF (s), sF (s) regular on the j axis and in the right half-plane
Table 3. Branch Equations in the Frequency Domain

Component

Parameter(s)

Resistor

Capacitor

Inductor

v(t) = Ri(t)
dv
dt

Coupled inductors

Frequency Domaina

Time Domain

M, L1 , L2

V (s) = RI(s)

i(t) = C

I(s) = sCV (s) CV0

v(t) = L

or:
1
V0
V (s) =
I(s) +
sC
s
V (s) = sLI(s) LI0

di
dt

di1
+M
dt
di1
v2 (t) = M
+L2
dt
v1 (t) = L1

or:
1
I0
I(s) =
V (s) +
sL
s
V1 (s) = sL1 I1 (s) + sMI2 (s) L1 I10 MI20

di2
dt
di2
dt

V2 (s) = sMI1 (s) + sL2 I2 (s) MI10 L2 I20

V1 (s) = sL1 I1 (s)

V2 (s) = sM I1 (s)
a

Note that V0 , I0 , I10 , and I20 are initial values computed at t = 0 .

Table 4. Impedance Z(s) and Admittance Y (s) of Resistors, Capacitors, and

Inductors

Component

Parameter

Z(s)

Y (s)

Resistor

G 1/R

Capacitor

Inductor

R
1
sC
sL

sC
1
sL

element with its impedance or admittance and adding the

appropriate sources to take into account initial conditions.
Furthermore, for this transformed circuit all general
theorems, valid for linear time-invariant resistive circuits,

or:


I10
I20
+ sM I2 (s)
s
s
I10
s

+ sL2 I2 (s)

I20
s

(superposition, Thevenins, Nortons, Tellegens, etc.), still

hold.
Example The above results are used to write tableau
equations for the very simple circuit of Fig. 2(a). The transformed circuit is shown in Fig. 2(b), where v3 (0) = V0 and
i4 (0) = I0 are initial values of capacitor voltage and inductor current, respectively. The frequency-domain tableau
equations, written in matrix form and partitioned accord-

Frequency-Domain Circuit Analysis

ing to Eq. (9), are

Loop Equations
Figure 1. (a) Symbols and associated reference directions for
voltages and currents of resistors, capacitors, inductors and coupled inductors; (b) Frequency-domain equivalent circuits of resistors, capacitors, inductors and coupled inductors. For capacitors and inductors both the series and the parallel frequencydomain equivalent circuits are shown. Initial values are denoted
by V0 = v(0), I0 = i(0), I10 = i1 (0) and I20 = i2 (0).

The set of loop equations may be written directly in the frequency domain by substituting each circuit element with
the appropriate series equivalent circuit of Fig. 1(b) and
then applying the standard technique used for resistive circuits. Note that for nonzero initial conditions, supplemental voltage sources of the form LI0 and/or V0 /s are added to
the original circuit.
The nal set of loop equations has the form

Figure 2. (a) A simple RLC circuit; at t = 0 the capacitor has an

initial voltage v3 (0) = V0 and the inductor has an initial current
i4 (0) = I0 . Associated reference directions are assumed. (b) The
frequency-domain transformed circuit.

where Zl (s) is called the loop impedance matrix, Vs (s) is

the vector of independent voltage sources, and V0 (s) is the
voltage vector due to initial conditions.
The restriction imposed in loop analysis is that all elements must be current-controlled. If this is not the case,
one may resort to circuit transformations or to the modied
loop analysis (8).
Loop equations may be written by inspection. If the
circuit is formed only by resistors, capacitors, and inductors, the rules are particularly simple: The matrix Zl is
symmetric, the kth diagonal element zkk is the sum of all
impedances in loop k, and any off-diagonal element zjk is
the sum of all impedances common to loops j and k if the
reference directions for the two loops are the same, the
negative of the sum otherwise.
Finally, for a circuit with a planar graph, meshes may
be used instead of fundamental loops. In this case, mesh
equations are obtained in terms of ctitious circulating currents, generally referred to as mesh currents.

Frequency-Domain Circuit Analysis

Figure 3. (a) Loop (mesh) analysis; at t = 0 capacitors Cp and C

have initial voltages v2 (0) = VCp0 and vc (0) = 0 V, respectively.
(b) The frequency-domain transformed circuit.

Figure 4. (a) Nodal analysis; capacitor C1 has an initial voltage

v1 (0) = V10 . The initial value of the current iL through the inductor L is IL0 . (b) The frequency-domain transformed circuit.

Example Consider the (planar) circuit of Fig. 3(a). The

initial values of voltages across capacitors Cp and C are
v2 (0) = VCp0 and vC (0) = 0 V, respectively. In this case,
meshes can be chosen as fundamental loops. Assuming for
the mesh currents I1 and I2 the reference directions shown
in the transformed circuit of Fig. 3(b), we write the following frequency-domain mesh equations:

ments which are not voltage-controlled, circuit transformations should be performed. Finally, nodal analysis may be
effectively extended to circuits with ideal voltage sources
and/or ideal operational amplier (9, Section 4.5).
Example Consider the circuit of Fig. 4(a). V10 and IL0 are
initial values of capacitor voltage v1 and inductor current
iL , respectively. The initial voltage across C2 is zero. To effectively write nodal equations, the voltage source is rst
transformed into a current source by a TheveninNorton
transformation. The nal circuit, used to write nodal equations in the frequency domain, is shown in Fig. 4(b). The
following equations are obtained by inspection:

Nodal Equations
Nodal equations may be written directly in the frequency
domain by substituting each circuit element with the appropriate parallel equivalent circuit of Fig. 1(b) and then
applying the standard technique used for resistive circuits.
Note that for nonzero initial conditions, supplemental current sources of the form I0 /s and/or CV0 are added to the
original circuit.
The nal form of nodal equations is

where Yn (s) is called the nodal admittance matrix, Is (s) is

the vector of independent current sources, and I0 (s) is the
current vector due to initial conditions.
Nodal equations may be written by inspection. If the circuit is formed only by resistors, capacitors, and inductors,
the rules are particularly simple: The matrix Yn is symmetric, the kth diagonal element ykk is the sum of all admittances connected to node k, and any off-diagonal element
yjk is the negative of the sum of all admittances connecting
node j and node k.
Nodal analysis may be directly applied only to circuits
containing voltage-controlled elements. If there are ele-

Modied Nodal Equations

Modied nodal analysis (MNA) has been introduced to cope
with the problems associated with nodal analysis (6, 10).
MNA follows the logical steps of nodal analysis. When an
element is found which is not voltage-controlled, its current
is added to the set of unknowns. To balance the number
of unknowns and the number of equations, the element
equation is added to the set of equations.
In matrix form we have

where E(s) is the vector of nodal voltages, I(s) is the vector

of unknown currents, Us (s) is the vector of transformed
independent sources, and U0 is the vector due to initial
conditions.

Frequency-Domain Circuit Analysis

The elements of the coefcient matrix P(s) depend solely

on the circuit topology, on complex frequency s, and on element values. They are either real constants or real polynomials of degree 1. If inductor currents are not added to the
unknowns, then also monomials of degree 1 are present.
In such a case, U0 may contain terms of the form I0 /s.
MNA has many attractive features. The coefcient matrix and the right-hand side vector of Eq. (17) can be assembled by inspection through stamps describing the contribution of each circuit element (10). MNA can be applied to
any circuit, including those containing transmission lines,
without the need of circuit transformations and keeping
the number of equations to a minimum. Furthermore, if
any current is required as output variable, it may be directly inserted in vector I of Eq. (17), adding the corresponding branch relation to the set of MNA equations.
Example MNA is illustrated by resorting to the circuit of
Fig. 5(a), where the operational amplier is supposed ideal.
The frequency-domain transformed circuit is shown in Fig.
5(b), where V20 and V30 are initial values of capacitor voltages v2 and v3 , respectively. The modied nodal equations
are

Figure 5. (a) A simple RC-active circuit; at t = 0 the capacitors

C2 and C3 have initial voltages v2 (0) = V20 and v3 (0) = V30 , respectively. (b) The frequency-domain transformed circuit.

In the above equation, X(s), X0 , and U(s) are the vectors

of transformed state variables, of initial conditions, and of
transformed independent sources, respectively. A and B are
matrices of appropriate dimensions (note that A is not the
incidence matrix).
Equation (19) may be rearranged to yield

where 1 is the identity matrix.

Natural Frequencies

STATE EQUATIONS
State equations are best suited for time-domain analysis,
even if sometimes it may be useful to solve these equations in the frequency domain. Also in this case, all known
methods used to write time-domain state equations (inspection, equivalent sources, or network graph theory; see
Ref. 11, Chapter 6) may be applied to the transformed circuit obtained by substituting inductors and capacitors with
the series and parallel circuits of Fig. 1(b), respectively. In
spite of that, state equations are generally written rst in
the time domain and then transformed to the frequency
domain, where they take the following form:

Let us consider a (linear time-invariant) circuit described

by its tableau equations [Eq. (9)]. This system of linear algebraic equations admits a unique solution if and only if
matrix T(s) is invertible; that is, det[T(s)] is not identically
zero. Furthermore, since all elements of T(s)) are polynomials of degree either 0 or 1 in s, det[T(s)] is a polynomial
in s too, with real coefcients, called the characteristic polynomial of the circuit. The roots i of

are called the natural frequencies of the circuit. They are

either real or occur in complex-conjugate pairs.
Note that when working in the time domain, T(s) becomes T(D), where D is the differentiation operator d/dt,
and hence the above denition of natural frequencies coincides with that given in the time domain (Ref. 12, Chapter
12).

Frequency-Domain Circuit Analysis

If all independent sources are set to zero (i.e., considering the circuit in the zero-input state), then, applying
Kramers rule, a generic output variable Wk (s) is given by

where ik is the cofactor of the element (b + n 1 + i), k of

T(s) and Ui0 denotes the ith source due to initial conditions.
Expanding the right-hand side of Eq. (22) in partial fractions and then taking the inverse Laplace transform of both
sides, it turns out that, in general, any zero-input response
is a linear combination of exponentials ei t (or polynomials
in t times eit ), called modes, where each i is a natural frequency of the circuit. For some particular response, some
modes may be absent.
If all the natural frequencies of the circuit have negative real part, then the zero-input response, for any initial
state, goes to zero exponentially with increasing time. In
this case, the circuit is referred to as strictly (or exponentially) stable.
Natural frequencies are an intrinsic feature of the circuit: They depend only on the circuit and not on the method
used to analyze it. In fact, it can be shown that the nonzero
natural frequencies of any linear time-invariant circuit are
identical to the nonzero roots of the determinantal polynomial of the matrix of any system of equations describing
the circuit, when framed as a set of linear algebraic equations of the form R(s)W(s) = F(s) (see Ref. 13, Chapter 14).
The total number of natural frequencies is not greater than
the number of energy-storing elements present in the circuit and it denes the order of complexity of the circuit (see
Ref. 14, Chapter 8). Zero natural frequencies are of limited
physical signicance, and in some cases their number may
be determined by inspection (see Ref. 12, Chapter 11).
In the case of tableau analysis and MNA, the determinantal polynomials of matrices T(s) and P(s) differ from
each other only for a multiplicative constant, and hence
they give the same set of natural frequencies, including
those at s = 0 (if any), with the same multiplicities (see Ref.
6, Section 10.4.2).
In the case of state equations, let us consider them in
the form given byEq. (20). The natural frequencies are the
roots of the determinantal polynomial

and hence they coincide with the eigenvalues of matrix A.

As in the case of tableau analysis and MNA, Eq. (23) supplies all natural frequencies, including zero natural frequencies, with their own multiplicities.
NETWORK FUNCTIONS
Given a lumped, linear time-invariant network in the zero
statethat is, with zero initial voltages across all capacitors and zero initial current through all inductorsa network function H(s) is dened as the ratio of the Laplace
transform W(s) of an output variable w(t) to the Laplace
transform Q(s) of an input variable q(t):

If the input is an unit impulse, then Q(s) = 1 and hence

H(s) turns out to be the Laplace transform of the impulse
response of the circuit.
If input and output variables are dened at the same terminal pair, the network function is either an impedance or
an admittance, as dened in Eqs. (10) and (11), respectively.
If input and output are measured at two different terminal pairs, the network function is referred to as a transfer
function. A transfer function may have the dimension of
impedance or admittance or be dimensionless.
In the case of multiple-input multiple-output circuits,
a matrix transfer function H(s) may be dened, whose k,
i element is the ratio of the Laplace transform of the kth
output variable to the Laplace transform of the ith input
variable, when all others input variables are set to zero.
Network functions may be efciently obtained by resorting to network symbolic analysis programs. In general, these programs are also able to perform mixed
numericalsymbolic analysis (15, 16) and to evaluate sensitivities (e.g., see Ref. 17, Chapter 10); and Ref. 18, Chapter
8).
Fundamental Properties
Consider, for simplicity, a single-input single-output
lumped, linear circuit. Any network function may be determined starting from any set of circuit equations described
in the previous section. Referring again to tableau equations [Eq. (9)] and using Kramers rule, we have

where Wk (s) denotes the kth output variable and ik is the
cofactor of the element i, k of T(s), where i is the position
of the independent source Qi (s) into the right-hand side
vector of Eq. (9).
From Eq. (25), it follows that any network function of a
lumped, linear circuit is a real rational function of sthat
is, the ratio of two polynomials with real coefcients. Its
nite poles are natural frequencies of the circuit, according
to Eq. (21); due to a possible pole-zero cancellation, some
natural frequencies may not appear as poles of the network
function (see Ref. 6, p. 612).
The transform Wk (s) of the output variable is given by

Transient response is computed by nding a partialfraction expansion of the right-hand side of Eq. (26) and
then taking the inverse Laplace transform of each term of
the expansion. If the network function has no poles inside
the right half-plane and if its j-axis poles (if any) are simple, then the (zero-state) impulse response of the circuit
remains bounded and the network function is said to be
stable. If there are no poles on the j-axis, then the impulse
response decays with time, and moreover, any (zero-state)
response remains bounded for any bounded input. In this
case the network function is said to be strictly stable (see,
for example, Ref. 19, Chapter 9).
When the network functions are impedances or admittances of RCLM networksthat is, networks composed of

Frequency-Domain Circuit Analysis

a nite number of resistors, capacitors, inductors, and coupled inductorsthey must be positive real functions; other
constraints are added for two-element-kind (i.e., RC, RL,
and LC) networks (20).
The Sinusoidal Steady State
The large use of network functions in circuit analysis in
only partially due to their utility in evaluating complicated
transients. One of the reasons for their acknowledged importance is related to their capability to describe the sinusoidal steady state of stable networks according to the
following theorem, usually referred to as the fundamental theorem of sinusoidal steady state (19, Section 9.4; 6,
Section 10.5).
Theorem Consider any linear time-invariant circuit,
driven by sinusoidal independent sources, all at the same
frequency . If the circuit is strictly stable (i.e., all the natural frequencies have negative real part), then, for any set
of initial conditions, all voltages and currents tend, as time
goes to innity, to a unique sinusoidal steady-state at the
same frequency .

Transfer functions play an important role in engineering, since they can be easily and accurately measured, resorting to stable sinusoidal oscillators and to precise measurement equipmentsfor example, to network analyzers.
On the other hand, they are the starting point for designing networks with a prescribed frequency behavior, as in
the case of electrical lters and equalizers.
When poles and zeros of network functions are known,
gain and phase versus frequency curves can be easily plotted, resorting to the so-called Bode plots (Ref. 21, Section
8.2). On the contrary, if curves of magnitude or phase, or
real or imaginary parts, versus frequency are given, methods have been developed to build realizable network functions (20).
It is important to remember that real and imaginary
parts of any stable network function are related to each
other and, hence, constraints on them cannot be assigned
arbitrarily. In fact, for a network function with no poles in
the right half-plane and on the j axis (innity included),
they satisfy the following equations (see, for example, Ref.
18, Chapter 7):

In the case of a single-input single-output circuit described by Eq. (24), magnitude Wm and phase w of the
output waveform are given by (see Ref. 6, Section 10.5)

where Qm and q are magnitude and phase of the input

signal, respectively.
In terms of phasors (see Ref. 6, Chapter 9) we have

= |W|ej

where W
w and Q = |Q|ejq are the phasors of output and input waveforms, respectively, and H is the transfer function dened in terms of the sinusoidal steady state.
A comparison of Eq. (29) with Eqs. (27) and (28) shows
that any phasor transfer function, dened in the sinusoidal
steady state, may be obtained simply by setting s = j in
the corresponding transfer function H(s) dened in terms
of Laplace transforms.
H(j) is a complex valued function of and may be written as

The parts of H(j)that is, real part R(), imaginary part

I(), magnitude |H(j)| (or gain 20 log|H(j)|), and phase
h ()are the quantities involved in the steady-state response to sinusoidal excitations. Generally speaking, the
overall information contained in any pair of these parts
[i.e., magnitude (or gain) and phase, or real and imaginary parts], when considered as a function of frequency
f = /(2), is referred to as frequency response of the circuit.
It is easily veried that real part R() and magnitudesquared function |H(j)|2 are even functions of , whereas
imaginary part I() and tan h () are odd functions of .

where R() is the value of the network function at innity. The above equations state that if the imaginary part is
specied over all frequencies, then the real part is determined to within an additive constant and that, if the real
part is specied, then the imaginary part is completely determined. Similar results hold also for gain and phase of a
network function, provided that it has no zeros in the right
half-planethat is, it is a minimum-phase function (18).

TWO-SIDED LAPLACE AND FOURIER TRANSFORMS IN

CIRCUIT ANALYSIS
In addition to the one-sided Laplace transform, other frequency representations of time functions are possible and
yield circuit equations closely related to the ones introduced in the previous sections. In this section, we discuss the use of two of such representations, the twosided Laplace Transform and the Fourier Transform. The
two-sided Laplace transform has a marginal role in circuit applications, however it is considered here because it
completes the theoretical framework of frequency-domain
analysis. The Fourier transform, instead, adds signicant
possibilities to the frequency-domain analysis of circuits
and, therefore, is discussed for both its theoretical and
practical importance. In the following, we briey review
the denition and the properties of the two transforms,
along with the frequency-domain circuit equations which
arise when such transforms are used.

Frequency-Domain Circuit Analysis

Two-Sided Laplace Transform

The two-sided Laplace transform of the function f(t) is

where s = + j, and lowercase and overlined uppercase

letters are used for transform pairs (22).
The following decomposition is useful to compute the
two-sided Laplace transform:

where F(s) is the one-sided Laplace transform of f(t) and

F (s) is the one-sided Laplace transform of f(t) computed
for t [0+, ] and argument s. The two-sided Laplace
transform exists for any s such that both F (s) and F(s)
exist. If F (s) has abscissa of convergence (i.e., it exists
for < ), F(s) has abscissa of convergence + (i.e., it exists
for > + ), and + < , then F (s) exists and is an analytic
function of s in the strip of convergence + < < . When
+ = , F (s) can exist as a distribution, whereas when +
> , F (s) does not exist.
The inversion of the two-sided Laplace transform can
be obtained by the line integral

where the integration line is in the strip of convergence, or

by the F (s) and F(s) decomposition and tables of one-sided
Laplace transform pairs. In the latter case, F (s) and F(s)
are identied by their poles, since the poles of F (s) are on
the right of and those of F(s) are on the left of + .
Fourier Transform
The Fourier transform of the function f(t) is

where lowercase and script uppercase letters are used for

transform pairs (23). The inverse transformation is

The term spectrum of f(t) is also used to indicate F(), or,

less often, the magnitude of F().
A sufcient condition for the existence of F() requires
that f(t) has bounded variations (i.e., nite variations for
nite time increments) and is absolutely integrable. For
time functions with nonvanishing asymptotic values, the
Fourier transform may exist as a distribution (23).
Properties of Two-Sided Laplace Transform and Fourier
Transform
Table 5 summarizes two-sided Laplace transform and
Fourier transform pairs of common use, with emphasis on
two-sided time functions, as algebraic, rational and har-

monic signals (22, 23). Table 6 lists the main properties of

the two transformation methods.
Most properties of Table 6 are identical to the corresponding properties of Table 2 for the one-sided Laplace
transform, or follow from these by simply replacing s with
j. A major difference in the properties of the two-sided
Laplace transform and of the Fourier transform concerns
the derivation formula, where the f(0) term is dropped.
Owing to the latter point, these transforms are not suited
for the inclusion of the initial conditions in the solution of
circuit equations.
Other properties, involving the parts of F(), are stated
for network functions in the section entitled The Sinusoidal Steady State.
Relations Between Transforms
The different transforms of a waveform can be obtained
one from the other via direct relations. Such relations ease
the shift between frequency representations, allowing one
to exploit their specic properties.
The two Laplace transforms coincide for one-sided functions (f(t) = 0 for t < 0).
The Fourier transform F() exists when F (s) exists on
the j axis and is given by F() = F (j) [see Eqs. (33) and
(36)]. Graphically, each part of F() is the prole of the
corresponding part of F (s) along the j axis. If the j axis
does not belong to the strip of convergence of F (s), F() does
not exist, whereas if the j axis is a boundary of the strip,
F() exists as a distribution (e.g., see Ref. 23, Section 9.2).
Finally, F (s) can be interpreted as the Fourier transform
of the function f(t)exp( t), which is F( + /j) = F(s/j) (see
Table 6, frequency shift) for every where f(t)exp( t) is
Fourier-transformable.
Circuit Equations and Network Functions
Frequency-domain circuit equations based on the twosided Laplace transform and on the Fourier transform
arise by applying such transformations to the time-domain
circuit equations. The equations obtained in this way differ
from those based on the one-sided Laplace transform only
in the branch relations of dynamic elements. The transformation of linear time-invariant dynamic branch relations
via two-sided Laplace transform and Fourier transform replaces the time-derivative operator with s and j, respectively, and adds no initial contribution.
For the two-sided Laplace transform, furthermore, the
time-integral operator is simply replaced by 1/s, and, hence,
the equivalent circuits of basic elements follow from those
of Fig. 1(b) by simply dropping the initial condition sources.
Accordingly, the one-sided Laplace equations written in the
section entitled Frequency-domain Circuit Equations become two-sided Laplace equations by setting initial conditions to zero and representing variables by two-sided
Laplace transform (i.e., F(s) F (s)).
For the Fourier transform, instead, some additional care
is required. In order to avoid frequency-domain equations
containing () terms, it is expedient to avoid the Fourier
transformation of time-domain equations involving the
time-integral operator (e.g., see row 3 of Table 6). Every
one-sided Laplace equation written in the section entitled

10

Frequency-Domain Circuit Analysis

Table 5. Elementary two-Sided Laplace Transform and Fourier Transform Pairs
W (s), s.c.a

W()

2(s), = 0
2 (s), = 0
2 (s), = 0
1, < <
2(s s0 ), 0
[(s j0 ) + (s + j0 )], = 0
2/s, = 0

2()
2 ()
2 ()
1
2( + js0 )
[( 0 ) + ( + 0 )]

2/ j
T
( nT )
n=

w(t)
1
t
t2
(t)
exp(s0 t)
cos(0 t)
sign(t)

n=

(t nT )

Note that s.c. indecates the strip of convergence of W (s);  () and  () are the rst and second derivative of the delta function,
respectively; s0 = 0 + j0 is a complex constant; and T = 2/T .
a

Table 6. Main Properties of Two-Sided Laplace Transform and Fourier Transforma

Property

(t)

W (s)

W()

Linearity

a1 f 1 (t) + a2 f 2 (t)
d f (t)
 t dt  
f (t )dt

a1 F 1 (s) + a2 F 2 (s)

a1 F1 () + a2 F2 ()

sF (s)

jF()
1
F() + F(0)()
j
F()exp(t0 )
F( + js0 )

Time differentiation
Time integration
Time shift
Frequency shift
Convolution
Moment theorem
a

f (t t0 )
f (t)exp(s0 t)

1F
(s)
s
F (s)exp(st )
0
F (s s )
0

f (t) g(t)

F (s)G(s)

t n f (t)dt

d n F (s)
(1)
dsn
n

F()G()
d n F()
jn
dn

Note that * and s0 indicate convolution and a complex constant, respectively.

Frequency-domain Circuit Equations which does not contain the factor 1/s can be turned into an equation based on
the Fourier transform by replacing s with j, setting initial
conditions to zero and representing variables by a Fourier
transform. As an example, the tableau equations in the
Fourier domain are

Similarly in the section Network Functions, we dene

network functions in terms of two-sided Laplace and
Fourier transforms by

and H are the different transThe network functions H, H

forms of the same impulse response h(t). Since h(t) is sup
posed to be a causal (i.e., one-sided) function, H(s)
= H(s)
and, provided H(s) is strictly stable (i.e., the j axis be
longs to its strip of convergence), H() = H(j)
= H(j) (see
the section entitled Relations Between Transforms). The
latter relation highlights also that H() yields the steadystate response to a harmonic input signal (see the section
entitled The Sinusoidal Steady State). In the following,
network functions are indicated only by H(s) and H(j).
Additional Fourier Transform Properties
Additional properties of the Fourier transform relevant to
circuit analysis are briey reviewed.

Physical Meaning of the Fourier Representation. The

Fourier representation describes signals in terms of harmonic components and the behavior of linear timeinvariant systems in terms of transformation of harmonic
components. This interpretation arises from Eqs. (37) and
(39):

where q(t) and w(t) are the input and output signals of
a circuit with network function H(s), respectively, and W
and Q are their Fourier transforms. In the above equation, [1/2W() d] ej t are the complex harmonic signals
composing w(t), each of which comes from the corresponding component of the input signal [1/2Q() d] ej t modied by H(j). Such an equation formalizes the operation of
linear frequency selective circuits and is the basis for the
physical interpretation of frequency responses.
Energy and Power Spectra. The Fourier transform allows
also a frequency representation of the energy content of
signals (24). The energy of q(t) can be expressed by the
sum of the energies of its harmonic components

where * denotes complex conjugation. The above equation

stems from the orthogonality of harmonic components and
is known as the Parsevals formula for nite energy signals.
This relation leads to the denition of the energy spectrum
Gq () Q()Q*()/2 (i.e., the energy density of q(t) within

Frequency-Domain Circuit Analysis

11

Figure 6. Behavior of vo and vs versus time.

[, + d]) and of the autocorrelation function Rq () as the

inverse Fourier transform of Gq ().
The autocorrelation and energy spectrum concepts can
be extended to signals with nite average power and to stationary stochastic processes, thereby providing a frequency
representation also for these important class of signals
(24). In this case, the energy spectrum is renamed power
spectrum and the frequency-domain analysis results extend to these signals by the transfer relation

where Gq () and Gw () are the power spectra of the input

and output related by the network function H(j), respectively.

When network functions are computed on the j axis

(i.e., the Fourier representation is used), they offer a
frequency-by-frequency portrait of the circuit behavior, describing how the harmonic components of the input signals
are changed. This is useful both in obtaining and in specifying the circuit frequency responses, helps the physical
interpretation of frequency-domain results, and allows the
frequency characterization of circuits by measurements.
For its properties, the Fourier approach is common in problems involving steady-state analysis, signal propagation,
and stochastic signals.
In this section we show examples of frequency-domain
circuit analysis, which illustrate typical applications and
remark the features of the different transformation methods.

APPLICATIONS OF FREQUENCY-DOMAIN ANALYSIS

Transient and Frequency Responses

The procedure for the frequency-domain analysis of circuits is almost independent of the transformation method
used. This latter decides only which waveforms can be represented, how they are represented, and which elements of
the circuit behavior are highlighted. Apparently, Laplace
transform seems able to handle a more general class of
functions and, therefore, seems preferable. This point, however, is controversial (e.g., see Ref. 23) and the transformation method, instead, should be chosen according to applications.
Roughly speaking, network functions in the s domain
offer zero-pole portraits of the circuit behavior and provide
the most reliable information on system dynamics and stability. Furthermore, the one-sided Laplace transform takes
into account the initial conditions of energy-storing elements and is the preferred transformation method for the
frequency-domain solution of transient problems.

In order to illustrate the evaluation of transient and frequency responses, we consider the circuit of Fig. 4(a). For
such a circuit, we compute the zero-state response of voltage vo (t) across resistor RL to a rectangular input pulse of
duration T and height E0 ; that is, vs (t) = E0 [u(t) u(t T)].
Besides, we compute also the frequency response of vo to
the input vs . The components have the following (normalized) values: Rs = RL = 1 , C1 = C2 = 1 F, L = 2 H, E0 = 2 V,
and T = 1 s.
To solve this problem, we rst compute the voltage
transfer function H(s) = Vo (s)/Vs (s), by using Eq. (16) and
setting to zero the sources related to initial conditions.

where  is the determinant of the nodal admittance matrix

Yn and 12 is the cofactor of element 1, 2 of Yn .

12

Frequency-Domain Circuit Analysis

puted directly by the two-sided Laplace transform (e.g., see

Ref. 26, Chapter 9).
The evaluation of the asymptotic part is particularly important for periodic input signals. In this case, the asymptotic response is usually named steady-state response. Here,
we illustrate two typical approaches to the evaluation of
such a response. For this, we write a periodic input signal
of period T as

where qT (t) is the cycle function, which coincides with q(t)

in [0, T] and is null elsewhere, and * denotes convolution.

Figure 7. Frequency response for the circuit of Fig. 4.

From Tables 1 and 2, the Laplace transform of the input waveform turns out to be
Vs (s) = E0 (1 eTs )/s = 2(1 es )/s. As a consequence,
the transform of output voltage is

By expanding in partial fractions, we obtain

Taking the inverse Laplace transform of each term of the

above equation and resorting again to Tables 1 and 2, we
have

where vo is expressed in volts and t in seconds. Fig. 6 shows

the behavior of vo and vs versus time.
To obtain the frequency response, we set s = j in Eq.
(43):

The parts of H(j) are easily computed from the

above equation. Figure 7 shows the curves of gain
gH = 20log|H(j)| and phase H = arg[H(j)] for 0 4
rad/s.
Asymptotic Responses of Circuits
The response of (strictly) stable circuits can be intuitively
divided into a transient part and an asymptotic part (see
Ref. 25 for a complete discussion). The two parts can be visualized and computed by a partial-fraction expansion of
the circuit response. Fractions from the poles of the circuit
transfer function H(s) represent decreasing time functions
and form the transient part, whereas the other terms form
the asymptotic part. The asymptotic part can be also com-

One-Sided Approach. The steady-state response wa (t) is

a periodic function of period T. The one-sided approach consists in applying the periodic input from t = 0 and leads to
the cycle function waT (t) of wa (t).
With this approach, the transform W(s) of the complete
response w(t) is given by

where Wt and Wa = WaT (s)/(1 esT ) collect the poles of H(s)

and 1/(1 exp(sT)), respectively (QT (s) is analytic everywhere but at innity). In Eq. (49), Wt (s) can be explicitly
computed from the partial fraction terms of W(s) involving
the poles of H(s). Once Wt (s) is computed, WaT (s) is obtained
as

The interested reader is referred to Ref. 27 for a detailed

discussion and illustrative examples.
Fourier Approach. In this approach wa (t) is obtained as
a Fourier series via H(j) and the Fourier transform of the
periodic input.
The Fourier transform of the periodic input is a line spectrum composed of equispaced ideal pulses (see Eq. (48) and
Table 5) and Wa () is composed of the same input lines
modied by H(j)

From above, the Fourier series of wa (t) follows

Though the computation of wa (t) via its Fourier series is

simple, it is practically useful only when the number of signicant harmonic component is small. On the other hand,
this representation can be exploited also for the asymptotic
responses of weakly nonlinear circuits driven by periodic
sources. For such an analysis, each nonlinear circuit element is characterized by generalized network functions describing how the element combines its input spectral lines
into output ones (28).

Frequency-Domain Circuit Analysis

13

The simplest approach to generate reduced order approximations of network functions relies on Pade approx
imants (30). A rational approximation H(s)
of order p to
H(s),

can be sought by expanding the Maclaurin series of H(s)

and H(s), up to order n = 2p 1

The above equation requires

Figure 8. Evaluation of equivalent noise sources for a two-port

element with noisy resistors: (a) Original problem; (b) transformed
circuit with equivalent sources V01 () and I01 ().

Noise Sources
In this section we illustrate the frequency-domain analysis
of circuits containing stochastic sources characterized by
their power spectra (24, Chapter 10).
We consider the very simple example of Fig. 8(a). Noise
sources e1 (t) and e2 (t) model the thermal noise generated
by the two resistors. A typical problem in noisy two-port
elements is the evaluation of the source terms of their
chain matrix constitutive relationsthat is, the equivalent
sources v01 and i01 shown in Fig. 8(b).
In order to obtain the equivalent sources for this example, we replace e1 (t) and e2 (t) with deterministic signals
with spectra E1 () and E2 () and generate the transformed
circuit of the problem. V01 () and I01 () can be computed as
the voltage and current at port one, ensuring null voltage
and current at port two. This analysis yields the following
transfer relations:

When noise sources are described by their power spectra Ge1 () and Ge2 (), the power spectra of the equivalent
sources are obtained by using the statistical independence
of e1 and e2 so that Eq. (42) yields

which yield the unknown parameters k j and s j as functions of the coefcients H(n) (0) = [dn H(s)/dsn ]s=0 . Such coefcients are shortly named moments of H(s) (see Table
6 moment theorem), and are much easier to compute than

H(s) itself. In this basic version, H(s)

approximates H(s) for
small s values (i.e., in the low-frequency range), however,
different series expansion and coefcient identities have
been devised to cope with different frequency ranges (the
interested reader may refer to (29) for a detailed discussion).
The moments of network functions can be easily obtained by MNA, however their evaluation is affected by
numerical error and the generation of rational approximations from them is an ill conditioned problem. As a result, rational approximations with more than a few tens
of poles can be hardly obtained via explicit moment calculation. Recently, several methods have been developed to
generate accurate high order rational approximation via
Krylov subspace projections and implicit moment calculation. These methods operate by projecting the vector of the
nodal voltages and supplemental currents of the network
on the Krylov subspace generated by the moments of the
network function matrix of the problem. Let the zero-state
frequency-domain MNA equations of a network be written
as

X = sAX + RU
Y = LT X

(58)

where U is the vector of sources, X is the vector collecting

the N nodal voltages and supplemental currents of the network, and Y is the output vector. The Krylov subspace of
order p of this problem is
Frequency-Domain Analysis of Large Circuits
The evaluation of network functions and of frequency responses amounts to the symbolic or numerical solution of
frequency-domain circuit equations. For large networks,
with hundreds or thousands of dynamic elements, both
tasks can be prohibitively expensive. In these cases, approximate frequency solutions are sought, which reproduce
the exact solution in a limited frequency range. The approximate solutions are dened by a reduced number of poles,
which approximate some of the poles of the exact solution.

Kr(A, R, p) = span{R, AR, . . . , A p1 R}

(59)

and the reduced order problem is dened by the reduced

unknown vector X p , X = V p X p , with p N and V p the
matrix collecting the elements of an orthonormal basis of
Kr(A, R, p). Such a basis is obtained without computing
the moments, e.g., via the Arnoldis algorithm. This reduction approach allows to handle huge networks with thousands of dynamic elements, obtaining accurate wideband
approximations, possibly preserving the stability and passivity properties of the original network (e.g., see (31)).

14

Frequency-Domain Circuit Analysis

relations are (see Fig. 9)

Figure 9. A two-conductor transmission line and the quantities

relevant to its analysis.

Transmission Line Frequency-Domain Analysis

Transmission lines (TLs) are important circuit elements,
because of their many applications (e.g., the modeling of
electrically long interconnects). As linear time-invariant
elements, TLs are effectively treated by the frequencydomain approach. Both one-sided Laplace transform (transient problems) and Fourier transform (steady-state problems and physical interpretation) are used for TL analysis.
The Fourier transform of voltages and currents along a
two-conductors uniform TL supporting a quasi-TEM eld
are related by the telegrapher equations (32):

In the above equations, z is the longitudinal coordinate

(see Fig. 9), and Z(j)

and y (j) are the TL per unit length
impedance and admittance, respectively (31).
The solution of Eqs. (60) is

where V+ () and V () are arbitrary functions and K and

Y are the TL complex propagation constant and characteristic admittance, respectively:

The waveform described by V+ ()exp(Kz) has harmonic components V+ ()exp[()z j()z + jt] d/2.
Each of such components is a harmonic function
V+ ()exp(jt) traveling toward increasing z with phase velocity v = /() and attenuating according to exp(-()z).
It describes a transverse electromagnetic eld concentrated on the line crossection and propagating along +z as
a plane wave.
The frequency-domain analysis of a circuit containing
the TL can be carried out by relating voltages and currents
at the line ends through the TL solution [Eq. (61)]. The

with  = K(j)
, where
is the line length. The arbitrary

functions V+ () and V () are determined by the above
relations and the constitutive relations of the circuit connected at the TL ends. Alternatively, the TL can be characterized as a two-port circuit by a set of network parameters. The network parameters can be obtained by expressing two of the TL end variables as a function of the other
two through Eqs. (63). As an example, the chain matrix of
the TL is obtained by computing V+ () and V ()) via the
second and fourth equations of Eqs. (63) and by using the
rst and third equations of Eqs. (63) to obtain V1 () and
I1 (). The chain relations are

Chain parameters can be interpreted as transfer functions

in the s domain by replacing j with s in  = K(j)
and
Y(j). The network functions of distributed circuits, however, are not rational functions of s, because they have innitely many poles. For small (s) values (i.e., electrically
short lines), the lumped parameter formulation can be recovered by approximating the TL transfer functions with
rational functions.
Multiconductor TLs can be treated similarly, by replacing scalar relations for voltages and currents along the line
with vector relations for voltages and currents on the different conductors (31). The formulation becomes considerably complicated, yet it maintains the same properties of
the two-conductor case.
BIBLIOGRAPHY
1. G. Doetsch, Introduction to the Theory and Application of the
Laplace Transformation, Berlin: Springer-Verlag, 1974.
2. M. R. Spiegel, Theory and Problems of Laplace Transforms,
New York: McGraw-Hill, 1965.
3. G. Doetsch, Tabellen zur Laplace-Transformation, Berlin:
Springer-Verlag, 1947.
4. F. Oberhettinger and L. Badii, Tables of Laplace Transforms,
Berlin: Springer-Verlag, 1973.
5. G. D. Hatchel, R. K. Brayton, and F. G. Gustavson, The sparse
tableau approach to network analysis and design, IEEE Trans.
Circuit Theory, CT-18: 101113, 1971.
6. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.
7. R. A. DeCarlo and P.-M. Lin, Linear Circuit Analysis, Englewood Cliffs, NJ: Prentice-Hall, 1995.
8. A. M. Rushdi, Development of modied nodal analysis into a
pedagogical tool, IEEE Trans. Educ., E-28: 1725, 1985.
9. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, New York: Van Nostrand Reinhold, 1983.

Frequency-Domain Circuit Analysis

10. C. W. Ho, A. E. Ruehli, and P. A. Brennan, The modied nodal
approach to network analysis, IEEE Trans. Circuits Syst.,
CAS-22: 504509, 1975.
11. B. C. Kuo, Linear Networks and Systems, New York: McGrawHill, 1967.
12. W.-K. Chen, Linear Networks and Systems: Algorithms and
Computer-Aided Implementations, 2nd ed., Singapore: World
Scientic, 1990.
13. C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York:
McGraw-Hill, 1969.
14. L. O. Chua and P.-M. Lin, Computer-Aided Analysis of Electronic Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1975.
15. G. Gielen, H. Walscharts, and W. Sansen, Isaac: A symbolic
simulator for analog integrated circuits, IEEE J. Solid-State
Circuits, SC-24: 15871597, 1989.
16. Anonymous, SspiceSymbolic SPICECircuit Analyzer and
Approximator, Version 1.0. Michigan State University,
1991.
17. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
New York: McGraw-Hill, 1977.
18. N. Balabanian and T. Bickart, Linear Network Theory,
Chesterland, OH: Matrix, 1981.
19. L. A. Zadeh and C. A. Desoer, Linear System Theory, New York:
McGraw-Hill, 1963
20. L. Weinberg, Network Analysis and Synthesis, New York:
McGraw-Hill, 1962.
21. F. F. Kuo, Networks Analysis and Synthesis, New York: Wiley,
1962.
22. B. V. der Pol and H. Bremmer, Operational Calculus Based
on the Two Sided Laplace Transform, New York: Cambridge
University Press, 1950.
23. A. Papoulis, The Fourier Integral and its Applications, New
York: McGraw-Hill, 1987.
24. A. Papoulis, Probability, Random Variables, and Stochastic
Processes, New York: McGraw-Hill, 1965.
25. P. Dorato, A. M. Lepschy, and U. Viaro, Some comments on
steady-state and asymptotic responses, IEEE Trans. Educ., 37:
264268, 1994.
26. G. V. Lago and L. M. Benningeld, Circuit and System Theory,
New York: Wiley, 1979.
27. S. Seshu and N. Balabanian, Linear Network Analysis, New
York: Wiley, 1959.
28. D. D. Weiner and J. F. Spina, Sinusoidal Analysis and Modeling of Weakly Nonlinear Circuits, New York: Van Nostrand
Reinhold, 1980.
29. E. Chiprout and M. S. Nakhla, Asymptotic Waveform Evaluation, Norwell, MA: Kluwer Academic Publishers, 1994.
30. G. A. Baker, Essentials of Pade Approximants, New York: Academic Press, 1975.
31. M. Celik, L. Pileggi, and A. Odabasioglu, IC Interconnects
Analysis, Norwell, Massachusetts: Kluwer Academic Publishers, 2002.
32. C. R. Paul, Analysis of Multiconductor Transmission Lines,
New York: Wiley-Interscience, 1994.

MARIO BIEY
IVAN A. MAIO
Politecnico di Torino, Torino
Italy

15

TRANSIENT ANALYSIS

TRANSIENT ANALYSIS
Transient circuit analysis is used to find the currents and
voltages in a circuit containing one or more capacitors and/or
inductors. The word transient describes a quantity that is
fleeting rather than permanent, and it distinguishes this
branch of circuit analysis from steady-state analysis, which is
concerned with the long-term or settled behavior of a circuit.
Transient circuit analysis asks not just Where will my circuit
end up? but also How will it get there? The charging of a
battery, the discharge of a flashbulb, and the oscillation of the
pointer in a voltmeter about its resting point are all examples
of transient behavior which can be analyzed using the techniques of transient circuit analysis.

383

Before proceeding, it should be noted that the circuits to

be considered in this article in fact form only a subset of the
universe of circuitsthey are all linear, time-invariant, and
lumped. A linear circuit is one in which each element (except
the independent sources that drive the circuit) is described
by one or more linear equations involving its current(s) and
voltage(s). For example, the resistor defined by v Ri is linear, but the diode defined by i Is(ev/VT 1) is nonlinear, and
any circuit containing the diode is therefore nonlinear. Nonlinear circuits can exhibit highly complex behavior and cannot be handled by the techniques described in this article. A
time-invariant circuit is one in which the equations defining
the elements (except the independent sources) do not change
with time. A lumped circuit is one which is small enough that
all electromagnetic waves in the circuit propagate virtually
instantaneously through the circuit, and the behavior of the
circuit is unaffected by physical distances between elements.
Circuits that are not lumped are handled by a special branch
of circuit theory known as distributed circuit theory or transmission line theory. We will assume throughout this article
that all circuits under consideration are linear, time-invariant, and lumped.
The equations describing a circuit arise from two sources:
Kirchhoff s laws tell us how the elements in the circuit are
interconnected, and then each element in the circuit has an
individual equation (or equations) describing its behavior. If
all of the circuit elements are described by algebraic equations (i.e., ones in which no derivatives appear) involving
their currents and voltages, these equations can be combined
with Kirchhoff s equations to give a set of algebraic equations
that completely describe the circuit. These equations are linear equations in terms of the currents and/or voltages in the
circuit, and they can be solved by any of the techniques of
linear algebra. The power of linear algebra means that these
circuits, known as resistive circuits, are (relatively) easy to
analyze. The behavior of these circuits is quite simple: If a
linear resistive circuit is driven by a 1 V battery, then changing to a 2 V battery will cause all voltages and currents in
the circuit to double. There is no time delay in this response:
The doubling of voltages and currents occurs at the precise
instant when the 2 V battery is inserted into the circuit. If
the battery is replaced by a more complicated voltage source
which varies with time, each voltage and current in the circuit will also vary with time as a scaled replica of the new
voltage source.
Although easy to analyze, the limited behavior of a linear
resistive circuit means that such circuits are not very useful.
Instead of producing a scaled replica of the signal that drives
them, most circuits are required to convert a signal into a
more useful form. For example, a radio receiver can receive a
jumbled signal containing contributions from the myriad of
stations that inhabit the airwaves and tune into a single one;
the graphic equaliser on a stereo system can change the
sound quality by boosting or diminishing certain frequencies;
and an ignition circuit in a car is driven by a battery, but its
output is a short sharp spark. These effects rely on the use of
capacitors and/or inductors. These circuit elements are defined by equations involving not just their currents and voltages, but the rate of change (or derivative) of these quantities
with time. Specifically, the current through a capacitor is proportional to the derivative of its voltage with respect to time,
and the voltage across an inductor is proportional to the de-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

384

TRANSIENT ANALYSIS

rivative of its current with respect to time. Capacitors and

inductors are known as dynamic circuit elements, to convey
the importance to them of time variation, or energy storage
elements, since they are capable of storing energy for later
release. Dynamic elements can be placed deliberately in a circuit, or they can be unwanted parasitic elements, modeling
for example the capacitance between wires in the circuit. If a
circuit contains even a single dynamic element, it is in general described no longer by a set of algebraic equations, but
by one or more differential equations in which the variables
are not only the voltages and currents but also the derivatives
of certain of these quantities with respect to time. A dynamic
circuit is one which contains at least one dynamic element.
The goal of transient circuit analysis is to solve the differential equations that describe a dynamic circuit and thus to
come up with expressions predicting the way in which the
voltages and currents in the circuit will vary with time. It
is concerned in particular with the response of the circuit to
changes, such as when a source is inserted, removed, or suddenly changed in some way, or a switch is closed and the
make-up of the circuit is thereby changed.
Dynamic circuits can exhibit more interesting behavior
than resistive circuits, but they are also more difficult to analyze. One of the simplest dynamic circuits contains a single
capacitor in series with a resistor and a constant voltage
source which is switched on at some specified time. This circuit is described by an equation involving the capacitor voltage vC and its derivative with respect to time dvC /dt. The absence of any higher derivatives gives this equation the
description first-order. A circuit containing just a single dynamic element is described by a first-order differential equation and is called a first-order circuit.
The solution of a first-order differential equation will contain an unknown constant. To find this constant, it is necessary to apply some additional information about the value of
the solution at a specified time instant. Since in general we
are concerned with finding the response of the circuit to
changes that occur at a certain time instant, we often know
the state of the circuit just before the change occurs and can
apply this information in order to find the unknown constant.
The value of the capacitor voltage (or inductor current, if the
circuit contains an inductor rather than a capacitor) just before the change occurs is known as the initial condition.
Solving the first-order circuit just described yields the result that the capacitor voltage plotted as a function of time is
of exponential form, moving from its initial value toward the
value of the constant voltage source and eventually settling
there. (Certain assumptions have been made here and are
discussed in the next section.) This is intuitively plausible
once the voltage source has been inserted the resistor voltage
and capacitor voltage must sum to equal the voltage of the
source. If the capacitor voltage does not initially equal that of
the source, the voltage difference must be developed across
the resistor by a current flowing through it. This current
charges the capacitor, bringing its voltage closer to that of the
source, and the net effect is to cause the capacitor voltage to
approach that of the voltage source. This circuit is reminiscent of a simple battery charger, with the battery voltage increasing over time to equal that of a source.
Already in this simple circuit we can see how dynamic circuits behave in ways that would be impossible for a resistive
circuit. If the circuit described above had been resistive, all

voltages and currents would have been scaled versions of the

source. In this circuit, however, the capacitor voltage takes on
a form quite unlike that of the source: It varies exponentially
with time, whereas the source is constant. The action of the
resistor and capacitor has processed the source signal, with
the capacitor voltage resisting the sudden change when the
source was inserted, but retaining the steady behavior of the
source. The resistor voltage, on the other hand, captures the
change in the source very well, but eventually dies away to
include nothing of the steady behavior of the input. This behavior is an example of the filtering behavior of this simple
resistorcapacitor combination, which is useful in a variety of
communications applications.
The exponential nature of the voltage observed in this simple circuit is not unusual; in fact, as we shall see, exponential
functions appear in various guises in the solution to linear
differential equations. Possibly the most widely known example of an exponential function appears in the analysis of radioactive decay, where the rate of decay of a substance is proportional to the amount of the substance present, and so the
amount remaining decays exponentially to zero at a rate depending on the half-life of the substance.
In general, a circuit which contains two dynamic elements
gives rise to a second-order differential equation (containing
the second derivative of the variable with respect to time) and
is termed a second-order circuit. If all sources in the circuit
are dc (constant) sources, this equation can be solved by application of standard theory of linear differential equations, with
the aid of two initial conditions, one for each dynamic element. Instead of the single exponential transient of the firstorder circuit, this circuit contains two exponential transients
which are added to give the overall transient. The relationship (via complex numbers) between the exponential and sinusoidal functions can give rise to a new type of behavior
arising from these transients. If the arguments of these exponentials are complex, as may turn out to be the case, then
they can be added to give a transient which oscillates sinusoidally. In most circuits the magnitude of this oscillation decays
exponentially with time. A common example of such a decaying oscillation is produced when a tuning fork is struck or
a childs swing given a single push. If there are no losses in
the circuit (not a practical requirement), the oscillation could
persist indefinitely without decaying; and if the circuit is unstable, it is possible that the oscillation can actually grow.
While it is possible to analyze simple first- and second-order dynamic circuits by applying standard theory of differential equations, such solution becomes rapidly more difficult
when the order of the circuit increases or when the sources
become more complicated. When faced with such a problem,
one might look enviously back at the much simpler process of
solving a resistive circuit. In fact it is possible to apply techniques of resistive circuit analysis to dynamic circuits with
the aid of a variety of transforms. A transform is a method of
changing a problem into a different form, solving it in the new
form (where the solution is easier to obtain) and then changing the solution back to the original form. For example, a student unfamiliar with binary arithmetic, when asked to add
two binary numbers, might convert the numbers to decimal
form (presumably with the aid of a table), add the decimal
numbers, and then convert back to binary. The transforms
to be applied in this context change a system of differential

TRANSIENT ANALYSIS

equations to a system of algebraic equations which are significantly easier to solve.

The most important and most widely used of these transforms in circuit analysis is the Laplace transform. A second
transform, the Fourier transform, is particularly useful in analyzing circuits designed for applications in communication
systems. These transforms convert a set of differential equations involving the time variable into a set of algebraic equations involving a new variable called the frequency (in the
case of the Fourier transform) or the complex frequency (in
the case of the Laplace transform). Application of these transforms allows us to analyze a circuit by transforming it into an
equivalent form in the frequency domain, where its equations
are purely algebraic, analyzing the circuit in this frequency
domain using the techniques of linear algebra, and then
applying the transform in reverse to convert the result of this
analysis into a function of time.
Once again, Laplace transform analysis shows up the
special role of the exponential function (and its complex
cousin the sinusoid) in the behavior of circuits. Every dynamic circuit favors certain exponential (including sinusoidal)
modes of behavior whose rate of decay (and frequency of oscillation, if applicable) is governed by the so-called natural frequencies of the circuit. These natural frequencies tell us
whether the currents and voltages in a circuit will, of their
own accord, tend to exhibit exponential or oscillatory decay,
constant behavior or steady oscillation, exponential or oscillatory growth, or some combination thereof. When an input signal is applied to the circuit, the currents and voltages may
contain components controlled by the natural frequencies as
well as a component controlled by the input. In practical circuits it is desirable that the output should depend on the input; and the prospect of an oscillation or exponential growing
in the circuit, swamping out the effect of the input and
wreaking havoc with the circuit components, is clearly a designers nightmare. This effect is similar to that demonstrated
by sound systems when a microphone is placed in the path of
a loudspeaker and an unwanted tone appears and swamps
the desired signal. Fortunately, Laplace transform techniques
allow us to analyze a system to determine if this effect is possible. An asymptotically stable system is one in which all exponential transients die away, leaving only the effect of the
input signal.
The effects of transients are seen in a huge range of electronic and electrical engineering applications, from the transmission of tiny pulses between parts of a communication system to the behavior of an electrical network struck by
lightning. The techniques described in this article provide the
reader with the ability to understand and analyze transient
behavior in a wide variety of circuits.
TIME-DOMAIN ANALYSIS
Natural Response and Step Response of a First-order Circuit
Consider the circuit shown in Fig. 1(a). Until the time t 0,
the switch S is in position 1, and the resistor R and capacitor
C are connected in a loop. At time t 0 the switch is moved
to position 2, connecting the dc voltage source E in series with
R and C. We assume that the switch closes instantaneously
and that it presents a short circuit between the terminals
which it connects. Mathematically, we say that the voltage

2 S
E

i
+
vC

1
C

+
E u(t)

(a)

385

i
C

+
vC

(b)

Figure 1. (a) The switch S moves from position 1 to position 2 at

time t 0, so the voltage applied to the RC series combination is 0
for t 0 and E thereafter. The switchvoltage-source combination is
represented in (b) by the single voltage source E u(t).

applied to the RC series combination is E u(t), where u(t) is

the unit step function given by


u(t) =

0
1

for t < 0
for t 0

(1)

The circuit of Fig. 1(a) can, therefore, also be drawn in the

form shown in Fig. 1(b).
The analysis of this circuit for t 0 will require knowledge
of the initial voltage across the capacitor just after the switch
0
is thrownthat is, vC(0), where 0 lim0
. We generally
know, or can find from analysis of a previous regime, vC(0),
the voltage at the instant just before the switch is thrown
0
(0 lim0
). If the capacitor current is finite, vC(0) must

equal vC(0 ), and we can refer to both as vC(0). Similarly if the

voltage across an inductor is finite its current waveform must
be continuous. We will assume these continuity conditions
throughout this analysis. The alternative case, where the capacitor current or inductor voltage can be infinite, is not practical but turns out to be mathematically interesting and useful in analysis. It can be handled by an extension of our
analysis in this section (see Ref. 1 for details), but we will
postpone consideration of this possibility until the later section on the Laplace transform where it can be handled more
conveniently.
For t 0, Kirchhoff s voltage law gives the equation
vC (t) + i(t)R = E
or, applying the constitutive relation i(t) C dvC(t)/dt for the
capacitor,
RC

dvC (t)
+ vC (t) = E
dt

(2)

This is a first-order differential equation in the capacitor voltage vC, and so this circuit is referred to as a first-order circuit.
It can be solved by a number of methods to give an expression
for vC as a function of time. One such method is to recast the
equation in the form
d(vC (t) E)
1
=
(v (t) E)
dt
RC C
This equation is of the familiar form
dx(t)
= ax(t)
dt

386

TRANSIENT ANALYSIS

which has the solution (see Ref. 2)

Rth

x(t) = x(0)eat
where x(0) is the value of x at time t 0. This initial condition
must be known if the equation is to be solved for x(t). Thus
Eq. (2) has the solution
vC (t) E = (vC (0) E)et/RC

(3a)

Resistive
one-port

Eth

Figure 3. A circuit consisting of a single capacitor in an otherwise

resistive circuit is simplified by replacing the resistive one-port seen
by the capacitor by its Thevenin equivalent.

or
vC (t) = vC (0)et/RC + E(1 et/RC )

(3b)

The response of the series RC circuit with zero initial capacitor voltage to the application of a voltage source given by the
unit step function is known as the step response of the series
RC circuit. (Note that we will use the word response to signify any current or voltage in the circuit, or any set thereof,
including for example the set of all currents and voltages.
Throughout this article the variable or variables which constitute the response in any given instance will be clear from the
context in which the word is used.)
It is clear from Eq. (3a) that the difference between vC and
E varies exponentially with time, and when the product RC
is positive (a condition that will be assumed to hold unless
otherwise stated) this difference tends to zero as t tends to
infinity. vC is plotted as a function of time in Fig. 2, where, as
expected, vC is seen to converge exponentially to E. The rate
of this convergence is governed by the value of RC, which is
termed the time constant of the waveform and denoted by the
symbol . The smaller the time constant, the faster the rate
of convergence. After one time constant has elapsed (i.e., at
t ), vC(t) E has decreased to e1 36.8% of its value at
t 0, and at time t 5 this difference has decreased to
e5 0.7% of its initial value. Although vC does not reach E
within any finite time (unless, of course, it started out at E),
after five time constants have elapsed the difference between
vC and E has been reduced to less than 1% of its initial value.
The time constant is a useful measure of the response speed
of a first-order circuit. For more general circuits, the rise time
is used as a measure of response time. This is defined as the
time taken for the step response to rise from 10% to 90% of

vC(t)
E

vC(0)

Time t
Figure 2. The capacitor voltage in the circuit of Fig. 1 varies exponentially from its starting value vC(0) to its steady-state value E, with
time constant RC.

the steady-state value. For the first-order circuit analyzed in

this section, the rise time can be found to be ln 9 2.2.
The value E to which the capacitor voltage converges is
termed the steady-state value of this voltage. It is the only
value of capacitor voltage at which the circuit can settle; in
other words, it is only when vC E that all currents and
voltages in the circuit cease to vary with time. Clearly, when
a quantity ceases to vary with time, its derivative with respect to time is zero, and so the steady-state of value of vC can
be found directly from the differential equation (2) by setting
the term dvC /dt to zero (or, in circuit terms, replacing the capacitor by an open circuit), yielding the equation vC E, as
expected. The overall waveform vC(t) is the sum of this steadystate component and a second component which dies away
with time. This second component is known as the transient
component (or just the transient). The exponential form of the
transient in this circuit is, as we will see later, particularly
common in linear circuits and other linear systems.
Note, however, that the procedure just outlined yields the
value of vC at which the circuit variables (currents and voltages) can remain constant, but it does not guarantee that the
circuit will actually converge to this state. For example, if
RC 0, Eq. (3a) implies that vC will diverge exponentially
away from E and the circuit has no steady-state response.
(The only exception to this divergence is when vC(0) E, in
which case it will theoretically remain fixed at E for all time.
The word theoretically is important: In practice, any noise
in the circuit that causes vC to differ even infinitesimally from
E will result in its diverging exponentially from E.) This distinction relates to the issue of the stability of equilibria of
differential equations (2).
Another useful view of the solution waveform (3b) for vC(t)
is that it is composed of two components: one caused by the
initial condition vC(0), and the other caused by the voltage
source E. If E 0 the response (3) reduces to vC(t)
vC(0)et/RC, which is termed the natural or unforced response
of the circuit. This is a viewpoint to which we will return
later.
Any circuit consisting of a single capacitor in an otherwise
resistive circuit containing only dc sources is generally analyzed by transforming it to single-loop form by means of a
Thevenin transformation (3), as shown in Fig. 3. The analysis
described above is then applicable, where E is the Thevenin
equivalent voltage source and R is the Thevenin equivalent
resistance. (The small number of circuits that do not have a
Thevenin equivalent can be handled separately.)
Before leaving the single-loop first-order circuit of Fig. 1
we note that the analysis of this section can be used to find
the response of a first-order circuit to a voltage source that is
piecewise-constantthat is, constant over certain time inter-

TRANSIENT ANALYSIS

vals with discontinuous jumps between these constant levels.

One important such waveform is the pulse

for t < 0

0
for 0 t < t0
p(t) = E

for t t0
0
The response of the first-order RC circuit to this source waveform is found by an extension of the analysis just performed.
For 0 t t0 the analysis proceeds as before and vC(t) is
given by Eq. (3c):
vC (t) = vC (0)et/RC + E(1 et/RC )

for 0 t < t0

(3c)

For t t0 the response is just the natural response found

previously, the only difference being that since this phase of
the analysis commences at t t0 instead of t 0 the initial
condition is vC(t0) instead of vC(0). Applying this initial condition in the usual way, we find that
vC (t) = vC (t0 )e(tt 0 )/RC

for t t0

(4)

vC(t0) is, by our assumption of bounded currents, equal to

vC(t0), the capacitor voltage just before the source waveform
drops to zero. Since Eq. (3b) gives vC(t) for all times in the
range 0 t t0, it can be used to find that
vC (t0 ) = vC (0)et 0 /RC + E(1 et 0 /RC )
Substituting this value for vC(t0) in Eq. (4) completes the analysis of the response of the series RC circuit to the voltage
pulse. This response is plotted in Fig. 4, for two different values of the time constant. The response of a circuit to a pulse is
particularly important in communication systems where such
pulses are used to carry information and must be clearly identifiable at the receiver. An RC combination of the type studied
here often occurs in such transmission systems, formed by the
output resistance of the part of the system where the signal
originates and the input capacitance of the part of the system
into which the signal is fed, and thus exponential distortion

387

iL

I u(t)

Figure 5. First-order circuit consisting of the parallel combination

of current source I u(t), conductance G, and inductor L.

will inevitably ensue. Clearly the smearing of the pulse evident in Fig. 4 when the time constant is large limits the rate
at which pulses can be transmitted if they are to be separated
at the receiver.
The response of the series RC circuit to any piecewise-constant source waveform is found by an extension of the analysis performed above. The circuit is analyzed using the standard method over each of the time intervals in which the
source is constant, starting with the first time interval. The
initial condition for the nth time interval, commencing at
time t tn, is found by evaluating the response from the previous time interval at time t tn.
The second type of first-order circuit is one in which the
single energy storage element in the circuit is an inductor
rather than a capacitor and, by application of a Norton transformation (where possible), is of the form shown in Fig. 5,
where the constant current source I is connected in parallel
with conductance G and inductor L for t 0. Kirchhoff s current law applied to this circuit gives the following differential
equation in the inductor current iL for t 0:
GL

diL (t)
+ iL (t) = I
dt

which can be solved as before to find

iL (t) I = (iL (0) I)et/GL
or
iL (t) = iL (0)et/GL + I(1 et/GL )

vC (t)

Thus the inductor current waveform for the circuit of Fig. 5

takes the same form as the capacitor voltage waveform for
the circuit of Fig. 1, with time constant GL and steady-state
value I. This is a consequence of the fact that the circuit of
Fig. 5 is the dual of that of Fig. 1. The response to a piecewiseconstant source waveform can be found by applying the
method previously described for the series RC circuit.

= t0/5
= t0/50

Natural Response of a Second-order Circuit

t0

2t0

Time t
Figure 4. The response of a first-order RC circuit to a voltage pulse
of amplitude E and duration t0. The solid line shows the response if
t0 /50, and the dashed line shows the response if t0 /5. Note
the smearing of the pulse when is large.

The circuit in Fig. 6 consists of a resistor and two energy storage elementsa capacitor and an inductor. Kirchhoff s voltage law gives the equation
vC (t) + L

diL (t)
+ RiL (t) = 0
dt

388

TRANSIENT ANALYSIS

Since there are no sources in the circuit, this is the natural

or unforced response of the series RLC circuit. The constants
A1 and A2 will be determined by applying the initial conditions vC(0) and iL(0) and solving the resulting simultaneous
equations:

iL

+
C

vC

Figure 6. Second-order circuit consisting of resistor R, capacitor C,

and inductor L.

vC (0) = A1 + A2
dv 
iL (0) = C C 
= CA1 s1 + CA2 s2
dt t=0

which on application of the relation iL(t) C dvC(t)/dt becomes

We will now consider the nature of the natural or unforced

voltage waveform represented by Eq. (6). We will use the following shorthand form for s1 and s2:


s1 = + 2 02 and s2 = 2 02

LC

d 2 vC (t)
dv (t)
+ vC (t) = 0
+ RC C
2
dt
dt

(5)

This is a second-order differential equation, and so the circuit

is termed a second-order circuit. The exponential waveform

where

vC (t) = Aest

is a solution to Eq. (5) provided that

R
2L

and

LCs2 + RCs + 1 = 0

1
0 =
LC

We will assume for now that 0.

The first case to be considered is the case where 02 2
and s1 and s2 are real and distinct. In this case the circuit is
said to be overdamped and the response vC(t) is the sum of
two exponentials with time constants 1/s1 and 1/s2. An example of an overdamped response is plotted in Fig. 7(a).
The second case occurs when 02 2 and s1 and s2 are
complex conjugates of the form jd, where d

which yields
R

s=
2L

1
R2

4L2
LC

If these two values, s1 and s2, are distinct (i.e., s1 s2), then
the general solution of Eq. (5) is of the form
vC (t) = A1 es 1 t + A2 es 2 t

(6)

vC (t)

vC (t)

Time t

Time t
0

(a)

(b)
vC (t)

vC (t)

Time t

(c)

Time t

(d)

Figure 7. Examples of the natural response of the series RLC circuit: (a) overdamped, (b) underdamped, (c) underdamped and lossless, and (d) critically damped.

TRANSIENT ANALYSIS

R
E u(t)

iL

+
vC

Figure 8. Second-order circuit consisting of resistor R, capacitor C,

inductor L, and voltage source E u(t).

02 2. In this case the circuit is said to be underdamped.

Equation (6) remains valid, but can be expressed more clearly
in the form


vC (t) = et (A1 + A2 )cos dt + j(A1 A2 )sin dt
A1 and A2 are complex conjugates, and so the coefficients
B1 (A1 A2) and B2 j(A1 A2) are real and can once again
be found from the initial conditions. The underdamped response takes the form of an oscillation of frequency d
multiplied by an exponential envelope et. If 0, the amplitude of the oscillation decreases exponentially with time, with
the rate of this decrease, known as damping, controlled by .
If 0, the response is an oscillation of constant amplitude
and frequency d 0 1/ LC. This is the case of the wellknown LC oscillator, which arises when R 0 and there is
no dissipation in the circuit. The underdamped response is
plotted in Figs. 7(b) and 7(c) for the two cases 0 and
0. Note that the underdamped response is always characterized by oscillation, sometimes termed ringing.
If 02 2, then s1 s2 R/2L. In this case the
general solution of Eq. (5) is no longer given by Eq. (6) but
instead by
vC (t) = (D1 + D2t)et
and is said to be critically damped (2). The constants D1 and
D2 are once again found by application of the initial conditions. An example of a critically damped response is plotted
in Fig. 7(d).
Step Response of a Second-order Circuit
The circuit in Fig. 8 is identical to that of Fig. 6 but for the
addition of the voltage source E at t 0. Applying Kirchhoff s
voltage law for t 0 gives the equation
vC (t) + L

diL (t)
+ RiL (t) = E
dt

which on application of the relation iL(t) C dvC(t)/dt becomes

LC

d 2 vC (t)
dv (t)
+ vC (t) = E
+ RC C
dt 2
dt

(7)

To solve this equation, we apply the fact that the general solution to a differential equation is the sum of two components,
which are known in mathematics as the homogeneous solution
and a particular solution (2). The homogeneous solution is the
solution to the differential equation obtained when all input
terms (i.e., all terms not involving the variable or its derivatives) are set to zero. In circuit terms, this is just the response

389

obtained when all independent voltage and current sources

are removedthat is, the natural or unforced response. A
particular solution is any solution to the differential equation.
This decomposition may seem to be of no particular benefit,
since it states that to solve the differential equation one must
obtain a solution to the differential equation. The benefit lies
in the ability to choose a particularly simple form for the particular solution, which can then be extended to yield the general solution by the addition of the homogeneous solution. The
simplest particular solution is the constant solution which is
obtained by setting all derivatives to zero.
The particular solution to Eq. (7) obtained by setting all
derivatives to zero is vC(t) E. Adding this solution to the
homogeneous solution which has already been found in Eq.
(6) yields the general solution, which is of the form

vC (t) = A1 es 1 t + A2 es 2 t + E

if 02 < 2
(overdamped)

vC (t) = et [B1 cos dt + B2 sin dt] + E

if 02 > 2
(underdamped)

vC (t) = (D1 + D2t)et + E

(8a)

(8b)

if 02 = 2
(critically damped)

(8c)

The appropriate constants A1 and A2, B1 and B2, and D1 and

D2, are found by applying the initial conditions. If the initial
conditions are zero, Eq. (8) represent the step response of the
series RLC circuit and is plotted in Fig. 9.
Depending on the system in which a circuit is to be used,
different demands may be made of its step response. In some
applications, for example, there may be a requirement that
the voltage reach its steady-state value as soon as possible,
while in others it may be necessary that the voltage never
exceed its steady-state value by more than some specified percentage, to avoid driving circuit elements into saturation. A
number of figures of merit have been defined to characterize
the step response of a circuit in order to test its suitability for
a given application (1). The rise time has already been defined. The settling time is the time beyond which the step response does not differ from its steady-state value by more
than 2%. The delay time is the time taken for the step response to reach 50% of its steady-state value. The overshoot
is defined as the difference between the peak value and the
steady-state value of the step response, expressed as a percentage of the steady-state value.
LAPLACE TRANSFORM CIRCUIT ANALYSIS
The analyses described previously have found the circuit variables as a function of time by directly solving the differential
equations that describe the circuit. While such a procedure is
reasonably straightforward for first- and second-order circuits
with simple source waveforms, it becomes significantly more
difficult as the order of the circuit increases and as the source
waveforms become more complex. It is desirable, therefore, to
have a more powerful method of finding a solution. In the
special case where all sources in the circuit are sinusoidal of
the same frequency, the transformation of circuit variables

390

TRANSIENT ANALYSIS

into phasor or complex number form (35) allows the circuit

to be handled using purely algebraic equations instead of differential equations. While extremely useful in certain circumstances, this is not a general circuit analysis method: It can
handle only sinusoidal sources, it is applicable only if the circuit is stable, it finds only the steady-state component of the
waveform, and it does not allow consideration of initial capacitor voltages and inductor currents.
The Laplace Transform
A more general transform than the phasor transform is the
Laplace transform, named after the French mathematician
Pierre-Simon Laplace (17491827). (See Refs. 36.) This
transform method retains the fundamental advantage of the
phasor transform, which is the ability to transform a system
of differential equations into a system of algebraic equations,
but has the additional advantages of being able to (a) handle
a much broader class of source waveforms (including all that
are of any practical interest), (b) accommodate initial conditions, and (c) yield solutions that incorporate both transient
and steady-state components without requiring that the circuit be stable.

vC(t)

The Laplace transform is discussed in the article on LINEAR

and we will merely summarize its properties here.
Given a function of time f(t), its Laplace transform is
SYSTEMS,


F (s) = L { f (t)} =

f (t)est dt

(9)

where the variable s is complex and is termed the (complex)

frequency. Thus the Laplace transform converts a function
f(t) from the time domain into a function F(s) in the frequency
domain. There exist functions which do not have a Laplace
transform, since the integral in Eq. (9) fails to converge, but
all functions of interest in circuit theory have a Laplace transform. Since the interval of integration is from 0 to , the
transform defined by Eq. (9) is sometimes called the one-sided
Laplace transform, to distinguish it from another version in
which the integration is from to , but we will not need
to draw this distinction here and will refer to it simply as the
Laplace transform. The lower limit of integration of 0 is chosen in order to accommodate functions with infinite spikes at
t 0. Such functions will prove extremely useful in our
analysis.
Some of the properties of the Laplace transform that make
it so useful in circuit analysis are the following (3,6), where
F(s) denotes the Laplace transform of f(t), F1(s) the Laplace
transform of f 1(t), and F2(s) the Laplace transform of f 2(t):
Uniqueness: f 1(t) f 2(t) for all t 0 F1(s) F2(s) [More
precisely, if F1(s) F2(s), then


Time t

| f 1 (t) f 2 (t)| dt = 0,

but for our purposes it will suffice to assume that F1(s)

F2(s) f 1(t) f 2(t) for all t 0.]

(a)

Linearity: L k1f 1(t) k2f 2(t) k1F1(s) k2F2(s), where k1 and

k2 are scalars.


d
f (t) = sF (s) f (0 )
Differentiation: L
dt
 t

1
Integration: L
f ( ) d = F (s)
s
0

vC(t)

Time t

Time shift: L f(t )u(t ) es F(s), where 0 and

u(t) is the unit step function given by Eq. (1).
Frequency shift: L et f(t) F(s )

(b)
vC(t)

Time t

(c)
Figure 9. Examples of the step response of the series RLC circuit:
(a) overdamped, (b) underdamped, and (c) critically damped.

The first three of these properties are particularly important. The uniqueness property guarantees that if a system of
differential equations is solved by transforming to the frequency domain, solving in the frequency domain and transforming back to the time domain, the solution obtained will
be the same as would have been obtained if the solution had
been carried out entirely in the time domain. The linearity
property guarantees that a system of linear equations in the
time domain will remain linear in the frequency domain,
allowing powerful linear analysis techniques to be applied in
both domains. The differentiation property allows differentiation in the time domain to be replaced by multiplication in
the frequency domain, together with the addition of an term
related to the initial condition. It is this property that allows

TRANSIENT ANALYSIS
Table 1. Laplace Transforms of Some Important Functions
F (s) L ( f (t))

f (t)

(t)

u(t)

1
s

tn

1
, n 1, 2, . . .
s n1
1
sa

s2 2
s
s2 2
n!

eat
sin t
cos t

degree of n(s) is less than that of d(s). The inverse Laplace

transform of r(s) can be found from Table 1, leaving only the
component n(s)/d(s) to be handled by the partial fraction
expansion. Thus, without loss of generality, we can assume
that the degree of the numerator of F(s) is less than that of
the denominator. The first step in the partial fraction expansion is the factorization of the denominator polynomial:
F (s) =

n(s)
n(s)
=
d(s)
(s p1 ) 1 (s p2 ) 2 . . . (s pm ) m

The quantities pi, the zeros of the denominator d(s) of F(s),

are known as the poles of F(s), and the multiplicity of the
pole pi is the number of times i it appears as a zero of d(s).
A pole of multiplicity one is called a simple pole. If all poles
are simple then

a system of differential equations in the time domain to be

replaced by a system of algebraic equations in the frequency
domain, which can be solved by a variety of powerful and elegant techniques. The Laplace transforms of some important
functions are given in Table 1, in which (t) is the delta function defined by

(t) = 0
for t = 0

(t) = 1

391

(10)

There are three steps to be taken in solving a set of differential equations using Laplace transform analysis: (1) The system of differential equations in the time domain is transformed to a set of algebraic equations in the frequency
domain; (2) this set of algebraic equations is solved in the
frequency domain, using standard linear techniques; and (3)
the solution is transformed from the frequency domain back
to the time domain. Step 1 involves application of the definition of the Laplace transform (9) together with certain of its
properties (notably the differentiation property). Step 2 involves standard techniques from linear algebra. Step 3 involves the application of the inverse Laplace transform, which
converts a function F(s) in the frequency domain to a function
of time f(t) L 1(F(s)) in such a way that L ( f(t)) F(s). Note
that the function f(t) is unique only for t 0, since two functions of time which differ for t 0 but are identical for t 0
will have the same Laplace transform.
The Inverse Laplace Transform
There is a closed-form equation for the inverse Laplace transform (see Ref. 6 for details), but it is rather difficult to apply
(involving contour integration) and is rarely used in circuit
analysis applications (although it is sometimes used for numerical inversion of the Laplace transform). Instead, the inverse Laplace transform of a function is generally found by
writing the function as the sum of simpler functions, each of
whose inverse Laplace transform is known. A technique that
is particularly useful here is the partial fraction expansion
(2,6). This is a technique which allows the decomposition of a
function F(s) which is the ratio of two real polynomials in s
into the sum of simpler terms. It is assumed that the degree
of the numerator of F(s) is less than that of the denominator;
if this is not the case, then F(s) can be expressed in the form
F(s) r(s) n(s)/d(s), where r(s) is a polynomial in s and the

n(s)
(s p1 )(s p2 ) . . . (s pm )
k1
k2
km
=
+
+ ... +
s p1
s p2
s pm

F (s) =

where ki [(s pi)F(s)]spi.

Ki is termed the residue of F(s) at the pole pi. If F(s) has a
pole of multiplicity j at pj, the partial fraction expansion
takes the form

F (s) =
=

n(s)

(s p j ) j d(s)
kj1
s pj

kj2
(s pj

)2

+ +

kj

(s pj ) j

n(s)

d(s)

where


kji =



d j i

1
j
(s pj ) F (s)
(j i)! ds j i

s= p j

Since the numerator and denominator of F(s) are real polynomials in s, poles appear in complex conjugate pairs, as do
their residues. This allows the combination of any complex
term in the expansion with its conjugate to give a real term.
The inverse Laplace transform of each of the terms in the
partial fraction expansion is known:


L

kj


j

(s pj )

= kj

t j 1
e pj t
j ( 1)!
j

In this way it is possible to find the inverse Laplace transform

of any function consisting of the ratio of two polynomials in s
by decomposing the function via the partial fraction expansion and taking the inverse Laplace transform of each of the
constituent functions. This method relies fundamentally on
the uniqueness and linearity properties of the Laplace transform. Clearly the method applies only to a restricted range of
functions, those which can be expressed as the ratio of two
polynomials in s. As will be seen, however, functions of this
type are particularly important in circuit analysis, and so this
is not a significant limitation.

392

TRANSIENT ANALYSIS

iC(s)

+
+

iC(t)

vC(t)

1/sC
or

vC(s)
vC(0)/s

Laplace Transform Circuit Analysis

The first step in the Laplace transform analysis of a circuit is
the transformation of the circuit from the time domain to the
frequency domain. All branch voltages v(t) and currents i(t)
which appear as variables in the differential equations describing the circuit will appear in the transformed equations
as variables V(s) L v(t) and I(s) L i(t). Independent
voltage and current sources are transformed from known
functions of time vs(t) and is(t) to known functions of frequency Vs(s) L vs(t) and Is(s) L is(t). A resistor is described in the time domain by the linear equation v(t)
Ri(t) and so is defined in the transformed circuit by the relation V(s) RI(s). Similarly, the linear equations describing
all resistive two-ports (including ideal transformers, gyrators,
and controlled sources), and indeed resistive n-ports, are unchanged in the transformation from time domain to frequency
domain. The capacitor is defined in the time domain by the
equation
dvC (t)
dt

Applying the differentiation property of the Laplace transform yields the frequency-domain equation for the capacitor:
IC (s) = sCVC (s) CvC (0 )
Thus the capacitor C with initial voltage vC(0) appears in the
transformed circuit as the parallel combination of the independent current source CvC(0) and the linear element defined by the relation V(s) (1/sC)I(s). This second element
can be thought of as a generalized resistance (known as an
impedance) 1/sC and throughout the analysis in the frequency domain can be handled as if it were a resistance. Figure 10 shows the transformation of a capacitor from the time
domain into the parallel combination of an impedance and an
independent current source in the frequency domain or, by
Thevenins theorem, into the series combination of an impedance and an independent voltage source.

CvC(0)

vC(s)
1/sC

Figure 10. Transformation of a capacitor

with initial voltage vC(0) into the frequency
domain.

iC (t) = C

iC(s)

In a similar manner, the inductor defined in the time domain by the relation
vL (t) = L

diL (t)
dt

is defined in the frequency domain by the relation

VL (s) = sLIL (s) LiL (0 )
Thus, as shown in Fig. 11, the inductor appears in the transformed circuit as the series combination of an impedance sL
and voltage source LiL(0) or the parallel combination of the
same impedance and current source iL(0)/s. Note that once
again this circuit transformation could have been obtained
from Fig. 10 by application of the principle of duality. Coupled
inductors can be transformed in a similar manner.
When all of the elements in the circuit have been transformed into the frequency domain, the first step of the analysis process is complete. The second step is to analyze the circuit in the frequency domain, employing any of a wide variety
of techniques such as loop current analysis, node voltage
analysis, modified nodal analysis, or sparse tableau analysis.
The analysis of a circuit in the frequency domain is described
in the article on FREQUENCY-DOMAIN CIRCUIT ANALYSIS and also
in most circuit theory textbooks, such as Refs. 35. The third
step is then to transform the results of the analysis back to
the time domain via the inverse Laplace transform.
Example 1 The circuit of Fig. 1 can be transformed into the
Laplace transform domain, yielding the circuit of Fig. 12.
Analysis in the frequency domain, followed by partial fraction
expansion, yields the following result:

1
E
vC (0 )
v (0 )
E
E
+  RC  = C
+
VC (s) =
1
1
1
1
s
s+
s s+
s+
s+
RC
RC
RC
RC

IL(t)

IL(s)

iL(t)
sL
vL(t)

Figure 11. Transformation of an inductor with

initial current iL(0) into the frequency domain.

or

VL(s)

LiL(0)

iL(0)/s

TRANSIENT ANALYSIS

393

the circuit has a unique solution, that solution is given by

R
+

X(s) = M1 (s)U(s) =

1/sC
E/s

1
Adj(M(s)).U(s)
det(M(s))

VC(s)
+

vC(0 )/s

Figure 12. Laplace transform of the circuit of Fig. 1.

The inverse Laplace transform is then applied to find

vC (t) = vC (0 )et/RC + E(1 et/RC )

for t 0

where the existence of a unique solution guarantees that the

determinant det(M(s)) is not identically zero (2). We assume,
unless otherwise stated, that all zeros p1, p2, . . . , pm of
det(M(s)) are simple. Each component Xi(s) of the vector X(s)
is the ratio of two polynomials in s, and so the partial fraction
expansion can be applied to yield the expression
Xi (s) =

k1
k2
km
+
+ +
s p1
s p2
s pm

The time-domain response xi(t) is, therefore,

which agrees with the time-domain analysis performed
earlier.
NATURAL RESPONSE AND ZERO-STATE RESPONSE
When converted into the frequency domain, a circuit contains
independent sources of two types. The first are the transformed versions of the independent sources from the time domain. These sources drive the circuit in the time domain and
are often termed the inputs to the circuit, borrowing a viewpoint from system theory. The second group of independent
sources in the frequency-domain circuit are those that are introduced during the transformation of energy storage elements and account for the initial conditions in the circuit
that is, the capacitor voltages and inductor currents at time
t 0. We will call these sources the initial condition
generators, to distinguish them from those sources that represent the independent sources from the time domain. By superposition, the response of the circuit to these sources (by
which we mean any current or voltage in the circuit, or any
collection thereof) is the sum of two components: one due to
the independent sources acting alone, with the initial condition generators removed, and the other due to the initial condition generators acting alone, with the independent sources
removed. Since these two components of the response arise
from different mechanisms, it is often useful to treat them
separately. The component of the response due to the independent sources, with the initial conditions set to zero, is
called the zero-state response, and the component due to the
initial conditions, with the independent sources set to zero, is
the natural or unforced response (also called the zero-input response).
Natural Response and Natural Frequencies
We will consider first the natural response of a circuit. Application of any of the standard frequency-domain analysis techniques will yield a matrix equation of the form
M(s)X(s) = U(s)
where M(s) is a matrix each element of which is a polynomial
in s; X(s) is a vector containing some subset of the unknown
branch voltages, branch currents, node voltages, and loop currents; and U(s) is a vector, each nonzero element of which is
a linear combination of the initial condition generators (3). If

xi (t) = k1 e p 1 t + k2 e p 2 t + + km e p m t
for t 0. [If some of the zeros of det(M(s)) have multiplicity
greater than one, the time response will contain terms of the
form tepit.]
Clearly the zeros pi of det(M(s)) play a crucial role in determining the natural response of the circuit. These quantities are known as the natural frequencies of the circuit. The
number of natural frequencies in a circuit is less than or
equal to the number of energy storage elements in the circuit.
The contribution of each natural frequency to the natural response depends on its location in the complex plane. A natural frequency at zero contributes a constant term to the natural response. A real and positive natural frequency pi
contributes a term kiepit that grows exponentially with time. A
real and negative natural frequency pi contributes a term
kiepit that decays exponentially with time. Complex natural
frequencies occur in conjugate pairs, and their contributions
add to make a real contribution to the response waveform. If
the natural frequencies in question lie on the imaginary axis
at j, their composite contribution to the time response is
of the form kiejt kiejt 2ki cos(t ki), an oscillation
of constant amplitude. If the complex natural frequencies lie
in the right half-plane at j, their composite contribution
is of the form kie(j)t kie(j)t 2kiet cos(t ki), an
oscillation whose amplitude grows exponentially with time.
Finally, if the complex natural frequencies lie in the left halfplane at j, their composite contribution is of the form
kie(j)t kie(j)t 2kiet cos(t ki), an oscillation whose
amplitude decays exponentially with time. (If some of the natural frequencies have multiplicity greater than one, their contribution to the time response will be more complicated, with
polynomials times exponentials in place of exponentials, but
can be handled by an extension of the above analysis.)
The above discussion leads to the important conclusion
that if all natural frequencies of a circuit lie in the open left
half-plane (i.e., if their real parts are less than 0), then for
any set of initial conditions the natural or zero-input response
of the circuit decays to zero as t . This decay may be
oscillatory, depending on the presence of complex natural frequencies. A circuit is said to be asymptotically stable or exponentially stable if all of its natural frequencies lie in the open
left half-plane. If any natural frequency lies in the open right
half-plane, then the initial conditions can cause certain currents and voltages to grow exponentially with time, which is

394

TRANSIENT ANALYSIS

clearly undesirable. Obviously in a real circuit this growth

cannot continue indefinitely as the circuit elements will eventually cease to function, possibly in dramatic fashion. Also obvious is the fact that this behavior cannot occur in a circuit
made up entirely of passive elements, since the exponential
growth requires that energy be supplied to the circuit by an
active element such as a controlled source or negative resistance.
While the natural frequencies determine the possible natural modes of behavior of a circuit, the actual response that
will be observed in a circuit with zero input depends on the
values of the initial conditions. Certain sets of initial conditions will excite one mode only, which means that all circuit
variables will exhibit the same exponential or oscillatory behavior, but for most sets the response will be the combination
of various modes. Also, all modes will not necessarily be observed in any given circuit variableit may be that certain
variables are not susceptible to the influence of one or more
natural frequencies.
Example 2 To find the natural frequencies of the circuit of
Fig. 13, the voltage source can be set to zero and the resulting
circuit can be analyzed in the frequency domain by any of the
usual methods. In this case, node voltage analysis is possible,
yielding the matrix equation

1
R + sC1
1

gm

 


V1 (s)
C1 v1 (0 )

V (s) = C v (0 )
1
2
2 2
+ sC2
R2
0

The natural frequencies are the values of s for which the determinant of the matrix in this equation is zero, and therefore
they equal 1/R1C1 and 1/R2C2. Solving explicitly for V1(s)
and V2(s) we find that

V1 (s) =

(v1 (0 )
1
s+
R1C1



1
gm
v (0 )
v1 (0 ) + s +
C2
R1C1 2



.
and V2 (s) =
1
1
s+
s+
R1C1
R2C2

Thus the voltage v1 (natural or zero-input component) exhibits only the behavior controlled by the natural frequency at
1/R1C1. and is unaffected by the natural frequency at
1/R2C2.
The Zero-State Response and Transfer Functions
The zero-state response of a circuit is its response to one or
more independent sources (inputs) with all initial capacitor
voltages and inductor currents set to zero. It suffices to con-

C1
+

vS

+
R2

R1

v1

gmv1

v2
C2

Figure 13. Circuit to be analyzed in Examples 2 and 3.

sider the response to a single input, since superposition can

then be applied to calculate the response due to multiple inputs. Application of any of the standard frequency-domain
analysis techniques to a single-input zero-state circuit will
yield a matrix equation of the form
M(s)X(s) = U(s)
where M(s) is a matrix, each element of which is a polynomial
in s; X(s) is a vector containing some subset of the unknown
branch voltages, branch currents, node voltages, and loop currents; and U(s) is a vector, each nonzero element of which is
a term involving the independent source, say Vs(s) (although
the theory applies equally to the case where the input is a
current source). It follows from linear algebra (2,3) that
Xi (s) =

n(s)
Vs (s) = H(s)Vs (s)
det(M(s))

(11)

where n(s) is a polynomial in s and det(M(s)) is not identically

zero, by our standing assumption of unique solvability. Thus
the zero-state response to a source vs(t) is obtained by multiplying its Laplace transform vs(s) by the appropriate function
H(s) n(s)/det(M(s)) and taking the inverse Laplace transform to return to the time domain. This function is known as
a transfer function or network function. Note that the poles of
a transfer function are zeros of det(M(s)) and are therefore
natural frequencies of the circuit. However, not all natural
frequencies need show up as poles of a given transfer function, due to cancellations with numerator terms.
Once again we see that the natural frequencies play a crucial role in determining the response of the circuiteven, as
in this case, when the initial conditions are zero. From Eq.
(11) the poles of Xi(s) will be some subset (determined by numerator cancellations) of the poles of Vs(s) and the natural
frequencies. xi(t) will in general, therefore, contain terms related to the input together with exponential, constant, or oscillatory terms governed once again by the natural frequencies. If the circuit is asymptotically stable, the contributions
governed by the natural frequencies will die away, leaving
only the component governed by the input.
The simplest application of Eq. (11) occurs when Vs(s)
1that is, when the independent source vs(t) is the delta
function or impulse function defined by Eq. (10). Although
this function is physically unrealizable, it proves extremely
useful in circuit and system analysis. When Vs(t) (t),
xi(s) H(s) L (y) H(s), and so the zero-state response is
xi(t) h(t) L 1H(s). The zero-state response to an impulse
function is known as the impulse response, and so we have
found that the Laplace transform of the impulse response
equals the transfer function. The expression
xi (s) = H(s) L {vs (t)}
gives the frequency-domain response of the system with
transfer function H(s) to an input vs(t) and can be expressed
in the time domain as

xi (t) = h(t) vs (t) =

t+

h(t )vs ( ) d
0

where h(t) L 1H(s) is the impulse response and * is called

the convolution operator (3,6).

TRANSIENT ANALYSIS

If the input is the unit step function u(t), which has Laplace transform 1/s, then xi(s) H(s) L u(t) H(s)/s and so
the step response is xi(t) L 1H(s)/s. It is easy to see that
the impulse response is the derivative of the step response.
Example 3 The transfer function V2(s)/Vs(s) of the circuit of
Fig. 13 is

gm
s
C2


H(s) = 
1
1
s+
s+
R1C1
R2C2

gm
R2C2
R1C1
C2



=

1
1
R2C2 R1C1
s+
s+
R1C1
R2C2
and so the impulse response is

h(t) =

g m R2
et/R 1 C 1
R2C2 R1C1
gm R1C1 /C2 t/R C
2 2

e
R2C2 R1C1

for t 0

The step response is

gm

C2



1
L
1
1

s+
s+

R1C1
R2C2
=

gm R1C1 R2
[et/R 1 C 1 + et/R 2 C 2 ]
R2C2 R1C1

for t 0

Note the exponential modes corresponding to the natural frequencies in both the step response and the impulse response.
Note also that the impulse response is the derivative of the
step response.
FOURIER TRANSFORM CIRCUIT ANALYSIS
The power of the Laplace transform in finding the transient
and steady-state response of a circuit, the variety of source
waveforms which it can handle, and its ability to accommodate initial conditions make it the method of choice in transient circuit analysis. Despite these advantages, another
transform, closely related to the Laplace transform, is preferred in certain situations. This is the Fourier transform (4
6), named after the French mathematician Jean Baptiste Joseph Fourier (17681830). The close relationship between the
Fourier transform of a signal and the frequency content of
that signal make it particularly useful in applications such as
communications and signal processing where this frequency
content is of paramount importance. However, the Fourier
transform is defined for a smaller class of source waveforms
than the Laplace transform, and it cannot handle initial conditions. The latter condition in particular makes it poorly
suited to transient circuit analysis and so we will merely give
a brief discussion of its properties here, with the intention of
(1) explaining why it is unsuited to transient circuit analysis
and (2) providing a link to other forms of transient circuit

395

analysis for circuits such as filters that are more usually handled using Fourier analysis.
The Fourier transform is closely related to the Fourier series (46), in which a periodic function with period T is decomposed into the weighted sum of sinusoids whose angular
frequencies are integer multiples of 2/T. By superposition,
the response of a circuit to a periodic function could be obtained by decomposing the function into the sum of sinusoids,
finding the response to each of these sinusoids via phasor
analysis, and summing these responses to find the overall response. The main disadvantage to this Fourier series method
of analysis is that many source waveforms of interest are not
periodic; and since the method is based on phasor analysis, it
finds only the steady-state component of the response. The
fundamental idea underlying this method, however, namely
the idea of a sum of input sinusoids being processed (i.e., altered in magnitude and phase) in different ways by a circuit
and then added to form the response, is a very useful one and
underlies the more general Fourier transform analysis.
The Fourier transform is a generalization of the Fourier
series to accommodate nonperiodic functions. A nonperiodic
function can be viewed as the limit of a periodic function as
the period T tends to infinity. The Fourier series of this periodic function consists of weighted sinusoids spaced in frequency at integer multiples of 2/T. As T tends to infinity,
the separation of these sinusoidal frequency components
tends to zero, and in the limit we have the nonperiodic function represented by a continuum or spectrum of sinusoidal
components. This spectrum of sinusoidal components constitutes the Fourier transform of the function. The Fourier
transform of a signal f(t) is found, as in the above discussion,
by taking the limit of the expression for the Fourier series of
a periodic function as the period tends to infinity, which turns
out to be

F ( j) = F { f (t)} =

f (t)e jt dt

(12)

and exists if the integral in Eq. (12) converges. Once again we

say that the Fourier transform converts a function from the
time domain into the frequency domain, with F( j) indicating
the frequency content of the signal at frequency . If f(t) 0
for t 0 and the above integral converges, the Fourier transform of f is just the Laplace transform with j substituted
for s. Given F( j), the function f(t) such that F( j) F f(t)
is found by application of the inverse Fourier transform
f (t) = F

{F ( j)} =

1
2

F ( j)e jt d

One important feature of the Fourier transform is the differentiation property, which states that differentiation in the
time domain is equivalent to multiplication by j in the frequency domain. Thus the Fourier transform can, like the Laplace transform, be used to transform a system of differential
equations in the time domain to a system of algebraic equations in the frequency domain.
In Fourier transform analysis a circuit is transformed into
the frequency domain by replacing all independent sources
by their Fourier transforms, replacing each inductor L by an
impedance jL (and replacing any time-domain coupling M
between inductors by the frequency-domain coupling jM), re-

TRANSIENT ANALYSIS

|H( j)|
1

Ideal

0.8
0.6
0.4
n=
n=
n=
n=

0.2
0
0

1
1.5
Frequency, (rad/s)

0.5

2
3
4
5

Figure 14. Amplitude response of the ideal low-pass filter with cutoff
frequency at 1 rad/s, together with the amplitude responses of the
normalized Butterworth filters of order n 2, 3, 4, and 5. Note that
the approximation more closely matches the ideal as the order of the
filter increases.

placing each capacitor C by an impedance 1/jC, and leaving

resistive components unchanged. Note the lack of any initial
condition generators; this is a consequence of the fact that
the lower limit of integration in the definition of the Fourier
transform is rather than 0. Analysis in the frequency
domain proceeds as described in the article on FREQUENCYDOMAIN CIRCUIT ANALYSIS or in Refs. 4 and 5, using the standard tools, and the frequency-domain response is converted
back to the time domain by application of the inverse Fourier
transform. Once again there is a transfer functionin this
case a function of frequency H( j)relating input and output
in the frequency domain. Note that the response obtained
through Fourier transform analysis is the zero-state response
only, since the method contains no provision for handling initial conditions.
Given a circuit with input sin(0t) and transfer function
H( j) [which in general is complex and, for the circuits in
which we are interested, has the property that H(j) is the
complex conjugate of H( j)], the output is obtained by taking
the inverse Fourier transform of H( j) F sin(0t), which
turns out to be H( j0)sin(0t H( j0)). In other words, the
sinusoidal input appears at the output as a sinusoid of the
same frequency, with amplitude multiplied by the magnitude
of the transfer function at that frequency and phase incremented by the phase of the transfer function at that frequency. If the input to the circuit is more general, it can be
viewed as the finite or infinite sum of sinusoids, which will be
altered in magnitude and phase by the action of the circuit
and then recombined to form the output of the circuit. The
magnitude and phase of the transfer function will generally
vary with frequency, and when plotted versus frequency they
are called the amplitude (or magnitude) response and phase
response plots.
Frequency-selective circuits which pass certain ranges of
frequencies from input to output while blocking other ranges
are known as filters (7). For example, an ideal low-pass filter
would pass to the output all frequency components of its input
up to a certain cutoff frequency and would pass no higherfrequency components. This ideal low-pass filter cannot be realized and is therefore approximated by a variety of functions
such as the Butterworth and Chebyshev approximations. Figure 14 plots the amplitude response of the ideal low-pass filter with cutoff frequency at 1 rad/s, together with the ampli-

tude responses of the normalized Butterworth filters of orders

2, 3, 4, and 5. The amplitude response of each of these Butterworth filters is 0.7071 or 3 dB at 1 rad/s, which is to
say that their 3 dB bandwidth is 1 rad/s.
In a communication system designed to transmit pulses,
the step response of a filter is crucial. Too slow a rise time
leads to neighboring pulses in a pulse train being smeared
over one another, rendering them indistinguishable at the
output. Too high an overshoot can drive circuit elements into
saturation. The step response of a filter can be found by Fourier transform methods, by taking the inverse Fourier transform of the function H( j)F u(t), but there is in general no
reason to prefer the Fourier transform over the Laplace transform in this situation, and it is usual to take instead the inverse Laplace transform of the function H(s)L u(t). For example, the normalized third-order Butterworth low-pass filter
has transfer function H(s) 1/(s3 2s2 2s 1) and so its
step response is L 11/s(s3 2s2 2s 1), which can be
found by the partial fraction decomposition to be 1 et
(2/ 3)et/2 sin(3/2)t for t 0. Figure 15 plots the step response of the normalized Butterworth filters of orders 2, 3, 4,
and 5, as obtained by application of the Laplace transform. It
can be seen that as the order increases (and the amplitude
response more closely approximates the ideal) the overshoot,
settling time, and delay time of the filters all increase, but
the rise time is approximately constant.
The procedure outlined above can be used to find the exact
step response of a filter, allowing a designer to compare the
suitability of various filters in pulse transmission applications. Designers should also have an intuitive understanding
of the relationship between amplitude response and transient
response of a filter. A low-pass filter allows low frequencies to
pass to the output, but blocks high frequencies. Thus when
the input is a step function, the output will preserve the
steady-state constant behavior of the input, but will act to
block the high frequencies involved in the transition from 0
to 1. This can be seen in Fig. 15, where the high-order filters
that are most effective at blocking high frequencies are least
effective in capturing the discontinuity in the input. We now
recognize the RC circuit of Fig. 1, with the output voltage
taken across the capacitor, as a low-pass filter. If the output
voltage were taken across the resistor, we would have a highpass filter, whose step response captures the initial discontinuity in the step, but then falls away to zero due to its inability to pass dc. Readers interested in a more detailed discus-

1.2
1
Output voltage

396

0.8
n=2 3 4 5

0.6
0.4
0.2
0

8 10 12 14 16 18 20
Time, t(s)

Figure 15. Step response of the normalized Butterworth filters or

orders n 2, 3, 4, and 5.

TRANSIENT ANALYSIS

sion of the relationship between frequency response and

transient response of filters are referred to Refs. 1 and 7.

HAZARDS FOR THE UNWARY

Computer Simulation of Transient Circuit Performance
Circuit simulation programs such as SPICE (8) are now ubiquitous, and it is important that users understand the operation of these programs so that their results can be interpreted. Our focus here is on the methods by which circuit
simulators approach transient circuit behavior. In order to obtain an approximate solution to a differential equation, a circuit simulator approximates all derivatives in the equation
by discrete-time approximations. Transient circuit simulation
proceeds in three steps: (1) The time interval of interest, consisting of a continuum of time values, is broken up into a set
of small individual time steps: (2) the differential equation is
approximated by an algebraic equation over each time step,
converting it into a form which the computer can readily
solve; and finally (3) the solutions over each of these time
steps are pieced together to form an approximation to the solution of the differential equation over the entire time interval. The key issue here is the nature of the simplifying approximation to the derivative. There are a number of these
approximations, known as numerical integration methods. For
example, the forward Euler approximation replaces the derivative dvC /dt at time tk by the approximation vC(tk1)
vC(tk)/(tk1 tk), which is exact if the solution vC(t) is a straight
line. In practice, the solution will rarely be of this form; but
if the time step tk1 tk is short enough, then the linear approximation is a reasonable one and the solution computed
by the numerical integration will in general be a reasonable
approximation to the actual solution. There are three other
numerical integration methods commonly used in circuit simulators: the backward Euler approximation, the trapezoidal
rule, and Gears methods. The two Euler approximations are
first order, giving exact results if the solution is in fact a
straight line; the trapezoidal rule is second order, and it gives
exact results if the solution is a quadratic; and Gears methods are of any order, with the second-order method most
widely used.
A poor choice of numerical integration method, or a poor
choice of time step for a given method, can result in an approximate solution which differs wildly from the exact solution. Unfortunately for the designer, these erroneous approximations often appear plausible, displaying behavior of the
types seen throughout this article. For example, poor use of a
simulator can cause the natural response of a stable firstorder circuit appear to exhibit damped oscillation, sustained
oscillation, or even growing oscillation. Alternatively, numerical integration can add artificial damping to a response, producing for example a damped oscillatory response in a lossless
LC oscillator. Designers who make use of circuit simulators
in their study of transient responses should be aware of these
hazards, and they are referred to Ref. 8 for further details.
Nonlinear Circuits
The theory and techniques of transient linear circuit analysis
are powerful and elegant and form part of the tool kit of all

397

electronic and electrical engineers. As has been seen throughout this article, the behavior of the linear circuits to which
this analysis is applied is actually rather limited. This is not
to say that these circuits are not usefulquite the reverse.
The power of transient circuit analysis (and other forms of
linear circuit analysis), coupled with the tremendous variety
of uses to which linear circuits can be applied, may tend to
give the impression that all circuits behave in a reasonably
simple fashion and that it is only by adding a complex signal
(such as noise) that complex behavior can be observed in a
circuit. This is not the case. The transient and steady-state
behavior of nonlinear circuits can be extraordinarily complex,
even in the absence of an input signal. An appreciation of the
complexity of nonlinear systems, together with an improved
ability to analyze and understand it, has been developed by
mathematicians, engineers, and scientists from various disciplines since the 1960s, with terms such as chaos entering
the lexicon and popular culture. In circuit theory this work
was pioneered by Chua and his co-workers, and readers interested in venturing from the comparatively tame world of linear circuit analysis into the fascinating world of nonlinear circuits are referred to the seminal paper (9) and to the article
NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS.
BIBLIOGRAPHY
1. F. F. Kuo, Network Analysis and Synthesis, 2nd ed., New York:
Wiley, 1966.
2. E. Kreyszig, Advanced Engineering Mathematics, 6th ed., New
York: Wiley, 1988.
3. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.
4. R. C. Dorf and J. A. Svoboda, Introduction to Electric Circuits, 3rd
ed., New York: Wiley, 1996.
5. J. W. Nilsson and S. A. Riedel, Electric Circuits, 5th ed., Reading,
MA: Addison-Wesley, 1996.
6. A. V. Oppenheim, A. S. Willsky, and I. T. Young, Signals and Systems, London: Prentice-Hall, 1983.
7. L. P. Huelsman, Active and Passive Analog Filter Design, Singapore: McGraw-Hill, 1993.
8. K. S. Kundert, The Designers Guide to Spice and Spectre, Boston:
Kluwer, 1995.
9. T. Matsumoto, L. O. Chua, and M. Komuro, The double scroll,
IEEE Trans. Circuits Syst., 32: 797818, 1985.

ORLA FEELY
University College Dublin

TRANSIENT INTERMODULATION MEASUREMENT. See INTERMODULATION MEASUREMENT.

TRANSIENTS OF ELECTRICAL MACHINES. See
ELECTRIC MACHINE ANALYSIS AND SIMULATION.

TRANSIENTS, OVERVOLTAGE. See OVERVOLTAGE PROTECTION.

TRANSIENT STABILITY. See POWER SYSTEM TRANSIENTS.

TRANSISTOR, BIPOLAR PERMEABLE. See BIPOLAR
PERMEABLE TRANSISTOR.

TRANSISTOR RELIABILITY. See POWER DEVICE RELIABILITY.

398

TRANSISTORTRANSISTOR LOGIC

TRANSISTORS, BIPOLAR. See BIPOLAR TRANSISTORS.

TRANSISTORS, CHARGE INJECTION. See CHARGE INJECTION DEVICES.

TRANSISTORS, POWER. See POWER DEVICES.

TRANSISTORS, STATIC INDUCTION. See STATIC INDUCTION TRANSISTORS.

TRANSISTORS, THIN FILM. See THIN FILM DEVICES;

THIN FILM TRANSISTORS.

NETWORK THEOREMS

227

S1

S1

S2

S2

NETWORK THEOREMS
In this article, we consider electrical networks from the Kirchhoff point of view. The descriptive equations are decomposed
into the constitutive relations for the network elements and
the Kirchhoff equations for the connection element (see Fig.
1). In the following, these networks are called Kirchhoff networks.
This decomposition was already used implicitly in the
nineteenth century by the founders of network theory. It was
Belevitch (1) who clarified this concept and used port currents
and voltages of the connection element for describing Kirchhoff networks. An advantage of this decomposition is that the
connection element can be described by linear equations in
linear as well as nonlinear networks. If dynamic network elements that are characterized by differential and/or integral
equations are included, we obtain a mixture of differential
equations and algebraic or transcendent equations that describe the network. Equations of this type are called differentialalgebraic equations (DAE) [see, e.g., Chua, Desoer, and
Kuh (2); Hasler and Neirynck (3); Mathis (4); or Vlach and
Singhal (5) for further details]. We adopt the point of view of
mathematical dynamical systems [see, e.g., Arrowsmith and
Place (6)] where DAEs, their set of solutions (the flow), and
the right-hand side (the vector field) are, under certain restrictions, simply different representations of the same abstract subject.
It is sufficient to consider subsets of IRn as solution manifolds in the case of resistive networks, and subsets of suitable
function spaces as solution manifolds in the case of more general dynamic circuits. Manifold theory is not really needed at
this stage. However, we emphasize the term manifold in order to recall that the solution sets of network equations are
not mere points-sets: In the vicinity of any solution point

i1
v1
i2

v2

ib
vb

Figure 1. Decomposition of a Kirchhoff network into circuits elements and the connection element (wires and ideal transformers).

Figure 2. The sets of solutions S 1 and S 2 the descriptive equations

of two networks (solution manifolds) and its intersection embedded
into a solution space S .

there is a continuum of solutions that locally behaves as a

Euclidean space, and there exists a smooth transition between any two discrete points within the solution set. In the
following, network theory is considered as a mathematical
theory consisting of definitions, theorems, and corollaries although a consistent presentation of network theory is rather
rare [see Slepian (7) and Reibiger (8)]. Roughly speaking, network theorems may be classified as follows:
1. Theorems that consider properties of an individual network
2. Theorems that consider interrelations of at least two
networks.
We will concentrate mainly on theorems of the second class.
Based on Kirchhoff s point of view, two networks can be different with respect to the connection element (network topology), the kinds of network elements, and/or the associated
network parameters. Interestingly, many of the network theorems and certain properties of networks can be discussed in
a unified manner using this classification. This was first
pointed out by Ghenzi (9), but in a rather restricted manner
(e.g., the duality theory presented in the following is based on
Ghenzis ideas). In addition, the abstract network theory of
Reibiger has been very useful.
In the next subsection, useful superposition theorems for
arbitrary linear networks are discussed. These theorems may
be applied when the solution manifolds differ only in the
value of parameters characterizing the independent voltage
and/or current sources. The following section is devoted to
networks that include different types of network elements but
have the same connection element. A well-known theorem
was first published by Weyl (10) and later by Tellegen (11)
and Ghenzi [see Mathis (4)] that analyses the energy or power
flow into the connection element. We discuss the relationship
of at least two networks and their solution manifolds that differ partly and/or entirely with respect to the types of the network elements and their parameters, as well as the connection element where only certain network characteristics
(impedances or admittances) are fixed. In a more abstract settheoretical framework, this can be illustrated by Fig. 2, where
the intersection of the solution manifolds S 1 and S 2 of two
networks that are embedded in a solution space S is nonzero.
Although this presentation can be used to give an idea of
what is behind theorems of this kind, a rather concrete formulation needs to present a mapping between two networks. We
will illustrate this point by formulating known network theo-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

228

NETWORK THEOREMS

rems like substitution theorems, interreciprocity, and duality

as special cases rather than separate theorems.

I
R1

V1

SUPERPOSITION THEOREMS
Although superposition theorems consider crucial properties
to be a single linear network, these theorems use at least two
networks to test it. It is well known that Helmholtz (12) derived a superposition theorem in 1853. Helmholtzs result was
extended by other researchers and was included by Maxwell
in his monumental treatise (13). But it seems that Hausrath
(14) was the first who derived these theorems under very general assumptions and studied their conditions of validity as
well as their many applications. Hausrath formulated the
principle of superposition in the following manner:
If a [linear time-invariant] network includes a number of arbitrarily distributed current and voltage sources, then each source
results in currents and voltages associated to the network elements as if the other sources are eliminated and the current or the
voltage of some network element can be calculated by summing up
the currents and voltages of each source, respectively.

He added a mathematical interpretation: the resulting current is a linear function of the potential distribution, or, in
reverse order, the resulting potential distribution is a linear
function of the currents.
Hausrath proved this statement by means of Maxwells
equations, where inductors and currents can be included in
the networks. He emphasized the superposition equations in
the case of ac currents differ from the dc case in that their
coefficients will be complex. A more general reasoning of superposition theorems can be given in the following manner:
If we assume that a network can be described by currents
and voltages and the network equations have the following
form
L1x = L2 y

(1)

where L1 and L2 are linear operators, x is a vector of voltages

and currents of the network elements, and y is a vector including independent current and voltage sources, in a linear
manner, then the principle of superposition can be proved
very easily. In the case of linear resistive networks, the operators are matrices and the result follows from linear algebra.
On the other hand, the superposition principle is also valid in
the case of differential operators with time-dependent coefficients, that is, for linear time-variant networks. Assuming
that the source vector y is determined by s currents and voltage sources, it can be decomposed into
y = y1 + + ys

VR 2

V2

Figure 3. Elementary circuit with two independent voltage sources.

The idea of a superposition theorem can be illustrated by using the simple network in Fig. 3 which contains two independent voltage sources.
Example. For determination of the voltage VR2 in this network, the best way is to replace both sources by one source,
V V1 V2, and to calculate VR2 by means of the well-known
rule of voltage dividers. On the other hand, the idea of superposition theorems suggests constructing two networks by setting all values of the voltage source (with the exception of
one) to zero. Using the rule of voltage dividers, the voltages
(2)
V(1)
R2 and VR2 are calculated and as a result of the superposition
(2)
theorem we have VR2 V(1)
R2 VR2 .
The approach in the last example can be generalized very
easily. We associate a number of test networks (corresponding to the number of independent sources) with the original
network by setting all sources except one to zero (i.e., current
sources I0 0 and voltage sources V0 0) and calculate the
desired network variable. The value of this variable in the
original network can be determined by a superposition
theorem.
Although superposition theorems can be very useful in network analysis, it should be kept in mind that they are generally not valid when considering power quantities (e.g., average power) as description variables. Commonly, they will not
be true even in linear time-invariant resistive networks. We
demonstrate this statement by means of the next example,
omitting the rather simple calculations.
Example. In Fig. 3 a linear resistive network that includes
two dc voltage sources V1 and V2 is shown. If the power of the
oneports is defined by P V I, the current I and the voltage VR2 are calculated under the condition that V2 is zero. The
power of R2 is P VR2 I. In the same manner P is calculated under the condition that V1 is zero; we obtain P
V R 2 I. But the superposition P P does not correspond
to the correct power P if both sources are included. In this
case, we have

(2)


P = (VR2
+ VR2
) (I  + I  )

If x1, . . ., xs are the (unique) solutions of L1xi L2yi (i 1,

. . ., s), the complete solution x is calculated by
x = x1 + + xs

R2

(3)


(VR2



+ VR2



I )+

(4)

(VR2



=: (P + P ) + PIA
where PIA is the interaction term.




+ VR2



I )

(5)
(6)

NETWORK THEOREMS

In contrast to this, it can be shown that the superposition

principle of (average) power quantities of reciprocal networks
with current and voltage sources can be valid if we add the
powers of current sources and voltage sources separately.
Martens and Le (15) proved the following theorem:
Let P be the power dissipated in a linear network in which
there are only resistors, current sources, and voltage sources.
Let PE(PJ) be the power dissipated when all the current (voltage) sources are open circuited (short circuited). Then P
PE PJ.
A first theorem of this kind was given by Guillemin (16),
pp. 127128) and more general cases for networks including
capacitors and inductors can be found in the paper of Martens. A simple example is shown in Fig. 4. It can be shown
that the superposition theorem in linear time-invariant networks is generally valid if the frequencies of the two sources
are different [see, e.g., Desoer and Kuh, Chap. 7.1 (17)].

a thermodynamic interpretation exists only if both quantities

are associated to the same port (or two-terminal element). In
the latter case, the integrals of these powerlike quantities
also have an energetic interpretation.
WEYLTELLEGEN THEOREM
We consider two networks N and N that have the same connection element and where the port quantities are denoted
by vk, ik and vk, k, respectively. These quantities satisfy the
following Kirchhoff equations where the port currents and
voltages are described by the vectors i, v, , v:
Aii = 0, Bvv = 0

and A i = 0, B v = 0

Definitions
Although other network variables are possible (see e.g.,
Mathis (4, chap. 6) we restrict this discussion to currents and
voltages. Furthermore, we consider only Kirchhoff networks
that include the standard set of network elements (R, L, C,
independent and controlled sources as well as the Kirchhoff
connection element). In this case, the descriptive equations
are formulated as
Ai = 0, Bv = 0

(7)

dx
= g(x)
f(i, v, t) = 0, M(x)
dt

(8)

where x (i, v). The pair of matrices (A, B) that describes

the Kirchhoff connection element is exact in the following
sense [Ghenzi (9), Mathis (4)]:

ABT = 0
Rk(A) + Rk(B ) = b
T

where b is the number of ports of the connection element.

In many applications, the solution manifold of these network equations with respect to the currents and voltages
needs to be calculated. But sometimes the power quantities
are of interest because a thermodynamic interpretation (e.g.,
by means of Joules theorem) is available. In general, products vk ik of currents ik and voltages vk are instantaneous
powerlike quantities with respect to physical dimension, but

1
I0

V0

Figure 4. Nambiars example of a circuit where superposition of

power is valid (both generators have the same frequency and phase).

(9)

It is easy to prove that the following relations hold:

vv) = 0
i, vv)
(i,
= 0, (i,

ENERGY AND POWER

229

(10)

The proofs are a direct consequence of the exactness of A

and B (see Mathis (4), appendix A, 1.17). Weyl (10) [see also
Cauers monograph (18)] presented a proof of the following
relations in 1923,
(ii, v ) = 0

(11)

but there is no difference from a mathematical point of view

to the above relations since both networks have the same connection element. Tellegen (11) reinvented Weyls result and
illustrated it with several examples and applications. A detailed discussion of the history of these theorems (as well as
many further applications) can be found in Penfield, Spence,
Duinker (19). It should be mentioned that the theorem of
WeylTellegen is very useful in sensitivity analysis (see also
the section Interreciprocity in this article).
EQUIVALENCE OF n-PORTS
Imagine two different multiports (black boxes) with the same
number n of externally accessible ports and assume they are
equivalent in the sense that they cannot be distinguished
from each other by any measurements of electrical parameters at the ports. Though they behave externally in an identical manner, their internal circuitry may be completely different; not even the numbers of internal nodes and meshes need
be the same. This concept of external equivalence of
multiports is the central theme in classical network synthesis
since the early work of Foster and Cauer (18). As opposed to
the analysis viewpoint that still pervades circuit theory textbooks, equivalence theorems like those of the Norton
Thevenin type may be attacked in a very clear and straightforward manner from the synthesis point of view, that is, one
starts with a mathematical description of the external behavior and then asks for different internal realizations.
When terminating a multiport with any fixed-load network
and collecting the n currents and n voltages measured simultaneously at the n ports in n-vectors i and v, respectively, one
obtains an admissible pair (i, v). The set of all admissible (i,
v)-pairs of an n-port N is called the driving point characteristic or the graph G(N ) of N . Assume N to be linear and time
invariant and all signals to be real valued (complex signals

230

NETWORK THEOREMS

G(N)
N

v0

v0
v

vo c

i0

i i0

v v0
isc
Figure 5. (a) (i, v)-characteristic or graph G(N ) of a linear resistive affine oneport N , and (b) its elementary
circuit model.



(b)

The slope of G(N ) equals the internal resistance R of the

circuit realization. According to Eq. (13), R is determined
by two admissible pairs (ii, vi), i 0, 1, as



i0
I
+ span
IRn IRn
V
v0

R=

(12)

where span[ ] denotes the space spanned by the columns of

a matrix. Except for pathological degenerations due to physically meaningless interconnections of nullors (cf. Ref. 20), I
and V are square matrices such that the columns of the 2n
n matrix
I
V

form a basis for the direction space


I
V

This latter term is suggested by a geometric interpretation of

Eq. (12): G(N ) is generated by a parallel shift of the direction
space from the origin (0, 0) to any reference point (i0, v0)
G(N ).
In case of a real oneport, the graph G(N ) is simply a
straight line in IR IR as shown in Fig. 5(a). Note that the
intercept points (isc, 0) and (0, voc) are measured as admissible
pairs when the oneport is connected to an external short circuit (v 0) or open circuit (i 0), respectively. Moreover,
admissible pairs outside the section between these intercept
points may occur exclusively in the presence of external
sources.
When the slope R of the graph G(N ) in Fig. 5(a) is nonzero
and finite, we may write down the equation of a straight line
in point-slope form
(v v0 ) = R(i i0 ),

(i0 , v0 ) G(N )

R=

where the reference point (i0, v0) may be any admissible pair.
Clearly, Eq. (13) is Ohms law for not necessarily passive N ,
and it has the obvious and most elementary circuit realization
shown in Fig. 5(b). From each of the three representations for
N [Eq. (13), Fig. 5(a), or (b)] the following facts are readily
seen:

(14)

voc
isc

(15)

as the ratio of open-circuit voltage and short-circuit current.

When the N does not contain any independent sources,
the equivalent circuit of N shrinks to a single resistor R
and G(N ) is a proper linear subspace [a line passing
through (0, 0)]. Hence, one may choose (i0, v0) (0, 0)
and determine R v1 /i1 by the usual form of Ohms law.
For R 0, the graph G(N ) is a horizontal line and N
reduces to an independent voltage source with v0 voc or
to a short circuit in the case v0 0.
For R , the graph G(N ) is a vertical line and N
reduces to an independent current source with i0 isc or
to an open circuit in case i0 0.
TheveninNorton Theorem
The TheveninNorton equivalent circuits as shown in Fig. 6
are the earliest and most elementary equivalence results for

i
v

(13)

v1 v0
i1 i0

If N is not a dead circuit (free of independent sources),

one may choose the admissible pairs (i0, v0) (isc, 0) (external short circuit) and (i1, v1) (0, voc) (external open
circuit) to determine in the well-known method



span

(a)

may be used as well in the spot-frequency senseotherwise,

see Complex Variables below). Equivalently, G(N ) is a fixed
linear manifold, that is, the linear affine subspace
G(N ) =

i0

isc

R
voc

(a)

(b)

Figure 6. (a) Norton and (b) Thevenin equivalent circuits for a linear
resistive affine oneport.

NETWORK THEOREMS

i
v

N1

N2

i
(a)

N1

voc

N2

(b)
Figure 7. (a) Decomposition of a network into a purely linear-resistive affine oneport N 1 and a more general (possibly nonlinear,
time-varying and dynamic) remainder N 2. (b) Replacing N 1 by a volt 1 without independent sources.
age source and a oneport N

oneport networks. The main value of these equivalent circuits

is that they may replace any generic linear resistive oneport.
No matter how complicated its internal structure is, and insofar as its external behavior is of concern, it is equivalent to
the most simple circuits in Fig. 6. The main applications of
TheveninNorton equivalents are in modeling noisy circuits
(21) and in conventional circuit analysis (17). In the latter
case, one may split a complicated network into two parts,
N 1 and N 2, as shown in Fig. 7. When collecting all nonlinear,
time-varying, and dynamic components in N 2 such that N 1
embraces exclusively linear-resistive parts of the network
(and no components whose individual electrical quantities are
of any interest for the solution), N 1 may be replaced by a
single voltage source in series with a oneport N 1 that contains no independent sources (see Fig. 7), and which, in turn,
may be replaced by a single resistor. In the theory of noisy
networks, equivalent sources serve to replace a noisy resistor
or a complicated noisy oneport network by a noise (current or
voltage) source and a noiseless resistor.
Before discussing TheveninNorton equivalents in more
detail, a warning seems appropriate. One should bear in
mind that these equivalences are strictly limited to the data
at the accessible (external) ports; for example, the currents
through the internal resistors in the equivalent Thevenin and
Norton circuits in Fig. 6 are not the same. Consequently, internal power consumption of the equivalent sources is different!
Linear Resistive Oneports. Define a linear oneport N to be
generic or nondegenerate when its graph G(N ) is a one-dimensional linear manifold (cf. Fig. 5(a); this condition excludes nullors) and it is neither an independent voltage, a
current source, nor a short or open circuit.

Proof. The graph G(N ) being an affine line as shown in Fig.

5(a), the Thevenin and Norton equivalent sources trivially follow from Fig. 5(b) when choosing as a reference point (i0, v0),
the admissible pairs (0, voc) and (isc, 0), respectively.
Note that this proof (besides the usual assumptions of nondegeneracy) invokes exclusively the linearity property of the
oneport. No recourse is made to other theorems (such as the
substitution theorem) or to external circuitry. A conceptually
similar proof, based on an abstract network model and a rigorous exploitation of the consequences of linearity, has been
given in Ref. (22).
Depending on the applications at hand, one may determine
the parameters R, voc and isc of the Thevenin and Norton
equivalents by external black box measurements or by analysis of a given internal circuit diagram. Since G(N ) is a
straight line, it is sufficient to measure two admissible pairs
(ii, vi), i 1, 2 as discussed above [see Eqs. (13)(15)]. Clearly,
the easiest way is to measure voc and isc directly and to determine R from Eq. (15). However, when the oneport might be
damaged by open- or short-circuit measurements, one must
use Eq. (14) and calculate voc and isc from Eq. (13).
In case of a given circuit diagram for N , the equivalent
circuit parameters must be calculated by means of network
analysis. This is usually done by two independent analyses.
Define N to be a copy of N with all (say s) independent
sources off, that is, setting i0i v0i 0, i 1, , s, and
hence open-circuiting current sources and short-circuiting
voltage sources. Then, one analysis serves for computing R as
the input resistance of N and another one for computing voc
or isc (with all sources on). Many instructive examples including networks with controlled sources may be found in circuit theory text books (2).
When N is a quite complex circuit, one may proceed as
follows in order to avoid two complete circuit analyses: (1)
Pull all s independent sources out of N as new ports and compute a matrix representation for the resulting (1 s)-port; (2)
connect the independent sources to the s source ports and determine isc or voc by ordinary matrix calculus as well as R
(with all s sources off ). A similar procedure has been proposed in Ref. 23 based on the concept of interreciprocity (see
also Interreciprocity).
Linear Resistive Multiports. There are natural generalizations of TheveninNorton equivalent circuits to nondegenerate n-ports N that is, when G(N ) in Eq. (12) has dimension
n. Clearly, Eqs. (12)(13) and Fig. 5 hold mutatis mutandis,
that is, all currents i and voltages v are n-vector valued. The
resistor in circuit in Fig. 5(b) symbolizes an n-port with n
n resistance matrix R, where each port is loaded separately
by a parallel-connected current and a series-connected voltage
source. The question of existence of R is not crucial, since one
may choose any other basis


I
V

for the direction space

Theorem (TheveninNorton). Any generic, linear, time-invariant, resistive oneport N may be replaced by the equivalent realizations shown in Fig. 6.

231





I
I
span
= span
R
V

232

NETWORK THEOREMS

where 1 denotes the n n unit-matrix. Clearly, since





1
I 1
=
I
R
V

existence of R VI1 requires detI 0, that is, the n-port

has to be current controlled.
As to the choice of a reference point (i0, v0) IRn IRn
along G(N ), there is no further restriction beyond detI 0
in choosing (0, v0). Equivalently, when the n-port is voltage
controlled (detV 0), one may reduce (i0, v0) to (i0, 0). This
way, the number of independent sources is reduced by n and
one ends up with the n-port analogs for the Thevenin and
Norton equivalent circuits in Fig. 6 [see Fig. 8(a) for a twoport
Thevenin circuit].
Unlike oneport equivalents, n-ports have more than the
standard solutions (0, v0) and (i0, 0) for choosing a reference
point in order to turn n source currents or voltages to zero. In
general, there are ( 2nn ) different choices, each resulting in a
different equivalent circuit. Figure 8 shows two nonstandard
equivalent circuits from the six possible choices in the case
n 2. These may be described by the equations



v1 v01
i
= [H] 1 ,
i2 i02
v2

v1 v01
v2
= [A]
i1 i01
i2


(16)

where H and A denote the hybrid and chain matrices of the

twoport.
In order to determine the parameters of an affine n-port,
n 1 admissible pairs (i, v) are necessary: one reference
point (i0, v0) and n basis vectors for the direction space span


I
V

This can be done by network analysis quite in the same way

as for oneports. Measurements, however, may be tricky. In
case of a hybrid equivalent circuit [Fig. 8(b) and left part of
Eq. (16)] one gets the reference data (0, i02, v01, 0) for the inde-

v01

v01

i1

i1
i01

v1

v1

i2

i2
i02

v2

v2

(a)

(b)

Figure 8. Equivalent circuits for a linear affine twoport deduced

from (a) a chain matrix and (b) a hybrid matrix representation. N
contains no independent sources.

pendent sources in the familiar way from simultaneous openand short-circuit measurements according to i1 v2 0. It is
instructive to verify that a chain-type circuit [Fig. 8(a) and
right part of Eq. (16)] would require a rather exotic measurement setup in order to determine for instance v01 v1i2v20.
Complex Variables. There is no limitation in using Laplace
transform and in applying the TheveninNorton theorem on
a complex variables basis for circuits which contain capacitors
and inductors. Because of initial values there may be additional sources that have to be treated as independent ones.
As a consequence, the characteristics of the equivalent current and voltage sources may depend on the initial values of
the internal inductors and capacitors. Moreover, when using
complex quantities, one implicitly works in sinusoidal steady
state when the complex variable s is replaced by j. Therefore, referring to a circuit decomposition as shown in Fig. 7,
not only N 1 but also the external circuitry in N 2 must be
linear and time invariant.
Darlington Theorem
Darlingtons theorem certainly is the most penetrating frequency domain result of classical network theory. It is not
usually presented outside specialized books on network synthesis [(1,18); see also (24 and 25)], since its derivation requires spectral factorization and, therefore, quite a lot of analytic function theory. However, in the present context, it is
essential to get an idea of what it is. In many cases, a spotfrequency version of the theorem may be sufficient.
The most elementary version of this theorem is for lumped
oneports that are passive and therefore have a positive real
rational input impedance Z(s) (i.e., the real part of Z(s) has
no zeros in the right-half plane and does not vanish identically on the real frequency axis s j).
Theorem (Darlington, 1939). Any positive real function
Z(s) may be realized as the input impedance of a lossless twoport terminated in a positive resistor R.
Clearly, one may choose R 1 by using an added ideal
transformer in the lossless twoport. Darlingtons theorem has
become generalized for multiports [see, e.g., Newcomb (26)
and Belevitch (1); for a correct form of the multiport-cascade
Darlington-realization of rational matrices, however, it is still
indicated to consult Ref. 27]. Extensions of the Darlington
theory to nonpassive devices have been demonstrated by Ball
and Helton (28). Furthermore, affine multiports N containing
independent sources may be treated as well, since Darlington
representation deals with the input impedance Z of N (with
all independent sources off ). For that reason only the direction space of the external behavior in terms of the slope or
angle operator Z is affected. Hence, a large class of linear
lumped multiports has a Darlington-type representation like
that in Fig. 9(b). In order to figure out the precise limitations,
it is useful to think of the equivalence of the Thevenin and
Darlington representations shown in Fig. 9 as a special case
of a lossless cascade transformation F between two Theve 0, Z) and (V0, Z) F (V
0, Z), where, in case of
nin circuits (V
the Darlington circuit, we have Z R diag(Ri). Adhering
to the familiar impedance coordinates and defining ReZ :

NETWORK THEOREMS

(a)

v01

v01

(b)

R1

v02

Lossless
four port

v02

R2

Figure 9. (a) Thevenin equivalent circuit for an affine passive twoport with impedance matrix Z and (b) its Darlington equivalent twoport with real positive resistors R1 and R2.


(Z Z*), where Z* denotes the Hermitian conjugate matrix,

it is not difficult to show that
,
V0 = T V
0

Re{Z(j)} = T Re{Z(j)}T

(17)

Clearly, T T(j) but at a fixed frequency it can be any

nonsingular constant matrix by proper choice of the lossless
transformation. It becomes clear that the question about what
can be done by means of lossless cascade transformations
amounts to a study of the congruence classes of ReZ(j) or,
equivalently, ReZ(j). In case of Darlington equivalents with
all resistors Ri normalized to 1, ReZ(j) diag(Ri) becomes a signature matrix J diag(1); as a consequence,
such circuits exist only if the factorization problem
Re{Z(j)} = T(j)JT (j),

J = diag(1)

(18)

has a solution. When fixing a particular frequency, the problem boils down to the congruence diagonalization of constant
indefinite Hermitian matrices; hence, standard linear algebra
software packages may be used to determine spot-frequency
equivalent circuits as they are widely used in noise analysis
(29). In network synthesis and modeling of stationary stochastic processes (30), one is interested in circuits that are continuously valid for all frequencies, that is, one looks for a rational matrix T(s) that in addition to Eq. (17) fulfills certain
analyticity requirements. In case of a passive impedance
Z(s), all resistors Ri are positive; hence we have J 1. Solutions of ReZ(j) T(j)T*(j) may be found by classical
spectral or Wiener-Hopf factorization.
In case of an indefinite matrix J it should be intuitively
clear that Eq. (17) does not have a solution when the inertia
of ReZ(j) varies with j: One cannot imagine a lossless 2nport that transforms positive resistors into negative ones. In
fact, it is known in mathematics that this condition is necessary and sufficient to solve Hermitian factorization problems
of this kind (28,31); as a result, continuous-frequency Darlington equivalents exist only in case of constant inertia of the
Hermitian matrix ReZ(j). In this case, Eq. (17) can be
solved by J-spectral factorization; for this reason, this extension of the classical theorem is also called a J-Darlington
theorem (28).

233

Beyond the celebrated low-sensitivity properties of lossless

cascade realization for selective filters, the main value of Darlington-type models lies in the invariance properties of the
lossless 2n-port. Lossless transformations do not alter the
characteristics of stationary power or energy flow into the embedded n-port and, consequently, leave its most fundamental
physical properties invariant. Whereas TheveninNorton circuits are based exclusively on the linear properties of a device, Darlington models additionally reflect the quadratic constraints imposed by conservation of power or energy. This fact
makes them natural canonical models par excellence for linear
physical systems as well as for spectral models in a thermodynamic interpretation when only second-order properties are
of interest.
Though computation of Darlington circuits may be cumbersome (especially for continuous models), they offer much information and place the fundamental characteristics directly
in evidence (e.g., passivity of N is obvious when all resistors
Ri 0). Moreover, they provide for a clear partitioning of the
model into pure resistors and dynamical elements, thus limiting frequency dependence and complex numbers to the lossless 2n-port. In fact, Darlington representation may be viewed
as real diagonalization of a complex impedance matrix Z by
means of a linear fractional map F : Z R.
When emphasis is on analysis or modeling of power flow
in linear systems, it is conceptually more appealing to work
with scattering parameters instead of voltages, currents, and
impedances. The inherent normalization to external loads
was limited originally to resistors. In order to extend applicability of scattering analysis to complex as well as to multiport
loads, the theory of complex normalization of scattering matrices has been developed (3234). Rather late it became evident
that this formalism amounts to replacing the complex load
multiports by their Darlington equivalents and to performing
normalization with respect to the decoupled real resistors Ri
(35).
EQUIVALENT AND PARTIALLY EQUIVALENT NETWORKS
Foundations
According to Belevitch (1) electrical networks are characterized by network elements and their connection element,
where branch currents and voltages are used to describe a
network mathematically.
The interaction with other networks and/or the observation of certain network variables requires the introduction of
oneports (pairs of terminals) in the networks. From a systematic point of view, it is suitable to replace the oneports by
norators. By definition, branch currents and voltages of these
singular network elements [see Carlin (20)] are arbitrary,
and therefore each nonlinear and linear resistive characteristic (including current and voltage sources as well as open
circuits and short circuits) can be represented. In this manner, twoports can be represented as network elements with
private network variables if a mathematical representation
of such a network is given by both the Kirchhoff equations
and the constitutive relations of all network elements (including the norators). In this section, networks with a certain set
of b norators are called n-port networks.
There are several levels at which one can compare two networks and their descriptions. The strongest condition seems

234

NETWORK THEOREMS

to be that the network topology and structure of the Kirchhoff

matrices, respectively, as well as the constitutive relations of
the network elements be the same. Obviously these conditions
lead to the same manifold of solutions of the descriptive equations. If dynamic networks are considered, then such a condition may be valid only for a certain time point or, in the case
of linear time-invariant networks, only for a specified frequency.
Whereas this strong comparability is rather trivial and
useless, it is easy to define weaker kinds. In 1929, based on
ideas of Cauer (36), Ghenzi (9) defined that two networks are
homological if parts of their network topologies and the solutions of the associated branch variables have the same behavior.
In network theory, many results on homological networks
are known. The famous theorem of Helmholtz (12) published
in 1853 (often called as theorem of Thevenin) was the first
example of this kind. This was generalized by Mayer (37) and
Norton [see Brittain (38) for some historical remarks] to networks with controlled sources in 1926. Another remarkable
network theorem was derived by Kennelly (39), who proved
the Y equivalence. In both cases, the homology of two networks was considered with respect to the network part that
includes one and three norators, respectively. In the case of
Helmholtzs theorem, the quotient of the norator current and
voltage has to be the same, whereas the Y equivalence is
based on the condition that the norator currents have to be
equal. Cauer (36) was the first to define a general concept of
equivalence where the fixed part of the network topology consists only of the norators that replace the oneports for interaction with network surroundings. He pointed out that the theory of equivalent networks is the central subject of network
synthesis, where the main goal is to design different networks
of equivalent behavior with respect to the ports. In the next
subsections we will present some prominent results of network theory that can be understood in a unified manner using
the framework of homological networks. For example, the duality of networks is studied in the literature apart from the
subjects discussed above. But as Ghenzi emphasized, duality
of networks is only a special case in the homology of networks.
Substitution Theorem
There are many interesting applications of the homology of
networks in network theory. A very general theorem is the
so-called substitution theorem that allows us to replace any
particular branch of a network by a suitable chosen independent source without changing any branch current or any
branch voltage. In many instances, the substitute network is
easier to solve than the original one. [See Desoer and Kuh
(17).] We can find several versions of this idea in the monograph of Chua, Desoer, and Kuh (2) where nonlinear resistive
as well as dynamic networks are considered. A very general
substitution theorem was published by Haase and Reibiger
(40), but we restrict ourselves in this subsection to describing
special cases of this general theorem.
This statement can be demonstrated in a simple manner if
we consider nonlinear resistive networks. For this case Chua,
Desoer, and Kuh (2) presented the following theorem together
with a proof:

N1

N2

Figure 10. Decomposition of a resistive network into oneport networks N 1 and N 2. The electrical behavior at the common port is completely determined by i(t) and u(t).

Theorem. Let a resistive network N including time-variant

sources be decomposed into two oneport subnetworks N 1 and
N 2 that are connected at their ports (see Fig. 10); this port is
characterized by a current i and a voltage u. If N has a
unique solution i(t) (for all t), then N 2 may be substituted by
a voltage source u(t) without affecting the branch voltages
and the branch currents inside N 1, provided the substituted
circuit N S has a unique solution (for all t).
Remark. If a voltage source is used for replacing N 2, an
analogous theorem holds.
Example. Let N 1 in Fig. 10 be a network consisting of a nonlinear resistor (N 1) connected with an independent voltage
source in series with a linear resistor (N 2). If a unique intersection of the nonlinear characteristic N 1 and the load characteristic N 2 is considered, the intersection can be determined by means of a horizontal and a vertical characteristic
(voltage or current source) if these lines do not intersect the
nonlinear characteristic a second time. This case is illustrated
in Fig. 11.
Remark. If N 1 is a linear resistive network with sources, it
can be characterized at its port by means of another line.
With the exception of singular cases the intersection can be
determined with a current or voltage source, too.
Miller Theorem. In many monographs about circuit design,
the so-called Miller theorem and its applications are discussed [e.g., Millman and Grabel (41)]. Probably the first detailed presentation of Millers result is included in the Radiation Laboratory Series [see Vol. 19 Waveforms written by
Chance et al. (42)]. After some extensions of this theorem

N2
N1

v
Figure 11. Uniqueness of intersection for a decomposition according
to Fig. 10 when N 1 is a nonlinear resistor and N 2 is a linear affine
oneport (an independent voltage source in series with a linear resistor).

NETWORK THEOREMS

were published, a more complete version was presented recently by Rathore (43). Based on the connections of twoports
using parallel (P) or/and series (S) connections, Rathore
showed that the different versions of Millers theorem can be
derived in a unique manner. The four corresponding connections of twoports are denoted by PP, PS, SP, SS if P or S is
the type of connection of the input and output ports of both
twoports. In each case, one of the twoports includes a controlled source that depends on the kind of connection,
whereas the other twoport is arbitrary. By means of an equivalent network of the latter twoport that includes controlled
voltage or current sources and the corresponding gain (PP or
SS) or transfer impedance or admittance (SP or PS), we obtain the Miller equivalent network. Note that the first twoport can be fully characterized by its voltage or current gain.
If we have PP connection, the first twoport consists only of a
single impedance Z and the gain of the second twoport is
U2 /U1. This will be represented in the Miller equivalent
network by means of input and output impedances with the
following values:
Z1 = Z

1
1

and Z2 = Z

(19)

This example (see Fig. 12) is the one presented by Miller

to illustrate his theorem. Note that at least one of these impedances can be negative if 1. Therefore, the Miller theorem results in an equivalent network with a negative resistor
and cannot be realized with real devices. On the other hand,
it is very suitable in circuit design, for example, to study the
frequency behavior of this network.
WyeDelta and StarMesh Transformation. A theorem that
considers two networks with equivalent three-pole-subnetworks of special topologies is well known as the stardelta
transformation, since the network topology of one of the subnetworks looks like a star and the other subnetwork looks
like a delta. This type of equivalence was given for the first
time by Kennelly (39) in 1899 and studied intensively with
respect to the theory of electrical transmission lines by Herzog and Feldmann (44) in 1903. Later on it became a standard
subject in elementary textbooks of network theory [e.g., Guillemin (45), Desoer and Kuh (17)]. In Guillemins book (see p.
131) we find a nice statement for the calculation of the delta
conductances or resistances the product of the adjacent two,
divided by the sum of all three. For example, the wye resistors
of deltawye transformation are calculated by
R i =

R j Rk

(20)

R1 + R2 + R3

Z
Linear
two-port

(a)

Z1

Linear
two-port

Z2

(b)

Figure 12. The decomposition of the impedance Z by the Miller theorem into Z1 and Z2.

235

R3
R2

R1

R1 R2
R3
Figure 13. A simple replacement of a delta-type resistor network
(without tilde) into a wye-type resistor network (with tilde).

where (i, j, k) is a permutation of (1, 2, 3), the Rs are the

s are the wye resistors. The delta
delta resistors and the R
wye transformation is illustrated in Fig. 13. Furthermore,
Guillemin pointed out that with the wyedelta transformation, a node of the network is eliminated (that is a node
potential) and with a deltawye transformation an elementary mesh is eliminated (that is a mesh current). Repeated
applications of this procedure lead to a simplified network.
Obviously, this statement is closely related to the Gauss algorithm for solving linear algebraic equations (LU factorization).
It should be emphasized that not every linear resistive
three-pole-network can be represented by a subnetwork with
one of these topologies if it is assumed that all resistive values
are positive. Therefore, this theorem is only applicable to such
networks that include three-pole subnetworks with a wye or
a delta topology. It should be mentioned that a generalization
of the wyedelta transformation to networks with sources can
be found in a paper of Herzog (46) [see also Chang and Chu
(47)].
In their famous paper from 1964, Brayton and Moser (48)
presented a derivation of this theorem in a geometrical framework using the so-called Legrendre transformation. They
proved that it has no analog for nonlinear networks although
some exceptions under certain restrictions are known (see
also Chua (49). This result is related to a more recent result
published by Boyd and Chua (50). These authors showed that
even a simple cascade of two linear blocks (where a nonlinear
block is embedded the inputoutput behavior) is not preserved by any commutation operation. That is to say that the
classes of equivalent nonlinear networks essentially consist of
one network only.
The more generalized star-mesh transformations for npole-subnetworks were published in 1924 with a star or mesh
topology [see Kupfmuller (51) and Rosen (52)] but in these
cases no bijective relationships between these two subnetworks exist if there are more than three poles [further literature and remarks are included in Bedrosian (53)]. However,
it is pointed out in these papers that these results can be
applied in certain areas of network analysis.
RECIPROCITY
Reciprocity is an essential property of electrical networks, although its physical idea has been applied previously to other
physical systems. Rayleigh considered a reciprocity relation
in his famous monograph Theory of Sound (54). In all cases,
reciprocity is related to an interchange between cause and

236

NETWORK THEOREMS

response of a system or network. In order to define as well as

test this property of a single network, we associate a family
of networks to it. If the network contains n norators (that
cannot combine with nullators into a nullor) the networks are
called n-ports, where a port is characterized by the voltage
and the current of the corresponding norator. One of these
networks can be constructed in the following manner (restricted at first to the classical case of linear time-invariant
n-ports):
All norators, with exception of two, are replaced by short
circuits.
Network 1: Both of the remaining two norators I and II
are replaced by an independent voltage source where
vI1 0 and vII1 0.
Network 2: Both of the remaining two norators are replaced by an independent voltage source where vII2 0
and vII2 0.
This n-port is reciprocal with respect to these two ports
(norators) if the following conclusion is satisfied: vI1 vII2
iII1 iI2 where the currents are the corresponding port (norator) currents. This n-port is reciprocal if it is reciprocal with
respect to all pairs of ports (norators). Obviously we have an
operational definition that can be used to construct a measurement process in order to test this property. The idea is
illustrated with a two-port network.
Unfortunately, it is not possible to use voltage sources for
the test of reciprocity in all cases of linear time-invariant nports. But a more general approach uses independent current
sources and open circuits, or a mixture of current and voltage
sources [for further details see Balabanian, Bickart, Seshu
(55), Chap. 9].
Although the basic definition of reciprocity uses a family of
networks, it is more suitable to formulate criteria that are
related to properties of a certain network. For this purpose,
the WeylTellegen theorem can be used since it is formulated
for two different networks with identical connection elements.
For simplicity, we will consider only the case of a pair of ports
(norators). If currents and voltages of these ports are denoted
by index 1 and 2, respectively, we have by the properties of a
Kirchhoff network

(v 1 i1 v1 i1 ) + (v 2 i2 v2 i2 ) +

X
b

(v k ik vk ik ) = 0

(21)

k=3

where b is the number of branches of the network (including the two ports or norators). Using the special properties
of the two associated networks and reciprocity with respect
to these ports, the following condition for the twoport network arises

X
b

(v k ik vk ik )

(22)

k=3

where the sum encompasses all nonport branches of the network. In contrast to the external definition, this relation is
based on internal quantities only. Therefore an internal characterization of reciprocity is given. In the case of linear time-

invariant n-ports, a similar relation can be derived from the

WeylTellegen theorem

(v k ik + vk ik ) =

ports

(v k ik vk ik )

(23)

internal branches

where the reciprocity of the n-port network results in the vanishing of the left side (external condition) or the right side
(internal condition). In the case of linear reciprocal n-ports,
reciprocity can be characterized by means of certain invariant
properties of the n-port matrices. For example, the impedance
and the admittance matrices have to be symmetric. For further details, see Balabanian, Bickart, and Seshu (55). These
invariant properties are formulated in a different manner if
different types of excitations (different n-port matrices) are
considered. Fortunately, a geometric characterization is available to unify these different formulations. In the case of linear
time-invariant n-ports, the external behavior is characterized
by a totally isotropic linear space. A more general characterization of n-ports, including the nonlinear n-ports based on
paper of Brayton and Moser (48), was generalized by Brayton
(56) and Chua, Matsumoto, and Ichiraku (57); see also the
monograph of Mathis (4). The main idea behind this approach
is that the reciprocity of an n-port is characterized by a 2form (in the sense of Cartan)

dik dvk

(24)

ports

that vanishes on the set of all admissible currents and voltages. If this 2-form is represented in a suitable coordinate
system, one of the classical characterizations of reciprocity
can be derived. In this sense, we speak of a geometrical formulation of the internal representation of reciprocity.
It is well known that linear reciprocal n-ports can be analyzed in a simplified manner using the symmetry of the nport matrices. In this case, only half of the nondiagonal coefficients have to be calculated. An elegant formulation of the
dynamic state space equations of linear or nonlinear RLC networks can be derived if the network is reciprocal and complete (see, e.g., Weiss and Mathis (58) for recent results).
Based on these conditions, Brayton and Moser (48) proved
that a scalar function P(vC, iL) exists (where (vC and iL are the
voltages of the capacitors and currents of the inductors, respectively) that can be used to formulate the dynamic equations
C(vC )

P
dvC
=
dt
vC

(25)

L(iL )

P
diL
=
dt
iL

(26)

For the proof of the existence of P, Brayton and Moser used

the 2-form as an integrability condition. These authors applied their mixed potential function P to derive stability conditions for this class of nonlinear networks without solving the
dynamic equations. Furthermore, it should be mentioned that
reciprocity is a sensitive assumption for a thermodynamic interpretation of electrical networks and other physical systems
[see, e.g., Weiss and Mathis (58) and Stratonovich (59)].

NETWORK THEOREMS

INTERRECIPROCITY
Unfortunately, many interesting networks are not included
in the class of reciprocal networks. Therefore Bordewijk (60)
introduced a new property in 1956 that extends the reciprocity in some sense. In order to define the reciprocity of a network including norators (ports), a family of networks was
generated where the norators are replaced by different
excitations (independent sources) as well as open and short
circuits. It is assumed that the connection element and the
other network elements are not changed.
Bordewijk assumed the external condition of reciprocity

(v k ik + vk ik ) = 0

(27)

ports

for two n-port networks with the same connection element

but possibly different network elements. Therefore, we say
that two n-port networks with the same connection element
are interreciprocal if this condition for all admissible port currents and voltages is satisfied.
Using the internal condition of interreciprocity, it is easily
shown that the admittance and impedance matrices of linear
and interreciprocal n-port networks N and N that are related by
= YT ,
Y

= ZT
Z

(28)

It was already known to Bordewijk that, in general, there

is more than one way of associating one network with another
in such a manner that the two networks are interreciprocal,
even in the linear case (61). Therefore, he introduced the
transposition operation to linear n-port networks, where the
separate network elements are replaced by network elements
that are interreciprocal with regards to the aforesaid network
elements. A complete table of network elements and their
unique interreciprocal network elements can be found in
[Balabanian, Bickart, Seshu (55), p. 376].
Bordewijk proved that two n-port networks that arise from
one another by transposition are interreciprocal. Note that it
is not generally true that two interreciprocal n-port networks
arise one from the other by transposition. Obviously, transposition is a self-inverse operation. Therefore this approach is
closely related to duality of networks (see the next section).
It is easy to conclude that an n-port network composed of
reciprocal network elements is invariant for transposition.
Therefore, reciprocal n-port networks form an invariant set
in the set of all linear n-port networks. With respect to this
prominent property, a pair of n-port networks that are generated by transposition are said to be adjoint of each other.
The paper of Bordewijk contained many applications of interreciprocity. In particular, he studied the analysis of amplifiers with pairwise interreciprocal network models. Furthermore, he considered an extended noise theory of linear and
interreciprocal networks. Another prominent application of
adjoint networks is the sensitivity analysis of networks with
respect to network parameters. Although a straightforward
method is available to calculate small absolute or relative
variations of currents and voltages with respect to variations
of certain network parameters, the analysis results of the adjoint network are of some advantage if more than one sen-

237

sitivity has to be calculated. In contrast to the method of

first-order approximation, where each parameter has to be
considered separately, only one analysis of the adjoint network is necessary. For further details, see Hasler and Neirynck [(3), pp. 236ff]. A more detailed comparison is contained
in Vallese (62). The relationship between the concepts of adjoint networks and transposed networks was discussed by
Bordewijk (61).
DUALITY
A very interesting relationship between two different networks and their solution manifolds, respectively, is discussed
by means of the so-called duality theory of electrical networks. Introduced by Russel (63), the first results were published by Matthies and Strecker (64). Since these results were
based on considerations of the corresponding network graph,
this duality concept was restricted to networks with a planar
network graph. Cauer (36) reformulated these early results in
the framework of mathematical graph theory and presented
conditions that an arbitrary graph is planar. More detailed
information can be found, for instance, in Weinberg (65). An
illustration of this approach to dual networks is shown in the
following example.
Example. Obviously the RLC network in Fig. 14 has a planar network graph. Therefore it is possible to map this network on the surface of a ball where it decomposes the surface
of the ball into three areas. Now we associate a node to each
of these three areas and connect each of these nodes by a
branch that crosses a branch of the original network. As a
result, the skeleton of another graph is constructed that can
be interpreted as a network graph. This is called the dual
network graph. As the next problem, we have to determine
the kind of network element in each branch. A table of network elements and its corresponding dual elements can be
found in Hasler and Neirynck [(3), p. 218]. In the most simple
cases, an Ohmian resistor has to be replaced by an admit R/R02, where R0 is the duality constant. Using these
tance G
correspondences, the dual network can be constructed (see
Fig. 15).
In order to clarify this duality operation and to extend it
to more general networks (where planarity of the network

Figure 14. Illustrating the construction of the dual graph of a simple

RLC network.

238

NETWORK THEOREMS

tion the celebrated duality relation between the parallel and

series RLC circuits.

BARTLETT THEOREM AND OTHER SYMMETRIES

Figure 15. The corresponding dual RLC network (see Fig. 14).

graph is not needed), Ghenzis axiomatic representation of

network theory was applied by Mathis and Marten (66).
Ghenzi reformulated the description of the connection element by means of an exact pair of incidence matrices (A, B)
mentioned above. The dual network is then defined by interchanging these two matrices (BT, AT) and by replacing each
network element by its dual (where the above mentioned table is used). In those cases where the connection element
with (A, B) can be represented by a planar graph, a planar
graph can be constructed for the dual connection element
with (BT, AT). In this manner, the classical duality theory is
reformulated. Unfortunately, this statement is invalid if (A,
B) represents a nonplanar graph. Using a theorem of Belevitch (1) Mathis and Marten (66) showed that for each pair of
real and exact matrices an ideal transformer b-port can be
constructed. Therefore, the dual network can also be represented by the usual network elements ideal transformers in
each case. The relationships of duality in the sets of resistive
networks can be illustrated by means of Fig. 16. Essentially,
duality is in a property of the connection element of a network. Therefore, the consideration of resistive networks with
ideal transformers (Ru networks) and without ideal transformers is no substantial restriction. It is known that a dual
planar network can be constructed for each planar resistive
network. In the case of nonplanar networks, ideal transformers are needed for the construction of the dual network. An
example can be found in Ref. 66. It should be mentioned that
an alternative representation of this duality theory was described by Reibiger using so-called bondgraphs (67).
Since the solution manifolds of dual networks are closely
related by transformations of currents and voltages, the solutions of one network can be used to represent the solutions of
the other. As a simple illustration of this approach, we men-

In many areas of physics, geometric symmetries of a system

can be used to simplify the analysis. In linear network theory,
symmetries of this kind were also applied in a successful
manner. Probably the first example was the application of
symmetries to polyphase networks; Fortescue (68) published
some results in 1918. In 1931, Bartlett (69) published his now
well-known result on reflection symmetric networks. This was
very useful in filter theory and has been generalized to electronic circuits. In order to illustrate Bartletts theorem, consider a network with two independent voltage sources that
can be decomposed with respect to a mirror plane into two
parts containing the same network elements. This is shown
in Fig. 17 using identical n-ports N . Obviously, each block
contains a voltage source that was extracted. Both parts of
the network are connected by a number of wires. If the network is excited with symmetric voltages v1 v2, the currents
in the connections are zero and open circuits occur. Therefore,
both parts can be analyzed independently. On the other hand,
if the voltages are antisymmetric v1 v2, the voltages between the connections are zero and there are short circuits at
both ports. Again, these parts can be analyzed in a separate
manner. By means of this approach, difference amplifiers can
be analyzed.
Unfortunately, the occurrence of three-dimensional geometric symmetries in a linear network is rather an exception.
Furthermore, the results of Fortescue and Bartlett are proven
by the superposition theorem, and for this reason, a direct
generalization to nonlinear networks is impossible. However,
some interesting symmetry results for nonlinear networks
were published. The papers of Chua and Vandewalle (70) and
Vandewalle and Chua (71) contain many references and results where the framework of permutation groups is applied
to generalize many ad hoc techniques that are well known in
circuit design for special circuits. They show that for a certain
choice of the reference nodes a symmetric network has a symmetric solution, provided the network has a unique solution.
Furthermore, the authors present a reduction technique for
nonlinear symmetric networks that generalizes Bartletts
method for linear networks and unifies various algebraic and
graphical reduction methods. Interesting applications of these
results are the analysis of networks with complementary

Ru networks
R networks
Nonplanar
N

Figure 16. Decomposition of the set of linear resistor networks with

ideal transformers with respect to duality classes.

. . .

Planar

Figure 17. A decomposition of an arbitrary network into symmetric

blocks.

NETWORK THEOREMS

symmetric network elements (e.g., npn and pnp bipolar transistors). An example is the push-pull transistor amplifier.
A fundamental symmetry of network equations as well as
other physical descriptive equations is the balance of physical
dimensions in addition to the numerical values of an equation. It is known that in the dimensional theory multiparameter Lie groups can be helpful. An overview of dimensional theory with its applications is given by Mathis (72). The method
of normalized linear networks that is useful in filter design is
a simple example of dimensional theory. In general, normalized equations include a number of dimensionless constants
that can be determined by dimensional theory in a systematic
manner. Mathis showed that different normalized representations of nonlinear network equations are very useful if the
singular perturbation theory is applied (72). A certain representation determines the initial solution for the perturbation
series.

BIBLIOGRAPHY

239

17. C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York:

McGraw-Hill, 1969.
18. W. Cauer, Synthesis of Linear Communication Networks, vols. 1,
2. New York: McGraw-Hill, 1958.
19. P. Penfield, R. Spence, and S. Duinker, Tellegens Theorem and
Electrical Networks, Cambridge: MIT Press, 1970.
20. H. J. Carlin, Singular network elements. IEEE Trans. Circuit
Theory, 11: 6772, 1964.
21. H. A. Haus and R. B. Adler, Circuit Theory of Linear Noisy Networks, New York: Wiley, 1959.
22. A. Reibiger, Geometrical proof of the TheveninNorton theorem,
Proc. ECCTD97, Budapest, 1997, pp. 2428.
23. S. W. Director and D. A. Wayne, Computational efficiency in the
determination of Thevenin and Norton equivalents, IEEE Trans.
Circuit Theory, 19: 9698, 1972.
24. Ph. Delsarte, Y. Genin, and Y. Kamp, On the role of the Nevanlinna-Pick interpolation problem in circuit and system theory,
Int. J. Circuit Theory Appl., 9: 8996, 1981.
25. P. Dewilde et al., The role of losslessness in theory and applica ) special issue, 5/6: 241
tions. Int. J. Electron. Commun., (AEU
382, 1995.

1. V. Belevitch, Classical Network Theory, San Francisco: HoldenDay, 1968.

26. R. W. Newcomb, Linear Multiport Synthesis, New York: McGrawHill, 1966.

2. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear

Circuits, Singapore: McGraw-Hill, 1987.

27. P. Dewilde, Cascade scattering matrix synthesis, Ph.D. thesis,

Stanford Univ. Tech. Rept. No. 656021, June 1970.

3. M. Hasler and J. Neirynck, Nonlinear Networks, Norwood, CT:

Artech House, 1986.

28. J. Ball and J. W. Helton, Lie groups over the field of rational
functions, signed spectral factorization, signed interpolation, and
amplifier design, J. Operator Theory, 8: 1964, 1982.

4. W. Mathis, Nichtlineare Netzwerke, Berlin: Springer-Verlag,

1987.
5. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis
and Design, New York: Van Nostrand Reinhold, 1983.
6. D. K. Arrowsmith and C. M. Place, An Introduction to Dynamical
Systems, Cambridge: Cambridge University Press, 1991.
7. P. Slepian, Mathematical foundations of network analysis, Berlin:
Springer-Verlag, 1968.
8. A. Reibiger, On the terminal behavior of networks. Proc.
ECCTD85, Prag, 1985, pp. 224228. See also an extended ver ber das Klemmenverhalten von Netzwerken. Wiss.
sion: U
Zeitschr. TU Dresden 35: 165173, 1986.
9. A. G. Ghenzi, Studien uber die algebraische Theorie der elektrischen Netzwerke, Dissertation, ETH Zurich, 1953.
10. H. Weyl, Reparticion de corriente en una red conductora. (Distribution of current in a conduction network) Rev. Mat. HispanoAmericana, 5: 153164, 1923. (Trans. J. Friedman, George Washington University Logistics Research Project, 1951.)
11. B. D. H. Tellegen, A general network theorem, with applications.
Philips Res. Rep., 7: 259269, 1952.
12. H. Helmholtz, Ueber einige Gesetze der Vertheilung elektrischer Strome in korperlichen Leitern mit Anwendung auf
die thierisch-elektrischen Versuche. Pogg. Ann., 89: 211233,
353377, 1853.

29. H. A. Haus and R. B. Adler, Canonical form of linear noisy networks, IRE Trans. Circuit Theory, 5: 161167, 1958.
30. P. Dewilde, A. Vieira, and T. Kailath, On a generalized SzegoLevinson realization algorithm for optimal linear predictors
based on a network synthesis approach, IEEE Trans. Circuits
Syst., 25: 663675, 1978.
31. A. M. Nikolaichuk and I. M. Spitkovskii, Factorization of Hermitian matrix-functions and their application to boundary value
problems, Ukrainian Math. J., 27: 629639, 1975.
32. D. C. Youla, On scattering matrices normalized to complex port
numbers, Proc. IRE, 49: 1221, 1961.
33. D. C. Youla, An extension to the concept of scattering matrix,
IEEE Trans. Circuit Theory, 11: 310311, 1964.
34. R. A. Rohrer, The scattering matrix: Normalized to complex nport load networks, IEEE Trans. Circuit Theory, 12: 223230,
1965.
35. R. Pauli, Darlingtons theorem and complex normalization, Int.
J. Circuit Theory Appl., 17: 429446, 1989.
36. W. Cauer, Topologische dualitatssatze und reziprozitatstheoreme
der schaltungstheorie, Zeitschr. Angew. Math. Mech., 14: 349
350, 1934.
ber das ersatzschema der verstarkerrohre, Tele37. H. F. Mayer, U
gr.u.Fernsprechtech., 15: 325327, 1926.

13. J. C. Maxwell, A Treatise on Electricity and Magnetism, 2 vols.,

New York: Dover, 1954.

38. J. E. Brittain, Thevenin theorem, IEEE Spectrum, 27 (3): 42,

March 1990.

14. H. Hausrath, Die Untersuchung elektrischer Systeme auf Grundlage der Superpositionsprinzipien, Berlin: Verlagsbuchhandlung Julius Springer, 1907.

39. A. E. Kennelly, The equivalence of triangles and three-pointed

stars conducting networks, Electrical World, 34: 413, 1899.

15. G. O. Martens and H. H. Le, On the superposition of power in

linear time-invariant networks, Proc. IEEE, 59: 17211722,
1971.
16. E. A. Guillemin, Theory of Linear Physical Systems, New York:
Wiley, 1963.

40. J. Haase and A. Reibiger, Verallgemeinerung und Anwendung

des Substitutions-theorems der Netzwerktheorie, Wiss. Zeitschr.
TU Dresden, 34: 125129, 1985.
41. J. Millman and A. Grabel, Microelectronics, New York: McGrawHill, 1987.
42. B. Chance et al., Waveforms, New York: McGraw-Hill, 1949.

240

NEURAL ARCHITECTURE IN 3-D

43. T. S. Rathore, Generalized Miller theorem and its applications,

IEEE Trans. Educ., 32: 386390, 1989 with corrections IEEE
Trans. Educ., 33: 224, 1990.

70. L. O. Chua and J. Vandewalle, A unified theory of symmetry for

nonlinear multiports and multiterminal resistors, Int. J. Circuit
Theory Appl., 7: 337371, 1979.

44. Herzog and Feldmann, Die Berechnung elektrischer Leitungsnetze in Theorie und Praxis. Berlin: 1903.

71. J. Vandewalle and L. O. Chua, A unified theory of symmetry for

nonlinear resistive networks, J. Franklin Inst., 308: 533577,
1979.

45. E. A. Guillemin, Introductory Circuit Theory, New York: Wiley,

1953.
46. W. Herzog, Stern-Dreieck-Umwandlung mit Quellen, Bull. SEV,
61: 10971106, 1970.
47. S. Chang and Y.-I. Chu, Active -to-Y transformation, Proc.
IEEE, 59: 326328, 1971.
48. R. K. Brayton and J. K. Moser, A theory of nonlinear networks I
and II, Quart. Appl. Math., 12: 133, 81104, 1964.
49. L. O. Chua, -Y and Y- transformation for nonlinear networks,
Proc. IEEE, 59: 417419, 1971.
50. S. Boyd and L. O. Chua, Uniqueness of a basic nonlinear structure, IEEE Trans., CAS-30: 648651, 1983.
ber einen Umwandlungssatz zur Theorie der li51. K. Kupfmuller, U
nearen Netze, Wiss. Veroffentl. Siemens-Konzern, 3: 130134,
19231924.
52. A. Rosen, A new network theorem, J. IEE, 62: 916918, 1924.
53. S. D. Bedrosian, Converse of the Star-Mesh Transformation, IRE
Trans. Circuit Theory, 491493, 1961.
54. J. W. S. Lord Rayleigh, Theory of Sound, vol. 1, London: MacMillan, 1924.
55. N. Balabanian, T. A. Bickert, and S. Seshu, Electrical Network
Theory, New York: Wiley, 1969.
56. R. K. Brayton, Nonlinear reciprocal networks, in Mathematical
Aspects of Electrical Network Analysis, Providence, RI: Amer.
Math. Soc., 1971.
57. L. O. Chua, T. Matsumoto, and S. Ichiraku, Geometric properties
of resistive nonlinear n-ports: Transversality, structural stability,
reciprocity, and antireciprocity, IEEE Trans. Circuits Syst., 27:
577603, 1980.
58. L. Weiss and W. Mathis, A thermodynamical approach to noise
in nonlinear networks, Int. J. Circuit Theory Appl., 26 (2): 147
165, 1998.
59. R. L. Stratonovich, Linear and nonlinear fluctuation dissipation
theorems, Berlin: Springer-Verlag, 1992.
60. J. L. Bordewijk, Inter-reciprocity applied to electrical networks,
Appl. Sci. Res., B, 6: 174, 1956/57.
61. J. L. Bordewijk, Comments on Automated network design and
the interreciprocity concept, IEEE Trans. Circuit Theory, 18:
179, 1971.
62. L. M. Vallese, Incremental versus adjoint network models for network sensitivity analysis, IEEE Trans. Circuits Syst., 21: 46
49, 1974.
63. A. Russel, Alternating Currents, Chap. 27, Cambridge: Cambridge University Press, 1904.
ber reziprozitat bei wechselstrom64. K. Matthies and F. Strecker, U
kreisen, Arch. f. Elektrotechn., 14: 115, 1924.
65. L. Weinberg, Network Analysis and Synthesis, New York:
McGraw-Hill, 1962.
66. W. Mathis and W. Marten, On the structure of networks and duality theory. Proc. 31st Midwest Symp. Circuits Syst., St. Louis,
USA, 1988.
ber die Darstellung von Minty-Netzwerken durch
67. A. Reibiger, U
Bondgraphen. TU Dresden, TU Informationen 09-02-90, 1990.
68. J. C. L. Fortescue, Method of symmetrical coordinates applied to
the solution of polyphase networks, Trans. AIEE, 37: 1027
1040, 1918.
69. A. C. Barlett, The Theory of Electrical Artificial Lines and Filters,
New York: Wiley, 1931.

72. W. Mathis, Equivalence and transformation, in W. K. Chen (ed.),

The Circuits and Filters Handbook, Boca Raton, FL: CRC Press
and IEEE Press, 1995.

WOLFGANG MATHIS
University of Magdeburg

RAINER PAULI
Technical University of Munich

462

TRANSMISSION USING CHAOTIC SYSTEMS

that a chaos like signal y(t) enters the receiver. The receiver,
which will be explained further, extracts by a suitable procedure the information signal from y(t). This produces a signal
s(t) that should be as accurate as possible a copy of the original information signal s(t). Before going into details, we
briefly list the advantages of chaos when properly used in
communication systems.
1. Deterministic chaotic systems produce deterministic
signals which look like noise and are wideband signals.
2. Two exact copies of a chaotic system, when started with
infinitely small different initial conditions, produce decorrelated output signals after a short transient. In
other words, it is said that one manifestation of chaos is
the property of extreme sensitivity to initial conditions.
3. Very simple systems can be designed in such a way that
they behave chaotically.
4. Certain classes of chaotic oscillators can be shown to be
synchronizable.
5. Determinism in chaotic signals can be exploited to enhance these signals when they are corrupted by noise.

TRANSMISSION USING CHAOTIC SYSTEMS

As surprising as it might seem, conveying information using
chaotic carrier signals can be highly beneficial and desirable
in many applications in which the information (1) has to be
delivered to somebody with a certain level of secrecy and (2)
has to be spread over a channel without interfering with other
communications. The purpose of this article is to show why
and how it is possible to design chaotic systems that encode
information signals by mapping them onto chaotic signals. We
will describe special modulation processes in which the information signal modulates a chaotic deterministic signal. Of
course this kind of modulation is only meaningful if one is
able to design a demodulation process that can extract the
information from the modulated signal. Therefore the main
problem we will address is the design of receiver systems that
are able to detect the information signal by processing the
modulated chaotic signal.
The information transmission systems we will deal with
can be decomposed according to Fig. 1. An information signal
s(t) is injected into a chaotic dynamical system that produces
a chaotic output signal y(t). The transmission of y(t) through
some medium, called the channel, degrades it in such a way

s(t)
Information
signal

Figure 1. Transmission system.

Chaotic
system
(transmitter)

It is now easy to understand why chaotic signals and systems

can be useful for transmission purposes. Property 1 suggests
that chaotic oscillators could be used to spread (in frequency)
information through a channel. Property 2 indicates that two
identical oscillators started or modulated with two different
initial conditions will produce two uncorrelated modulated
signals. This decorrelation of modulated signals active in the
same band suggests that a receiver properly tuned to one of
the oscillators and started with the appropriate initial condition will barely notice the other transmissions if one uses a
detection based on correlation techniques. Therefore chaotic
modulation can be seen as an alternative spread-spectrum
modulation in which other communications, although sharing
the same channel, are transparent to each other as well as to
other interfering signals. In other words, each transmitter
receiver pair possesses a transmission key that ensures that
two different transmitterreceiver pairs will send two orthogonal signals through the channel. What would this key be?
The key could be, for instance, a combination of parameter
values of the oscillator and initial conditions in the transmitter. Figure 2 depicts an example. In this example, two communications have been sent through the same channel, which
is modeled by a constant delay plus an additive constant
noise. To highlight the good decorrelation properties of chaotic systems, the two information signals are modulated using
two exact copies of discrete-time chaotic dynamical systems.
The only difference in the modulation comes from two slighly
different initial conditions in the oscillators. Note that this
difference is very small, only 1 106. As indicated by prop-

Channel
y(t)

^
y (t)

Modulated
chaotic signal

Received
signal

Receiver

^s(t)

Retrieved
information
signal

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

TRANSMISSION USING CHAOTIC SYSTEMS

s1(nT )

y1(nT )

x1(nT )

^s (n k)T )
1

Information
detection

463

x1((n k)T )

Chaotic system 1
x1(0)

Delay
kT

y(nT )

Chaotic system 1

Transmitter 1
Noise
Channel
s2(nT )

Receiver 1

y2(nT )

x2(nT )

^s ((n k)T )
2

Information
detection

x2((n k)T )

Chaotic system 1

Chaotic system 2

x2(0)
Transmitter 2
Receiver 2
Figure 2. Chaotic modulation and demodulation of two information signals sent through the
same channel.

erty 3, the chaotic system does not have to be very complicated. This is the case in the example, in which the oscillator
is a skew tent map system that is described in Fig. 3. The
parameter a of the skew tent map is chosen in such a way
that the system operates in a chaotic regime (0 1).
For each bit of information to be sent to the channel a signal
sequence of 500 iterations of the skew tent map system multiplies a constant signal whose value is 1 or 1 according to
the value of the bit we want to transmit 0 or 1. This principle
of modulation is shown in Fig. 4. The receiver oscillators are
supposed to be synchronized by adjusting their delay to that
of the channel for their corresponding signals of interest.
Therefore in this (academic) example we have chosen to detect the information signal by measuring a filtered version of
a sliding correlation function. Ideally the demodulation
should provide a positive constant C when a bit 1 is transmitted while giving us C when a 0 is transmitted. The communication noise in the example has been adjusted in such a
way that its power is equal to that of y1(n). Despite the consec-

utive very bad signal-to-noise ratio, the retrieved sequences

after filtering provide the correct sequences of bits since any
thresehold detector would produce the exact information sequences. This example illustrates some of the appealing aspects of chaos modulation; that is, we can spread information
on a channel and make this information transparent. The
user who wants to demodulate the information has to find the
key. The key in our example is just an initial condition and a
parameter value both the transmitter and the receiver have
agreed to use in advance. The property of sensitivity tells us
that there is a large number of keys available, and this number of keys can be enlarged if we decide to use more sophisticated maps or combinations of 1D skew tent maps. Therefore
the chaotic modulation gives us some level of security since
finding the key would suppose that a codebreaker would be
able to identify both the parameter value and the initial con-

1.5
s1(n)
x1(n)
y1(n)

1
s1(n), x1(n), y1(n)

x(n)
+1

0.5
0
0.5
1
1.5

+1

x(n 1)

Figure 3. Skew tent map system.

1000

2000

3000
Time

4000

5000

6000

Figure 4. Principle of modulation of the chaotic sequence x1(n).

Detected s1(n) versus original s1(n)

464

TRANSMISSION USING CHAOTIC SYSTEMS

1.5
1
0.5
0
0.5
1
1.5
0

2000

4000

6000

8000

10000

Time

Figure 5. Detection of the s1(n) sequence using a correlation

measure.

Detected s2(n) versus original s2(n)

dition in oscillator state-space. Although certainly not impossible in theory, this operation of identification would require
in general a great amount of computation time for highdimensional chaotic systems.
We have assumed until now that the transmitter and the
receiver are synchronized, and this synchronization can be attained in different ways ranging from absolute time measurement to periodic transmission of predefined synchronizing sequences. The illustrative example presupposes that both the
transmitter and the receiver use two exact versions of a digital chaotic system and use the same rounded initial conditions in state-space; otherwise synchronization would fail.
What happens if we are unable to build an accurate copy of
the transmitter? For instance, if we decide to modulate a chaotic analog system, would we be able to retrieve the modulating signal? Since any analog implementation of an oscillator
would mean that we are able to replicate parameter values
and initial conditions in a range of 1% to 5%, it seems a priori
impossible to retrieve the information. The purpose of this
article is to show that in certain circumstances it is, however,
possible to synchronize even imperfect copies of chaotic oscil-

1.5
1
0.5
0
0.5

lators. This is given by property 4, which seems at first to

contradict property 2. In addition, if the receiver knows in
advance the equations of the dynamics of the chaotic signals
sent by the transmitter, it can check to see if the received
signals follow the a priori known trajectory constraints (determinism), and take advantage of the constraints to clean the
noisy carrier (property 5) before extracting the information.
This synchronization, the definition of which will be given
later, means that the receiver is able to reconstruct the transmitter state-space independently of its initial conditions. Although this intriguing property seems to defy the intrinsic
sensitivity property of chaotic systems, different methods of
synchronization have been already developed. This article investigates two groups of chaotic-based transmission systems.
One group is based on synchronization. The second is based
on purely statistical properties of chaotic systems. In addition, we exploit property 5 and show how determinism can be
used to improve the capabilities of the spread-spectrum
systems.

SYNCHRONIZATION OF CHAOTIC SYSTEMS

Listed here are three different methods used to synchronize
chaotic systems:
1. Synchronization by decomposition into subsystems
2. Synchronization by linear feedback
3. Synchronization by inverse system design
The notion of synchronization is usually linked to periodic
systems. Conventional communication systems generally use
sinusoidal carriers that are either amplitude-modulated or
frequency-modulated. In this context, phase-locked-loop systems (PLL) have been specifically designed to extract the information signal from the frequency-modulated carrier. The
information extraction is facilitated by the carrier sinusoidal
form, and the notion of synchronization refers to a notion of
phase synchronization in which a feedback system, the PLL,
is able to track the instantaneous phase of the carrier (with a
constant shift of /2). In the case of chaotic modulation the
notion of phase synchronization is hardly exploitable and the
notion of synchronization is generally considered as the asymptotical convergence of two signals when time tends towards infinity.
To understand this notion of synchronization, consider the
masterslave relationship shown in Fig. 7. In this setup a
master system (i.e., an autonomous dynamical system) sends
its output signal to a slave system and controls this slave system in such a way that the slave produces a signal y(t). The
signal y(t) is often called the driving signal. The slave system

1
1.5
0

2000

4000

6000

8000

10000

Time

Figure 6. Detection of the s2(n) sequence using a correlation

measure.

Slave system

Master system
y(t)

Figure 7. Masterslave setup.

^
y (t)

TRANSMISSION USING CHAOTIC SYSTEMS

= Ax(t) + bu (t)
x(t)
1
A is stable

y(t)
X(t) = [x(t), y(t)]

x1(t)

^
x^(t) = Ax(t)
+ bu1(t)

465
^ (t)
x
1

x(t)

u1(t)
Figure 8. Decomposition of the system as an interaction between
two subsystems.

u1(t)

f( )

f( )

Figure 10. Synchronization by open-loop state estimation for

Lures systems.

synchronizes with the master system if

| y(t)
y(t)| 0

when t

(1)

independent of the initial conditions in both the master and

the slave systems.
This definition can be enlarged to take into account both
inaccurate system parameters and nonideal signal transmission. We will, however, stick to this definition in the scope of
this article since the purpose is to arrive at an understanding
of the basic principles of chaos synchronization.
It is possible to synchronize two systems with chaotic behavior. Such systems have sensitive dependence on initial
conditions (i.e., any two solutions drift apart) even if their
initial conditions are very close to each other. It is the driving
signal that forces the slave system to follow the time evolution of the master system. The following sections present
three methods to achieve this.
Synchronization by Decomposition into Subsystems
This idea was first proposed by Pecora and Carroll in 1990 (1)
and is called open-loop state estimation in the control literature.
Suppose that a nonlinear dynamical system can be described by state equations of the form
dxx
= F (xx, y1 ),
dt

where F : Rn+1 R n

(2)

dyy
= F (xx1 , y),
dt

where G : R m+1 R m

(3)

where x (x1, . . ., xn) and y (y1, . . ., ym) form the state

space of the nonlinear dynamical system X (x, y). Therefore
the system can be decomposed into two subsystems that interact through the signals x1 and y1 (see Fig. 8).
The synchronization by decomposition into subsystems
consists of building a slave system which is an open-loop version of the master system. In this open-loop version the subsystem whose state is x is forced with the signal y1 (see Fig.
9) while the output x1 of this subsystem feeds the subsystem

y(t)
y1(t)

x1(t)
x(t)

y(t)

y^1(t)

^
x(t)

y1(t)

whose state space is y. If both the systems of Fig. 9 were

started with the same initial conditions x(0) x(0) and
y(0) y(0), then the time evolution of the state variables in
both systems would be identical; that is, the two systems
would be perfectly synchronized. However, in practical situations either we have no control over the initial conditions and
we are not able to design accurate subsystem copies. Therefore synchronization may or may not take place. Depending
on the example, synchronization can be easy or it can be difficult, if not impossible, to prove. A typical example in which
the proof is easy is the following coupling of two Lures systems (Fig. 10). Lures systems are such that a linear subsystem interacts with a nonlinear static nonlinearity. The masterslave setup of Fig. 10 can be described using the following
equations:
dxx
= Ax + b u1 ,
dt

dx
= Ax + b u1
dt

(4)

u1 = f (x1 ),

u1 = f (x1 )

(5)

Thus, if all eigenvalues of A have negative real parts, the

slave system synchronizes with the master system. A more
complicated case is one in which the synchronization is
mainly investigated using simulations; as an example we take
Chuas circuit (see Fig. 11). The state space of this oscillator
is a three-dimensional state space, where the state space variables are v1, v2, and iL. Chuas circuit is described by the following state equations:
C1

dv1
1
= (v2 v1 ) g(v1 )
dt
R

(6)

C2

dv2
1
= (v2 v1 ) + iL
dt
R

(7)

diL
= v2
dt

(8)

in which the nonlinear resistor characteristic g(v1) is shown

in Fig. 12.

x^1(t)
v1(t)

iL(t)

NR
C1

C2

Figure 9. Synchronization by open loop state estimation.

Figure 11. Chuas circuit.

v2(t)

466

TRANSMISSION USING CHAOTIC SYSTEMS

IR
G1

1.5

1
0.5

vR

Bp
G0

vC1

+Bp

0
0.5

1
1

G1
1
Figure 12. Nonlinear characteristic in Chuas circuit.

1.5
0

2000

4000

6000

8000

10000

Time

By choosing the parameters to be R 1730 , L 18 mH,

C1 10 nF, C2 100 nF, Bp 1 V, G0 0.44/R and G1
0.23/R, Chuas circuit is set in a chaotic mode. A projection
of the state-space attractor of the oscillator is shown in the
plane v1 iL (see Fig. 13), while Fig. 14 gives a sample of the
irregular behavior of v1(t).
Suppose that we decide to send v1(t) and want to design a
slave system so that this slave system will produce a signal
v1(t) that converges asymptotically to v1(t). By decomposing
Chuas circuit in two subsystems, the role of x and y in Fig. 9
are played by x (v2, iL) and y v1. The first subsystem
driven by v1(t) aims to reproduce the state space variables v2
and iL. This first subcircuit is shown in Fig. 15. This subsystem is linear and its elements have positive values, and therefore it is an asymptotically stable circuit. This implies that
the state variables v2 and L will converge toward the state
variables of the master circuit as t tends toward infinity. It is
now clear that for accurate values of C2, L, and R the first
subsystem of the slave will accurately reproduce two of the
state variables of the master system. The second subsystem
shown in Fig. 16 will be driven by the signal v2(t), which is
the output of the first slave subsystem. The aim of this second
subsystem is to reproduce the state-space variable v1(t). Depending on the circuit parameters, synchronization may occur
or not (2). The exact conditions for synchronization can, however, be computed in this case. Derivation of these conditions
are beyond the scope of this article and can be found in Ref. 3.

4
3

Figure 14. Behavior of v1(t) for the Chuas circuit operating in chaotic mode.

Synchronization by Linear Feedback

This approach is a typical automatic control approach in
which the master and the slave compare their output to form
a synchronization error signal. The synchronization error signal is fed back as a control input of the slave system, which
is a copy of the master system (see Fig. 17). This approach
has been introduced in Ref. 4 under the topic of control of
chaos. Usually the synchronization is linearly fed back to the
state variables, and therefore the state equations of the whole
system are such that
dxx
= f (xx )
dt

(9)

y(t) = c Tx (t)

(10)

dx
= f (x ) + k e(t)
dt

(11)

y(t)
= c T (x )

(12)

e(t) = y(t) y(t)

(13)

If both the master and the slave had agreed to start from the
same initial conditions, then at all times we have x(t) x(t),
y(t) y(t), and e(t) 0. With no constraints on initial conditions, the slave system may or may not synchronize and the
synchronization has to be studied case by case. In some instances, conditions on the coupling matrix k that ensures synchronization can be derived by using Lyapounov functions (4).

2
iL

1
0

iL(t)

v1(t)

3
4
3

C2

0
vC1

v^ 2(t)

Figure 13. Chuas circuit attractor projection in the plane v1iL.

Figure 15. Slave system first subsystem; subsystem driven by the

master circuit.

TRANSMISSION USING CHAOTIC SYSTEMS

y(n)

R
v^ 1(t)

NR

v^ 2(t)
C1

x1(n)

x^ 1(n)

x2(n)

x^ 2(n)

xN(n)

x^ N(n)

T
s(n)
f(s, x)

Figure 16. Slave system second subsystem.

Synchronization of the Inverse System

T
T
f 1(x, y)

^s(n)

Figure 18. Discrete-time system and its inverse.

In this method we consider the general setup of Fig. 1. The

goal is to control a chaotic system with an information signal.
The output of the transmitter, a chaotic broadband signal
where the information is hidden, becomes, after transmission,
the input of the receiver that must retrieve the information
signal independent of the state space and the initial conditions of the receiver. In order to do this, the receiver must
perform an inputoutput relationship that is inverse to that
of the transmitter. Therefore this kind of synchronization has
been referred to as inverse system synchronization. Consider
the following example borrowed from Ref. 5 (see Fig. 18). Similar examples can be also found in Ref. 6. In Fig. 18 it is supposed that the function f(x, s) is invertible with respect to s.
Independent of the state-space initial conditions in the receiver, it can be seen that after N iterations of the transmitter
x (k) = x (k)

467

if k N

(14)

Therefore as f(x, s) is invertible with respect to s, we get

s s for k N.
For continuous-time systems the synchronization by the
inverse system approach can be explained as follows. Consider the nonlinear dynamical 1-port of Fig. 19 excited by an
independent current source with current i(t). If we would take
the voltage across the current source and drive an exact copy
of the same 1-port by a voltage-controlled source, we would
find exactly the same current i(t) flowing through the voltage
source, provided that the initial currents in the inductors and
the initial voltages across the capacitors in the two 1-ports
are identical (see Fig. 19). This method of synchronization has
been sucessfully applied to various circuits. Consider the example borrowed from Ref. 7 in which two Chuas circuits have
been synchronized using the inverse system approach (see
Fig. 20). In this case it is possible to prove exactly the synchronization because imposing the voltage across the nonlinear resistor forces the current in the receiver nonlinear resistor to follow exactly the current in the transmitter nonlinear

resistor. Therefore 1(t) i1(t) for all times, and consecutively

2(t) converges asymptotically to i2(t) since i2 is the port current of a linear passive 1-port. An analysis of the inverse system approach can be found in Ref. 5. Despite its clear foundation the inverse system approach suffers from different
drawbacks that limit its applicability. It has been reported by
many researchers that the inverse system approach is very
sensitive to channel noise. Furthermore, the transmitter
should be designed in such a way that it remains chaotic with
all admissible signals; unfortunately there is no general
method known for this.
EXPLOITING CHAOS SYNCHRONIZATION FOR
TRANSMISSION OF INFORMATION
So far we have explained three methods to ensure synchronization between a master system and a slave system. Now we
will present different methods for modulating chaotic carriers
and retrieving this information from the observation of the
chaotic carrier:
1. Chaotic masking
2. Chaotic shift keying
3. Direct chaotic modulation.
Chaotic Masking
In this method (8) an analog information carrying signal s(t)
is added to the output y(t) of the chaotic system in the transmitter. On the receiver side an identical chaotic system tries
to synchronize with y(t). From this point of view, the information signal s(t) is a perturbation, and synchronization will

i(t)

x(t)

+
y(t)

^
x(t)

+
e(t)

^
y(t)

Figure 17. Masterslave setup for synchronization by linear

feedback.

i(t)

v(t)

Nonlinear
dynamical
1-port

v(t)

Nonlinear
dynamical
1-port

Figure 19. Realization of the inverse system for analog circuits.

468

TRANSMISSION USING CHAOTIC SYSTEMS

i(t)
^

i1(t)

i1(t)
R
^

v1(t)

i(t)

NR
C1

Figure 20. Synchronization of Chuas

circuit by the inverse system.

In this method (2,10) the information signal is supposed to be

binary. This binary information modulates a chaotic system
by controlling a switch whose action is is to change the parameter values of a chaotic system (see Fig. 22). Thus according to the binary value of s(t) at any given time, the chaotic system can use either the parameter vector p or the
parameter p. The receiver consists of two sets of receivers:
One uses the parameter vector p, while the other uses the
parameter p. At any given time, the receiver which is able to
synchronize or which synchronizes best tells us what set of
parameters has been used in the transmitter (see Fig. 22).
When the transmitter switch is on position p, the receiver
with parameter p will synchronize, whereas the receiver with
parameter p will desynchronize. Therefore when the parameter p is used in the transmitter the error signal e(t) converges
toward 0 while the error signal e(t) has an irregular waveform with nonzero amplitude. Information is retrieved by detecting synchronization and desynchronization of errors signals. In such a method the switching speed is inversely
proportional to the time of synchronization. We give below a

detailed example in which this synchronization speed is assessed.

Example of Chaos Shift Keying Transmission. We take the example already developed in Ref. 2. The transmitter is based
on a Chuas circuit (see Fig. 23) whose chaotic behavior has
been widely studied (1114). It consists of a single nonlinear
resistor (see Fig. 24) and four linear circuit elements: two capacitors, an inductor, and a resistor. Details of the synthesis
of the nonlinear resistor can be found in Ref. 15. The modulation device runs as follows. A binary data stream (the signal
to be transmitted) modulates the chaotic carrier vC1(t). If an
input bit 1 has to be transmitted, the switch of Fig. 23 is
kept open for a time interval T. If the next bit to be transmitted is 1, the switch is closed, connecting in parallel the resistor r with the nonlinear negative resistor. During the
transmission of the 1 bit, the device can be seen as a Chuas
circuit with a three-segment piecewise-linear resistor having
a slope G0 G0 1/r in the central region and a slope G1
G1 1/r in the outer region. The breakpoints Bp remain unchanged. The following three equations describe the dynamics
of the modulation system:
C1
C2
L

dvC (t)
1

dt
dvC (t)
2

dt
diL (t)
1

dt

Transmitter

1
(v (t) vC (t)) h (vC (t))
1
1
R C2

Chaotic
system

^
y(t)

^
s(t)

Figure 21. Transmission using chaotic masking.

(16)

= vC (t)

(17)

p
Chaotic
system

^
y(t)

p
Chaotic
system

^
y(t)

e(t)
+

y(t)

Chaotic system

Receiver

(15)

1
(v (t) vC (t)) + iL (t)
1
1
R C2

y(t)

s(t)

C2

i2(t)

Transmission Using Chaotic Shift Keying (CSK)

y(t)

NR
C1

i2(t)

take place only approximately. However, if the synchronization error is small with respect to s(t), the latter can be approximately retrieved by subtraction (see Fig. 21). This is the
case if the signal s(t) is small with respect to y(t) and/or if the
spectra of the two signals do not overlap too much. Both of
these requirements can apparently be relaxed (9). However,
if the purpose of using a chaotic signal for transmission is to
hide the information, s(t) should not be large. Therefore, it
can be expected that the method is sensitive to channel noise.
Indeed, additive noise cannot be distinguished from s(t) by
the setup of Fig. 21, and it has to be eliminated at a later
stage. This is a difficult, if not impossible, task if the amplitude of s(t) is not large with respect to the noise level.

Chaotic
system

v(t)

C2

e(t)
+

Figure 22. Transmission using chaotic shift keying.

TRANSMISSION USING CHAOTIC SYSTEMS

469

+
L1

vC2

C2

iR

NR

vR

vC1

C1

vC1

iL1

vC21

C2

iL2

Transmitter

Figure 23. Transmitter for binary chaotic shift keying using Chuas
circuit. Chaotic signal vC1 is transmitted.

Figure 25. First receiver subsystem.

The function h in Eq. (15) has the following meaning: During

a bit 1 transmission we have h h, where h is the threesegment piecewise-linear function with slopes G0, G1 and
breakpoints Bp and Bp; during a bit 1 transmission we
have h h, where h is the three-segment piecewise-linear
function with slopes G0, G1 and breakpoints Bp and Bp. We
suppose that the signal vC1(t) is transmitted to the receiver
without any alteration.
The receiver is made of three subsystems (see Figs. 25 to
27). The goal of the first subsystem is to create as close as
possible a copy of the signal vC2(t); this signal will be referred
to as vC21(t). The first subsystem is governed by the two following equations:

Additional elements for the circuits in Figs. 25 to 27 remain

to be designed for the synchronization detectors. The interested reader can find in Ref. 2 a method explaining how it is
possible to compute a bound for the synchronization time.
This method is based on the computation of the relative duration time of the driving signal in the different areas of the
piecewise characteristic of the nonlinear resistor of the transmitter.
We present here simulations using the subsystems described in Figs. 25 to 27. The value of r was chosen in order
that G0 and G1 exhibit variations of 1% with respect to G0
and G1. The values of circuit elements were fixed as follows:
R 1680 , L 18 mH, C1 10 nF, C2 100 nF, G0
753 s, G1 396 s, and Bp 1 V. The value of T was
4.65 ms.
Figure 28 shows the chaotic message from 10 ms to 40 ms
and the corresponding binary message.
Figure 29 shows the double-scroll attractor in the phaseplane (vC1(t), vC2(t)) during the transmission of the binary message presented in Fig. 28.
Figure 30 shows the relationship between vC12(t) and vC1(t)
during the transmission of 120 bits which were alternatively
1, 1 while Fig. 31 displays the relationship between vC12(t)
and vC1(t) during the same transmission.
Obviously the receiver subsystems are not synchronized
during the whole transmission (it is hoped that the receiver
not matched to receive the right bit exhibits a desynchronized
behavior). Finally, Fig. 32 shows the relationship between
vC12(t) and vC1(t) during the transmission of 60 nonconsecutive
1 bits. The signals were sampled during the last half duration of each bit in order to avoid transients. Figure 33 is the
alter ego figure of Fig. 32; it shows the relationship between
vC12(t) and vC1(t) during the transmission of 60 nonconsecutive
1 bits. The interested reader can find in Ref. 2 an implementation of the chaotic shift keying method which confirms the
above-presented simulations.

C2

dvC (t)

21

dt
diL (t)
2

dt

1
(v (t) vC (t)) + iL (t)
2
21
R C1

(18)

= vC (t)

(19)

21

The second and the third subsystems are designed to produce

the signals vC12(t) and vC12(t). As will be shown in the theoretical part of this article, vC12(t) converges to vC1(t) during the
transmission of 1 bit while vC12(t) converges to vC1(t) during
the transmission of 1 bit. Equation (20) governs the second
subsystem, while Eq. (21) governs the third subsystem:
C1
C1

dvC (t)
12

dt
dvC
(t)
12

dt

1
(v (t) vC (t)) h+ (vC (t))
12
12
R C 21

(20)

1
(v (t) vC
) h (vC
(t))
12
12
R C 21

(21)

IR
G1

+Bp
R

vR

Bp

G0
1

vC21

G1
1
Figure 24. Three-segment piecewise-linear function. The inner region has slope G0; the outer regions have slopes G1.

NR

C1

vC12

Figure 26. Second receiver subsystem.

470

TRANSMISSION USING CHAOTIC SYSTEMS

0.8

vC21

NR

C1

0.6

vC12

0.4

0.2

VC12

Figure 27. Third receiver subsystem.

0.2
0.4

Direct Chaotic Modulation

Figure 28. Behavior of the chaotic signal

vC1(t) () and of the binary message
( ).

0.6
0.83

0
V C1

Figure 29. Double-scroll attractor in the phase plane vC1(t), vC2(t) during modulation.

in Fig. 34, where a phase-modulated signal is transmitted

on a chaotic carrier, using Saitos circuit. At the beginning,
the receiver needs some time to synchronize, but afterwards
the receiver tracks the 180 phase shifts perfectly. In Fig.
35, the transmitted signal is represented for the same experiment. Both figures were created with computer simulation.

1.5

0.5

0.5

3
10

15

20

25
Time (ms)

30

35

1.5
40

Message

vC1

In this method the inverse system approach is used directly

in a straightforward manner. Thus, no additional circuitry
must be used, the chaotic system is the transmitter, and the
inverse system is the receiver. If we look at a circuit realization (e.g., in Fig. 18), we can see that s(n) drives the chaotic
circuit and thus modulates the chaotic signal in some way.
The information can be injected directly in analog form, as
proposed in Ref. 7, or s(t) can be itself an analog signal modulated by binary information, as proposed in Ref. 16, with the
obvious advantages and drawbacks. The transmission of a
digital signal modulated onto s(t) can be expected to reach
higher bitrates than with chaotic switching. In chaotic switching, whenever the signal changes its value, one has to wait
for synchronization since the initial conditions in the transmitter and the receiver subsystem that have to synchronize
are different. In direct chaotic modulation, the receiver continuously tracks the transmitter and thus the states of the
two chaotic systems are never very different. This can be seen

TRANSMISSION USING CHAOTIC SYSTEMS

471

3
2

2
1

VC12

VC12

0
1

1
3
3

3
3

0
V C1

Figure 32. vC12(t) as a function of vC1(t) during the transmission of

several bits 1.

0
V C1

Figure 30. vC12(t) as a function of vC1(t) during the transmission of

several bits 1, 1.

EXPLOITING CHAOS FOR INFORMATION TRANSMISSION BY

MEANS OF STATISTICAL DECISION
Until now we have presented examples in which synchronization has been used in order to detect the information signal.
In digital communication systems, this approach would belong to the coherent detection approach in which the signal
sent to the channel is made of a combination of basis functions. At the receiver the basis functions are usually regenerated using synchronization and the symbols which were associated with the combination of the basis functions are
therefore detected. This is in fact the scheme which has been

used for the CSK technique in which a bit 1 is associated

with a segment of chaotic waveform belonging to one of two
different attractors (i.e., produced by two slighly different systems). At the receiver, two systems are also used, and the
system which best synchronizes with the incoming signal
allows the detection of the right bit of modulation.
We now present some basic ideas that are based on the
noncoherent detection approach; in contrast to the coherent
detection approach, we now rely on the estimation of one or
more characteristics of the basis functions, and will not assume that the basis functions are regenerated at the receiver.
Coherent detection-based receivers are known to have advantages over noncoherent receivers in terms of noise performance and bandwidth efficiency. However, these advantages
are lost if synchronization cannot be maintainedfor example, under poor propagation conditions. In these circumstances, communication without synchronization may be preferable. In the following sections we present two classes of
systems which exploit the noncoherent detection approach. In
that kind of approach, it is mainly the macroscopic features
of deterministic chaos which will be usedthat is, the good

2
3

1
VC12

VC12

0
1

2
2

3
3

0
V C1

Figure 31. vC12(t) as a function of vC1(t) during the transmission of

several bits 1, 1.

3
3

0
V C1

Figure 33. vC12(t) as a function of vC1(t) during the transmission of

several bits 1.

472

TRANSMISSION USING CHAOTIC SYSTEMS

be a PN signalthat is, a signal which is formed by linearly

modulating the output sequence cn of a pseudorandom number generator onto a train of pulses, each pulse having a duration Tc called the chip time:

0.6
PSK Wave
Detected PSK Wave

0.4

0.2

c(t) =

n=+

cn p(t nTc )

(22)

n=

where p(t) is the basic pulse shape which is assumed to be of

rectangular form.
The bit duration Tb of the information signal m(t) is such
that

0.2

0.4

Tb  Tc

10

(23)

Time (ms)
Figure 34. Original and retrieved information signal, for direct modulation with Saitos circuit ( PSK wave; detected PSK
wave) (From Ref. 16.)

decorrelation properties between two different segments of

chaotic trajectories. This is in contrast with the methods presented in the section entitled Synchronization of Chaotic
Systems, in which we mainly used the microscopic nature of
chaos (i.e., the determinism), since we implicitly used (in the
synchronization approach) the dynamical constraints between
consecutive points of a chaotic trajectory.
Example 1: Chaotic Direct-Sequence Spread-Spectrum Systems
Spread-spectrum systems are systems that are designed to
resist to external interference, to operate with a low-energy
spectral density, to provide multiple-access capability without
external control, or to make it difficult to unauthorized receivers to observe the message. Among different classes of methods, we briefly describe the direct-sequence spread-spectrum
approach which uses as a carrier signal a pseudonoise (PN)
which consists usually of a binary PN sequence; our objective
will be to show that a better alternative would be to use a
chaotic sequence.

A standard direct-sequence spread-spectrum (DSSS) system

operates with a double modulation. At the emitter the message m(t) is spread by multiplying m(t) by c(t). This first
modulation is followed by a second standard modulation
which centers the spectrum of the transmitted signal around
a frequency carrier 0. At the receiver the same PN sequence
is used to unspread the signal. For the sake of simplicity we
will ignore in the following the second modulation. The complete simplified modulationdemodulation scheme is shown
in Fig. 36. As shown in Fig. 36 the product of the received
signal v(t) by a delayed version of the spread spectrum is integrated. Let us suppose that the integration time is equal to
the message bit duration Tb. Furthermore, let us suppose that
in an ideal manner the output of the integrator is reset to
zero at the beginning of each message bit while this output is
precisely observed at the end of each message bit. In our simplified scheme of transmission the received signal is of the
form
v(t) = m(t )c(t ) + (t)

where (t) is the observation noise. If we suppose that (t)

and c(t ) are uncorrelated, we get at the output of the
integrator

m(kT

b) =

Basic Principle for Standard Direct-Sequence Spread-Spectrum

Systems. Let m(t) be a binary message 1 and let c(t) 1

(24)

kTb
(k1)Tb

v(t)c(t
) dt = m(kTb )Rc (
)

(25)

where Rc() is the cross-correlation function of c(t). The result

will therefore be maximum if equals zerothat is, if
the emitter and receiver sequences are synchronized.

Vr (V)

5
0

4
6
Time (ms)

10

Figure 35. Transmitted signal, for direct modulation with Saitos

circuit. (From Ref. 16.)

Limiting Properties of PN Sequences. In order to spread

bandwidth, PN sequences have been used extensively in
spread-spectrum communication systems. The maximallength linear code sequence (m-sequence) has very desirable
autocorrelation functions. However, in the case of multipath
environments, large spikes can be found in their cross-correlation functions. Another limitation is that they are very
small in number. In order to overcome these limitations,
HeidariBateni and McGillem (17) have been among the first
to propose the use of chaotic sequences as spreading sequences.
Advantages Associated with Chaotic Sequences. Chaotic sequences present the following advantages:

TRANSMISSION USING CHAOTIC SYSTEMS

473

n(t)
v(t)

m(t)

Delay

X
c(t)

1
Tb

^ )
m(t

Decision
unit

t Tb

c(t )

Channel

Transmitter

Receiver

Figure 36. Simplified modulationdemodulation scheme for a DSSS system.

It is easy to generate a great number of distinct sequences.

The transmission security is increased.
Correlation properties which are very similar to those of
random binary sequences. In some cases, superior properties have been reported (18,19).

The process is pictured in Fig. 37. If both the receiver and

emitter have agreed on y0, C1, C2, r1, r2, the sequence can be
regenerated at the receiver in exactly the same manner as
the emitter does. Note that as there is a change in initial
conditions at each new bit transmission, the decorrelation between adjacent y(t) corresponding to adjacent bits will be almost zero. Every receiver will be assigned distinct y0, C1, C2,
r1, r2, and therefore the resulting spreading sequences for
each receiver in a multiple-access communication system will
be completely different and almost decorrelated. Since there
is a large number of initial conditions, bifurcation parameters, and chaotic maps to choose from, there are no limitations on the number of users that could be accommodated by
these spreading sequences. The modulation and detection of
the data sequence is otherwise the same as the conventional
DSSS systems. The detection will be based on correlating
the received signal with the chaotic sequence of the receiver.
Transmitterreceiver synchronization is supposedly attained
either from absolute time measurement or from periodic
transmission of predefined synchronizing sequences.

We should add to this list one major difference: these sequences are nonbinary sequences. This property and the fact
that these sequences are produced by deterministic systems
can be used to clean the chaotic sequencesthat is, to get rid
of the noise by checking the deterministic constraints between
consecutive points of the sequence. This property will be exploited in the section entitled Improving Chaos Transmission
by Exploiting the Deterministic Feature of Chaos.
Example. Here is a system proposed in Ref. 17 in which
both the emitter and the receiver have agreed to use two chaotic systems. A first digital chaotic system has a clock rate
1/Tb while the second has a clock rate 1/Tc. The first system
implements a one-dimensional chaotic map xn1 C1(xn, r1),
where r1 is a bifurcation parameter; the second one implements also a one-dimensional chaotic map yn1 C2(yn, r2)
with bifurcation parameter r2. The chaotic maps and their bifurcation parameters may or may not be the same, and their
uniqueness among the different pairs of transmitters and receivers is not necessary.
The two chaotic systems are associated in such a way that
the first chaotic system forces periodically the second one by
imposing the initial condition of the second system at the
starting time of each bit. Let N be the number of chips per
bit, that is, N Tb /Tc.
yn+1 = C2 (yn , r2 )

if n modulo N = 0

(26)

yn+1 = C1 (ynN+1, r1 )

if n modulo N = 0 and N = 0

(27)

Example 2: Differential Chaos Shift Keying (DCSK)

Kolumban proposed in Ref. 23 to develop a noncoherent receiver based on an idea which combines differential encoding
with chaos shift keying (CSK) modulation. Every incoming
symbol is mapped to two sample chaotic signals, one of which
acts as a reference while the other carries the information
according to some very simple transformation of the first one.
At the receiver the information is retrieved by correlating the
two samples and finding out the relationship which links two
adjacent signals. For example, let us denote as x(t) the output
of the chaos generator. For the sake of simplicity, let us consider the binary case. The symbol 1 will be represented by
a positive correlation between two adjacent signals which are
built according to

C1()

C1()

C2() C2() C2()

y1

y2

y3

Bit 1

C2()

yN

C2() C2() C2()

yN+1 yN+2 yN+3

Bit 2

C2()

y2N

C2() C2() C2()

y2N+1

C2()

Bit 3

Figure 37. Illustration of the proposed method of generating the chaotic spreading sequences.

y3N

474

TRANSMISSION USING CHAOTIC SYSTEMS

s1 (t) =

x(t)

x t

Tb
2

T
Tb
t < (2k + 1) b
2
2
Tb
Tb
t < (2k + 2)
(2k + 1)
2
2

The main disadvantage of DCSK results from differential coding: Eb is doubled and the symbol rate is halved.

(2k)

(28)

IMPROVING CHAOS TRANSMISSION BY EXPLOITING THE

DETERMINISTIC FEATURE OF CHAOS

For the symbol 0 the magnitude of the correlation remains

the same, but its sign becomes negative.

s0 (t) =

x(t)

x t

Tb
2

We have until now seen some principles of communication

which exploited the features of deterministic chaotic systems.
Indeed when we presented in the sections entitled Synchronization of Chaotic Systems and Exploiting Chaos Synchronization for Transmission of Information some synchronization principles we took advantage of the deterministic aspects
of the chaotic systems since we built the receiver system by
using a perfect knowledge of the emitter system. Therefore in
these sections we implicitly used through the synchronization
scheme the microscopic nature of chaosthat is, the fact
that successive points in the state space of the emitter system
belongs to some deterministic trajectory. In the section entitled Exploiting Chaos for Information Transmission by
Means of Statistical Decision, we used the macroscopic nature (i.e., the statistical feature of chaos) since we considered
chaotic signals as noise carriers which mainly ensured information spreading and no correlation between successive signals bearing information. It may be argued that we could still
improve our transmission features introduced in the aforementioned section if we were able to take into account the
microscopic nature of deterministic chaosthat is, the deterministic constraints which link successive points of the
state space trajectory. How to use both the statistical properties and the dynamical constraints when dealing with deterministic chaotic signals is the subject of this final section.

T
Tb
t < (2k + 1) b
2
2
Tb
Tb
t < (2k + 2)
(2k + 1)
2
2
(2k)

(29)
The reference part of the transmitted signal is the inherently
nonperiodic output signal of the chaotic generator. A block
diagram of a differential chaos shift keying (DCSK) demodulator is shown in Fig. 38. The received noisy signal is delayed
with the half symbol duration T Tb /2, and the cross-correlation between the received signal and the delayed copy of itself
is determined. The cross-correlation of the reference and information-bearing sample signals is estimated from signals of
finite duration and therefore this estimation has a variance,
even in the noise-free case. The variance can be reduced by
increasing the estimation time (i.e., the symbol duration), but
of course a larger estimation time results in a lower data rate.
Reference 20 gives an example in which an analog chaotic
phase lock loop is used in a DCSK framework. The authors
give some indication about how the optimum value of the estimation time could be determined experimentally. They show
from simulations that the noise performance of a DSCK communication system in terms of bit error ratio (BER) versus
Eb /N0 (Eb is the energy per bit and N0 is the power spectral
density of the noise introduced in the channel) outperforms
the BER of a standard CSK system. The DCSK technique offers different advantages:

Mixing the Deterministic and Statistical Aspects

In the section entitled Exploiting Chaos for Information
Transmission by means of Statistical Decision we were faced
with the problem of the measurement of the correlation between a received chaotic signal and a chaotic signal which is
generated by a local chaotic system which is assumed to be
identical and synchronized with that of the emitter (see section entitled Example 1: Chaotic Direct-Sequence SpreadSpectrum Systems). In the section entitled Example 2: Differential Chaos Shift Keying, we were faced with the problem of correlating two consecutive pieces of signal (DCSK
framework). In both cases we had to compute a correlation
function from a finite number of samples. According to the

Because synchronization is not required, a DCSK receiver can be implemented using very simple circuitry.
Demodulation is very robust and as in noncoherent receivers, problems such as loss of synchronization and imperfect recovery of basis functions do not arise.
DCSK is not as sensitive to channel distorsion as coherent methods since both the reference and the information-bearing signal pass through the same channel.

Decision
circuit

Correlator

s^ i

zi
ri(t) = si(t) + n(t)

T
0

dt

Decoder
T
Threshold

Figure 38. Block diagram of a DCSK receiver. (From Ref. 23.)

Delay
T

bk

TRANSMISSION USING CHAOTIC SYSTEMS

central limit theorem, the variance of the estimate of this correlation function varies as the inverse of the number of samples used. In order to decrease this variance we could use the
dynamical constraints that are imposed by the emitter system, the dynamics of which are assumed to be known by the
receiver. The basic problem we have to deal with is a problem
of noise reduction in which a deterministic signal (the chaotic
one) is corrupted by a noise time series which is considered
to be a realization of a stochastic process. There are different
methods which have been developed to solve the problem of
the decontamination of chaotic signals. We will give details in
the following, a simple approach which is inspired from the
work of Ref. 21 in taking from a more sophisticated method
developed by Farmer and Sidorowich (22).
We are given an M-dimensional system described by the
difference equation
x n+1 = f (xx n )

(30)

Let x be a system orbit made of N consecutive M-dimensional

points of the system (21), that is,
x = [xx 1 , x 2 , . . ., x N ]T

(31)

We can observe a contaminated version of Ref. 22 such that

each coordinate of xn, n 1, . . . N, is corrupted with an
additive Gaussian noise. The corrupted version of the orbit is
denoted y, that is,
yn = xn + w n ,

n = 1...N

(32)

stance,

C2 (x ) =

 f (x n ) x n+1 2

1. A first term ensures that the global shape of x is close

to y according to a Euclidean distance or a correlation
distance.
2. A second term involves the dynamical nature of the system using the deterministic relationship existing between consecutive points of the orbits.
For instance, as described in Ref. 21 the first cost function
can be a simple Euclidean distance

C1 (x , y ) =

x n y n 2

(33)

n=1

or can be associated with the correlation coefficient between

the enhanced orbit x and the noisy orbit y:

C1 (x , y ) = 1



N



T
n yn
n=1 x

N
n 2
n=1  x

(34)

N
y n 2
n=1 y

The second cost function measures the compatibility of the

enhanced points with the dynamics of the system, for in-

(35)

n=1

The global cost function appears as a linear combination of

C1(x, y) and C2(x) such as
c(x , y ) = C1 (x , y ) + C2 (x )

(36)

where is some positive scalar weight.

The problem addressed amounts to finding an iterative
method in x(i) which converges toward a local minimum of Eq.
(36). Such a method can be easily implemented by using a
simple gradient method in which the update of the current
estimate is in the direction opposite to that of the gradient of
the cost function, that is,


c(x , y )
(i)
(i1)

(37)
x = x
x
x =x (i1 )
Provided that is chosen small enough, the gradient method
will converge to a local minima of the cost function [Eq. (37)].
Applying the method for the cost function given in Eq. (37)
with 1, we obtain for the gradient method

my (i1)

m
m
y

m
x

(i)
(i1)
x y 1
xy
+
x 1 = x 1

mx 1
mx my
(i1)

Our goal is to find an estimate x of the noise-free orbit x

given y.
In order to achieve such a goal, the estimation problem can
be seen as an optimization problem in which a cost function
has to be minimized with respect to x. In order to exploit the
deterministic nature of the system, we can design a cost function which is made of the sum of two terms:

475

(i)

x n

(i1)

(i1)

D f (x 1
)( f (x 1
) x 2
)]
+ [2D

my (i1)
x

mx my y n mxy
(i1)
= x n
+

mx n
mx my
+

(i1)
2[( f (x n1 )

(i1)
x n )

(38)

(i1)
(i1)
D f (x n )( f (x n )

(i1)

x n+1 )],

(i)

x N

n = 2...N 1

my (i1)
x

mx my y N mxy
(i1)
= x N
+
mx N
mx my
(i1)

(i1)

+ [2( f (x N1 ) x N

)]

The gradient method is a first-order optimization method

that can converge slowly. Second-order methods are known to
converge quickly in terms of the number of iterations; however the computational load per iteration is considerably
greater compared to that of the gradient method since a Hessian matrix has to be inverted at each iteration. Alternative
de-noising methods have been developed in Ref. 22, in which
the minimization of the cost function C1(x,y) has been considered under equality constraints (constrained optimization).
When de-noising N trajectory points, N 1 equality constraints are given by the N 1 trajectory constraints f(xn)
xn1 0, n 1 . . . N 1. The constrained optimization
amounts to introduce a cost function which mixes C1(x,y) and
a linear combination of the equality constraints. This linear
combination involves the Lagrange multipliers. The augmented cost function is the co-called Lagrangian and the fun-

TRANSMISSION USING CHAOTIC SYSTEMS

damental problem is to find an extremum of the Lagrangian

with respect to x and to the N 1 Lagrange multipliers
(2N 1 unknowns). Writing the derivatives of the Lagrangian
with respect to x and to the Lagrange multipliers one has to
solve 2N 1 nonlinear equations. A large variety of search
algorithms can be used; a Newtons method can be implemented to linearize the nonlinear equations under their current solution. Ref. 22 contains the details of such a constrained optimization method. Please note that the method is
computationally demanding since a 2N 1 2N 1 dimensional matrix has to be inverted at each iteration. Other denoising methods have been developed recently. Of particular
interest is the probabilistic approach introduced by Marteau
and Abarbanel (24). The de-noising method is referred to as
probabilistic because it relies on the p of the attractor generated by the dynamical signal we observe. These probabilistic
properties are expressed in terms of the invariant distributions of data points on the attractor. Although the term probability is not fully adequate, it is used in the sense that these
invariant distributions act like probability distributions (24).
After a quantization of the phase space of the chaotic trajectories the probabilistic approach relies on the computation or
measure of the probability of passing from one quanta to any
other quanta. At the receiver end the signal can be seen as a
first order Markov chain process, the states of which are hidden by the channel noise. Given the Markov chain transition
probabilities which are known in advance at the receiver and
the noisy trajectory, the problem amounts to finding the best
Markov chain which maximizes a maximum likelihood criterion. The determinist constraints in the chaotic trajectory are
taken into account through the Markov chain transition probabilities. These probabilities can be evaluated using two techniques; for some simple piecewise linear systems they can be
computed analytically, and for most systems they can be computed by producing a very long reference clean orbit. The
maximum likelihood problem can be solved elegantly by using
powerful dynamic programming algorithms such as the Viterbi algorithm.
Example
Let us consider the Henon map, the dynamics of which are
given by

80
70
SNR on x1 after cleaning

476

60
50
40
30
20
10

10

20
30
40
50
SNR on x1 before cleaning

60

70

Figure 39. Mean-squared error according to various signal-to-noise

ratios (SNRs).

tion of chaos seems to be a solution which is not suitable for

imperfect communication channels since it is difficult to
maintain synchronization when noise is added in the channel.
These aspects have been addressed in the sections entitled
Synchronization of Chaotic Systems and Exploiting Chaos
Synchronization for Transmission of Information. The statistical properties of the chaotic signals can be exploited in different manners, by replacing the conventional PN sequences
of standard spread-spectrum systems by a chaotic oscillator
(see section entitled Example 1: Chaotic Direct-Sequence
Spread-Spectrum Systems) or by using differential coding
techniques (see section entitled Example 2: Differential
Chaos Shift Keying) if one wants to develop noncoherent receivers. The statistical aspects as well as the deterministic
aspect of chaos can be exploited together to improve the statistical approach. This view which has been developed in the
section entitled Improving Chaos Transmission by Exploiting the Deterministic Feature of Chaos offers new avenues in communicating with chaos and will be certainly exploited in a next generation of spread-spectrum systems.
BIBLIOGRAPHY

x1,n+1 = 1 1.4x21,n + x2,n

(39)

x2,n+1 = 0.3x1,n

(40)

1. L. M. Pecora and T. L. Carroll, Synchronization in chaotic systems, Phys. Rev. Lett., 64: 821824, 1990.

Figure 39 shows the performances of the noise reduction algorithm when applied to the the state of the map. The number
of points was set to N 200.

2. H. Dedieu, M. P. Kennedy, and M. Hasler, Chaos shift keying:

Modulation and demodulation of a chaotic carrier using self-synchronizing Chuas circuits, IEEE Trans. Circuits Syst., Part II,
40: 634642, 1993.

SUMMARY
We have given an overview of the different methods which
allow the transmission of information with chaotic carriers.
We have higlighted that chaotic carriers could be of great interest in communication applications in which one needs to
spread the information and/or desires some level of secrecy.
The demodulation of the information can be achieved in different ways. Synchronization can be one of these ways if one
wants to develop coherent receivers. Until now, synchroniza-

3. R. Genesio, A. Tesi, and A. De Angeli, Self-synchronizing continuous and discrete chaotic systems: Stability and dynamic performance analysis of several schemes, Int. J. Electron., 79: 755
766, 1995.
4. G. Chen and X. Dong, Controlled Chuas circuit, J. Circuits, Syst.
Comput., 3: 139149, 1993.
5. U. Feldmann, M. Hasler, and W. Schwartz, Communication by
chaotic signals: The inverse system approach, Int. J. Circuit Theory Appl., 24: 551579, 1996.
6. D. R. Frey, Chaotic digital encoding: An approach to secure communication, IEEE Trans. Circuits Syst. II, 40: 660666, 1993.

TRANSMITTERS FOR AMPLITUDE MODULATION BROADCASTING

7. K. S. Halle et al., Spread spectrum communication through modulation of chaos, Int. J. Bifurc. Chaos, 3: 469477, 1993.
8. A. V. Oppenheim et al., Signal processing in the context of chaotic
signals, Proc. IEEE ICCASP92, 1992, pp. IV-117IV-120.
9. R. Lozi and L. O. Chua, Secure communications via chaotic synchronization II: Noise reduction by cascading two identical receivers, Int. J. Bifurc. Chaos, 3: 145148, 1993.
10. U. Parlitz et al., Transmission of digital signals by chaotic synchronization, Int. J. Bifurc. Chaos, 2: 973977, 1993.
11. T. Matsumoto, A chaotic attractor from Chuas circuit, IEEE
Trans. Circuits Syst., 31: 10551508, 1984.
12. R. N. Madan (guest ed.), Chuas circuit: A paradigm for chaos, J.
Circuits Syst. Comput., Part I, 3 (1), 1993; Part II, 3 (2), 1993.
13. M. J. Ogorzalek, Chaotic regions from double scroll, IEEE Trans.
Circuits Syst., 34: 10551508, 1987.
14. L. O. Chua, M. Komuro, and T. Matsumoto, The double scroll
family, Parts I and II, IEEE Trans. Circuits Syst., 33: 1072
1118, 1986.
15. M. P. Kennedy, Robust op amp implementation of Chuas circuit,
Frequenz, 46 (34): 6680, 1992.
16. M. Hasler et al., Secure communication via Chuas circuit, Proc.
NOLTA93 Workshops, Hawaii, 1993, pp. 8792.
17. G. Heidari-Bateni and C. D. McGillem, A chaotic direct-sequence
spread-spectrum communication system, IEEE Trans. Commun.,
42: 15241527, 1994.
18. G. Mazzini, G. Setti, and R. Rovatti, Chaotic complex spreading
sequences for asynchronous DS-CDMA, Part I: System modelling
and results, IEEE Trans. Circuits Syst. I, 44: 937947, 1997.

G. Heidari-Bateni, Chaotic signals for digital communications, Ph.D.

dissertation, School of Electr. Engi., Purdue Univ., West Lafayette, IN, 1992.
H. G. Kantz and T. Schreiber, Nonlinear Time Series Analysis, Cambridge, UK: Cambridge Univ. Press, 1997.
M. P. Kennedy, Three steps to chaos, IEEE Trans. Circuits Syst., Part
I, 40 (10): 640674, 1993.
M. P. Kennedy and M. J. Ogorzalek (Eds.), Special issue on chaos
synchronization and control: Theory and applications, IEEE
Trans. Circuits Syst., Part I, 44 (10): 8531040, 1997.
L. Kocarev and U. Parlitz, General approach for chaotic synchronization with application to communication, Phys. Rev. Lett., 74 (25):
50285031, 1995.
L. Kocarev et al., Experimental demonstration of secure communications via chaotic synchronization, Int. J. Bifurc. Chaos, 2: 709
713, 1992.
G. Kolumban, M. P. Kennedy, and L. O. Chua, The role of synchronization in digital communication using chaos, Part I: Fundamentals of digital communications, IEEE Trans. Circuits Syst. I, 44:
927936, 1997.
V. Milanovic, K. M. Syed, and M. E. Zaghoul, Combating noise and
other channel distorsions in chaotic communications, Int. J. Bifurc.
Chaos, 7: 215225, 1997.
M. J. Ogorzalek, Taming chaos-Part I: Synchronization, IEEE Trans.
Circuits Syst., Part I, 40 (10): 693699, 1993.
C. W. Wu and L. O. Chua, A unified framework for synchronization
and control of dynamical systems, Int. J. Bifurcation and Chaos,
4: 979998, 1994.

HERVE DEDIEU

19. R. Rovatti, G. Setti, and G. Mazzini, Chaotic complex spreading

sequences for asynchronous DS-CDMA, Part II: Some theoretical
performance bounds, IEEE Trans. Circuits Syst. I, 44: 937947,
1997.
20. G. Kolumban, M. P. Kennedy, and L. O. Chua, The role of synchronization in digital communication using chaos, Part II: Coherent and noncoherent chaos modulation schemes, IEEE Trans.
Circuits Syst. I, 44: 927936, 1997.
21. C. Lee and D. B. Williams, Generalized iterative methods for enhancing contaminated chaotic signals, IEEE Trans. Circuits Syst.
I, 44: 501512, 1997.
22. J. D. Farmer and J. J. Sidorowich, Optimal shadowing and noise
reduction, Physica D, 47: 373392, 1991.
23. G. Kolumban et al., FM-DCSK: A new and robust solution for
chaotic communications, Int. Symp. Nonlinear Theory Appl.,
NOLTA97, Honolulu, 1997, pp. 117120.
24. P. F. Marteau and H. D. I. Abarbanel, Noise reduction in chaotic
time series using scaled probabilistic methods, J. Nonlinear Science, 1: 313343, 1991.

Reading List
H. D. I. Abarbanel, Analysis of Observed Chaotic Data, New York:
Springer Verlag, 1996.
G. Chen and X. Dong, From chaos to order: Perspectives and methodologies in controlling nonlinear dynamical systems, Int. J. Bifurc.
Chaos, 3: 13431389, 1993.
M. Hasler, Engineering chaos for encryption and broadband communication, Philos. Trans. R. Soc. London A., 353: 115126, 1995.
M. Hasler, Synchronization Principles and Applications, in C. Toumazou, N. Battersby, and S. Porta (eds.), Circuits and Systems Tutorials, New York: IEEE Press, 1994, pp. 314327.
S. Hayes, C. Grebogi, and E. Ott, Communicating with chaos, Phys.
Rev. Lett., 70: 30313034, 1993.

477

Swiss Federal Institute of

Technology

TRANSMITTER, IMPATT DIODE. See IMPATT DIODES

AND CIRCUITS.

500

FILTER SYNTHESIS

FILTER SYNTHESIS
AN OVERVIEW OF CLASSICAL FILTERS
Electrical filters are, as a rule, lossless two-ports embedded
in resistances R1 and R2, as shown in Fig. 1. A lossless twoport may only contain inductors, capacitors, and ideal transformers. The filters allow a band of the input frequencies to
pass with only a small attenuation while all remaining fre-

R1

V0

I1

V1

I2

Lossless
two-port

V2

Figure 1. Lossless two-port embedded in resistances R1 and R2.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

R2

FILTER SYNTHESIS

quencies are to a large extent suppressed. The transfer function

V2 ( p)
= F ( p)
V0 ( p)

|F *( j )|2

(1)

q2

also called the transfer voltage ratio or the insertion voltage

gain, is a function of the complex frequency p, where p j
stands for the natural and measurable angular frequencies .
For brevity will from now on be called simply the frequency.
From F*( j) A()ej() are derived the magnitude A()
F*( j) and the phase () arg F*( j) with the group delay
() d()/d. The attenuation function is a() 20
logF*( j) in dB (decibels) or, more seldom, lnF( j) in Np
(nepers). The relation is 1 Np 8.686 dB.
The synthesis of filters follows a well-established pattern.
First the properties of a transfer function F*(p) of a two-port
with given types of components have to be established. This
guarantees the existence of a solution with realizable positive
values of the components as long as the desired transfer function exhibits the before-mentioned properties. The most common types of components for classical filters are lossless inductors and capacitors, as well as ideal transformers for the
two-port and resistances R1 and R2 as internal resistance of
the source and as the terminating load. This case is treated
in this article. Other types of components are switches such
as FETs, capacitors, and operational amplifiers in so-called
switched capacitor filters or delays, adders and multipliers in
digital filters or resistors, capacitors and operational amplifiers in RC-active filters, or electro-mechanical transducers and
a set of electrodes in surface acoustic wave (SAW) filters
which are treated in the last section.
The next step in filter synthesis is the approximation of
given specifications for a particular filter by functions meeting
the requirements of F*(p). The last step is the calculation of
the values of the components by mathematical means from
the functions approximating the specifications. This step also
provides the topology of the two-port. For approximations it is
mathematically easier to handle the square of the magnitude
F*( j)2. For a lossless two-port in Fig. 1 F*(p) has the following properties (1,2):

q3
2

1. F*(p) is a rational function in p, real valued for realvalued p; as a consequence, the coefficients in F*(p) are
real valued if the numerator and the denominator of
F*(p) do not contain a common complex factor.
2. Stability requires the poles of F*(p) to lie in Re p 0
and the degree of the numerator not to exceed the degree of the denominator. The denominator is hence a
Hurwitz polynomial.
3. The numerator is either an even or an odd polynomial
in p if common factors in the numerator and the denominator are not cancelled.
4. The maximum power available at the output reveals the
upper bound (Feldtkeller condition).

|F ( j)|

1
2

1
R2
=
R1
q

*c

Figure 2. Low-pass with cutoff frequency c, 3 dB cutoff frequency

*c , and the equiripple between q2 and q2 a2.

can also be expressed by the reflection coefficient introduced

by S. Darlington (3)
S11 ( j) =

R1 Z1 ( j)
R1 + Z1 ( j)

(3)

as
|F ( j)|2 =

R2
(1 |S11 ( j)|2 )
4R1

(4)

where Z1( j) represents the input impedance of the two-port

loaded by R2. S11 is an element of the scattering matrix. Instead of transfer functions the inverse of the transfer function V0 /V2 or V0 /2V2 is also applied. These functions are also
called the insertion voltage loss. In this article
V0 ( p)
= K ( p)
V2 ( p)

(5)

will be used.
The insertion loss (4),
20 log

R2
R1 + R2



 V0 ( j) 
P0


 V ( j)  = 10 log P
2
2

(6)

is based on the ratio between the power P0 V0( j)2R2 /

(R1 R2)2 dissipated in R2 without the two-port inserted in
between the source V0 with R1 and the load R2 and the power
P2 V2( j)2 /R2 dissipated in R2 in the presence of the twoport.
Figures 2 through 5 depict examples for F*( j)2 of characteristic filters, such as a low-pass, a high-pass, a bandpass,

|F *( j )|2
a

a
2

(2)

A given F*(p) meeting these requirements is always realizable by a lossless two-port embedded in R1 and R2. F*( j)2

501

*c
Figure 3. High-pass filter.

502

FILTER SYNTHESIS

Series parallel resonator with

resonant frequency 1

|F * ( j )|2

R1

V0

V1

R2
V2

Figure 4. Bandpass filter.

and a bandstop. The beginning and the end of the passband

are defined by a cutoff frequency c or *c . For the low-pass in
Fig. 2, *c is chosen as the frequency, where F*( j)2 has decreased to 1/2 of the value at 0 (3 dB frequency).
Another choice is a specific frequency c. For example, in
Fig. 2 F*( j)2 leaves the band of equiripple behavior, later
also called Chebyshev behavior.
A typical example for a low-pass circuit is shown in Fig. 6.
The zeros of F*(p) that generate a zero output voltage are
visible in the circuit diagram. The series parallel resonator
exhibits an infinite impedance at the resonant frequency 1,
preventing signals from reaching the output. The same is true
for the shunt series resonator exhibiting a zero impedance at
the resonant frequency 2. Finally, a zero output is observed
at because the shunt capacitors have a zero impedance
and the series inductor exhibits an infinite impedance. Nonideal resonators represent a resistor R at the resonant frequency. The larger the quality factor Q of a resonator is, the
better the transmission zero is realized. For series resonators
Q Z/R, whereas for parallel resonators Q R/Z with Z
L/C. L stands for the value of the inductor and C for the
value of the capacitor. F*( j) const. means a lack of amplitude distortion; together with an arbitrary phase () it defines an allpass, the transfer function of which is

Shunt series resonator

with resonant
frequency 2
Figure 6. Example of a lowpass circuit.

and a linear phase t0 is called an ideal low-pass, which

works as a delay line with delay t0 for frequencies in the
passband.
A filter cascaded by an amplitude equalizer exhibits an
overall transfer function with an approximately constant
magnitude, whereas a phase equalizer in cascade provides a
linear phase of the overall two-port (4). The phase equalizer
is an allpass.
If all reactances in a two-port are discharged at time t 0,
then F*(p) is the Laplace transform of the impulse response
h(t) with
1
2 j

h(t) =

+ j
j

F (p)e pt d p

where F*(p) is an analytical function in Re p 0 . The

step response is


a(t) =

h( )d
0

r(p)
F (p) = k
r(p)

where r(p) is a Hurwitz polynomial in p and k a constant.

F*(p) with a linear phase () t0 reflecting in a constant
group delay t0 and with an arbitrary magnitude belongs to a
two-port without phase distortion. F*(p) with a constant nonzero magnitude in [0, C], zero magnitude otherwise,

Some lowpasses with specific characteristics are discussed

together with amplitude and phase equalizers in the following subsections.
Guidelines will be presented on how to determine from filter tables the component values of a filter meeting given specifications. This should enable a system engineer to achieve a
quick filter design by selecting the appropriate type of filter
and by then finding the component values in a table.
Butterworth Low-passes

|F *( j )|2

Figure 5. Bandstop filter.

A Butterworth lowpass (9) in Fig. 7 exhibits a maximum flat

magnitude F*( j) at 0that is, d F*( j)/d 0 for
1, 2, n, where n is the degree of F*(p). The decay of
the magnitude is moderately steep in the transition region
and approaches n 20 dB per frequency decade for large values of . K*(p) 1/F*(p) is a polynomial.
We investigate the step response a(t) for various lowpasses, including the Butterworth low-pass. To compare a(t)
for those lowpasses, we normalize all of them with the frequency c, where F*( jc) 0.9 F*(0) holds. For low-passes
with equiripple behavior, c also stands for the end of the

FILTER SYNTHESIS

503

Table 1(a). Overshoot and Rise Time of Butterworth Lowpasses with F *( p) of Degree n 1 to 7.

|F *( j )|2
F *2(0)

F *2(0)
2

*c

Figure 7. A Butterworth low-pass, maximally flat at 0.

equiripple band. The normalized time is ct. Figure 8

shows a()/a() for a Butterworth low-pass with F*(p) of seventh degree (10). There is an overshoot of 15.4% over the
value a(), the largest of the low-passes compared, but followed by rapidly decreasing oscillations around the value
a(). Values for the overshoot in % and for the rise time in
from 10 to 90% of a() are listed in Table 1(a) for Butterworth
low-passes with F*(p) of degree 1 to 7. For a Butterworth lowpass with F*(p) of 7th degree the rise time is t 2.511
c , the
2nd smallest rise time of all low-passes in Table 1(e).
Thomson Low-passes
Thomson low-passes (11) are given by K*(p) 1/F*(p) representing a modified Bessel polynomial. They are therefore often also called Bessel low-passes. F*(p) exhibits a maximum
flat group delay t0 at 0. The decay of the magnitude is
moderately steep in the transition region and for a large is
again n 20 dB/decade, where n is the degree of F*(p). The
step response a()/a() for the Thomson low-pass with n 7
is plotted in Fig. 8 (10). It is a remarkably good approximation of an undistorted delayed step. The overshoot is only
0.49% over a(). Oscillations around a() are only marginal.

Overshoot, In %

Rise Time, 10 To 90%,

In

1
2
3
4
5
6
7

0
4.32
8.15
10.83
12.78
14.25
15.41

1.06
1.50
1.80
2.03
2.22
2.38
2.51

Normalizing frequency c is given by F *(ic) 0.9 F *(0) leading to the

normalized time ct.

Table 1(b) contains values for overshoot and rise time of a()
for n 1 to 7 (10). The rise time for n 7 is according to
Table 1(e) t 1.221
c , the smallest value of all low-passes
listed in Table 1(e).
Chebyshev Low-passes
Chebyshev low-passes (Fig. 2) possess a magnitude oscillating
between two constant boundaries in the passband, where
each extremum touches the boundaries. This is called an
equiripple, or a Chebyshev behavior in the passband. K*(p)
1/F*(p) is a polynomial. The larger the ripple a2 in Fig. 2
the steeper is the decay of F*( j)2 in the transition region
from the passband into the stopband. From all polynomials
this decay is steepest. However, independent of a2 the decay
at large s is again n 20 dB/decade. The step response
a()/a() for n 7 in Fig. 8 (10) exhibits the third largest
overshoot over a(); however, the oscillations around a() decay rather rapidly. According to Table 1(e) the value for the
overshoot is 12.7%, whereas the rise time is t 3.41
c , the
2nd largest value in Table 1(e). Overshoot and rise time of
a() for n 1 to 7 are listed in Table 1(c) (10).
Cauer Filters as Low-passes
Elliptic filters or Cauer filters (12) (Fig. 9) are low-passes exhibiting an equiripple behavior both in the passband and in
the stopband. They arebased on elliptic integrals which is
why they are also called elliptic filters. K*(p) 1/F*(p) is a
rational function in p. The step response of the Cauer lowpasses for n 7 in Fig. 8 exhibits the second largest overshoot and only slowly decaying oscillations around a() (10).
Overshoot and rise time for n 1 to 7 are listed in Table

a( )
a()
1.2
1.0
0.8
Butterworth
0.6

Table 1(b). Overshoot and Rise Time of Thomson Low-passes

with F *( p) of Degree n 1 to 7.

Chebsyshev
Cauer (elliptic)

0.4
Bessel (Thomson)
0.2
0.0
0

10

20

30

40

50

= t c

Figure 8. Step responses a()/a() of various filters with transfer

functions F*(p) of seventh degree. The common characteristics of the
filters are provided in the caption and footnote of Table 1(a).

Overshoot, In %

Rise Time, 10 To 90%,

In

1
2
3
4
5
6
7

0
0.43
0.75
0.84
0.77
0.64
0.49

1.06
1.21
1.25
1.25
1.24
1.23
1.22

Normalization as in Table 1(a).

504

FILTER SYNTHESIS
Table 1(d). Overshoot and Rise Time of Cauer Low-passes
with F *( p) of Degree n 1 to 7.

Table 1(c). Overshoot and Rise Time of Chebyshev Lowpasses with F *( p) of Degree n 1 to 7.
n

Overshoot, in %

Rise Time, 10 to 90%,

in

Overshoot, in %

Rise Time, 10 to 90%,

in

1
2
3
4
5
6
7

0
14.0
6.82
21.2
10.7
24.25
12.68

1.06
1.59
2.36
2.45
2.98
2.95
3.40

1
2
3
4
5
6
7

0
14.0
7.10
22.2
12.2
25.9
13.72

1.06
1.59
2.38
2.57
3.23
3.31
3.81

Normalization as in Table 1(a); in addition, minimum attenuation in stopband

60 dB.

Normalization as in Table 1(a).

1(d) (10). In addition to the properties of the normalization

mentioned previously for Butterworth low-passes, the minimum stopband attenuation of the Cauer filters is chosen to
be 60 dB.
Table 1(e) shows a comparison of overshoot and rise time
of the step response for four filter types with F*(p) of degree 7.
Further filters such as bandpasses, high-passes, bandstops, or filters with several passbands are obtained by a frequency transformation applied to the low-pass, where the frequency characteristics are preserved.
Design of Filters by Using Filter Tables
There are three characteristic low-passes tabulated to choose
from for a given task. They are the Butterworth, the Chebyshev, and the Cauer low-pass, the features of which have been
discussed above. The Bessel low-pass is, as a rule, not contained in tables as it main deals with properties in the time
domain.
After the selection of the appropriate type of low-pass the
designer turns to the pertinent filter tables. As a rule only
solutions for the special case R1 R2 are tabulated. If this is
not acceptable because an additional amplifier may be required one has to go through the general design procedure as
described in the next paragraph. The general procedure is
also mandatory if different types of specifications are given,
such as steps in the attenuation in the stopband or the suppression of specific pilot frequencies.
As shown in Fig. 12, the filter requirements are given by
four values for the attenuation a() 20 logF*( j) in dB,
where
=

(7a)

is the normalized frequency. Those four values in dB are A0

the minimum attenuation in the passband, Amax the maximum
attenuation in the passband, Amin the minimum attenuation
in the stopband, and the frequency s defining the end of the
transition region with a(s) Amin. For R1 R2 we obtain
A0 0 as a special case. This reduces the number of specifications to three.
First the reflection coefficient 1 100.1Amax has to be
calculated. A table with Amin 10 log(2 1) as ordinate and
s as abcissa reveals the required degree n for a given s , ,
Amin , and filter type. Then one turns to tables for the chosen
type of low-pass, the degree n and the value which provide
the normalized values of the components.
The normalized values and c of the reactances provided
by the tables are with a normalizing resistor R1
c L
L
=
=
R1
c R1

(7b)

and
CR1 =

cCR1 =  c
c

(7c)

where
=

c L
R1

(8a)

and
c = cCR1

(8b)

and c are values without dimension.

|F *( j )|2

Table 1(e). Comparison of Overshoot and Rise Time of the

Step Response for Four Low-passes with F *( p) of Degree 7.
Low-Pass Type

Figure 9. A Cauer low-pass (elliptic filter) with equiripple in passband and stopband; s is end of transition region.

Overshoot, in %

Rise Time, 10 to 90%,

in

0.49
15.4
12.7
13.7

1.22
2.51
3.40
3.81

Thomson
Butterworth
Chebyshev
Cauer
Normalization as in Table 1(a).

FILTER SYNTHESIS

The denormalized values are, for the inductors

L=

505

R1
l
c

and for the capacitors

C=

1
c
c R1

This concludes the design with the help of a table.

Equalization of Amplitude and Phase
In systems the need can arise to change the amplitude, that
is the attenuation a(), most often to render it constant in a
given range of frequencies. A simple solution is to replace the
resistance R2 at the output by a two-port with input resistance R R2, but a frequency-dependent inverse transfer
function K*B (p) and the associated attenuation a() 10
logK*B ( j)2. K*B (p) is multiplied with the inverse transfer
function of the given two-port, whereas a() is added to its
attenuation. Such an amplitude equalizer is shown in Fig. 38
with the design equation in the figure caption. If several of
those equalizers have to be cascaded it is easily done by replacing the loading resistance R R2 of the first equalizer by
the next equalizer and so on. Table 5 shows a() for various
equalizer two-ports. The shapes of a() are chosen such that
they add to the attenuation to be equalized at the frequencies
where this is needed. The equalizers however also change the
phase of the entire two-port which is tolerable for all filters
where phase is not important, such as in audio systems.
The correction of the phase or the group delay of a given
two-port is done by cascading phase equalizers at the output
of the given two-port. They are allpasses as depicted in Fig.
40. The phase equalizers exhibit an input resistance R R2
if terminated by R2 thus replacing the load R2 of the given
two-port. The design equations are given in the caption of Fig.
40. The equalizers further offer a unit magnitude that is an
attenuation a() 0 and a group delay as shown in Figs.
39(a) and 39(b). By cascading two-ports the transfer functions
are multiplied and hence the phases in the exponent of the
exponential functions are added. This also applies to the
group delay. The attenuation of the given two-port remains
unchanged due to a() 0 of the allpasses. Figs. 39(a) and
39(b) reveal how the allpasses must be chosen to add to the
group delay at those frequencies where an increase is needed.
Most often the group delay has to become constant by a
phase equalization.
So far we have dealt with two-ports. There are also m-nports with n input ports and m output ports. They can realize
filter banks.
THE SYNTHESIS OF FILTERS
To obtain general results for low-passes independent of the
values of the cutoff frequencies c, we introduce a normalized
frequency /c pertaining to the s-plane with the imaginary axis s j. This translates K*(p) in Eq. (5) in which
p j as follows:



V0
= K ( j) = K j c = K ( jc ) = K( j)
V2
c

1 x

1
1
(a)

Tm (x)

m=4

m=5

1
(b)
Figure 10. (a) A Chebyshev polynomial y(x). (b) The Chebyshev polynomial of fourth and fifth degree m.

and hence
V0
= K (p) = K(s)
V2
The synthesis follows the steps as listed and explained here:
1. The given tolerance scheme for K( j)2 P() is approximated by a realizable
|K( j)|2 q2 = 4

R1
R2

(9)

with q in Eq. (2).

2. From K( j)2 the function K(s), the characteristic function f(s); and the elements of the chain matrix A(s) are
determined.
3. A(s) is realized by a lossless two-port by a pole removal
process.
Calculations For The Individual Steps
The approximation and calculation may be performed by a
general approach based on a least square procedure. However, as a rule, special functions with suitable properties are
chosen to solve the approximation problem. These functions

506

FILTER SYNTHESIS

where c is the integration constant. For c 0 we obtain

|K( j )|2
q 2+e2

Tm (x) = y = cos m

(11a)

= arccos x for |x| 1

(11b)

Tm (x) = y = cosh m

(12a)

= arcosh x for |x| 1

(12b)

and

q2

and

2
Tm
( )

Tm ( )

and

The known trigonometric equality

1

cos(m + 1) = cos m cos sin m sin = cos m cos

Figure 11. The square of the magnitude K( j)2 of a Chebyshev lowpass with K( j)2 e2T 2m() q2.

will be discussed. Finally, a general approximation procedure

based on a conformal mapping will be outlined.
The Chebyshev Approximation and the Calculation of K(s). The
square K( j)2 of the magnitude of the function K( j) according to the Chebyshev approximation is plotted in Fig. 11.
In the passband K( j)2 completely exhausts the tolerance
stripe; that is, each extremum of K( j)2 touches the limit of
the tolerance band from the inside. In the stopband K( j)2
tends to infinity. As these filter characteristics are most
widely used, more detailed information on the Chebyshev approximation must be given. The differential equation for a
Chebyshev polynomial y(x) is

m2 (1 y2 ) =

dy
dx

dy 2
dx

cos(m + 1) = 2 cos m cos cos(m 1)

or the recursion for Tm1(x):
Tm+1 (x) = 2Tm (x) x Tm1 (x)

(13)

The starting solutions for m 0 and m 1 are provided

by Eqs. (11a) and (11b) as T0(x) 1 and T1(x) x. Some polynomials Tm(x) for m 2, 3, . . . 11 obtained from Eq. (13) are
listed in Table 2 and plotted for m 4 and m 5 in Fig.
10(b). Even m provide even and odd m odd polynomials
Tm(x). The coefficient at the leading term xm is 2m1.
We first construct the function V0 /V2 K(s) from a given
K( j)2. K( j)2 P() in Fig. 11 is expressed by
|K( j)|2 =  2 Tm2 () + q2 = P()

(10a)

(14)

For 1 we obtain with the coefficient 2m1 of the leading

term

or
m2 ( y2 1) =

yields

2
(1 x2 )

1
(cos(m 1) cos(m + 1) )
2

(x2 1)

|K( j)|2  2 22(m1)2m

(10b)

where m is a constant. The differential equation equates the

zeros in Fig. 10(a) of y 1 and y 1 with the zeros of
y2 and x 1 as well as x 1 . The statement

and
a() = 10 log |K( j)|2 20[m log  + (m 1) log 2 + log ]
(16)

x = cos and y = cos

Table 2. Chebyshev Polynomials of Degree 2 to 11.

provides the solution

y = cos(m + c) with = arccos x for |x| 1
whereas the statement
x = cosh and y = cosh
yields the solution
y = cosh(m + c) with = arcosh x for |x| 1

(15)

T2(x)
T3(x)
T4(x)
T5(x)
T6(x)
T7(x)
T8(x)
T9(x)
T10(x)
T11(x)

2x2 1
4x3 3x
8x4 8x2 1
16x5 20x3 5x
32x6 48x4 18x2 1
64x7 112x5 56x3 7x
128x8 256x6 160x4 32x2 1
256x9 576x7 432x5 120x3 9x
512x10 1280x8 1120x6 400x4 50x2 1
1024x11 2816x9 2816x7 1232x5 220x3 11x

FILTER SYNTHESIS

507

;; ;;
;
;; ;;;
;;

for s j and extend s into the entire complex plane. On the

other hand, as K(s) is real for real s, we obtain

a()

|K( j)|2 = K( j)K( j) = K( j)K( j) = K(s)K(s) (21)

A min

for s j, which is also extended into the s-plane. Equations

(20) and (21) hence provide
K(s)K(s) = Q(s)

(22a)

A max

A0

1 s

Figure 12. The tolerance scheme in decibels for a Chebyshev

low-pass.

This reveals that for a small ripple 1, log 0 decreases

the rise of the attenuation for large and for a large ripple
1, log 0 increases the rise of the attenuation for large
. The increase of a() for a decade 10 is a() 20 m;
that is, 20 dB per decade and per degree m of Tm(). The
attenuation a() belonging to Fig. 11 is depicted in Fig. 12
with minimum (respectively maximum) attenuation A0 (respectively, Amax) in the passband and the minimum attenuation Amin in the stopband. The upper limit of the transition
region is s. Chebyshev filters represent the rare case in
which all characteristic values q, , and m in Eq. (14) can be
determined from the given values A0, Amax, and Amin at s by
the equations

10 log q2 = A0
(17)

and hence
q2 = 10A 0 /10

Q(s) = q2 +  2 Tm2

s
j

=0

(22b)

or
Tm2

 
 q 2
s
=
j


As the zeros are complex, we form

 
s
= cos m = cos m(1 + j2 )
Tm
j

(23)

and

s
= cos
j
(24)

from which follows

 
q
s
= cos m1 cosh m2 j sin m1 sinh m2 = j
Tm
j

(25)
The solutions are

10 log(q2 +  2 ) = Amax
(18)

and hence

Obviously, Q(s) is even in s, and real for real s. Hence the

zeros occur at s si and s si as well as at s si and s
si, as plotted in Fig. 13. For q 0, zeros on s j are
feasible and have an even multiplicity. The zeros in Re s 0
and half the multiplicity of the zeros on s j are assigned
to K(s), thus forming a stable or at least quasi-stable K(s) if
the zeros on s j are single. We perform these operations
on K( j)2 in Eq. (14) starting from P() and Q(s) in Eqs. (20)
and (22b), which yields

cos m1 cosh m2 = 0
sin m1 sinh m2 =

 2 = 10A max /10 10A 0 /10

q


and
j Im s

a(s ) = 10 log(q2 +  2 cosh m arcosh s ) = Amin

Zeros assigned to K(s)

and hence


1
10A min /10 10A 0 /10
m=
arcosh 
arcosh s
10A max /10 10A 0 /10

(19)

In Eq. (19) the expression for Tm() for 1 was used.

The general synthesis procedure outlined next was established by W. Bader (1,16a,16b). It is explained with Chebyshev low-passes as an example.
From the known K( j)2 we have to calculate the rational
function K(s). We consider
 
s
= Q(s)
(20)
|K( j)|2 = P() = P
j

si

sk

si

si

sk

Re s

s i

Figure 13. Zeros of Q(s) K(s)K(s) in Eq. (22a).

508

FILTER SYNTHESIS

Determination of the Chain Matrix A and of f(s). The chain

matrix of the lossless two-port in Fig. 1 is

Zeros assigned to K(s)

cosh 2
Zeros of f (s) f (s)

A11
A21

A=

A12
A22

!
(29)

with

V1
I1

sinh 2

or
2v + 1
m 2

= 0, 1, 2 . . . 2m 1

V
=A 2
I2

!
(30)

Necessary and sufficient conditions for a realizable LC chain

matrix are as follows (17):

Figure 14. Zeros of K(s)K(s) and f(s)f(s) for Chebyshev filters

with m 3.

1 =

(26a)

1. The four elements of A are rational in s and real for

real s. A11 and A22 are even, and A12, A21 are odd functions of s.
2. det A 1.
3. At least three ratios of horizontally or vertically adjoining elements are LC driving point impedances. For
A12 0 or A21 0 or A12, A21 0, the elements A11 and
A22 are constants reciprocal to each other.
K(s) can be expressed as


 q 2
V
A
K(s) = 0 = A11 + 12 +
(R2 A21 + A22 )
V2
R2
2

with q = 2

and
2 =

q
1
arsinh
m


(26b)

A11 +

sinh 2

cosh 2

= sin 1 + cos 1 = 1
2

m


(s si )

1
(K(s) f (s))
2

(32b)

(A22 + R2 A21 ) =

According to condition 1, A11 respectively, (q/2)2A22 are the

even parts of 1/2 (K(s) f(s))respectively, 1/2 (K(s)
f(s)). A12 /R2 respectively, (q/2)2 R2A21 are the odd parts of
1/2 (K(s) f(s))respectively, 1/2 (K(s) f(s)). This provides

(28a)

i=1

or

1
F (s) =
m

 2m1
(s si )

(32a)

(27)

The zeros obviously lie on an ellipse, as shown for m 3 in

Fig. 14. Finally,
K(s) =  2m1

A12
1
= (K(s) + f (s))
R2
2

and

q 2
2

(31)

(26c)

This finally provides

2

R1
R2

The term q is explained in Eq. (2). With an unknown characteristic function f(s), we obtain

The location of the zeros is, with Eq. (24), s j cos j

cos(1 j2) or
s = sin 1 sinh 2 + j cos 1 cosh 2 = + j

 q 2
(28b)

i1

represents the solution for the desired K(s) and F(s) with the
m zeros of Eq. (22b) and the coefficient of the leading term
stemming from the Chebyshev polynomial in Eqs. (14) and
(15).

2
 q 2
2

1
(K(s) +
4
1
= (K(s) +
4
1
= (K(s)
4
1
= (K(s)
4

A11 =

f (s) + K(s) + f (s))

(33a)

A12
R2

f (s) K(s) f (s))

(33b)

f (s) + K(s) f (s))

(33c)

f (s) K(s) + f (s))

(33d)

A22

R2 A21

From det A 1, we derive

A11

 q 2
2

A22

 q 2
A12  q 2
R2 A21 =
R2 2
2

FILTER SYNTHESIS

or, with Eqs. (33a) through (33d),


with q = 2 R1 /R2

K(s)K(s) q2 = f (s) f (s),

(34)

As K(s) and q2 are known, f(s) can be determined by the same

consideration as applied for finding K(s). The product
f(s)f(s) is even; its zeros are assigned in complex conjugate
pairs, if complex, to f(s) and the location with the opposite
sign to f(s). The constraint of stability, mandatory for K(s),
does not apply for f(s) as f(s) is no insertion voltage loss.
For Chebyshev filters we obtain, from Eqs. (22a), (22b),
and (34),
 
s
=0
(35)
f (s) f (s) =  2 Tm2
j
The zeros can be derived from Eqs. (23), (26a), and (26b) for
q/ 0, yielding
1 =

2 + 1
m 2

(36a)

and
2 = 0

(36b)

with the zeros in Eq. (26c) as

2 + 1
m 2
= 0, 1 . . . 2m 1 and hence k = 1, 2 . . . 2m

sk = j cos 1 = j cos

(37a)

These zeros on the imaginary axis are double as demonstrated in Fig. 14 for m 3.
Finally, from Eq. (35) we obtain
f (s) =  2m1

m


(s sk )

k=1

where sk are half the zeros in Eq. (35) and where a single zero
is taken from each location.
Now the elements Aik of the chain matrix can be calculated
using Eqs. (33a) through (33d). There are four possibilities to
calculate A depending on the selection of the signs for K(s)
and f(s).

509

Development of an LC Two-Port. Starting with a chain matrix A with known elements Aik, the steps leading to an LC
two-port embedded in the resistances R1 and R2 in Fig. 1 will
be given and explained. The basic concept is the development
of an LC reactance function into an LC circuit in such a way
that the poles of K(s) are realized. The poles of K(s) in Eq.
(31) are the zeros of the denominator and the n m poles at
s that occur if the degree n of the numerator exceeds the
degree m of the denominator, manifested by n m 0. For
an all-pole filter, K(s) is a polynomial where all poles lie at
s . The Chebyshev filter is an example of an all-pole filter
as well as the Butterworth filter or the Thomson filter, which
are treated later.
The development of A into an LC two-port starts with the
selection of an element AikL with the largest degree in s. If
there is more than one such element any one may be chosen,
yielding different solutions with the same inverse transfer
function K(s). Then we form the ratio D AikL /AikN or the inverse D AikN /AikL, where AikN is the element horizontally or
vertically next to AikL. The ratios are LC two-terminal functions. There are four possibilities to form them depending on
the selection of the neighbor to AikL. Together with the four
possible chain matrices, we are at this point already faced
with at least 16 possible LC one-ports, with every one ensuring an equivalent solution.
The ratios may represent either an input or an output driving point impedance function with a short circuit or an open
circuit at the receiving end. The short circuit or the open circuit is later replaced either by the load R2 or the input voltage V0 with the resistance R1 depending on the physical
meaning of the two-terminal function.
The development of the LC driving point impedance function is based on a modified continued fraction expansion
(16a,16b) with partial pole removals (1820) only allowed at
poles of K(s) and preferably at those poles of K(s) at s or
s 0. The process is explained by the pole-zero plot in Fig.
15. The headline shows the poles of K(s) to be realized. A full
circle or cross mark stands for the two zeros or the two
poles at s j and for the associated degree 2 in s, whereas
a half circle or a half cross mark stands for the degree 1
in s. We assume that Y in the second line is the admittance
D we have chosen from the chain matrix. The partial fraction
to the pole at s 0 is a0 /s. We remove part of this pole by
subtracting a1 /s with a1 a0. It can be shown (16a,16b) that

j 0
0
Y

j 1

Poles of K (s)
Pole-zero plot of D
Partial removal of poles at s = 0

Y
Z

Remaining part of D
The inverse of line above
Full removal of poles at s = j 0

Z
Y

Remaining part of D
The inverse of line above
Full removal of poles at s = 0

Y 0 as remaining part of D

Figure 15. Pole-zero plot of D with admittances Y

and impedances Z during partial and full removal
of poles.

510

FILTER SYNTHESIS

Full pole removal at s = j 0

2

L1

L2

C1

L3

R2

C2

V1

Figure 16. LC two-port generated by the development in Fig. 15.

by doing this all zeros beside the one at s move toward

the pole partially removed. a1 is chosen such that the zero at
s j1 moves to s j0. a1 /s is realized by the first inductor
in Fig. 16. A proof that there is always an 0 a1 a0 able to
generate the desired zero is missing. Now the admittance Y
is inversed, and the pole of the impedance Z at s j0 is fully
removed () and realized by the series parallel resonator in
Fig. 16. The two-port shall exhibit a transmission zero at s
j0 because the infinite impedance of the series parallel resonator prevents energy from being delivered into the resistor
R2, which hence exhibits a zero voltage at frequency 0. The
same is true for a shunt zero impedance. It is even true for a
series infinite impedance or a shunt zero impedance, which
are generated by a partial pole removal, because these impedances block the energy transfer to the output resistance R2.
This imposes the constraint that a partial pole removal is only
allowed at poles of K(s).
The partial removal of a pole does not lower the degree
of the driving point function. As a consequence, the two-port
generated does not exhibit the minimum number of compo-

V *2

Full pole
removal
at s = 0

Partial pole
removal
at s = 0

Poles of K(s), multiplicity 5

nents. To minimize the number of components, partial pole

removal preferably should take place at s 0 or s , as it
is there associated with only one reactance.
So far, the procedure for rational functions D has been described. The function K(s) of Chebyshev filters in Eq. (28a) is
a polynomial where all poles lie at s . The development of
the LC two-port is a special case plotted in Figs. 17 and 18
(16c). We start with an impedance, the pole of which at s
is fully removed, realizing a pole of K(s) at s by the
inductor L1 in Fig. 18. The full pole removal in the admittance
of the next step provides the shunt capacitor C1 realizing another pole at s . The process continues in Figs. 17 and 18
(16c) until all poles are realized by three inductors and two
capacitors. Since for the Chebyshev filter only full pole removals were used, the circuit generated exhibits the minimum
number of components.
So far, from the given matrix A in Eq. (29), the matrix A*
in Eq. (37b)
A =

A T=

A12
A22

kA11
kA21

(37b)

is realized if we assume that the driving point function D was

selected as D A11 /A21. In D a common constant factor k may
have been canceled. The physical meaning of A11 is A11
V1 /V2 for I2 0 and of A*11 kA11 V1 /V*2 for I*2 0, where
V*2 (respectively, I*2 ) are the output voltage (respectively, current) in Fig. 19 at the LC-two-port A* so far realized. The
terms are evaluated at an arbitrarily chosen frequency,
where s0 0 or s0 are especially easy to handle. The
result is k A*11(s0)/A11(s0). The correction for k 1 is achieved
by an ideal transformer in Fig. 19 with matrix T in cascade
with A* providing

L1

C1

V2

Figure 18. An LC two-port if K(s) is a polynomial.

1:k

kA11
kA21

A12
A22

 1
k
0



0
k

kA12
kA22

A11
A21

(37c)

We claim that with this last step the given matrix A is realized. For proof we consider for the matrices A and A*T the
equations
det A = A11A22 A12A21 = 1

L2
Z
Y

I *2

R1

C2

1:k

I2

Y
Z
L3

V0

V1

A*

V *2

V2

R2

Figure 17. Always in full pole removal if K(s) is a polynomial in

s; Y admittances, Z impedances.

Figure 19. The intermediate steps A*, the ideal transformer, and
the embedding in R1 and R2 during the synthesis of two-ports.

FILTER SYNTHESIS

511

and
det A T = A11kA22 kA12A21 = 1
The poles of K(s) are given by the denominators of the elements Aik according to Eq. (31). They are already realized by
the synthesis procedure and are equal in A and A*. Therefore,
we now concentrate on the numerators of Aik. We assume
that A11 has the highest degree in s. At the n zeros of A11 we
obtain A12 1/A21 and kA*12 1/A21. That means that the
numerators of A12 and kA*12 of degree n are identical at n
points; hence they are identical for all s. The same applies to
A22 and kA*22. Therefore, A*T A, as desired.
Some remarks about the procedure for synthesizing an
LC two-port are necessary:
1. As mentioned previously, a proof has not yet been found
that partial pole removal with positive value of the components is always feasible. However, so far there has
always been a realizable two-port among all the alternatives for equivalent solutions.
2. If in each element in A the common factors are canceled, then it can be proved that horizontally or vertically adjoining elements exhibit no common zeros. However, for some developments it is necessary to represent
all elements with one single common denominator.
Then common zeros of adjoining elements may occur.
They are also zeros of K(s) and are realized by a partial
fraction expansion. The pertinent circuits are added in
series of an open circuit reactance function and in the
shunt of a short circuit reactance function D. This brief
remark may suffice.
3. The alternative solutions can differ in the number of
inductors and capacitors. Hence a search for a circuit
with the minimum number of inductors is worthwhile
because capacitors are, as a rule, less costly.

Figure 20. Equivalent circuit of a quartz oscillator.

behavior in the passband [Fig. 22(b)], and a low-pass with

Chebyshev behavior in the stopband [Fig. 22(c)] can be
generated.
The Butterworth Approximation (9). Contrary to the Chebyshev approximation, the normalizing frequency usually

1
2
Tm
c

( )

1
(a)

2
Tm

4. Developments with capacitors connected to a common

terminal, such as ground, are advantageous since parasitic capacitances can be included in these capacitors.

( )
c

5. Tuning of the transmission zeros can be carried out by

adjusting one element, preferably the capacitor, in the
series or parallel resonators.
6. The procedure can be used to generate specific one-ports
such as the equivalent circuit for a quartz oscillator in
Fig. 20.
2
Tm

The general procedure for the synthesis of an LC filter embedded in R1 and R2 from a given K( j)2 was presented with
Chebyshev filters as an example. The procedure shall be applied to all further filters discussed in this article.
Further Filters Derived from Chebyshev Polynomials. In the
previous section a low-pass was derived from the squared
Chebyshev polynomials T m2 (), /c. Further filters are
generated from 1/T m2 (), T m2 (1/), and 1/T m2 (1/). These functions are depicted in Figs. 21(a) through 21(c). In the Figs.
22(a) through 22(c) the pertaining filters and their K(s) are
shown. It can be seen that a highpass with Chebyshev behavior in the stopband [Fig. 22(a)], a highpass with Chebyshev

1
(b)

1
(c)

1
c

( )

Figure 21. (a) The polynomial T 2

m (/c). (b) The polynomial
T 2m(c /). (c) The polynomial T 2
m (c /).

512

FILTER SYNTHESIS

chosen for the Butterworth filters is *c , the 3 dB frequency,

yielding /*c . We again work with the function K( j)
instead of F( j) K( j)1.
The function
|K( j)| = A0 (1 +  ) = P() q = 4R1 /R2
2

2n

q2

1
(a)

K( j) A0n and the attenuation a() 20 log K( j)

20n log 20 log A0, from which an increase in attenuation a for one frequency decade of a n 20 dB/decade can
be seen.
According to Eq. (38), we obtain
 
s
= A0 (1 + (1)n s2n ) = K(s)K(s)
Q(s) = P
(39)
j
The zeros of Q(s) are given by s2n (1)n1 ej(n12k) for k
0, 1, 2, . . ., 2n 1. This yields the zeros

(40)

Obviously, the zeros lie on the unit circle of the complex splane. If they are complex, they have to be complex conjugate,
as Q(s) possesses only real coefficients. For n 4 the zeros
are plotted in Fig. 24. The zeros in Re s 0 are assigned to
K(s), yielding a stable two-port. For n 4 we obtain
 




K(s) = A0 s e j 5 /8 s e j 5 /8 s e j 7 /8 s e j 7 /8
1
(b)

sk = e j 2n (n1+2k)

q2

F( j)

A0

q 2 +e 2

K j
c

1
2 A0

Figure 23. The magnitude F( j) of the transfer function and the

magnitude K( j) of the inverse transfer function for Butterworth
filters.

q 2 +e 2

K j
c

K( j)

2 A0

(38)

exhibits d P()/d 0 for 0 and 1, 2, . . . 2n 1

and is hence maximally flat at 0.
The inequality in Eq. (38) is met for A0 q2. K( j) and
F( j) K( j)1 are plotted in Fig. 23. The 3 dB cutoff frequency is reached at 1. For large 1, we obtain

K j
c

1
A0

or

K(s) = A0 (s4 + 2.613s3 + 3.414s2 + 2.613s + 1)

Zeros to K(s)
j Im s

5
8

+e 2

1
7
8 2

q2

3
8

Zeros to e

7 8

Re s

1
(c)

Figure 22. (a) The highpass with K( j(/c))2 q2 2 T2

m (/c)
and Chebyshev behavior in the stopband. (b) The highpass with
K( j(/c))2 q2 2 T 2m (c /) and Chebyshev behavior in the passband. (c) The lowpass with K( j(/c))2 q2 2 T2
m (c /) and Chebyshev behavior in the stopband.

9
8

11
8

6
4

15
8

5
13
8

Figure 24. The zeros of Q(s) K(s)K(s) in Eq. (39) of Butterworth

filters for n 4.

FILTER SYNTHESIS
Table 3. Polynomials K(s) for Butterworth Filters.

l2, and c in Fig. 25, where the denormalized values L1, L2, and
C are also listed.

K(s)/ A0
s1
s2 2s 1
s3 2s2 2s 1
s4 2.613s3 3.414s2 2.613s 1

n
1
2
3
4

The Thomson or Bessel Approximation (11). A filter with a

linear phase () t0 provides an ideal delay by t0 and exhibits the function

K

Table 3 lists K(s)/ A0 for Butterworth filters with degree n

1 through n 4.
The characteristic polynomial is determined due to Eq. (34)
by
K(s)K(s) q2 = f (s) f (s)

(42)

The zeros are given by


s

2n

= (1)

n1

q2
1
A0

(43)

where k 0, 1, . . . 2n 1 and hence r 1, 2, . . . 2n.

The 2n zeros lie on a circle in the s-plane with radius


1/2n
q2
r0 = 1
A0
and are complex conjugate or real. Any complex conjugate
pair and any real zero can be assigned to f(s), while the negative locations of these zeros belong to f(s). This yields

sinh s = s +

A21 =

2s
;
R2

s4
s2
+
+ ...
2!
4!

(45a)

s5
s3
+
+ ...
3!
5!

(45b)

is an odd function in s.
A theorem states that if the ratio of the even part of a
polynomial over the odd part is an LC driving point function
and if the even and odd parts are coprime, then the sum of
the even and odd parts is Hurwitz. To check the property of
an LC driving point impedance function, we develop the continued fraction based on Eqs. (45a) and (45b).

cosh s
1
1
= +
sinh s
s
1
3
+
s
1
5
+
s
1
7
+ ...
s
2N 1

r=1

A11 = 2s2 + 1;

(44)

is an even function and

n
 
f (s) = A0
(s sr )

With K(s) and f(s) now known, the elements of the chain
matrix are calculated by Eqs. (33a) through (33d), followed by
the development of the matrix into a two-port with the procedure outlined previously. As an example, the solution for the
chain matrix A and for the pertaining two-port is now listed
for n 3, A0 1, and R1 R2:

This normalization with 0 is different from the one used previously for the comparison of a(t). It is commonly used and
emphasizes the delay t0 1/0 as the most important property of Bessel filters.
The group delay d /d t0 is a constant. We have to approximate the filter with constant group delay by a realizable
function K(s). A Taylor series for es is no more Hurwitz from
the fifth-order term on. A realizable solution is provided by
setting K(s) aes a(cosh s sinh s), where
cosh s = 1 +

(n1+2k)
2n

j 0 t 0

K(s) = aes

or

1/2n

q2
sr = 1
ej
A0

= ae

With 0t0 1 and /0 we obtain for s j extended

into the s-plane

(41)

or
A0 (1 + (1)n s2n ) q2 = f (s) f (s)

513

m(s)
n(s)

(46)

+ ...

Since all terms in the infinite continued fraction expansion

are positive, h(s) m(s) n(s) calculated from Eq. (46) trun-

A12 = R2 (2s3 + 2s);

R2

A22 = 2s2 + 1

As all elements are polynomials in s, the pertaining two-port

in Fig. 25 was found by full pole removals and therefore exhibits the minimum number of components.
The solution, based on the normalized frequency
/*c , provides the normalized values for the components l1,

l 1, L 1

l 2, L 2

c, C
V0

R2
V2

l1 = l2 = 1
*
L1 = L2 = R2/ C
c=2
C = 2/ c R2

Figure 25. The Butterworth filter for n 3, A0 1, and R1 R2.

514

FILTER SYNTHESIS

Table 4. A List of Modified Bessel Polynomials B(s) and

Their Factored Form for up to 5.
B0(s)
B1(s)
B2(s)
B3(s)
B4(s)

1
s 1
s2 3s 3
s3 6s2 15s 15 (s 2.322)(s2 3.678s 6.460)
s4 10s3 45s2 105s 105 (s2 5.792s 9.140)
(s2 4.208s 11.488)
B5(s) s5 15s4 105s3 420s2 945s 945
(s 3.647)(s2 6.704s 14.272)(s2 4.679s 18.156)

Cauer Filters (4,12,21). These filters exhibit Chebyshev behavior in the passband and in the stopband, as depicted in
Fig. 26. They are based on elliptic functions as derived by
Cauer and are therefore also called elliptic filters. The theory
of elliptic filters is very involved. A simpler approach based
on the results is given here.
The filter function in Fig. 26 is represented by
|K( j)|2 = q2 +  2 Fn2 ()

(49)

with
cated at (2N 1)/s is Hurwitz. For 2N 1 7, we obtain
from Eq. (46)

Fn () =

s4 + 45s2 + 105
m(s)
=
and K(s) = aC[m(s) + n(s)]
n(s)
10s3 + 105s
= aC(s4 + 10s3 + 45s2 + 105s + 105)
The factor C is needed to render K(0) a, as required by Eq.
(44). In the example C 1/105, m(s) n(s) can be expressed
by modified Bessel polynomials:
 
1
= m(s) + n(s)
(47a)
B (s) = s B
s
with
B

1
s


k=0

( + k)!
( k)! k! (2s)k

(47b)

n/2


2 2

2 ( / )2


s

=1
(n1)/2

2 2

k

2 ( / )2

s

=1

B (s) = (2 1)B 1 (s) + s2

(48)

Table 4 lists the Bessel polynomials up to 5 (4).

The constant a is chosen such that the constraint for
K( j) is met. The characteristic function is determined by
K(s)K(s) q2 f(s)f(s). The LC two-port is then calculated
by the procedure given previously, applied for polynomials.

n odd

(51)

where

K(s) = a B (0)1B (s)

(50)

The equiripple behavior of F n2() in [0, 1] in Fig. 27 is

guaranteed by the choice of according to

 
1

E
(2

1)

n even, = 1, 2, . . . n (52a)

sn
s

n
 =
 

E
n1
2

sn
n odd, = 1, 2, . . .


2
(52b)
n

A recursion formula is given by

B2(s). With Eqs. (47a) and (47b),we finally obtain

n even

1
s

/2

=
0

d

1/2
1
1 2 sin2
s

(53a)

is the complete elliptic integral of the first kind and the Jacobi-elliptic function sn(u) sin is calculated from the
inverse (u) of the incomplete elliptic integral of the first
kind:

d
u=
(53b)


1/2
1
0
1 2 sin2
s

|K( j )|2

q2 +

q2 +

q2

Figure 26. The characteristic K( j)2 of a

Cauer filter for n odd in Eq. (49).

3 1 s s / 3

s / 2

s / 1

FILTER SYNTHESIS

515

Fn2 ( )

1
1

3 1 s s / 3

s / 2

s / 1

followed by forming sin sn(u). s is chosen as s 1; Eqs.

(52a) and (52b) yield 0 1, 1, 2, . . . n/2, or (n
1)/2. Obviously, the zeros of F n2() lie in 1 and the poles
in s. k in Eqs. (50) and (51) is chosen such that F n2()
in Fig. 27 oscillates between 0 and 1 in [0, 1].
Finally, the minimum value B of F n2() in the stopband in
Fig. 27 is given by

B=

n/2


2s 2

s (s / )2
=1
(n1)/2

2s 2

ks
2
s (s / )2
=1

n even

(54a)

n odd

(54b)

if the degree n of Fn() is chosen as

Figure 27. F 2n() for a Cauer filter in Fig. 26 and

in Eqs. (50) and (51).

conformal mapping. This includes also the case of Chebyshev

behavior in the passband and the stopband as a special case.
The procedure is based on the fact that the Hurwitz polynomial
h(s) = m(s) + n(s)

(56)

where m(s) is even and n(s) is odd, provides the reactance

function m(s)/n(s). It can be further shown that the driving
point impedance function

w(s) =

m(s)
m/n
m = m(s) + n(s)
1+
n

(57)

has the property


E(1/s )E( 1 1/B)


E( 1/B)E( 1 (1/s )2 )

|w( j)|2 =

(55)

If the minimum value for n is not an integer, then the next

larger integer has to be chosen. In this case the realized B in
Eqs. (54a) and (54b) is larger than the desired B in Eq. (55).
From Eq. (49) and Fig. 27, we derive

m2 ( j)
j) n2 ( j)

m2 (

[0, 1]

(58)

for [, ]. This shall provide the Chebyshev behavior.

We investigate
f (z2 ) =

m2 (z)
with z = u + jv
m2 (z) n2 (z)

(59)

|K( j1)|2 = q2 +  2
and the transformation
and
z2 = 1 +

|K( js ) = q +  B
2

For the filter design the desired R1 and R2 yield


q=2

R1
,
R2

Approximation of K( j)2 by Conformal Mapping (4). Lowpasses with Chebyshev behavior in the passband and arbitrary characteristics in the stopband can be designed by a

(60)

providing



1
f (z2 ) = f 1 + 2 = g(s2 )
s
*
m

the desired ripple in the passband provides , and the minimum q2 2B of K( j)2 in the stop-band yields B in Eqs.
(54a) and (54b).

1
s2

*
m2

1+

1
s2

1
1+ 2
s
n2

!
(61)
*
1+

1
s2

The properties of the transformation in Eq. (60) are investigated in Figs. 28(a) through 28(e), where the passband s
j with 1, denoted by dashed lines, and the stopband

516

FILTER SYNTHESIS

w1

w2
w1 = s

w2 = 1 = 1
w1
s2

Re s

(a)

(b)

w3

jv

z= + 1 +

w3 = w2 + 1
1
= 1 + 2 = z2
s

 [1, 1] into v [, ]

(62a)

|| 1 into u [0, 1]

(62b)

and

(d)

with 1, denoted by solid lines, are step by step mapped

into the z-plane. The steps from the s-plane to the z-plane in
Fig. 28 are w1 s2, w2 1/w1, w3 w2 1, z w3. The
result is the following mapping:

1
s2
Passband

Figure 28. The steps in the conformal

mapping z 1 1/s2 for s j.

(c)

Stopband

(e)

With these results

g(2 ) =


m2 ( 1 + 1/s2 )


for s = j
m2 ( 1 + 1/s2 ) n2 ( 1 + 1/s2 )

assumes the shape in Fig. 29. The function g(2) oscillates

between 0 and 1 in the passband as long as m(s) is even and
n(s) is odd and h(s) m(s) n(s) is Hurwitz. The selection
of m(s) and n(s) is the freedom for the design of filters.
For the filter we obtain, as in all previous cases,
|K( j)|2 = q2 +  2 g(2 )

The complex conjugate pair of poles in 1 results

in a double pole in u [0, 1]. The consequences of this mapping for f(z2) g(s2) in Eqs. (59) and (61) are as follows: for
z jv, v [, ], and the pertaining [1, 1]:

f (v2 ) = g(2 ) =

m2 (

m2 ( jv)
jv) n2 ( jv)

[0, 1]

g( 2)

(63a)
Passband

for z u, u [0, 1], and the pertaining 1 with the

constraint m(u) n(u) and hence

f (u2 ) = g(2 ) =

Stopband

n2 (u)
1
m2 (u)

m2 (u)
=
n2 (u)

m2 (u)

(64)

1
1
n2 (u)
1 2
m (u)

(63b)

1
2

Figure 29. The function g( ) of Eq. (63a) in the passband and

the stopband.

FILTER SYNTHESIS

with


m ( 1 + 1/s2 )
2
2
2


 g(s ) = 
m2 ( 1 + 1/s2 ) n2 ( 1 + 1/s2 )

20 log coth

517

| i |
2

(65)

or



1 m+n 1 mn
2
1+
+
2
2 mn 2 m+n

 2 g(s2 ) =

The dominant term in the stop-band, especially around the

poles, is
|K( j)|2

 2 m(z) + n(z)
4 m(z) n(z)

r


(z + zi )2

(68)

(z + zi )2

(69)

i=1

and by exchanging z with z

m(z) + n(z) = (z + 1)

r

i=1

The term z zi in Eq. (68) represents the double pole in z

[0, 1], while z 1 stands for the pole of multiplicity at
. The even part in Eq. (69) provides m(z), whereas the odd
part yields n(z). Hence
f (z2 ) = g(s2 ) =

i+1

Figure 30. The templates 20 log cothi /2 for the approximation

of the given characteristics in the stopband.

For zi 1 we obtain

r = 10 log

(70)

z + zi
= 20 log  10 log 4 +
10 log
z
+ zi
i=1
+ 10 log


= 10 log coth

| |
2

1. The given R1, R2 and the ripple in the passband yield q

and .
a. If only discrete pilot frequencies


zi =

1
2i

have to be suppressed, then these zi provide Eq. (68).

2

b. If a tolerance scheme in the stopband has to be met,

templates provide the pole locations zi together with
r and in Eq. (68).

(z + 1)
(z + 1)

3. Form

The substitution

m(z) n(z) = (z + 1)

r


(z + zi )2

i=1

= ln z and i = ln zi

m(z) + n(z) = (z + 1)

yields

r


(z + zi )2

i=1


ri = 10 log


2

e i + e
e i e


2
 
+1

= 20 log coth  i
1
2 

z + zi
z + zi

e i
= 10 log
ei

2

(72)

The terms ri and r can be considered a template in Fig. 30

that can be shifted to all pole locations i and 0.
Any given tolerance scheme in the stopband can be met by
a sum of the templates in Eqs. (71) and (72). The number of
those templates is minimized by shifting them to appropriate
locations i. This numerical search procedure is performed either by a computer program or by trials consisting of shifting
and adding templates. The result consists of pole locations zi,
their number r, and the multiplicity of the poles at z 1.
As all considerations for the conformal mapping have now
been discussed, we are ready to list the sequence of the synthesis steps:

and K( j)2 in Eq. (67) valid in the stopband are known. The
attenuation pertaining to Eqs. (67) through (69) is

r


z+1
z + 1

2. Determine poles zi.

m2 (z)
n2 (z)

m2 (z)

a() = 10 log |K( j)|2

(67)

with z [0, 1] and 1 in the stopband. The term with

the denominator m(z) n(z) h(z) in Eq. (66) exhibits no
poles in the stopband as h(z) is Hurwitz. Hence the term with
the denominator m(z) n(z) provides the poles. Now we determine m and n from the requirements in the stopband. With
the pole locations zi [0, 1] in Eq. (67), which are found later,
we obtain
m(z) n(z) = (z + 1)

i = 0

(66)

and

= 10 log

(71)


m2 ( 1 + 1/s2 )


f (z ) = g(s ) =
m2 ( 1 + 1/s2 ) n2 ( 1 + 1/s2 )
2

518

FILTER SYNTHESIS

4. Form

 
s
= Q(s)
|K( j)|2 = q2 +  2 g(2 ) = P() = P
j
and

K(s)K(s) = Q(s)
The zeros and poles of Q(s) provide a stable K(s).
5.


m ( 1 + 1/s2 )
2
2


f (s) f (s) = Q(s) q = 
m2 ( 1 + 1/s2 ) n2 ( 1 + 1/s2 )

The zeros and poles of Q(s) q determine f(s).

6. With K(s) and f(s), calculate the elements Aik of the
chain matrix and synthesize the LC two-ports embedded in R1 and R2.
2

Transformation of Low-passes Into Other Filters (19). The synthesis procedures presented were all geared to low-passes.
The standard approach to generate other filter types is a
transformation of the low-pass with frequency variable s and
s j into a new filter with frequency w and w j. The
general transformation is
s = f (w)

a
+ bw
w

band, as outlined by the transformation of sixth degree:

s = aw +

a
+ b

(74)

1
s= a
+ bw
w

with a, b > 0

(80)

(75)

as depicted in Fig. 31. The passband of the low-pass with

[1, 1] is translated into the passband with [1, 2]
of the bandpass, as indicated by bold lines in Fig. 31. The
cutoff frequencies are

the function f() is shown in Fig. 34 with a stopband for

[1, 2] with 1, 2 and 0, as in Eqs. (76) through (78).
The doubling of the reactances is demonstrated in Fig. 35.
The Low-pass High-pass Transformation. The transformation
s=

1
1
a
+
1 =
+
2b
4b2
b
*
1
1
a
+
2 =
+
2b
4b2
b

(79)

with a, b, c, d, c2, d2, 0.

The mapping of s j into w j is shown in Fig. 33,
where three passbands are generated. The number of reactances has increased by a factor of 6 due to f(w) of sixth
degree.
The Low-pass Bandstop Transformation. For the transformation

with a, b 0 maps s j into w j according to

=

cw
b
dw
+
+ 2
w w2 + 2c
w + 2d

(73)

where f(w) is a reactance function. This will also allow transformation of the reactances Ls and Cs into realizable reactances in the w-domain.
Low-pass Bandpass Transformation. The transformation
s=

Figure 31. The low-pass bandpass transformation.

a
w

(81)

(76)
(77)

Ls

a
s = w + bw

La
w

Lbw

The center frequency as an image of 0 is

*
0 =

a
b

(78)

with 02 12 representing the geometrical mean of 1 and

2. The reactances Ls and Cs translate into the series and
parallel resonators in Fig. 32. Due to f(w) in Eq. (73) of second
degree, a doubling of the reactances is observed. A transformation f(w) of higher degree provides more than one pass-

Cs

a
s = w + bw

Cbw
Ca
w

Figure 32. Transformation of reactances for bandpasses.

FILTER SYNTHESIS

519

11

21

12

31

d
22

32

Figure 33. Transformation of a low-pass

into a bandpass with multiple passbands.

a 0 yields
=

(82)

which is drawn in Fig. 36.

The cutoff frequency of the highpass is

voltage loss function K(s) at least in a limited frequency

range. An often encountered solution to this problem is cascading the unequalized two-port with the bridged-T network
in Fig. 38. If the impedances Z1 and Z2 are chosen according
to
Z 1 Z 2 = R2

1 = a

(84)

(83)

According to Fig. 37, inductors and capacitors are interchanged.

Amplitude and Phase Equalizers. Amplitude equalizers generate two-ports with a constant magnitude of the insertion

and if the network is terminated by the resistor R, then the

input impedance is also R. This implies that the bridged T
terminated by R can replace the load R2 R of the original
two-port without interaction. The inverse transfer function of
the bridged T loaded by R is
KB ( p) = 1 +

Z1 ( p)
R

(85)

For

Z1 /R =

1
G + jY ()

we obtain

|KB ( j)|2 =

(1 + G)2 + Y 2 ()
G2 + Y 2 ()

Ls

Lw
a
L
bw

Cs

Figure 34. Low-pass bandstop transformation with 0 a/b.

1
s= a
w + bw

1
s= a
w + bw

C
bw

Cw
a

Figure 35. Transformation of reactances for bandstops.

520

FILTER SYNTHESIS

Z1

Z2

Figure 38. Bridged-T network with Z1Z2 R2 for amplitude equalization.

with the phase () and the group delay () as

1 () = arg K1 ( j) = 2 arctan
and

Figure 36. Low-pass high-pass transformation.

2 () = arg K2 ( j) = 2 arccot
and
(1 + G)2 + Y 2 ()
a() = 10 log
G2 + Y 2 ()

(86)

The term a() is the attenuation added to the attenuation of

the original two-port in order to equalize the magnitude.
Table 5 lists a() for various impedances Z1 and Z2
R2 /Z1 (4).
Phase equalizers have the task to provide a linear phase
or a constant delay for the equalized two-port. They are commonly allpasses. The inverse transfer function of a first-order
and of a second-order allpass are
K1 ( p) =

p + 0
p + 0

(87)

and

20
p + 02

b
K2 ( p) =
20
p + 02
p2
b
p2 +

Ls

a
s= w

Cs

a
s= w

b
2

2
0
 2

1+
0
 2
0
1
+
b
d arg K2 ( j)

=
2 () =
2
 2
d
0

1+
0
4
0

d arg K1 ( j)
=
1 () =
d

(89)

(90)

The group delays 1() and 2() are depicted in Figs. 39(a)
and 39(b). For 2() the maximum is approaching 0 depending on increasing values of b. These bell-like curves are
added to the nonconstant group delay of the given two-port
and thus straighten it out. Several different frequencies 0
may be needed for this end. The network in Fig. 40 represents
a second-order allpass if it is terminated by R and if the element values are as listed in the figure caption. With the element values given in the figure caption, it exhibits constant
input and output impedances and can therefore be cascaded
without interaction with the unequalized two-port.

(88)
SURFACE ACOUSTIC WAVE FILTERS

La
w

Cw
a

Figure 37. Transformation of reactances for high-passes.

Filters for high frequencies in the megahertz or gigahertz

range are difficult to realize as the calculation of a three-dimensional electromagnetic field is required. To achieve this,
one has to resort to numerical methods, which, as a rule, are
inaccurate and hence necessitate complicated tuning of the
filters. Filters based on surface acoustic waves (SAW) are
somewhat easier to design and build. They are economically
one of the most important extensions of classical filters and
have reached operating frequencies of more than 10 GHz.
The surface of a piezoelectric substrate such as monocrystalline barium-titanate or -tantalate carries input and output
transducers as shown in Fig. 41. They translate the electrical
field E stemming from the input voltage V1 through the piezo-

FILTER SYNTHESIS

521

Table 5. A List of Impedances Z1 and Z2 and the Pertinent a() for

Amplitude Equilization.

Z1

Shape of a () in Eq. (86)

Z2

a ()

a ()

a ()

a ()

electric effect into a mechanical wave that travels with speed

v mainly in the surface of the substrate to the output transducer. Waves traveling backward or through the bulk of the
substrate disappear in an absorbing layer in Figs. 41 and 42.
The inverse piezo effect changes the mechanical wave in the
output transducer back to a charge separation, resulting in
the output voltage V2.
In its simplest form, the fingers and the gaps of the transducers exhibit all the same width as depicted at the top of
Fig. 43. In a more complicated but also more versatile case,
they are all unequal, as shown also in Fig. 43. The latter layout provides more degrees of freedom for the filter design. The
electrical field in the gaps as response to Dirac impulses at
the input reaches infinite values in the borders of the fingers,

as depicted in Fig. 43. This shape is approximated also by

Dirac impulses, as drawn in the last plot in Fig. 43. This socalled -approximation renders the calculation of the transfer
function F(p) rather easy. Each location of a -impulse is the
origin of a mechanical -impulse traveling with the speed v to
the output transducer. Figure 44 shows the distances from
the pair of fingers in the input transducer to the pair of
fingers in the output transducer; in Fig. 44 x0 is the distance
between the last fingers of the input transducer and the first
fingers of the output transducer. A most important parameter
is the overlap h (respectively, g) of a pair of fingers in the
transducers. They determine the width of the wave leaving
the input and being received by the output. Due to diffraction,
the width expands while the wave travels through the sub-

522

FILTER SYNTHESIS

generating the voltage

0 1( )

e (t) = k((t tL ) + (t tL ))

1.8

1.4

k=

1.2
1
0.8
0.6
0.4
0.2
0

0.5

1.5

3 / 0

2.5

(a)

k0
(1) (1) min(h , g )
p + q

min(h , g ) = h

b = 3.0
b = 2.5

b = 2.0

b = 1.5

h(t) =

2
1

0.2

0.4

0.6

0.8

1.2
(b)

1.4

1.6

1.8

2 / 0

Figure 39. (a) The group delay of a first-order allpass in Eq. (87). (b)
The group delay of a second-order allpass in Eq. (88).


 
x + ( + )r + c d
t 0
v
=0 =0


x + ( + )r c b
+ t 0
(96)
v
N1

M1

k0 (1) + h
2c + b d

A Laplace transform of Eq. (96) yields the transfer function

F ( j) = k0 e j x 0 /v

N1

M1

(1) +

=0 =0

x0 + ( + )r + q
v

h
e j( +)r/v
2c + b d



e j c/v e j d /v + e j c/v e j b /v

strate. This effect is limited by the dummy electrodes in Fig.

41. They form a surface with equal potential from where the
wave again starts with a given width.
The two -impulses in the edges of the finger pair in the
input transducer in Fig. 44 reach the center of the gap of the
finger pair in the output transducer after the delays
tL =

(95)

meaning g h for all and ; thus the output transducer

receives the full energy transmitted by the input transducer.
The full impulse response h(t) of the SAW filter is given by
adding over all N transmitting finger pairs and over all M
receiving pairs, which provides, with Eqs. (91) through (95),

6
5

(94b)

The factor k describes the strength (area) of the impulse,

which is inversely proportional to the width of the gap 1/
(p q) of finger pair , proportional to the min(h,g) because the minimum of either the width h of the transmitted
wave or the width g of the overlap of the receiving finger pair
determines the received wave, and, finally, proportional to the
alternating sign of E in the gaps represented by (1) (1);
k0 is a factor of proportionality representing the transducer
constant. As a synthesis with min(h,g) is hard to achieve,
we put

0 2( )
7

(94a)

with

1.6

(97)

L1

C1

(91)

C2
C2

and
tL =
2

x0 + ( + )r p
v

with
p = c + b

L2

(92)

(93a)

Figure 40. Bridged-T network realizing a second-order allpass with

constant input and output impedances R for the element values
L1 = 2

and
q = c d

(93b)

R2 C1C2
2C1 + C2

and for a termination by R.

L2 =

1 2
R C1
2

FILTER SYNTHESIS

Input transducer

523

Output transducer
Dummy electrodes

Absorber

Absorber

H
v

Ex

Ex

x
V1

V2

This general result is, for practical applications, usually simplified by setting b 0 and d 0 for all , which means
that all fingers have the same width r/2, which is also the
width of all gaps. This reduces F*( j) in Eq. (97) to

F ( j) =

c j x 0 N1
k0
v
cos
e
(1) h e j r/v
c
v
=0
M1

(98)

j r/v

(1) e

=0

In Eq. (98) the term ejx0 /v stands for the delay x0 /v of the
wave between the two transducers; the sum over is the essentially unwanted contribution of the output transducer,
whereas the cos term stems from the two -impulses per finger pair. The desired frequency characteristic has to be realized with the individual overlaps h of the input transducer.
We set
(1) h = h

Figure 41. Top view on surface acoustic

wave filter (SAW filter).

on the left has to be approximated by the right-hand term.

This term is the same as the transfer function of digital filters
with finite impulse response (FIR filters). Therefore, the synthesis procedures known from FIR filters can be applied
(21,22). Even though SAW filters are continuous time systems, the approximation by -impulses renders them similar
to time discrete systems, where r/v in Eq. (99b) plays the role
of the sampling time.
We cannot expect the approximation to provide h with alternating signs. Hence the layout of the fingers must be modified according to Fig. 45, where the alternation of signs is interrupted.
The pitch r in Fig. 46 is chosen such that the output signal
is maximum at the center frequency of the passband. This is
achieved by a constructive interference of the wave traveling
the distance 2r in time 2r/v and the sin wave with frequency
0 imposed by the voltage V1 exhibiting the period 2/0. This
yields
2r
2
=
v
0

(99a)
or

and
z = e j r/v

r=

(99b)

v
v
=
0
2 f0

and obtain from Eq. (98)

F ( j)
M1

c j x /v
k0
0
cos
e
c
v

=
(1) e j r/v

N1


=0

h z

(100)

=0

F*( j) is the desired transfer function to be synthesized; the

denominator on the left-hand side of Eq. 100 is the unavoidable contribution of the transducers. The ratio of both terms

Absorber
Figure 42. Cross section of SAW filter.

(101)

524

FILTER SYNTHESIS

SAW filter
Center of gap
r
+
c

r/2

Transducer with width

and gaps of fingers
all equal

r
c= 4

r/2

x0
b

Transducer with width

and gaps of fingers
not equal

h
p

p= c + b

Ex

q= c d

x
Strength of electrical field
Ex in the gaps

Ex
Approximation of Ex
by Dirac Impulses
x

Figure 43. Top view of fingers and electrical

field in the gaps.

Due to the approximations made, the design of SAW filters

as a rule requires a corrective redesign based on the measured deviations from the desired characteristics. Further
damaging parasitic effects are the triple transit signals,
which are reflected by the fingers at the output transducer
and then again reflected back to the output by the input
transducer.
Economically important applications of the SAW technology are filters for the intermediate frequency in TV sets and
filters for mobile communications.
The bandpass for TV sets possesses a center frequency of
38 MHz; the SAW substrate exhibits v 1000 m/s. This
yields, according to Eq. (101), a width of the fingers that
equals the gaps of r/2 13 m. A shortcoming of SAW filters
is the relatively large insertion loss in the passband of around

8 dB, stemming mainly from the loss in the substrate material. The loss can be decreased to around 5 dB by employing
a second output transducer in Fig. 47, which catches the so
far unused backward-traveling wave. However, the placement
of the two output transducers both in the distance x0 has to
be accurate in order to maintain the same phase of the waves
added in the output transducers.

AREAS FOR FUTURE STUDY

Classical filter synthesis is a well-established area for which
the first contributions were published more than 70 years
ago. Most of the important problems were indeed solved in
the meantime. Some remaining unresolved problems will be

FILTER SYNTHESIS

Input transducer

525

Output transducer

x0

t L1
t13

...

...
g

t12

V2

V1
p

t L2

Figure 44. Top view of input and output transducer with unequal widths and gaps of fingers.

outlined in this section. There has been increased focus on

those problems in recent years because the classical filters
serve as models for filter implementations in new technologies, such as digital filters, RC-active filters, and switchedcapacitor filters.
The following problems need to be resolved:
1. A proof that the synthesis of lossless two-ports with
partial and full pole removal is always possible with realizable reactances is still missing. It is a difficult task,
as many unsuccessful attempts may testify. However, a
proof would certainly offer a deeper insight into one of
the most important synthesis procedures. A helpful hint

for further investigations would be the fact that negative impedances are also tolerable for partial pole removal, as they can represent the negative component,
an inductor or a capacitor, in the equivalent circuit for
a transformer with tight couplings.
2. Guidelines on how to find lossless two-ports with a minimum number of the more expensive inductors would be
of economic interest. The guidelines could make use of
the large number of equivalent solutions.
3. A procedure is needed to control the various possibilities for synthesizing a lossless two-port such that the
component values lie in a desired range. This could help

+ Ex = 0 +

Ex

Ex

Ex
Ex

Ex

Ex

Ex

V1
_

Ex = 0

r
No alternation of sign
Figure 45. Top view of layout of fingers without alternating signs of
electrical field.

2r
Figure 46. Construction of superposition of traveling wave and wave
fed in by V1.

526

FILTER SYNTHESIS

x0

x0

V2

V1

Figure 47. SAW filter with two parallel

connected output transducers in two identical distances x0 from the input transducer.

Output
transducer

in using the components of an advantageous price- and

performance category and in implementing parasitic
components of a given value.
For filters in new miniaturized technologies, the
solution to the problem could provide component values that are feasible in the new technology, such as
multipliers with values in the raster 2, integer, in
digital signal processing or capacitors in the pF range
for CMOS technology while still maintaining a closedloop gain around 1 of the operational amplifiers. The
same goal may be reached by a linear transformation
into an equivalent two-port either for the time continuous classical filters (12,23) or for digital filters (24).
4. A method is needed to generate equivalent reactance
circuits for nonelectric components, such as coupled
quartz oscillators, or for other mechanical oscillators
during the synthesis procedure for lossless two-ports.
5. In the approximation method based on a conformal
mapping, the approximation of arbitrary but realizable
requirements in the stopband by a minimum number of
coth (i )/2 functions should be achieved by an analytical solution and not by a search procedure, guaranteeing that the minimum number of coth functions is
always reached. This design method would be one of the
most powerful.
6. There is a need for synthesis of RLC two-ports that
also include lossy two-ports with a complex impedance
as a load and as internal impedance of the voltage
source. This becomes more important the higher the
operating frequencies are, which imply complex impedance loads. The synthesis of either lossy two-ports
with resistive loads or of lossless two-ports with complex impedance loads (25) has been solved. Still unknown is the synthesis of two-ports combining the
two properties.

Input
transducer

Output
transducer

7. There is a need for synthesis of SAW filters based on a

more accurate but still easy-to-handle simulation of the
device, which should eliminate the need for a corrective
redesign.
8. A straightforward synthesis of SAW filters with the
large number of geometrical parameters in Eq. (69) will
save fingers and hence chip area. The synthesis should
also compensate for parasitic effects, such as the triple
transit signal.
9. Materials science ought to synthesize piezoelectric substrates with a diminished attenuation of the SAW in
order to decrease the insertion loss of filters.
ACKNOWLEDGMENTS
The author acknowledges the valuable discussions with and
the proofreading by his coworkers Markus Gaida, Joachim
Selinger, Axel Wenzler, Markus Wintermantel, and Christof
Zeile.
BIBLIOGRAPHY
1. W. Bader, Elektrische Netzwerke mit vorgeschriebenem Einschwingvorgang, VDE-Fachberichte, 13: 289295, 1949.
2. E. Lueder, Die Verwirklichung der Kettenmatrix des allgemeinen
passiven Vierpols durch eine Schaltung mit der geringsten Zahl
von Teilen, Habilitationsschrift, University of Stuttgart, 1966.
3. S. Darlington, Synthesis of reactance four-poles which produce
prescribed insertion loss characteristics, J. Math. Phys., 18: 257
353, 1939.
4. R. W. Daniels, Approximation Methods for Electronic Filter Design, New York: McGraw-Hill, 1974.
5. M. S. Ghausi, Principles and Design of Linear Active Circuits, New
York: McGraw-Hill, 1965.
6. D. O. Pederson and E. S. Kuh, Principles of Circuit Synthesis,
New York: McGraw-Hill, 1959.

FINGERPRINT IDENTIFICATION
7. L. Weinberg, Network Analysis and Synthesis, International Student Edition, New York: McGraw-Hill, 1962.
8. S. K. Mitra, Analysis and Synthesis of Linear Active Networks,
New York: Wiley, 1969.
9. S. Butterworth, On the theory of filter amplifiers, The Wireless
Engineer, 13: 536541, 1930.
10. Private communication by A. Wenzler and M. Wintermantel, Institute of Network and Systems Theory, University of Stuttgart,
1997.
11. W. E. Thomson, Delay networks having maximally flat frequency
characteristics, Proc. IEEE, part 3, 96: 487490, 1949.
12. W. Cauer, Synthesis of Linear Communication Networks, transl.
from the German by G. E. Knausenberger, 2nd. ed., New York:
McGraw-Hill, 1958.
13. R. Saal and W. Entenmann, Handbuch zum Filterentwurf [Handbook of Filter Design], 2nd ed., Heidelberg: Huthig, 1988.
14. E. Christian and E. Eisenmann, Filter Design Tables and Graphs,
New York: Wiley, 1966.
15. R. Saal, Der Entwurf von Filtern mit Hilfe des Kataloges normierter
Tiefpasse, Backnang: Allg. Electricitats-Ges. AEG-Telefunken,
1968.
16a. W. Bader, Kopplungsfreie Kettenschaltungen, TelegraphenFernsprech-Funk- und Fernseh-Technik, 31: 177189, 1942.
16b. W. Bader, Kettenschaltungen mit vorgeschriebener Kettenmatrix, Telegraphen-Fernsprech-Funk- und Fernseh-Technik, 32:
119125, 144147, 1943.
16c. W. Bader, Polynomvierpole vorgeschriebener Frequenzabhangigkeit, Archiv Fur Elektrotechnik, 34: 181209, 1940.
ber die Realisierbarkeitssatze der Kettenmatrix von
17. H. Piloty, U
Reaktanzvierpolen, Telegraphen-Fernsprech-Funk- und FernsehTechnik, 30: 217223, August 1941.
18. R. M. Foster, A reactance theorem, Bell Syst. Tech. J., 3: 259
267, 1924.
19. E. Guillemin and S. A. Ernst, Synthesis of Passive Networks: Theory and Methods Appropriate to the Realization and Approximation
Problems, New York: Wiley, 1957.
20. M. E. Van Valkenburg, Analog Filter Design, New York: Holt,
Rinehart & Winston, 1982.
21. B. Gold and C. M. Rader, Digital Processing of Signals, New York:
McGraw-Hill, 1969.
22. S. K. Mitra and J. F. Kaiser, Handbook for Digital Signal Processing, New York: Wiley, 1993.
quivalente Schaltungen und Topologie der Schal23. E. Lueder, A
tungen geringsten Aufwandes, Ph.D. Thesis, University of Stuttgart, June 1962.
24. E. Lueder and K. Haug, Calculations of all equivalent and canonic 2nd order digital filter structures, IEEE Int. Conf. Acoustics,
Speech Signal Process, Tulsa, April 1012, 1978, pp. 5154.
25. W. Bader, Die Synthese des linearen passiven Vierpoles bei beliebigen komplexwertigen Quellen- und Abschluwiderstanden,
Nachrichtentechnische Zeitschrift, 549555, November 1964.

Reading List
L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Non-Linear
Circuits, New York: McGraw-Hill, 1997.

ERNST LUEDER
University of Stuttgart

FILTERS, TIME-VARYING. See TIME-VARYING FILTERS.

527

SENSITIVITY ANALYSIS

IMPORTANCE OF THE SENSITIVITY CONCEPT

In physics and engineering, we usually mean by sensitivity of a system a measure for determining the amount of
change an outcome undergoes if the relevant parameters
xing the outcome are somewhat modied (15). In some
situations, for example in a measurement or in a decisionmaking situation, such an outcome may be an individual
result. In others, an outcome may be one or several functions of some further independent variable(s), especially a
time or frequency response. Obviously, such a general definition of sensitivity is somewhat vague and, in order to
make it quantitatively useful, needs more precise specication.
If we are dealing with only small modications, appropriate sensitivity measures can usually be based on differential expressions, that is, on rst-order derivatives of the
desired outcome with respect to the component parameters. In other situations, the encountered changes may be
so large that a rst-order approach may be insufcient.
One then must either consider also higher-order derivatives or determine the resulting modied behavior by direct precise computation. The latter approach can be simplied drastically if the functions under consideration have
an appropriate simple structure, as is the case for system
functions of linear circuits and systems. However, the number of instances in which inuences of order higher than
the rst have to be taken into account is probably much
smaller than what is sometimes believed. Indeed, if the
expected parameter changes are such that higher-order effects must be taken into account, one is frequently dealing
with what may be termed poor engineering design.
Interest in sensitivity aspects may arise in quite different contexts. For analog circuits, the most immediate
concern results from the errors due to manufacturing inaccuracies, temperature changes, and aging. The resulting
requirements become particularly severe for applications
for which stringent criteria have to be met. One such type of
application are lters since these may have to present dramatically different behavior in passbands and stopbands.
Another type are high-performance ampliers. Some attention to such circuits will therefore be given later. However, it may be mentioned now already that in order to alleviate the problem, it has been found, in both those cases,
to be very advantageous to have recourse to passivity and
its limiting form losslessness. It seems indeed that despite
the enormous importance of active devices there exists a
universal law of sound engineering practice: Any apparatus having to satisfy very stringent requirements should
preferably be built either in purely passive fashion or, especially if that choice is inherently excluded (ampliers,
combustion engines, power stations), in such a way that
the most critical performance aspects are determined by
passive devices or subsystems.
This does not imply at all, however, that passivity and
losslessness are the only criteria one should aim for in
the case of critical applications. As an example, the stop-

band sensitivity of lters in bridge-type conguration increases dramatically with increasing stopband requirements. Hence, even very slight manufacturing inaccuracies, temperature changes, and aging may inadmissibly
perturb the behavior of such lters, also in the case of passive (lossless) implementations.
The values of, for example, parasitic elements can also
be considered as relevant parameters in the sense used at
the beginning of this section. Hence, sensitivity analysis
encompasses the analysis of the inuence that parasitic
elements have upon the behavior of a circuit.
In digital circuits, the arguments listed so far for emphasizing the importance of sensitivity lose their meaning.
Indeed, under the usually permitted assumption of fully reliable digital operation, manufacturing inaccuracies, temperature changes, and aging have no effect. There is, however, a different aspect due to which sensitivity is of direct
relevance: the limited number of bits available in the registers for storing the parameters that x the circuit behavior.
Hence, low sensitivity is also of interest for digital systems.
Nevertheless, bridge-type congurations are now admissible even for critical ltering purposes. There is no limit
to the achievable stopband attenuation provided the lter
coefcients have been determined with sufcient accuracy
and the relevant registers are long enough.
One of the reasons for the present dominance of digital circuits has itself also partly to do with sensitivity: The
ever smaller features of highly integrated circuits cannot
be controlled with such precision that accurate analog operation could be ensured. In digital circuits, however, the details of the analog operations, that is, the transitions from
one state to another, are irrelevant as long as these transitions occur sufciently fast.
Sensitivity may also be of relevance in a more indirect fashion. Indeed, various types of imperfections such
as noise and nonlinear distortion can frequently be interpreted as being caused by parameter uctuations. If this
is the case, a reduction of sensitivity with respect to such
a parameter change will also imply a corresponding reduction of the disturbance caused by the imperfection. In this
sense, there exists a highly benecial relationship between
sensitivity on the one hand and noise and nonlinear distortion on the other. This holds true for analog as well as for
digital circuits (68).
At this point, one question immediately comes to mind:
While properties such as passivity and losslessness have
no natural meaning for digital circuits, is it nevertheless
possible to carry them over to the digital domain and thus
to prot also there from the sensitivity benets potentially
available from such properties? The answer to this is afrmative, and corresponding structures are known as wave
digital lters (8). [These lters, due to their passivity, offer, however, a much broader resistance against disturbing
imperfections, a property also referred to as robustness (9),
than what we are discussing in the present context.]
So far, we have taken it for granted that a low sensitivity
is desired, but the opposite situation also has some interest.
This is the case in particular in measuring and sensing
equipment, where one does indeed want to obtain large
deviations of the output for small changes of the device to
be measured or of the phenomenon to be detected. Hence,

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Sensitivity Analysis

circuits such as bridges, which are to be avoided for critical

analog ltering, are precisely preferred arrangements, for
example, for measuring purposes.
Finally, sensitivity expressions are also of great interest in numerical work (10). In particular, optimization
problems can usually be solved only by iterative procedures involving individual linear steps, which in turn rely
in many cases on the use of sensitivity-type expressions.
These should again be reasonably large in order to accelerate convergence. Related to optimization is the problem of
computer-based circuit adjustment. Corresponding strategies also rely on knowledge of the relevant sensitivities.
The present text is not an attempt to give a comprehensive summary of the subject but rather a brief exposition of
those sensitivity aspects that, according to the experience
of the author, have proved to be of particular importance
in the area of circuit design and operation (with prime emphasis on linear circuits). For other aspects and many further details, the reader may wish to consult specialized
books such as Refs. (15), or relevant chapters in books
with wider scope (1114).
SENSITIVITY DEFINITIONS
Let F be a real or complex quantity of interest. It is a function of a certain number of parameters, say 1 to n ; these
are frequently real, for example, if they represent component values, but they can also be complex. In general, F also
depends on one or several further physical quantities, say
on time t or on the frequency or the complex frequency
s = + j, but such dependencies will be made explicit only
if strictly required. Hence, we can write F = F(), = ( 1 , . . . ,
n )T . If one of the is changed by a small amount  , F
is changed in rst approximation by

An appropriate measure for sensitivity, more precisely for

what is called absolute sensitivity of F with respect to ,
is therefore

Frequently, one is more interested in relative changes of F

with respect to relative changes of , that is, in the relative
sensitivity

sometimes also in one of the semirelative sensitivities

which all are closely related to the original expression.

The relative sensitivity [Eq. (2)] is frequently the preferred
quantity. However, it loses its meaning if F = 0 and/or = 0.
Corresponding remarks hold for the semirelative sensitivities.

One can also represent in a compact fashion the complete sensitivity vectors. Thus
S(F ; )

S(ln F ; ln ) =

1
DF
F
ln F
1
F
F T
= (1
, . . . , n
)
ln
F
1
n

DF, S(ln F ; ) =

(4)

where

If instead of a single F one is interested in a vector F = (F1 ,

. . . , Fm )T , one has, for example,

where F/ is the Jacobian matrix of F with respect to .

If F is a system function (impedance, admittance, transmittance, reectance, etc.) of a linear constant (i.e., time
independent) circuit and if refers to a one-port constituent (resistance, inductance, capacitance, impedance,
admittance, etc.), F is a bilinear function of of the form
(see below)

where F11 , F12 , F21 , and F22 are independent of . The same
holds true if is the multiplicative parameter characterizing a controlled source. However, if is a mutual inductance, a turns ratio of an ideal transformer, or the gyration
constant of a gyrator, we have

where F11 , F12 , F13 , F21 , F22 , and F23 are independent of .
The case of Eq. (7) is the most frequent, and the simplicity
of such an expression can be of considerable help not only
if rst-order sensitivities as given by Eqs. (1) to (6) are of
interest, but in particular if arbitrary large changes in
are to be taken into account.
The bilinearity of Eq. (7) is itself a consequence of the
linearity of the steady-state equations of the circuit. As
an example, assume that F = V0 /E, where V0 is a response
voltage and E a source voltage; that = Z, where Z is some
impedance in the circuit; and that V and I are the voltage
across, and the current through, Z. We may replace Z by a
voltage source whose voltage V is controlled by the current
according to V = ZI. Applying superposition we may write
V0 = AE + BV, I = ace + DV, where A, B, C, and D are independent of the voltages and currents. Eliminating V and
I, one obtains indeed Eq. (7), with F11 = A, F12 = BC AD,
F21 = I, F22 = D. In a similar way, Eq. (8) can be shown to
hold, observing that in the case of a mutual inductance, an
ideal transformer, or a gyrator, one has to make use of two
auxiliary controlled sources.
If F is in fact a transfer function to be evaluated at real
frequencies (thus for s = j), one may be more interested in

Sensitivity Analysis

the loss and the phase dened by

Hence, we have, for example,

In the passband of a good lter, we have 0; hence S(ln

; ) and S(ln ; ln ) would there have no meaning.
Usually, one has | / | where is independent of
. The change of F is thus in rst-order approximation
bounded according to

This shows that the sums in the expressions just presented

can be interpreted as worst-case sensitivities. Such concepts can be extended to apply, for example, to the worst
case over a frequency range of interest.
Worst-case sensitivities are often too pessimistic for
practical applications. A better way of proceeding is then
offered by statistical considerations. For this, let 0 be
the nominal value of = (1 , . . . , n )T , thus 0 the nominal value of , and F0 = F (0 ), the relative changes being
( 0 )/0 and (F F0 )/F0 . If we can restrict ourselves
to rst-order terms, we have

0
n

F F0 =

=1

F
|=0
ln

(13)

Let then the be real random variables, with = E{ }

and F = E{F } the expected values of and F. Ideally, =

0 for = 1 to n, in which case also F = F0 , but this ideal

situation is frequently not achieved, especially if effects
due to temperature changes and/or aging have to be taken
into account. Since Eq. (13) is linear in F and we can also
write

F F =

n



=1

F
|=0
ln

(14)

Figure 1. (a) A two-port N driven at port 1 by a source of voltage

E and internal resistance R1 and terminated at port 2 by a load
resistance R2 . (b) A one-port N driven by a source of voltage E and
internal resistance R1 .

what is really prescribed is a so-called tolerance plot of, for

example, the loss () with respect to the value (0 ) at
some reference frequency 0 (see the section entitled The
Passband Sensitivity Theorem).
SENSITIVITY IN PASSIVE, ESPECIALLY LOSSLESS
CIRCUITS
Linear Constant Two-Ports at Steady State
In Fig. 1(a) is shown a two-port N under canonic operating conditions, that is, inserted between a resistive source
(source voltage E, source resistance R1 ) and a resistive load
R2 . We assume N to be linear and constant (time independent) and consider its steady state at complex frequency
s = + j, the voltages E, V1 , and V2 being assumed to be
complex rms values. For N operated from left to right, as
shown, the quantities of primary interest are the transmittance S21 , the reectance S11 , the characteristic function
,
and the effective (transducer) loss and phase . In addition to , the insertion loss i is frequently used; it is related
in a simple way to , to which it is equal for R1 = R2 , but
is less convenient for our purpose. The rst three of these
quantities are dened by

Finally, we assume that the are uncorrelated and such

that the /0 all have the same variance . Dening the
variances F and F/F0 , also in the case of complex F, by

2
F2 = E{|F F |2 } and F/F
= E{|F F |2 /F02 }
0

we obtain from (13) and (14),

F2 = 2

n


=1

ln F
F 2
2
2
|=0 , F/F
=

|
|2

0
ln
ln =0
n

=1

Hence, the sums in these two expressions can be interpreted as statistical sensitivities, and it may again be appropriate to determine the worst case over the frequency
range of interest.
Although worst-case and statistical sensitivities may be
useful design tools, they frequently do not offer a sufciently precise picture. In particular, in the case of lters,

and are thus functions of s, while and are dened only

for = 0, that is, according to

the second equality in Eq. (19) holding (and

thus being
fully meaningful) only if N is lossless. For any two-port N,

Sensitivity Analysis

Figure 2. Typical plots of the output power P2 and the effective

loss versus for an optimally designed low-pass lter.

however, we have

may assume any corresponding to be chosen equal to

the element value so that we still have > 0. Coupled
inductances may be assumed to be replaced by positive inductances and ideal transformers. Altogether, we may thus
assume > 0 (which denitely implies to be real). More
specically, let 0 = ( 10 , . . . , n0 )T > 0 be the vector of the
nominal values of the , that is the one for which ideal
plots such as those of Fig. 2 are achieved.


Let now 0 be any frequency for which ( 0 , 0 ) = 0,
which in the lossless case is indeed achievable by proper


design. Referring to Fig. 2, we may thus choose 0 = 0, 2 ,

or 3 . Let us then change the parameter vector from 0 to
any other value > 0, in which case N denitely remains



passive, ensuring ( 0 , ) 0, that is, ( 0 , ) ( 0 ,


0 ) = 0. Hence, the loss ( 0 , ), evaluated at the xed 0
but considered as a function of , has a minimum at = 0 .


But since S21 (j 0 , 0 ) = 0 and = , ( 0 , ) dened by

is differentiable with respect to all the at = 0 . Hence,

that is,

P1 being the power transmitted to N via port 1, P2 the

power delivered to the load, Pd the power dissipated in N,
and Pmax the maximum power available from the resistive
source, thus with P1 Pmax (the term power denoting, in
the present context, everywhere active power at real frequency, i.e., for = 0). If N is passive, we have Pd 0 and
thus

and furthermore

Classical lters are not only passive, but, ideally, even

lossless and thus satisfy Pd = 0. Hence, if at some we have
S11 (j) = 0, we also have there |S21 (j)| = 1 and () = 0, and
vice versa. Typical plots of P2 and versus are shown in
Fig. 2 for an optimally designed low-pass lter of fth order
(critical regions being enlarged to make them more visible).

The Passband Sensitivity Theorem

We now consider the dependence of the quantities just described not only on or s but also on the parameter vector
= ( 1 , . . . , n )T , that is, we write (, ) instead of (), etc.
The components of the circuit of Fig. 1(a) are the elements
of N as well as the resistances R1 and R2 . We assume N to
be passive, that is, for any referring to a resistance, an
inductance, or a capacitance we have > 0. Strictly speaking, no such restriction exists in the case of an ideal transformer or a gyrator, but in order to simplify our writing we

Therefore, at any frequency where is zero the sensitivities

of with respect to any vanish for = 0 . This allows
us to conclude that in practice all sensitivities are small
whenever is small, thus throughout the passband of the
lter.
This is the content of the standard version of what we
are here calling the passband sensitivity theorem. This content is far reaching and astonishing. A ladder-type low-pass
lter capable of giving the performance of Fig. 2 comprises
seven reactive elements, to which must be added the terminating resistances. Hence, n = 9, that is, the number of
sensitivity values that vanish is equal to 3 9 = 27, which
is far more than the available number of degrees of freedom. But these should in the rst place be used to obtain
a good ltering property. The result of Eq. (21) expresses
that the latter property is the only thing we have to look
for, and the excellent passband sensitivity is then automatically obtained, without any further expense.
In view of Eq. (20), the sensitivity of i with respect
to any parameter other than R1 and R2 vanishes at the
same time as that of . However, if properly interpreted,
the excellent sensitivity behavior of with respect to R1
and R2 also carries over to i . Indeed, the difference i
is independent of , that is, the plot of i () can always be
obtained by simply parallel shifting that of (), even after
R1 and/or R2 have been changed. However, what counts in
practice is almost always the actual distortion exhibited by
the plot, that is, the deviation of () with respect to the
loss (0 ) at some reference frequency 0 , or equivalently,
the deviation of i () with respect to i (0 ), and we have
() (0 ) = i () i (0 ). The same holds, obviously, for
any other loss  dened in such a way that  () () is

Sensitivity Analysis

frequency independent, in particular, for  () = ln|E/V2 |. In

other words, if () remains within a given tolerance plot,
the same will be true for any such  ().
The passband sensitivity theorem has apparently been
discovered several times independently, although only after lters had been in use for several decades. The present
author, for example, discovered it in 1956 after the application of Darlingtons so-called predistortion method to lters built with inductors of rather mediocre quality factors had led to disappointing sensitivity problems. As required by this method, (, 0 ) [and, equivalently, |S11 (j,
0 )|] had indeed been raised to a passband level substantially above zero so that the argument that had led to Eq.
(28) was completely destroyed. This mechanism had been
briey explained in a tutorial paper published in Dutch in
1960 (15). A short independent exposition by Orchard appeared in 1966 (16, 17), but experts at the Siemens Communications Laboratories had also discovered the theorem. It is being referred to in the literature as Orchards
theorem, the FettweisOrchard theorem (11, 13) or the
OrchardFettweis theorem (18).
The theorem holds for a large variety of lter types, in
particular if losslessness can be involved in an appropriate
fashion. It is thus immediately applicable to classical LC
and microwave lters, to crystal lters, and to mechanical
lters (19). The transmittance of a periodically switched
linear lossless lter is not only a function of s but also a
periodic function of t. The coefcients of the corresponding
Fourier expansion are the conversion functions, of which
usually only one is of primary interest. Although the corresponding effective loss cannot be made strictly equal to
zero, it can be made very small by proper design, so that
the theorem is essentially applicable (20). To lters of a
type for which the concepts of passivity and losslessness
have no inherent relevance it is applicable if they are derived in an appropriate way from a reference (prototype)
lter of classical lossless type. This includes not only active
lters, for which a simple solution consists in realizing inductors by means of capacitively terminated gyrators that
in turn are implemented by means of active devices, but
also switched-capacitor and switched-current lters as well
as digital lters (2129). The most important solution for
the latter are the so-called wave digital lters (WDFs) (8).
For WDFs, one can make use of a generalized passband
sensitivity theorem that extends its signicance even to parameter changes that are well beyond those for which a
rst-order theory is sufcient and that would thus be inadmissible in analog ltering (see the rst section). In the
case of such larger parameter changes, the loss at any of


the frequencies such as 0, 2 , and 3 in Fig. 2 can indeed,
due to passivity, only move upwards. Hence, the resulting
distortion will be substantially less than the one that would
be observed if upward movements occurred at some of those
frequencies and downward movements at others. For this
reason it has been possible to design ladder WDFs that
have amazingly simple coefcients but still satisfy quite
severe requirements (8).
For the phase , a strict theorem like the passband
sensitivity theorem does not hold. Nevertheless, for a
minimum-phase circuit (i.e., a circuit whose phase shift is
not larger than needed for achieving the given loss behav-

ior), which is the usual situation, is strictly related to

and we then have, due to the Bayard-Bode relation (6),

Hence, any procedure that reduces the sensitivities D(,

) tends to reduce at the same time the sensitivities D(,
).

Stopband Sensitivity and Tuning

The most important lter sections by means of which classical lters can be composed are of ladder or lattice type.
If high selectivity is desired, an input signal arriving at
stopband frequencies must be attenuated by many orders
of magnitude. This cannot be achieved in a single ladder
section but is, at least in principle, feasible in a single lattice section (or one of its equivalents). Let X1 and X2 be
the two lattice reactances. In the stopband we have X1
X2 and, as can be shown, ln|2X0 /X|, the bound being almost tight, and X2 0 = X1 X2 , X = X1 X2 . Hence, for
any increase of by 20 dB the ratio |X/X0 | must be decreased by a factor of 10, at all relevant frequencies. This
imposes unrealistic accuracy requirements if large values
of are needed, but even for moderate values the accuracy
requirements can only be met by using highly stable components such as quartz crystals. Alternatively, the best way
to circumvent the problem is to use ladder instead of lattice
structures, that is, congurations that can be composed by
chain-connecting simple series and shunt branches.
Such branches produce transmission zeros (attenuation
poles) and thus poles of the function
[cf. Eqs. (15c) and
(17)] by parallel or series resonances, to which we refer
hereafter as pole resonances (main resonances). The location of the transmission zeros can easily be determined by
measuring the lter output in an arrangement according
to Fig. 1(a), and it is thus possible to bring the location of
these zeros very close to their desired position by tuning.
This makes the denominator of
(assumed to be written
as a monic polynomial) to becoming very close to its ideal
expression. The numerator zeros usually are all located in
the passband and are the frequencies at which () is zero.
If these zeros also have to become more accurate, tuning of
some further resonances, referred to hereafter as auxiliary
resonances, is needed, as is in particular the case for narrow band-pass lters. Such further tuning, however, cannot
usually be based directly on the zeros of
, but if the auxiliary resonances are properly selected, the zeros of
will
be moved at least close to their ideal locations. The mechanism behind this can be easiest understood by examining
a simple related example.
Consider indeed two series resonant circuits with inductances L1 and L2 and resonant frequencies 1 and 2 ,
the nominal values being L10 , L20 , 10 , and 20 , respectively.
We write L1 = L10 + L1 and L2 = L20 + L2 and assume that
by tuning we have obtained 1 = 10 and 2 = 20 . If these
two circuits are connected in parallel, a parallel resonant
frequency 3 will be created, with nominal value 30 . Neglecting higher-order terms and assuming 10 to be close

Sensitivity Analysis

to 20 , one can show that

stopband performance, these frequencies then being kept

xed during the nal optimization of the transfer function.
Sensitivity to Reactive and Resistive Parasitic Elements

Hence, as a result of tuning the series resonances (which

involves two independent operations), the change in the
(dependent) parallel resonance is far smaller than what
might be expected from L1 and L2 .
Due to a similar mechanism one can ensure, by properly adjusting a sufcient number of independent auxiliary
resonances, that all zeros of
become quite close to their
nominal values. After this, even in the case of narrow-band
lters,
differs from its nominal shape only by the very
small remaining inaccuracies of its zeros and the small
change of its constant factor. The inuence of these errors
is further reduced by the validity of the passband sensitivity theorem. For selecting suitable auxiliary resonances,
taking into account the unavoidable presence of parasitic
elements (see also the following section), the original circuit should be reduced to circuits of simpler type (each one
of them possibly involving more than one branch of the
original circuit), but this should be done by applying appropriate short circuits and not by creating interruptions,
since these might wrongly affect the location of the parasitic capacitances. In this selection process, one can advantageously make use of approximate transformations of the
type explained in Ref. 30. On the other hand, in simpler
cases, especially for low-pass lters, it may be sufcient
to tune only the pole resonances and thus ignore auxiliary resonances. In all cases, resonant frequencies can be
maintained close to their nominal values throughout the
required temperature range, for example, by using components with mutually compensating temperature coefcients or, if appropriate conditions are met, by implementing critical parts by means of high-quality crystals.
For a ladder structure, the order in which transmission
zeros are best implemented is also related to sensitivity
and tuning, a mistuning of such a zero being more the critical the closer its nominal value is to a cutoff frequency.
On the other hand, taking into account the discussion
about Eq. (23), tuning is very helpful near the tuned frequency but much less helpful further away from it. Hence,
since resonances in circuit parts close to an access port are
strongly damped by the terminating resistance and thus
less critical, the following rule emerges for ordering the
pole resonances inside the structure: If no tuning is used,
transmission zeros close to the cutoff frequency should be
implemented by branches close to the access ports of N [Fig.
1(a)], but the opposite holds if the pole resonances but not
the auxiliary resonances are tuned. If pole and auxiliary
resonances are tuned, the ordering of the branches implementing the transmission zeros should be quite irrelevant
from the sensitivity point of view.
In some important digital lter structures there exists
for each transmission zero a one-to-one correspondence between its location and an associated multiplier. Numerical tuning may then be applied in the following sense:
The transmission zeros are selected to occur at frequencies
for which the associated multiplier coefcients are as simple as possible without unduly deteriorating the available

Parasitic elements may be interpreted as small changes

of parameters, the nominal values of which are zero.
Care must therefore be exercised when trying to apply
the passband sensitivity theorem since this theorem had
been proved under the assumption that the changes  ,
whether greater or less than 0, would not affect the validity of > 0. At strictly real frequencies, however, the formal losslessness (i.e., the losslessness at steady state) of a
reactive element is not affected by the sign of its component value. Hence, the reasoning that had led to Eq. (21)
remains valid, that is, well-designed lossless lters inherently have strongly reduced passband sensitivity to parasitic capacitances and inductances. This argument clearly
breaks down in the case of parasitic resistances, that is, if
parasitic resistances are introduced into N in Fig. 1(a), we
must expect noticeable changes that depend on rst-order
derivatives.
Let us assume, therefore, as is quite justied in practice,
that on the one hand all inductors have the same quality factor QL = 1/L and, on the other, all capacitors have
the same quality factor QC = 1/C . If L = C = the inuence
upon S21 (j) can be shown to be equivalent to replacing
by (1 j). This raises to +  and to + . In rst
approximation, we then have

where is the so-called group delay and  is negligible

in the passband of a well-designed lter. If L = C , as is
more realistic, we can separate the effect into two parts,
at least in the case of narrow-band lters. One of these
parts depends on L C and amounts to inserting at each
of the ports either a small series reactance or a small shunt
susceptance, which can be taken care of by retuning the
terminal branches. The remaining effect is then exactly as
described above, but with = (L + C )/2.
Assume next that we are having both dissipation due
to lossy components (nonvanishing L and C ) and deviations  in the parameters . Since we are examining
rst-order effects, both inuences can be considered to be
independent. In particular, the excellent sensitivity behavior resulting from the passband sensitivity theorem will be
fully retained.
This result is in a sense a special case of a more general principle. An effective loss > 0, implying P2 < Pmax
[cf. Eqs. (16) and ((18) ], can indeed result from two different mechanisms, either from reection, that is, by P1 < Pmax
and Pd = 0, or from dissipation, that is, by Pd > 0 [Eq. (19)].
In the rst case, the assumptions that had led to Eq. (21)
are violated. In the second case, it usually so happens that
a basic loss 0 () [such as, for example, the one given by
()] is unavoidable, and we thus have, in some neighborhood of 0 , (, ) 0 (), with (, 0 ) reaching the

Sensitivity Analysis

bound 0 () at some frequencies. We are then again led to

Eq. (21). The predistortion method (see the section entitled The Passband Sensitivity Theorem) aims at equalizing the distortion that () suffers from the presence of
losses in ideally lossless components [see Eq. (24)]; it does
this by creating reection, which explains the poor sensitivity performance obtained by this method. A better way
of equalizing () is therefore to rely on introducing further
dissipation in appropriately chosen locations.
SENSITIVITY ASPECTS IN OTHER TYPES OF CIRCUITS
AND IN COMPUTATION
Sensitivity Reduction in Continuous-Time Active Circuits
A classical way of reducing sensitivity in ampliers is to use
feedback. We consider only the simplest case, in which a forward transfer function and a backward transfer function
yield an overall transfer function

Clearly, the realization of requires the use of active devices, but for , which essentially determines the value of H,
only passive components are needed. Hence, although the
gain of pure active devices is quite inaccurate, the value of
H can be implemented with the far greater accuracy available from passive components. This is conrmed by means
of the sensitivity of H with respect to , that is, by

Expressions such as Eqs. (25) and (26) assume that there is

no interaction between the functions and . In practice,
there is at least some interaction, and the expressions can
then be made more precise by the use of the concept of
return difference (6).
The problem of sensitivity is of prime importance also
in active lters. Many design approaches therefore attempt
to model an active lter after some suitable lossless lter
of classical type. Others, however, use the desired transfer
function H as point of departure and attempt to implement
it as directly as possible. We can write

a and b being real polynomials of degree m and n m, respectively, with b monic. A direct implementation on the
basis of the coefcients B , = 0, . . . , n 1, is very critical because in a good lter the zeros s , thus the poles of
H(s), are clustered (although distinct) near the cutoff frequency(ies). We thus have, as can be shown, for the sensitivities of these zeros with respect to the coefcients

Hence, these sensitivities can, in practice, become very

high, especially for larger values of n. Consequently, for n
3, H should be implemented by cascading rst- and second-

order sections. This conclusion is a simple example of a

much wider observation, that is, that proper parametrization of functions such as polynomials and rational functions is of decisive importance for keeping the relevant sensitivities as low as possible.
It should be mentioned in this context that the critical
property expressed by Eq. (27) is also a major cause for
the numerical computation of classical lossless lters by
the insertion loss method to be ill-conditioned, and this despite the excellent sensitivity behavior that lters designed
this way do offer. This is a reason why in many places this
superior design method had not been adopted in practice
until after electronic computers had become more easily
accessible.
Sensitivity Reduction in Analog Discrete-Time and in
Digital Filters
In the case of discrete-time circuits, one can express all relevant functions as rational functions in z = esT or, equivalently, in = (z 1)/(z + 1) = tanh(sT/2), s being the actual
complex frequency, as before, and the sampling rate being F = 1/T. The parameter largely plays the role of a
(normalized) equivalent complex frequency. For = 0, we
have = j, = tan(T/2). All sensitivity aspects discussed
earlier in the section entitled Sensitivity Reduction in
Continuous-Time Active Circuits carry over to the present
situation, especially if we adopt as the equivalent of the
former s. This applies in particular if lters are designed
by modeling them after classical lossless structures and
also if cascading is used as a solution to overcoming the
problem explained subsequently to Eq. (27).
A few specic aspects should be mentioned, however.
In switched-capacitor lters (11,14,20-24), the critical frequencies (i.e., the zeros and poles of the relevant functions)
are determined by capacitance ratios rather than by absolute capacitance values, thus strongly alleviating the problem of the acceptable tolerances for the capacitance values
themselves. A somewhat similar situation holds true for
switched-current lters (27), for which transistor aspect ratios are the relevant quantities. In digital lters (26, 29),
for which actual physical circuits indeed play only an indirect role, that is, that of a means to implement algorithms,
an added difculty is the need for ensuring computability.
However, WDFs (8) offer a full solution to transposing reference lters of a classical type, such as ladder and lattice
lters, into the algorithmic domain.
Lattice WDFs (i.e., WDFs derived from reference lters
in classical lattice conguration) often offer very attractive
solutions. Although they exhibit a relatively high stopband
sensitivity, for which allowance can be made by correspondingly increasing the coefcient word length, their passband
sensitivity is even better than that of ladder WDFs (i.e.,
WDFs derived from reference lters in classical ladder conguration). The reason for this is due to the fact that the
best possible lter performances are obtained for characteristic functions
[see Eq. (15)c] that are either even or
odd. If
is odd, the two-port N [Fig. 1(a)] is symmetric
and can then be implemented not only in ladder but also
in lattice conguration. If in a ladder conguration one of
the element values is changed, even slightly, N usually in-

Sensitivity Analysis

variably loses its symmetry. This unavoidably destroys the

oddness of
and thus forces all or at least some of the zeros
of
(s) to move away from the j axis, which in turn forces
the corresponding minima of () to move from zero to a
value greater than 0. A lattice structure, however, is inherently symmetric, that is, it is symmetric for any parameter
value, so that small changes of the parameters will usually
allow the minima of () to simply move along the axis.

Use of Sensitivities in Numerical Procedures

Optimization strategies constitute an important class of
numerical procedures used for circuits. The need for optimization arises not only during the design stage but also,
for example, during automated tuning and automated adjustment. A typical task then to be solved is to search for
that real parameter vector for which, for example, the
actual time response f(t, ) or, in the case of linear circuits,
the actual frequency response F(j, ) is as close as possible to a desired response f0 (t) or F0 (j), respectively. The
error to be minimized usually depends on |f(t, ) f0 (t)| or
|F(j, ) F0 (j)|, respectively, and the actual optimization
procedure may aim at nding the least-square or the minimax (minimum of the maximum deviation) error (possibly
after including some weighting function). Although a wide
class of other criteria may be of interest, the least-square
criterion has the advantage of analytic simplicity and the
minimax criterion that of being of particular engineering
relevance.
Except for a few special cases, optimization problems of
this sort cannot be solved by analytic procedures. Hence,
iterative numerical strategies are needed. Many of these
strategies involve the use of the sensitivities of the actual
response function with respect to the and thus the use
of either Df or DF [cf. Eq. (5)], and possibly generalizations
thereof (e.g., if f or F is actually to be replaced by a corresponding vector). As an example, if we are interested in an
operation lasting from an initial time t0 to a nal time t1
and if is the corresponding mean square error, requiring
to be real but allowing f and f0 to be complex functions,
the gradient D is given by

where the asterisk designates complex conjugation.

So far we have assumed that an ideal reference function
such as f0 (t) is uniquely dened. This is not strictly the case
in practice, especially if the design should be based on a criterion of minimax type. This is taken into account in design
centering, that is, in approaches that aim to keep the tolerances to be imposed on the components as small as possible in order to guarantee that the performance remains
within allowed limits. Alternatively, design centering aims
for yield optimization. Strategies for achieving such goals
can be quite involved and can again benet from using sensitivities.

Figure 3. (a) A three-port N terminated at port 3 by Z0 and

open-circuited at port 2, as needed for dening the basic transfer
function H21 = V2 /I1 as well as the transfer function H31 = I3 /I1 . (b)
Same three-port N in an arrangement obtained from (a) by inserting a voltage source V0 and a current source I2 . This augmented arrangement reduces to (a) for V0 = I2 = 0 but allows us to dene the
transfer functions H23 = V2 /V0 |I1 =I2 =0 and H32 = I3 /I2 |I1 =V0 =0 .

SOME GENERAL SENSITIVITY PROPERTIES

Sensitivity Calculations in the Frequency Domain
We rst consider a linear constant circuit operating in
steady state. We are interested in the sensitivity of some
transfer function H21 with respect to some impedance parameter Z0 . One nds that H21 /Z0 is equal to H31 H23 ,
where H31 is some transfer function from the input to the
location of Z0 , and H23 some other transfer function from
this location to the output. We show this by means of the example illustrated in Fig. 3. In Fig. 3(a) the circuit is drawn
as a three-port N fed by a current source at port 1 and
terminated by the impedance Z0 at port 3, while the opencircuited port 2 is provided in order to give access to the
desired output voltage V2 .
The second and third impedance equations of the threeport N can be written

Referring to Fig. 3(a), we thus obtain, since I2 = 0,

and, referring to Fig. 3(b)

Sensitivity Analysis

This shows that

which can also be obtained from Fig. 3(b) for I2 = 0 by assuming V0 to be the voltage caused by a small increase Z0
of Z0 , thus by writing

Equation (29) is immediately rendered even more practical if N is reciprocal, since then H23 = H32 . In order to
determine functions like H31 and H32 for all parameters
such as Z0 it then is indeed sufcient to analyze the circuit
once by exciting it at port 1 and once at port 2. This advantage can be extended to nonreciprocal circuits by replacing
N for the second analysis by its interreciprocal (adjoint),
that is, by a three-port for which the reciprocal elements
are unchanged while the nonreciprocal elements are replaced by those of opposite type (a gyrator with gyration
constant R, e.g., being replaced by one with R). Furthermore, the analysis of the interreciprocal circuit can essentially be reduced to that of the original circuit if the matrix
M to be inverted in the process of analysis is rst factored
in the form M = LU, L and U being lower and upper triangular matrices, respectively; indeed, the corresponding
matrix for the interreciprocal is MT = UT LT so that its corresponding factorization is immediately deduced. Finally,
all this can in full generality be derived in a very systematic
way by making use of Tellegens theorem, more precisely,
by a generalized version of the difference form of that theorem (3). On the other hand, an interesting special case
occurs if the voltage of actual interest is V1 rather than V2
so that H21 is equal to the input impedance Z at port 1. We
may then replace subscript 2 by 1 and obtain from Eq. (40)
in the reciprocal case, using also Y = 1/Z, Y0 = 1/Z0 ,

a result also known as the Vratsanos-Cohn theorem.

Similar results also hold true for linear constant
discrete-time circuits, the role of Z0 in Fig. 3 being then
assumed by any multiplier coefcient (29).
Sensitivity Calculations in the Time Domain
The generalized version of the difference form of Tellegens
theorem and the adjoint concept are even more useful for
the time-domain sensitivity analysis (31), as will be apparent from the brief, simplied outline given hereafter
(but nowhere restricted to linear circuits). Let thus v and
i be the vectors of all branch voltages and all branch currents, respectively, in the circuit under consideration, say,
the original circuit. The entries of the matrices DvT and
DiT form the totality of the sensitivities of all voltages and
currents with respect to all , which we may assume to
be real. All vectors D v and D i satisfy Kirchhoffs voltage
and current laws at the same time as v and i, respectively.
Consider then a second circuit, the adjoint circuit, with
the same topology as the original one, and let v and i be its
vectors of branch voltages and branch currents. These also

satisfy Kirchhoff s laws, say at any time instant t , where

t may be different from t. According to Tellegens theorem,

Let us examine the individual contributions to Eq. (31).

Suppose rst that some branch is formed by a resistance
described by some (possibly nonlinear) equation that involves at least one (and usually at most a few) of the and
that we may write as f(v , i , ) = 0. The quantities v and
i usually depend on all (a fact sometimes overlooked in
the literature). By differentiating f(v (t, ), i (t, ), ) with
respect to all the we can write

where

and where Dff concerns exclusively the partial derivatives with respect to the that appear explicitly (via ) in


f ( , i , ). Consequently, provided v and i are related
in such a way that

the vector

which is indeed the contribution of branch to the left

hand side of Eq. (31), reduces to the simple vector (i /fv )Df.
This vector (most of whose components are zero) is independent of any of the aforementioned sensitivities. Clearly, Eq.
(32) denes a resistance in the adjoint circuit. In the linear
constant case we have f(v , i , ) = v Ri and thus fv = 1,
fi = R; hence, Eq. (32) then denes a resistance of exactly
the same type.
For an algebraically dened element involving two
branches, the situation is similar and, in the linear case,
again reduces to the known results. If an appropriate range
of algebraic two-port elements is available, the only other
elements needed for generating the remaining elements
of usual interest are, for example, linear capacitances. As

sume thus that some branch is described by i = Cv ,

where C is a constant and the dot on top of the letter desig
nates time derivation, d/dt. Consequently, provided v and


i are related by i = Cv , that is

the contribution of Eq. (33) becomes equal to the vector

(where one of the components of DC is equal to 1 and all

others are equal to zero).
In order for Eq. (34) to make sense, let t0 again be the
initial time and t1 the nal time of interest [cf. Eq. (28)]

10

Sensitivity Analysis

and dene t = t1 t. We then have

which is the same type of equation as for the capacitance

in the original circuit, but the adjoint circuit is assumed to
run in opposite time direction, its initial time t = 0 corresponding to t = t1 and its nal time t = t1 t0 corresponding
to t = t0 .
In Eq. (35) the second term is independent of the sensitivities, as desired, but the contribution due to the rst
term can be made to vanish if we actually have to carry
out a time integration between limits as in Eq. (28). In this
case, the derivative d/dt in Eq. (35) yields

However, the initial value v (t0 ) is imposed independently

of , that is, Dv (t0 ) = 0. On the other hand, we may impose
the initial conditions of the adjoint circuit to be zero, that

is, v (0) = 0. Hence Eq. (36) is then indeed equal to zero.
We still have to consider the access to the circuit. Assume thus that branch 1 consists of an independent voltage
source in the original circuit and of a simple short circuit in

the adjoint circuit. We then have Dv1 = 0 and v 1 = 0, so that
Eq. (33) vanishes for = 1. Similarly, assume that branch
2 is simply open-circuited in the original circuit and that
it consists of some current source in the adjoint circuit, so

that Eq. (33) reduces to i 2 Dv2 for = 2.
These results can, for example, be used in the following way. Assume that the behavior of the original circuit
has been calculated for a rst choice of . Values such as
fi and fv in Eq. (32), etc., are then known so that the equations governing the elements of the adjoint network are
also known, and the same is true for vectors such as Df
mentioned subsequently to Eq. (33). The initial conditions
of the adjoint circuit being zero, the only freedom left is the

choice of i 2 (t ). To see how this can be xed, consider the determination of D in an optimization problem such as the
one that had led to Eq. (28). We assume that the present
2 is actually the function to be optimized; it is therefore
identical to the function designated f in Eq. (28), the desired behavior of 2 thus being f0 . Hence, we can identify

i 2 (t )Dv2 with the integrand in Eq. (28) by choosing

If we then integrate Eq. (31) from t0 to t1 and take the

real part, the contribution of Eq. (33) for = 2 becomes
equal to D , while, according to what we have seen, all
other contributions are known. Hence, D can be determined from the resulting equation. Extensions to multiple
inputs and outputs, to time-varying original circuits, and
to inclusion of weighting functions are quite immediate.
Note that the above analysis does not exclude v and i to be
complex, although in the case of nonlinear circuits one is
usually only dealing with real quantities.
Sensitivity Invariants
The steady-state behavior of a linear circuit is entirely determined by quantities that either have the dimension of

a resistance or are dimensionless. Let F again be any function of interest (impedance, admittance, transfer function,
loss, phase), let L, C, R, and n be the vectors of inductive,
capacitive, resistive, and dimensionless parameters xing
the circuit behavior, and let a and b be arbitrary auxiliary
parameters. Since F is homogeneous in any set of independent dimensions, we can write

where m = +1, 1, or 0. Differentiating Eq. (37) with respect

to a and b and then setting a = b = 1, we obtain

The left-hand sides in Eqs. (38) and (39) comprise simple

combinations of individual sensitivities, but the right-hand
sides depend only on m and on the behavior of F in terms of
. A given function F, however, can be realized by several
or even innitely many distinct circuits (32, 33), and for
each one of these the individual sensitivities will usually
be different. Yet, the overall values of the left-hand sides
in Eqs. (38) and (39) are independent of the specic realization; they are therefore known as sensitivity invariants.
Obviously, they can easily be applied in various specic situations. As an example, we have

and therefore, if F is a transmittance and thus ln

F = j, we can derive

where is again the group delay [see Eq. (24)c].

Other interesting sensitivity expressions can be obtained for a two-port N operated as in Fig. 1(a). Using
known expressions of S11 and S21 [see Eq. (15)] in terms
of, for example, the impedance matrix of N, one nds in
view of Eq. (16),

where Eq. (43) is obtained by dening S22 analogously to

S11 . These results can, for example, usefully be combined
with Eqs. (38) and (39), especially if N does not comprise
any further resistive parameter. They also hold true for

Sensitivity Analysis

and dened by + j = ln S12 , S12 referring to the direction of transmission opposite to that in Fig. 1(a).
Unfortunately, Eqs. (38) and (39) do not involve sums of
magnitudes of sensitivities. Hence, they do not in general
offer upper bounds, as would be desirable, but only lower
bounds, for example

11

(62) reduces simply to j2W / , where

W being thus the average energy stored in the corresponding element. We have

Pmax being the maximum power available from the source,

the reectance, and r the corresponding phase. One nds
M1 = j|I1 |2 X/ , altogether thus
In some important special cases, however, some much
more useful conclusions can be drawn. Thus, let F be the
input impedance Z(j) = jX() of a lossless circuit. Let us
modify this circuit by adding to some inductance L a series

resistance R . This amounts to replacing L by L (1 j ),

with = R /L , and thus, in a rst approximation, to
adding to jX a resistive term X/ ln L . Since due to passivity this term must be nonnegative, we conclude, 0,
assuming that for any inductance we have X/L 0. Similarly X/C 0 for any capacitance C . Consequently, since
due to Eq. (40),

all terms on the left-hand side of this expression are nonnegative so that none of them can grow excessively.
A similar conclusion can be drawn if F is a transmittance. The appearance of the quantity just given will indeed add to + j a rst-order correction (j/ ln L + /
ln L ) . If = 0, passivity now requires /L 0, and similarly /C 0, that is, the argument used for Eq. (44) is
also valid for Eq. (41)b. This holds true at least for frequencies at which () vanishes and thus, in practice, in
the entire passband of good lters, conrming the observations we had made with respect to Eq. (22). In fact, it
holds true even more generally as will be seen in the next
section.
Sensitivity and Energy
Many sensitivity quantities are related to power and energy expressions (3436). A few important examples for
this will be discussed hereafter. We rst consider the
impedance Z(j) = jX() of a circuit N composed of inductors, capacitors, ideal transformers, and gyrators. Assume
it to be fed by a source of voltage E and internal resistance
R1 [Fig. 1(b)], the internal branches of N to be numbered
= 2, . . . , n, and the branch voltages V and currents I to
be oriented as usual, while V1 = V , I1 = I. The generalized
version of Tellegens theorem allows us to write

where the rst equality can be veried by using the denition of . The result of Eq. (46) conrms in particular that
X/ 0 for 0, while we obtain from Eq. (44)

the sum being extended over all branches that consist either of an inductor or a capacitor and W being thus the
total average energy stored in N.
Next, we apply the same analysis to the two-port arrangement of Fig. 1(a) in which N is composed of the same
types of elements as before. The rst equation, Eq. (45), has
to be replaced by

the internal branches of N being thus numbered = 3, . . . ,

n. For the M in the right-hand side of Eq. (64) everything
remains as before. Using Eq. (15), one nds for branches
consisting of an inductor or a capacitor
M 1 + M2
W1

= S11
S11 = j
2Pmax 1
Pmax 1
where the second equality holds in view of Eq. (64) and
where we have added a subscript 1 to Pmax and W in order
to make clear that the source is applied at port 1. After
moving E into the terminating branch at port 2, an expression similar to Eq. (64) can be written, with W2 and
Pmax2 = |E|2 /4R2 taking the role of W1 and Pmax1 . Adding the
two expressions and taking the imaginary part, we obtain
altogether




(|S11 |2 11
+ |S22 |2 22
+ |S21 |2 21
+ |S12 |2 12
) = (


where we have made use of S 11 S 11 = |S11 |2 (ln S11 ) and

11 = Im ln S11 , etc. But for a lossless two-port the scattering parameters satisfy

the prime indicating, as also everywhere hereafter, a partial derivative with respect to some parameter occurring
inside of N. If is an inductance or a capacitance characterizing some specic branch , the summation  in Eq.

W1
W2
+
)
Pmax 1
Pmax 2

and therefore also 11 + 22 = 21 + 12 . Hence, Eq. (69)

simplies to
(11 + 22 )
(21 + 12 )
W1
W2
=
= (
+
)
ln
ln
Pmax 1
Pmax 2

12

Sensitivity Analysis

In particular, if N is reciprocal, thus if S21 = S12 and hence

21 = 12 =

the upper sign holding for = L and the lower one for
and P 1 are, in general, complex,
= C . The quantities W
but their magnitudes have the energy and power interpretations encountered before.

This shows that / 0 and also, together with Eq. (41b),

that
BIBLIOGRAPHY
where W01 and W02 are the total average energies stored
in N when E is located in the terminating branch of port 1
and 2, respectively.
If N is not only reciprocal (S12 = S21 ) but, more specifically, symmetric (S22 = S11 ) or antimetric (S22 = S11 ), in

which case 11 =  , we can proceed directly from Eq. (48)
instead of going via Eq. (49). This yields

Consider still the real part of the second equality in Eq.

(48) [or, equivalently, take the derivative with respect to
of the third equation, Eq. (50)]. Using

we obtain

that is,

The last expression allows us to compute the sensitivities

of in terms of those of S11 , in fact for any referring
to an element inside of N. Since = 0 implies S11 = 0, the
passband sensitivity theorem is immediately conrmed.

The sensitivities S 11 can be determined using relations
such as Eq. (29). To illustrate this, let us replace the resistive source in Fig. 1(a) by an equivalent current source
with parallel resistance R1 . We must, of course, be aware
that the meanings of N, V1 , I1 , V2 , and I2 , in Fig. 1(a) differ from those in Fig. 3(a). Furthermore, since the output
quantity of interest is now V1 (cf. Eq. 15b ) we may, when
addressing Fig. 3(a), assume the access provided by the terminals 2,2 to be in fact an access to 1,1 . Altogether we may
thus assume in Fig. 3(a) to have I1 = E/R1 , V1 = V2 , I3 = I ,
and V3 = V . In particular, the transfer functions H21 and
H31 dened in the section entitled Sensitivity Calculations
in the Frequency Domain are now given by H21 = R1V1 /E
and H31 = R1 I /E, while either Z0 = jL or Y0 = 1/Z0 = jC .
A similar relation holds true for H23 , which is also needed
in Eq. (29) . On the other hand, if we restrict ourselves to
the reciprocal case we may immediately use Eq. (30) with
Z = H21 . On the other hand, in view of Eq. (15)b, we have


S 11 = 2H 21 /R1 = 2Z /R1 . Finally, one nds for branches consisting of an inductor or a capacitor

1. R. Tomovic, Sensitivity Analysis of Dynamic Systems, New

York: McGraw-Hill, 1964.
2. K. Geher, Theory of Network Tolerances, Budapest: Akademiai
Kiado, 1971.
3. R. K. Brayton and R. Spence, Sensitivity and Optimization,
Amsterdam: Elsevier, 1980.
4. A. Deif, Sensitivity Analysis in Linear Systems, Berlin:
Springer-Verlag, 1986.
5. M. Eslami, Theory of Sensitivity in Dynamic Systems, Berlin:
Springer-Verlag, 1994.
6. H. Bode, Network Analysis and Feedback Amplier Design,
New York: Van Nostrand, 1945.
7. A. G. J. Holt and M. R. Lee, A relationship between sensitivity
and noise, Int. J. Electron., 26: 591594, 1968.
8. A. Fettweis, Wave digital lters: theory and practice, Proc.
IEEE, 74: 270327, 1986,75: 729, 1987.
9. A. Fettweis, On assessing robustness of recursive digital lters, Eur. Trans. Telecommun., 1: 103109, 1990.
10. F. F. Kuo and W. G. Magnuson, Jr., (eds.), Computer Oriented
Circuit Design, Englewood Cliffs, NJ: Prentice-Hall, 1969.
11. M. Hasler and J. Neirynck, Electric Filters, Dedham, MA:
Artech House, 1986.
12. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.
13. I. M. Filanovsky, Sensitivity and selectivity, in W.-K. Chen
(ed.), The Circuits and Filters Handbook, Boca Raton, FL: CRC
Press and IEEE Press, 1995, pp. 22052236.
14. W.-K. Chen (ed.), The Circuits and Filters Handbook, Boca Raton, FL: CRC Press and IEEE Press, 1995.
15. A. Fettweis, Filters met willekeurig gekozen dempingspolen
en Tschebyschewkarakteristiek in het doorlaatgebied, Tijdschrift Ned. Radiogenootschap, 25: 337382, 1960.
16. H. J. Orchard, Inductorless lters, Electron. Lett., 2: 224225,
1966.
17. H. J. Orchard, Loss sensitivities in singly and doubly terminated lters, IEEE Trans. Circuit Syst., CAS-26: 293297,
1979.
18. R. Boite, H. Leich, Les Filtres Numeriques, 3rd ed., Paris: Masson, 1990.
19. G. C. Temes andS. K. Mitra (eds.), Modern Filter Theory and
Design, New York: Wiley, 1973.
20. A. Fettweis, Transmultiplexers with either analog conversion
circuits, wave digital lters, or SC-Filters, IEEE Trans. Commun., COM-30: 15751586, 1982.
21. G. S. Moschytz (ed.), MOS Switched-Capacitor Filters: Analysis and Design, New York: IEEE Press, 1984.
22. R. Gregorian and G. C. Temes,Analog MOS Integrated Circuits
for Signal Processing, New York: Wiley, 1986.
23. R. Unbehauen, A. Cichocki, MOS Switched-Capacitor and
Continuous-Time Integrated Circuits and Systems, Berlin:
Springer-Verlag, 1989.

Sensitivity Analysis
24. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog Filters: Passive, Active RC, and Switched Capacitor, Englewood Cliffs, NJ: Prentice-Hall, 1990.
25. L. P. Huelsman, Active and Passive Filter Design, New York:
McGraw-Hill, 1993.
26. S. K. Mitra, J. F. Kaiser (eds.), Digital Signal Processing, New
York: Wiley, 1993.
27. C. Toumazou, J. B. Hughes, N. B. Battersby (eds.), Switched
CurrentsAn Analogue Technique for Digital Technology,
London: Peter Peregrinus, 1993.
28. Y. Tsividis, J. A. Voorman (eds.), Integrated Continuous-Time
Filters: Principles, Design, and Implementations, New York:
IEEE Press, 1993.
29. A. Fettweis, Digital circuits and systems, IEEE Trans. Circuits
Syst., CAS-31: 3148, 1984.
30. A. Fettweis, Image parameter and effective loss design of symmetrical and antimetrical crystal band-pass lters, Revue HF
tijdschrift, V (11): 318, 1963.
31. S. W. Director and R. A. Rohrer, The generalized adjoint network and network sensitivities, IEEE Trans. Circuit Theory,
CT-16: 318323, 1969.
32. J. D. Schoefer, The sensitivity of minimum-sensitivity networks, IEEE Trans. Circuit Theory, CT-11: 271276, 1964.
33. M. L. Blostein, Sensitivity analysis of parasitic effects in
resistance-terminated LC-two-ports, IEEE Trans. Circuit Theory, CT-14: 2125,1967.
34. W. Poschenrieder, Steile Quarzlter groer Bandbreite in
Abzweigschaltung, Nachrichtentechnische Z., 9: 249253,
1956.
35. G. Kishi and T. Kida, Energy theory of sensitivity in LCR networks, IEEE Trans. Circuit Theory, CT-14: 380387, 1967.
36. G. Temes, H. J. Orchard, First-order sensitivity and worst
case analysis of doubly terminated reactance two-ports, IEEE
Trans. Circuit Theory, CT-20: 567571, 1973.

ALFRED FETTWEIS
Ruhr-Universitat
Bochum ,
Bochum, Germany

13

BROADBAND NETWORKS

589

Antenna

Signal
generator

Nt

Nr
Load
Receiver
site

Transmitter
site

Figure 1. Generic block diagram of a high-frequency wireless communication system.

BROADBAND NETWORKS
The problem of broadband matching is one of the major concerns when working with high-frequency communication systems. All broadcasting networks such as radio and television,
and all wireless communication networks, such as cellular
telephones and satellite networks, are the most frequently encountered examples of such systems.
A typical high-frequency wireless communication system
contains two major sites, namely, a transmitter and a receiver
(Fig. 1). On the transmitter site, the generated signal must
be properly transferred to the antenna, preferably over a nondissipative (lossless) network so that maximum power of the
generated signal is pumped into the antenna. Similarly, on
the receiver site, the received signal of the antenna is transferred over a lossless matching network and dissipated at the
user end. The user end may be, for example, a radio, a TV
set, or a headphone. In this case, again, the role of the match-

ing network is to provide the maximum power transfer of the

received signal to the user end. In the literature, several
terms are associated with the nondissipative power transfer
network, such as impedance matching network, equalizer,
lossless two-port, lossless network, or interstage-equalizer these terms are all used interchangeably. The classical
broadband matching theory deals with the proper design of
the lossless matching networks between prescribed terminations.
It is common that the signal-generation section of the
transmitter can simply be modeled as an ideal signal generator in series with internal impedance ZG. The transmitter antenna will behave as a typical passive load termination ZL to
the lossless power transfer two-port E (Fig. 2). Similarly, the
receiver antenna can be considered as an ideal signal source
with an internal impedance ZG. The user end of the receiver
site can also be considered as a dissipative load ZL to the lossless two port E.
In the discussion above it is evident that both transmitter
and receiver sites present a similar model as far as the signal
flow is concerned. In both cases, the crucial issue is the maximum power, transferred from the generator ZG to load ZL.
Therefore, once the signal generator and the load are given,
the system performance can be optimized with the proper design of the nondissipative or lossless two-port E.
In all the cascaded high-frequency systems, one is faced
with the problem of power transfer between cascaded sections
or so called interstages. As a principal, using Thevenins
theorem, the left site of the interstage can be modeled as an
ideal signal generator EG in series with an internal impedance ZG. Similarly, the right site is simply regarded as a passive load ZL, as shown in Fig. 2.

PA

PL

+
E

Generator

ZG

ZL

Load

Figure 2. Power-transfer problem between a generator and a load

network over a lossless equalizer.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

590

BROADBAND NETWORKS

T( )

T0

Figure 3. Rectangular flat transducer power gain characteristics

with sharp roll-off over a passband (1 to 2), which describes ideal
power transfer between generator and load through a lossless matching network.

Hence, the classical broadband-matching problem is defined as one of constructing a lossless reciprocal two-port or
equalizer so that the power transfer from source (or generator)
to load is maximized over a prescribed frequency band.
The power-transfer capability of the lossless equalizer or
so called matching network is best measured with the transducer power gain T, which is defined as the ratio of power
delivered to the load PL by the available power PA of the generator; over a wide frequency band. That is,
T=

PL
PA

(1)

Ideally, the designer demands the transfer of the available

power of the generator to the load, which, in turn, requires
the flat transducer power gain characteristic in the band of
operation at a unitary gain level with sharp rectangular rolloff, as illustrated in Fig. 3. But unfortunately, the physics of
the problem permit the ideal power transfer at only a single
frequency. In this case, the equalizer input impedance Zin is
conjugately matched to the generator impedance ZG. Therefore, the design of a matching equalizer over a wide frequency
band with high and flat gain characteristics presents a
very complicated theoretical problem. It is well known that
the terminating impedances ZG and ZL impose the possible
highset flat gain level over frequency band B, so called the
theoretical gain bandwidth limitation of the matched
system.
Before introducing the design methodologies it is important to classify the broadband matching problems.
Single Matching. This is a matching problem where either
one of the passive terminations of the equalizer is resistive; the other is complex or frequency dependent
[Fig. 4(a)].
Double Matching. This is a matching problem where both
passive terminations of the equalizer are complex [Fig.
4(b)].
Active Matching. This is a matching problem of active devices. A typical example of an active matching is the
design of a microwave amplifier [Fig. 4(c)].
It should be mentioned that the filter or the insertion loss
problem might also be considered as a very special form of the

broadband matching problem, which deals with the resistive

generator and resistive load [Fig.4(d)]. In this respect, wellestablished filter design techniques may be employed for
broadband matching problems where appropriate.
There are two main approaches to the solution of broadband matching problems, namely, (1) analytic solutions and
(2) computer-aided solutions. The classical procedure is
through analytic gain-bandwidth theory (1). Solutions of the
second type are accomplished by numerical optimization and
are referred to as real frequency techniques, after Carlin (2).
In both cases it is optimal to seek the achievement of maximum level of minimum gain within the passband.
The analytic gainbandwidth theory is essential to understanding the nature of the matching problem but, in general,
is not accessible beyond simple problems. The real frequency
computer-aided solutions, however, are very practical and
easy to carry out for more complicated problems.
In this article, first the analytic matching theory will be
briefly discussed. Then several real frequency approaches to
the problem will be summarized.
Generally, the lossless matching network to be designed
can be described in terms of two-port parameters (such as
impedance, admittance, chain, real, or complex normalized
regularized scattering or transmission parameters), or by
means of driving point so-called Darlington immitance or
bounded real (real normalized) reflection coefficient.
At this point it is appropriate to state the modified version
of Darlingtons famous theorem: (3).
Theorem. Any positive real impedance (Z) or admittance
(Y) function or corresponding bounded real reflection coefficient S (Z 1)/(Z 1) or S (1 Y)/(1 Y) can be
represented as a lossless two-port terminated in unit resistance. The resulting lossless two-port is called the Darlington
equivalent (Fig. 5).
Based on the fundamental gainbandwidth theory introduced by Bode (1), the analytic approach to single matching
problems was first developed by Fano (4), using the concept
of Darlington equivalent of the passive load impedance
(ZL). In Fanos approach, the problem is handled as a pseudofilter or pseudo-insertion loss problem, since the tandem
connection of the lossless equalizer E and Darlingtons load
equivalent L is considered as a whole lossless filter F (Fig. 6).
Later, Youla (5) proposed a rigorous solution to the problem using the concept of complex normalization. In order to
solve the double-matching problem, Youla described the lossless matching network in terms of complex normalized scattering parameters with respect to frequency dependent impedances of generator and load terminations. Youlas theory
provided an excellent solution to handle the single-matching
problems, but was not practical to solve the double-matching
problems since the realizability conditions based on the complex normalized scattering parameters of the matching equalizer was complicated to implement.
The complete analytic solution to the double-matching
problem has been more simply formulated by the main theorem of Yarman and Carlin (68), which relates to the real,
and the complex normalized-regularized generator and load
reflection coefficients of the doubly matched system. This theorem enables the designer to fully describe the doubly
matched system in terms of the realizable"-real normalized

BROADBAND NETWORKS

591

RG
+
E

EG

ZL

ZB

SF,ZF
(a)
ZG
+
E

EG

ZF

ZL

ZB
(b)

+
EK

Signal
generator

Load

Ak 1

Ak
ZG

ZL
(c)

Figure 4. (a) Single-matching problem

between a resistive generator and a
complex load impedance. (b) Doublematching problem between a complex
generator and a complex load impedance. (c) Active matching problem which
involves design of interstage matching
networks for multistage microwave amplifiers. (d) Filter or insertion loss problem in view of broadband matching: A
special form of the matching problem between a resistive generator and a resistive load.

RG
+
F

EG

ZF

RL

ZB
(d)

RG
+

Lossless
two-port

EG

RL

EL

Z,S
Figure 5. Darlington representation of a positive real impedance or
admittance function or a bounded real reflection function.

F11

ZL

F22

Figure 6. Single-matching problem with Darlington equivalent representation of a load impedance.

592

BROADBAND NETWORKS

(or unit normalized) scattering parameters after replacing

generator and load with their Darlington equivalents, as in
the filter design theory.
Instructional accounts of gainbandwidth theory for both
single- and double-matching problems have been elaborated
by Chen (9).
In the following sections, the essence of Fanos and Youlas
theories will be reviewed. Subsequently, an attempt will be
made to introduce analytic solutions for single- and doublematching problems under the unified approach. Then, modern computer-aided design (CAD) or the real frequency techniques which are employed to construct wide band matching
networks will be summarized (10). Finally, practical design
techniques to construct matching networks with mixed
lumped and distributed elements will be discussed.
In order to understand the analytic theory of broadband
matching, it may be appropriate to first review the filter or
insertion loss problem, which constitutes the heart of the unified approach and clarifies the basic properties of lossless
two-ports.
FILTER OR INSERTION LOSS PROBLEM
IN VIEW OF BROADBAND MATCHING
A typical filter or insertion loss problem is depicted in Fig.
4(d). In view of broadband matching, the problem is stated
as follows:
PROBLEM. Given the resistive generator R1 and the resistive load R2, construct the reciprocal-lossless filter two-port
F to transfer the maximum power of the generator to the load
R2 only over the passband 1 to 2; stop it otherwise.
In this problem, it is suitable to describe the reciprocallossless filter two-port F in terms of its real (or equivalently
unit) normalized scattering matrix F with respect to port normalization numbers R1 and R2. For unit normalization

F=

F11
F21

F12
F22

h
,
g
f
= ,
g

F12

F21 =
F22

f
g
h
=
g

(5)

or

F11F11 + F21 F21 = 1

or, on the j axis

|F21 |2 = 1 |F11 |2
(6a)

F12F11 + F21 F22 = 0

or, on the j axis

F22 = F11
F12/F21
(6b)

F22F22 + F12 F12 = 1

or, on the j axis

|F22 |2 = 1 |F12 |2
(6c)

F11F12 + F21 F22 = 0

or, on the j axis

F11 = F22
F21 /F12
(6d)

where I designates a 2 2 unitary matrix, superscript T indicates the transpose of a matrix, and the asterisk indicates
either paraconjugate as subscript or complex conjugate as superscript.
The complex frequency variable is taken as s j j as
in lumped filter design, and the equation set Eqs. (6a6d) can
be written in terms of the canonic polynomials h(s), f(s), and
g(s):
hh = gg ff

(7a)

h(s)h(s) = g(s)g(s) f (s) f (s)

(7b)

or in the open form

In terms of the canonic polynomials f and g, the transducer

power gain is given by

(2)

f ( j) f ( j)
g( j)g( j)

(8a)

f (s) f (s)
g(s)g(s)

(8b)

or in complex variable s,

(3)

If the filter consists of one kind of elements (i.e., either

lumped or distributed elements), the real normalized bounded
real (BR) scattering parameters are given in the following, socalled Belevitch canonic form (11)

F11 =

FT F = I

T (2 ) =

The system performance of the filter two-port F is measured

with the transducer power gain T() given by
T () = |F21 ( j)|2

in the design of reciprocal lossless two-port filters, which require equal F12 and F21, (i.e., F21 F12). In this case
f * /f 1, where the plus sign is applied if f is even; the
minus sign if f is odd.
It is well known that a lossless two-port must possess a
bounded real paraunitary scattering matrix. That is,

(4)

where f * /f and h, f, g are the real polynomials in complex

variable s j for lumped element design or in
j if F is constructed with equal length or commensurate
transmission lines. Here, designates the Richards variable,
given by tanh(s) (12). In practice, one is mainly interested

T (s2 ) =

In essence, Eq. (8) dictates all the performance measures of a

lossless-reciprocal filter. When the transducer gain T is other
than zero, the lossless system allows the signal transmission.
However, there are complex frequencies sI such that T(s2)
is zero. Eq. (8b) indicates that the forward and backward signal transmission is dictated by F21 and F12, respectively.
Therefore, the function F(s) F21(s)F12(s) determines forward
and backward signal transmission of the lossless reciprocal
filter F. In the following the definition of transmission zeros
(8) are given:
Definition. Transmission zeros of a lossless two-port are the
closed right half plane (RHP) zeros of F21(s)F12(s) F(s) or,
more explicitly, the closed RHP zeros of the expression
f (s) f (s)
F (s) =
g2 (s)

(9)

BROADBAND NETWORKS

where all possible common factors between the numerator

and the denominator have been canceled and the zeros on the
j-axis are counted for their half multiplicity.
It should be noted that for reciprocal structures, F
f 2(s)/g2(s) since F21(s) F12(s). In this case, transmission zeros
of the lossless reciprocal two-port will simply be the closed
RHP zeros of transmittance parameter F21(s) f(s)/g(s) with
even multiplicity, which obviously overlaps with the zeros of
transducer gain function T(s2) of Eq. (8b). Transmission
zeros at infinity are considered as the real frequency zeros on
the j axis and determined as the degree difference between
the polynomials g(s) and f(s).
Construction of Doubly Terminated Lossless-Reciprocal Filters
Based on the above theoretical overview, design steps of doubly terminated lossless reciprocal filters are straightforward.

Analytic Approach to Single-Matching Problems

Single matching problems deal with the construction of a
broadband lossless equalizer E, which is placed between a resistive generator and a complex load, as shown in Fig. 4(a).
In Fanos theory, the frequency dependent non-Foster load
is replaced with its Darlingtons equivalent (Fig. 7). Let ZL(s)
denote impedance of the non-Foster load, L Lij scattering
parameters of its lossless Darlingtons equivalent and let the
unit normalized scattering parameters of equalizer E be designated by E Eij. The cascaded connection of equalizer E
and L is represented by F, whose scattering parameters are
denoted by F Fij.
Scattering Description of the Darlington Equivalent of Load
Network (68). Employing paraunitary properties of the lossless load equivalent network L, as stated in Eqs. (6a6d), the
unit normalized scattering parameters are given in terms of
the impedance ZL(s) NL(s)/DL(s):

Step 1. Choose an appropriate transducer power gain

form T(2) which includes all the desired transmission
zeros of the doubly terminated system. Any readily
available form such as Butterworth, Chybeshev, elliptic,
or Bessel type of function may be suitable, depending
on the application.
Step 2. Using the Belevitch notation, spectral factorization
of the numerator and the denominator of the selected
gain function T(s2) is carried out to obtain the polynomials f(s) and g(s). At this stage it should be pointed out
that the numerator f(s)f(s) must be of even multiplicity so that F21 F12. The polynomial g(s) is uniquely
determined by the spectral factorization of the denominator of T(s2) since it must be strictly Hurwitz. Hence,
F21 F12 f /g is determined.
Step 3. The polynomial h(s) is formed via spectral factorization of hh as given by Eq. (7a). However, zeros of
*
hh are freely divided between the polynomials h and
*
h*. The sole requirement in the allocation is that each
zero of one polynomial is reflected to the image location
in the other polynomial, as described in Ref. 11. Thus,
F11 h/g and F22 h* /g are determined within an
analytic all-pass , which also includes RHP zeros of
f(s). The general solution to the factorization problem is
F11 = F11m

ANALYTIC SOLUTION OF THE BROADBAND

MATCHING PROBLEM
In this section basic guidelines of Fanos and Youlas approaches are given and they are linked by means of the main
theorem of Yarman and Carlin which, in turn, leads to the
unified approach to designing broadband matching networks
(8).

ZL 1
ZL + 1
2WL
=
ZL + 1
Z 1
= L bL L
ZL + 1

L11 =

(10a)

L21

(10b)

L22

(10c)

where

DL
DL
nL
L (s) =
nL
WL = nL /DL

bL (s) =

(10d)
(10e)
(10f)

nL* is a polynomial formed on the closed RHP zeros of

RL(s2) WLWL*, RL(s2) being the even part of ZL(s). In
Belevitch form,

(10)

where F11m is the minimum phase solution.

Step 4. Finally, the filter is constructed by means of Darlingtons synthesis procedure of driving point impedance
Z (1 F11)/(1 F11) as a lossless two-port in unit
termination (8).

593

hL
gL
f
= L
gL

L11 =

(11a)

L21

(11b)

L22 = L

hL
gL

(11c)

where

hL (s) = NL (s) DL (s)

(11d)

f L (s) = 2nL (s)

(11e)

gL (s) = NL (s) + DL (s)

(11f)

Transmission Zeros of the Load Network. As in Eq. (9), transmission zeros of the load network are defined as the zeros of
the function
4RL (s2 )
FL (s) = L221 = bL (s)
[ZL (s) + 1]2

(12a)

594

BROADBAND NETWORKS

RG
+
G

EG

Figure 7. Double-matching problem with

Darlington equivalent representation of
load and generator impedances.

RL

GEL
F11

ZG

or

ZL

F22

of Eq. (16). Thus, the complex normalized regularized reflectance SYL(s) is, as defined in Youla sense,
4n2L (s)
FL (s) =
g2L (s)

(12b)

In Fanos work, the power performance of the singly matched

system is measured in terms of the unit normalized scattering
parameter F21 of F. In fact, the transducer power gain of the
system is given as in Eq. (3):
T (2 ) = |F21 |2 = 1 |F22 |2

T (2 ) =

|E21 | |L21 |
|1 E22 L11 |2
2

(14)

One may analytically handle the single-matching problem as

a pseudo-filter problem as in Fanos theory, which can be
stated as:
Theory. Construct the lossless two-port F with preferred
gain characteristic as an insertion loss problem subject to
load constraints so that the load two-port L is extracted from
F yielding the desired matching network E.
In Youlas Theory, however, matching network E and the
load ZL are treated as separate entities and the transducer
power gain of the singly matched system is defined in terms
of the complex normalized reflectance SCL at the load end.
That is,
T (2 ) = 1 |SCL |2

(15)

where SCL is given by

SCL =

ZB ZL
ZB + ZL

ZB (s) ZL (s)
ZB (s) + ZL (s)

(17)

In Youlas theory, instead of load extraction, complex normalized regularized reflectance is directly constructed from the
analytic form of transducer power gain, satisfying the gainbandwidth restriction. Then, the driving point impedance ZB
is obtained as a realizable positive real function as

(13)

In terms of the unit normalized scattering parameters of E

and L,
2

SYL = bL (s)

ZB (s) =

2bL (s)RL (s2 )

ZL (s)
bL (s) SYL (s)

(18)

where RL(s2) designates the even part of ZL(s).

Finally, employing the Darlington procedure, ZB(s) is synthesised, yielding the desired lossless matching network E in
resistive termination.
Based on the definition of the complex normalized scattering parameters of the two-ports involved, extension of Youlas
theory to double-matching problems is not a straightforward
matter (5). Therefore, what is called the unified approach to
broadband-matching problems is presented in the following
section. The unified approach combines Youlas and Fanos
works under a unique format by means of main theorem of
Refs. 6 and 7 and makes the analytic theory accessible for
many practical problems.
Before dealing with the main theorem, look at the definition of the bounded real (BR) analytic-complex normalized reflectance SYCL in the Yarman and Carlin sense (7).
Definition: BR-Analytic-Complex Normalized Reflectance. The reflectance SYCL defined by the expression
SYCL =

WL ZB ZL

WL ZB + ZL

(19)

is called the BR-Analytic-Complex Normalized Reflectance in

the Yarman and Carlin sense.
(16)

and ZB designates the driving point Darlington impedance of

E at the back end (5).
In this representation, the load impedance ZL is regarded
as the complex normalization number at the output port of
E. Clearly, in the complex s domain, SCL is not analytic due
to RHP poles of ZL(s). In order to make SCL analytic, an allpass factor bL(s) is introduced into SCL to cancel the RHP poles

Clearly, Eq. (19) can be related to SYL, described in the Youla

sense by Eq. (17):
SYCL (s) = L (s)SYL (s)

(20)

Furthermore, if the load is simple, consisting of a few reactive elements having all the transmission zeros at finite frequencies or at infinity, all-pass product L(s) 1 and SYCL(s)
SYL(s), which is the case in many engineering applications.

BROADBAND NETWORKS

Nevertheless, with proper augmentation of the load ZL, one

can make nLnL a perfect square yielding nL /nL 1. Thus,
*
*
invoking superfluous factors, one can always obtain SYCL(s)
SYL(s) as is described in Ref. (8). Therefore, in the following
sections SYCL(s) and SYL(s) will be used interchangeably. Now,
look at the main theorem (68).

595

and only if, at each transmission zero of the load, s0, of order k, the coefficients of the Taylor expansion of
bL (s) SYCL (s) =

2RL bL
[ZB + ZL ]

(21)

about s0 satisfy the following constraints:

Main Theorem. Referring to Fig. 6, let F22 be the unit normalized back end reflectance of the system F constructed by
the cascade connection of the lossless two-port E and the lossless two-port L. Then, F22 is equal to the analytic complexnormalized reflectance defined in the YarmanCarlin sense
at the input port of L. That is, F22(s) SYCL(s).

Class A. Res0 0:
bLr = SLr

The load network L is directly extracted from F by

applying the well established gain bandwidth restrictions of Youla on the analytic complex normalized reflectance SYCL(s) defined in the YarmanCarlin sense, in
a straightforward manner.
In the course of the extraction process, the entire structure F is described in terms of its realizable, unit normalized, bounded real scattering parameters without hesitation as in Fanos theory, since F22(s) SYCL(s) by the
main theorem.
These unique results constitute the basis of the unified approach.
One must now classify the transmission of zeros of the
load. Then, introduce the modified version of the Youlas theorem on gainbandwidth restrictions, allowing the extraction
of the load network L from the combined structure.
Classification of the Transmission Zeros (8). Let s0 denote any
transmission zero of ZL. Then, s0 belongs to one of the following mutually exclusive classes:
Class A. Res0 0: The transmission zero lies in the
open RHP.
Class B. Res0 0 and ZL( j0) : The transmission
zero lies on the imaginary axis at a point where the load
impedance ZL is finite (possibly zero)
Class C. Res0 0, and ZL( j0) : The transmission
zero lies on the imaginary axis at a point where the load
impedance has a pole.
The basic gainbandwidth theorem for single-matching problems relates properties of the system reflectance to the load
zeros of transmission so that extraction of the load becomes
possible.
Basic GainBandwidth Theorem for Single-Matching Problems
(8). A function T(2), such that 0 T(2) 1, , can be
realized as the transducer power gain of a finite lossless
equalizer E, inserted between a resistive generator (whose resistance is unit normalized) and a frequency dependent load
(whose impedance is a dissipative PR rational function ZL), if

(22a)

Class B. Real s0 0 and ZL( j0) :

bLr = SLr

The significant consequences of the main theorem may be

summarized as follows:

(r = 0, 1, 2, . . . k 1)

(r = 0, 1, 2 . . . 2k 2)

(22b)

and
[bL(2k1) SL(2k1)]
[2RL bL ]2k

(22c)

Class C. Res0 0 and ZL( j0) :

bLr = SLr

(r = 0, 1, 2, . . . 2k 2)

(22d)

and
[bL(2k1) SL(2k1)]
[2RL bL ](2k2)

1
0
c1

(22e)

In Eq. (22e), c1 is the residue of ZL at the s0 j0 pole;

otherwise, the subscripts identifies a Taylor coefficient.
It should be noted that similar sets of constraints are given
in the logarithmic and integral form. For details, interested
readers are referred to the reading list.
Analytic Approach to Double-Matching Problems
In order to handle the double-matching problem analytically,
the Darlington equivalent lossless two-ports G and L replace
the generator impedance ZG and the load impedance ZL, respectively. Hence, the system that will be doubly matched is
represented as the cascaded trio of the lossless two-ports
GEL as shown in Fig. 7. The entire structure is combined
under the lossless two-port F and described by means of the
unit normalized, bounded real scattering parameters Fij as in
the filter theory. The load network L is described by Eqs. (10)
and (11). Similarly, description of the generator network G
and its transmission zeros are given as follows:
Scattering Description of the Darlington Equivalent of Generator Network. Unit normalized scattering parameters of the
lossless generator network G are given in terms of the impedance ZG(s) NG(s)/DG(s)

ZG 1
ZG + 1
2WG
=
ZG + 1

G22 =

(23a)

G21

(23b)

G11 = G (s) bG (s)

ZG 1
ZG + 1

(23c)

596

BROADBAND NETWORKS

where

DG
DG
nG
G (s) =
nG
nG
WG =
DG

bG (s) =

(23d)
(23e)
(23f)

nG is a polynomial formed on the closed RHP zeros of

*
RG(s2) WGWG , RG(s2) being the even part of ZG(s).
*
In Belevitch form,

hG
gG
f
= G
gG

G22 =

(24a)

G21

(24b)

G11 = G (s)

hG
gG

(24c)

where

hG (s) = NG (s) DG (s)

(24d)

f G (s) = 2nG (s)

(24e)

gG (s) = NG (s) + DG (s)

(24f)

Transmission Zeros of the Generator Network. Zeros of the

2
are the transmission zeros of ZG(s), where
function FG(s) G21
4RG (s2 )
FG (s) = bG (s)
[ZG (s) + 1]2

(25a)

Darlington equivalents. In order to construct the desired

equalizer, Youlas gainbandwidth restrictions are simultaneously applied at the source and the load end, and then, extractions of G and L are accomplished.
At this point it is very important to outline some basic
properties of Fij related to source and load networks so that
an appropriate form of the transfer function T F212 is selected to end up with a realizable equalizer.
Essential Properties of F. In principal, F21(s) must contain all
the transmission zeros of G and L with at least the same multiplicity as well as the transmission zeros of E. The following
properties are either the direct results of the paraunitary condition of F or come from the definition of transmission zeros
or from the main theorem.
1. If F212 F21( j), F21(j) is a transfer function with
desired shape over the real frequencies.
a. When j is replaced by s, F21(s)F21(s) must contain
all the real frequency transmission zeros of G and L
in the numerator polynomial f(s) f(s).
b. RHP transmission zeros of G and L must appear in
F21(s) as all-pass functions preserving the shape of
F212;
2. Let (s) be any Blaschke product of order k of F21(s). It
should appear either in F11 or in F22 of order 2k, or it
appears simultaneously in F11 and F22 with respective
orders k11 and k22 satisfying the condition 2k k11
k22.
3. In order to end up with a realizable structure, the main
theorem and the paraunitary condition demand the following forms for F11 and F22:

F11 (s) = SYCG

or
4n2G (s)
FG (s) =
g2G (s)

(25b)

Before introducing the unified procedure to construct the

broadband matching equalizer E, the theorem for doublematching problems will first be introduced.

where F11 (s) = G (s) [(s)]k 11

h(s)
g(s)

(26a)

and

F22 (s) = SYCL

where F22 (s) = L (s) [(s)]k 22

h(s)
g(s)
(26b)

where is the sign term 1.

Theorem for Double-Matching Problems (8). Let a rational transducer power gain function T(2) be prescribed where
0 T(2) 1. Let PR dissipative impedances ZG and ZL, for
generator and load be given and zeros of transmission of these
impedances be contained in T. Then, assuming no double degenerecies, the necessary and sufficient condition that T be
physically realizable by the system consisting of the generator ZG, the load ZL, and a lossless equalizer E placed between
generator and load is that the single-matching gain
bandwidth restrictions be simultaneously satisfied at the generator and load ports of the equalizer.
Based on the above presentations, it is clear that for both
single- and double-matching problems, the entire matched
system can be described in terms of its unit normalized BR
scattering parameters F Fij as in filter theory when the
source (or generator) and the load are replaced with their

The unified approach as a step by step design procedure will

now be introduced, to construct matching equalizers for both
single- and double-matching problems.
Unified Analytic Approach to Design
Broadband Matching Networks
Step 1. Obtain analytic forms of the impedances to be
matched and find the Darlington equivalents G and L.
Determine the transmission zeros of G and L as in Eq.
(12) and Eq. (25), respectively.
Step 2. Choose a desired form of the transducer power gain
function as in the filter design T(2) F212 1 F222
with unknown parameters. Here it is crucial that F21
includes all transmission zeros G and L networks with
at least the same multiplicity.

BROADBAND NETWORKS

Step 3. Using the spectral factorization of F112 F222

1 F212 as described in step 3 of the filter design process, construct the unit normalized reflectances F11 and
F22 as equivalent BR-Analytic Complex Normalized reflectances in the Yarman and Carlin sense, as indicated below:

F11 (s) = SYCG

h(s)
where F11 (s) = G (s) (s)
g(s)

and

F22 (s) = SYCL

where F22 (s) = L (s) (s)

tion on the practical applicability of the analytic method.

Nevertheless, for simple terminations, it may be useful
to determine the ideal highest flat gain level within the
passband. For example, for a typical R/C load, even if
infinite number of elements are employed in E, the possible highest flat gain level is given by
Gmax = 1 exp

(27a)

h(s)
g(s)
(27b)

where is the sign term 1. Polynomials h(s) and

g(s) are obtained via spectral factorization of F11(s)
F11(s) 1 T(s2) [or equivalently F22(s) F22(s)].
Certainly, g(s) is strictly Hurwitz. (s) is an arbitrary
Blaschke product and it might be necessary to satisfy
the GBR, otherwise it is set to 1. G and L are also
Blaschke products constructed on the closed RHP zeros
of even parts of generator and load impedances, respectively. It should be noted, however, that in the course of
spectral factorization, unknown parameters of T are being carried into F11 and F22.
Step 4. Apply Youlas GBR theorem for single matching at
both generator and load sites simultaneously to determine the unknown parameters of T.
Step 5. Finally, synthesize the equalizer using ZB(s) as introduced by Eq. (18).
Remarks
Implementation of the above procedure by no means is
unique. First of all, one may wish to start with the expanded forms of the generator and load impedances to
force resulting G and L to unity, as described earlier.
Spectral factorization of T(s2) can be carried out in a
variety of fashions. For the sake of brevity details are
omitted. Interested readers are referred to Refs. (9) and
(13).
The ratio h(s)/g(s) may be chosen as a minimum phase
function so that all RHP zeros are combined in the
Blaschke product (s) where necessary.
Use of an all-pass factor (s) in T(s2) always penalizes
the minimum gain level in the passband. Therefore one
should avoid using any extra Blaschke product in step 3
if possible.
It is interesting to observe that, whenever ZG and ZL possess the same transmission zeros of Class A, it is not
possible to satisfy the gainbandwidth theorem simultaneously if they are inserted into F11 and F22 as all-pass
functions. In this case, a proper form of F21 must be selected, which naturally includes these RHP zeros of load
and generator, but not as all-pass products.
It should be emphasized that it is not an easy matter to
utilize the analytic gainbandwidth theory. It is generally the second step that imposes the most severe limita-

597

2 
RCB

(28)

where B designates the normalized frequency bandwidth

(1,4). For double-matching problems, however, ideal flat
gain over a finite passband cannot be obtained (14,15).
In the above presentation, a concise discussion of network
theoretical fundamentals underlying the concept of analytic
solutions to matching problems is given. Based on the basic
concept presented here, various alternative formulations of
the problem are available in the literature. In particular,
Wohlers (16) studied the problem of double matching by introducing the concept of compatible impedances. Chien (17),
Chen (1820), and Satyanaryana (21) utilized the complex
normalized scattering parameters in the tradition of Youla, to
obtain explicit solutions for some typical analytic load impedances. An extensive list of further studies on analytic matching theory, which includes various worked-out examples, can
be found in the Reading List.
MODERN APPROACHES TO BROADBAND
MATCHING PROBLEMS: CAD
TECHNIQUESREAL FREQUENCY SOLUTIONS
In the previous sections analytic solutions to broadband
matching problems were presented. Analytic theory is essential to understand the gainbandwidth limitations of the
given impedances to be matched. However, its applicability
is limited beyond simple problems. By simple is meant those
problems of single or double matching in which the generator
and load networks include at most one reactive element, either a capacitor or an inductor. For simple impedance terminations, low-pass equal ripple or flat gain prototype networks,
which are obtained employing the analytic theory, may have
practical use. On the other hand, if the number of elements
increase in the impedance models to be matched, the theory
becomes inaccessible. If it is capable of handling the problem,
the resulting gain performances turn out to be suboptimal.
Equalizer structures become unnecessarily complicated, and
it may not even be feasible to manufacture them. Therefore,
in practice, computer aided design (CAD) techniques are preferred; commercially available programs such as Super Compact, Cosmic, Ana, Touch Stones, and so forth, are employed
to solve the matching problems. Readily available tools are
very good in analyzing and optimizing the given structures,
but they do not include network synthesis procedures in the
literal sense. In other words, in designing a matching network
or a microwave amplifier, a topology for the matching network with good initial element values should be supplied
to a commercially available package. In this respect, many
CAD packages work as fine trimming tools on the element
values when the circuit is practically synthesized. Usually,
a simple two element, capacitor-inductor ladder network is
a practical solution for narrow bandwidth matching prob-

598

BROADBAND NETWORKS

lems. However, if the optimum topology of the equalizer is

unknown, or if substantial bandwidth is requested, the
design task becomes more difficult. In this case, modern
CAD techniques are strongly suggested to design matching
networks.
In all single- and double-matching CAD algorithms, the
goal is to optimize the transducer power gain (TPG), as high
and flat as possible in the band of operation. Matching network E, generator and load are considered as separate entities. TPG is expressed in terms of these entities. The lossless
equalizer E is either described in terms of its driving point
back-end impedance ZB (or equivalently admittance YB
1/ZB) or in terms of its unit normalized scattering parameters
Eij. The descriptive parameters of E are chosen as the unknowns of the problem and they are determined as the result
of the optimization process. In this way, the analytic extraction process of generator and load networks is simply omitted.
In the following, first, major ingredients such as Darlingtonscattering representation of ZB, and unit-normalized reflectance SF of the lossless E and L chain to generate TPG,
are given. Then, modern computer aided design techniques so
called real frequency techniques to construct broadband
matching networks, are reviewed (10).
Scattering Description of the Lossless Matching Network E
Based on the Darlington representation of the driving point
back-end impedance ZB NB /DB, the scattering description of
the matching network E is given in a similar manner to those
of Eq. (10) and Eq. (23), as follows:

ZB 1
ZB + 1
2WB
=
ZB + 1
Z 1
= B b B B
ZB + 1

E22 =

(29a)

E21

(29b)

E11

(29c)

where

DB
DB
nB
B (s) =
nB
WB = nB /DB

bB (s) =

L. Accordingly, swapping the subscripts L and B of Eq. (19),

SF is given by
SF (s) =

Real Frequency Line Segment Technique

In 1977 a numerical approach known as the real frequency
technique was introduced by Carlin for the solution of singlematching problems (2). The real frequency technique utilizes
measured data, by-passing the analytic theory. Neither the
equalizer topology nor the analytic form of a transfer function
is assumed. They are the result of the design method. Measured data obtained from the devices to be matched are directly processed.
It is important to recognize that the breakthrough of the
real frequency method is the recognition that the results of
numerical optimization will in general always be superior to
those of the analytic theory. In effect, the analytic method
squanders its degrees of freedom by introducing all-pass factors to achieve special gain function properties (e.g., maximal
flatness), whereas the real frequency approach directly optimizes passband gain without the artificial constraints of a
specific transfer function (12).
The precise optimization method is not the crucial factor
though clearly, as discussed below, some methods are more
efficient and practical than others. Carlins initial numerical
method used a line segment approximation scheme and contains features often employed in later more sophisticated optimization routines. The attractive feature of the line segment
scheme is its simplicity. The technique starts with the generation of a rational positive real (PR) input impedance ZB
RB() jXB() looking into a lossless matching network with
resistive termination [Fig.4(a)].
Let the measured load impedance be ZL( j) RL()
jXL(); then the transducer gain T() is given by
T () = 1 |SF |2

Unit Normalized Input Reflectance SF. The unit normalized

input reflectance SF of the bulk lossless section formed with
E and L is given by means of the main theorem. It is straightforward to show that SF is equal to BR-Analytic Complex,
Normalized Reflectance SYCB defined in the YarmanCarlin
sense at the backend of E. In this regard, the impedance ZB
is regarded as a complex termination to the lossless two-port

(31)

or by simple algebraic manipulation one obtains

(29f)

nB is a polynomial formed on the closed RHP zeros of RB(

*
s2) WB WB, RB(s2) being the even part of ZB(s).
*
In order to construct the transducer power gain function T
for single- and double-matching problems, it is useful to introduce the unit-normalized reflectance SF at the front end of the
equalizer when the other end has complex termination ZL.
This can be accomplished by means of the main theorem of
Refs. 6 and 22 as follows.

(30)

where WB is defined as in Eq. (29f).

(29d)
(29e)

WB ZL ZB

WB ZL + ZB

T (2 ) =

4RB ()RL ()
[RB () + RL ()]2 + [XB () + XL ()]2

(32)

In Carlins approach, the matching problem is handled within

three major steps. In the first step, RB() is represented by a
set of linear combinations of unknown line segments (Fig. 8),

RB () = R0 +

N


ai () ri

(33a)

i=1

where

1,

i1
ai =
,

i i1

0,

i
i1 i
i

(33b)

BROADBAND NETWORKS

RB
R1

the Bode or Gewertz procedure as a positive real function

(1,23).

Ri

R2

ZB (s) =

RN 1

R0

RN

N 1 N

Figure 8. Line segment representation of the real part of back-end

impedance RB().

i is called the break frequency at the point where RB takes

the value Ri, that is, Ri RB(i). Therefore, Ri is called the
break resistance, ri is the resistance excursions of the ith segment such that ri Ri Ri1 and N designates the number
of break points.
Here, ZB( j) is considered as a minimum reactance function. Therefore, XB() is also expressed in terms of the same
linear combination of the line segments using the Hilbert
Transformation relation:

XB () =

N


bi ()Ri

(34a)

i=1

where

bi () =

1
{[( + i ) ln( + i ) + ( i ) ln | i |]
(i i1 )
[( + i1 ) ln( + i1 ) + ( i1 ) ln | i1 |]}

for all i = 1, 2, . . . N

(34b)

In the second step, these straight lines are then computed in

such a way that TPG are optimized over the band of operation. The third step is devoted to approximate ZB( j) by a
realizable rational function that fits the computed data pair
(RB, XB). Then, ZB is synthesized, using Darlingtons procedure, as a lossless two-port with resistive termination.
A general realizable analytic form of RB is given as
RB (2 ) =

A0 + A1 2 + + Am 2m
0
B0 + B1 2 + + Bn 2n

nm+1

(35)

In many practical cases, it is appropriate to choose RB() to

yield a ladder matching network as follows:
RB (2 ) =

599

Ak 2k
B0 + B1 2 + + Bn 2n

(36)

where k and n are positive integers (k n) and they determine the complexity of the equalizer. Equation (36) describes
an LC ladder network with all zero of transmissions at zero
and infinity. More specifically, integer n designates the total
number of elements of the equalizer. Integer k is the total
number of transmission zeros at zero which, in turn, effects
the topology of the LC ladder. The coefficients Ak, and Bi are
computed to fit the real part data, obtained from the first step
of the technique, by linear regression. Afterwards, ZB(s) is
generated as a positive real analytic function from RB using

a0 + a1 s + + a(n1) s(n1)
b0 + b1 s + + b (n1)s(n1) + bn sn

(37)

It has been shown that the line segment technique yields

superior design performances over the analytic and other
CAD approaches. Almost optimum circuit topology is resolved. Furthermore, gainbandwidth limitations of a given
load may be determined by means of computer experiments.
However, the following may be regarded as disadvantages of
this technique.
The first two steps of the above described technique involves the computation of the unknown line segments and approximation problem, which requires the evaluation of Hilbert transformation during the optimization process. These
computations may be laborious and expensive. Even though
there is no longer any need to choose a circuit topology, decisions have still to be made as to whether the input impedance ZB is a minimum-reactance or, equivalently, YB 1/ZB
is a minimum-susceptance function. It should be noted that if
the design is restricted with minimum functions, some reactive elements can be extracted from the equalizer, leaving
a minimum-reactance or minimum-susceptance input immitance. Although this process improves the flexibility of the
technique, one must decide what to extract (capacitor or
inductor) and how to extract (series or parallel) by trial
and error, which, in turn, increases the computation time.
Despite the said drawbacks of this technique, it is reasonably satisfactory for single-matching problems. Later, the line
segment technique was extended to handle double-matching
problems as well, but the computational efficiency of the technique turned out to be poor. The follow-up CAD double matching design technique, namely, the direct computational technique, overcomes some of the difficulties of the line segment
approach. Details of the implementation of the line segment
technique can be found in Refs. 6, 22, and 24.
Direct Computational Technique
The basic idea employed in the direct computation method is
similar to that of the line segment technique. That is, referring to Fig. 4(a), the driving point impedance ZB NB /DB at
the back end describes the lossless matching network,
whereas the front end has resistive termination. In fact, the
scattering description of E is given with respect to ZB as has
been demonstrated in the previous section.
As in the line segment approach, here ZB is also considered
a minimum reactance (or YB is minimum susceptance) function. Therefore, it is determined from its even part RB(2) using the Hilbert transformation relation. For practical reasons,
it is the designers choice to start with the ladder form for
RB(2), as in Eq. (36).
The core of this method resides in the generation of the
overall transducer power gain T in terms of RB(2), which will
be determined by optimization. Referring to the doublematching configuration shown in Fig. 7, considering the generator network G and describing the lossless chain EL in

600

BROADBAND NETWORKS

terms of the unit normalized reflectance SF, it is straightforward to show that

T (2 ) =

(1 |G22 |2 )(1 |SF |2 )

|1 SF G22 |2

(38)

In the above presentation, clearly, SF is constructed as an implicit function of RB and it is initialized at the beginning of
the optimization process. By spectral factorization of RB, nB
*
and DB are computed. Then WB is formed as in Eq. (29f) and
SF is generated as described by Eq. (30). Employing the Gewertz procedure, minimum reactance ZB is generated. If desired, any appropriate reactive part can be introduced to ZB
as an unknown of the problem.
Once the TPG is generated, it is maximized to determine
the unknown coefficients Ak and Bi of Eq. (36) (22).
In this design method, the line segment approach is simply
omitted. Thus the computational efficiency is improved. Direct computational technique has all the merits of the line
segment technique. However, decisions must again be made
as to whether to make the input impedance ZB minimum reactance or minimum susceptance, and so forth. For interested
readers, the details can be found in the Reading List.
Parametric Approach to Matching Problems
Fettweis first introduced the parametric representation of
Burne functions in 1979 (25). Pandel and Fettweis (26) applied it to single-matching problems. Later, Yarman and Fettweis elaborated this method for double-matching problems
(27). In the parametric approach, the lossless equalizer E is
described in terms of its minimum reactance driving point
impedance ZB as in the other techniques, and it is expressed
in the form of partial fraction expansion with simple poles
pi i ji.

ZB = B0 +

N

i=1

Bi
(s pi )

(39)

Here, the real parts i and the imaginary parts i are chosen
as the unknowns of the matching problem. The coefficients or
the residues Bi are computed in terms of the poles pi i
ji. Once the unknowns are initialized, ZB is explicitly generated as an analytic function. Then it is straightforward to
form TPG as stated in Eq. (38). Hence, it is optimized over the
band of operation which, in turn, yields the unknown poles
pi i ji.
In the parametric approach, the Gewertz procedure, which
is employed in the line segment and direct computational
techniques, is simply omitted. Therefore, in the optimization
scheme, neither explicit factorization of polynomials nor the
solution of linear equations systems of Gewertz procedure is
required. Furthermore, consideration of ZB as a minimum reactance function, having only simple poles, does not imply
any loss of generality. This is because multiple poles do not
occur in impedances of practical interest, and any impedance
function can be expressed as a sum of a minimum reactive
function and a pure reactance, which is naturally included in
the parametric form of ZB.
For single-matching problems, gradients of TPG with respect to unknowns i and i are explicitly determined. Therefore, the parametric approach presents excellent numerical

stability. The parametric approach to broadband matching

problems possesses all the outstanding merits of the real frequency techniques. Furthermore, it presents improved numerical stability with less computation. Details of this
method can be found in Refs. 2529.
Simplified Real Frequency Technique: A Scattering Approach
The simplified real frequency technique (SRFT) is also a CAD
procedure for double-matching problems. In this method the
lossless equalizer is simply described in terms of its unit normalized scattering parameters. SRFT possesses all the outstanding merits of the other real frequency techniques. Moreover, it does not involve with any impedance or admittance
computation. Therefore, the gain optimization process of the
matched system is well behaved, numerically. It is faster than
the other existing CAD algorithms and easier to use. It is also
naturally suited to design broadband microwave amplifiers.
The basis for the scattering approach is to describe the
lossless equalizer E in terms of the unit normalized reflection
coefficient E11(s). Moreover, if E11(s) is described in Belevitch
form, E11(s) h(s)/g(s), for selected transmission zeros, the
complete scattering parameters of a lossless reciprocal equalizer can be generated from the numerator polynomial h(s) of
E11(s), using the paraunitary condition given by Eq. (5) to Eq.
(7). This idea constitutes the crux of the simplified real frequency technique. In other words, the TPG of the system to
be matched is expressed as an implicit function of h(s).
Replacing generator and load impedances by their Darlington equivalent lossless two-ports G and L, respectively, and
utilizing their unit normalized scattering descriptions, as
specified by Eq. (10) and Eq. (23), the transducer power gain
of the doubly matched system can be given as follows:
T () = |G21 |2

|E21 |2 |L21 |2
|1 E11 G22 |2 |1 E 22 L11 |2

(40)

where Gij and Lij are specified by the generator and the load
measurements. However, in terms of the measured generator
and load impedances,

ZG 1
ZG + 1
Z 1
= L
ZL + 1

G22 =

|G21 |2 = 1 |G22 |2

(41a)

L11

|L21 |2 = 1 |L11 |2

(41b)

E 22 = E22 +

2
E21
G22
1 E11 G22

(41c)

Now construct TPG, once h(s) is initialized.

For simplicity, assume that E is a minimum phase structure with transmission zeros only at , 0. This is
a convenient assumption since it assures realization without
coupled coils, except possibly for an impedance level transformer. Then, the unit normalized scattering coefficients of E
is given in Belevitch form as follows:

E11 (s) =

h + h 1 s + + h n sn
h(s)
= 0
g(s)
g0 + g1 s + + gn sn

sk
g(s)
k h(s)
E22 (s) = (1)
g(s)

E12 (s) = E21 (s) =

(42a)
(42b)
(42c)

BROADBAND NETWORKS

where n specifies the number of reactive elements in E; k

0 is an integer and specifies the order of the transmission
zeros at zero. Since the matching network is lossless, it follows that
g(s)g(s) = h(s)h(s) + (1)k s2k

(43)

In an SRFT algorithm the goal is to optimize the TPG over

the operational frequency band (i.e., maximize the minimum
of TPG in the band). The coefficients of the numerator polynomial h(s) are selected as the unknowns of the matching problem. To construct the scattering parameters of E, it is sufficient to generate the Hurwitz denominator polynomial g(s)
from h(s). It can be readily shown that once the coefficients
of h(s) are initialized at the start of the optimization process
and the complexity of the equalizer E is specified (i.e., n and
k are fixed), g(s) is generated as a Hurwitz polynomial by explicit factorization of Eq. (43). Thus the physical realizibility
of the scattering parameters E; i, j 1, 2 is already built
into the procedure. It should be noted that in choosing the
polynomial h(s) and integer k, h(0) 0 and g(0) 0 cannot
be allowed simultaneously, since this violates the losslessness
criterion of Eq. (43). Therefore, one has to pay a little attention to the initial values of the unknown coefficients. In generating the Hurwitz denominator polynomial g(s) from the initialized coefficients of h(s), one first constructs g(s)g(s) as in
Eq. (43). That is,
g(s)g(s) = G0 + G1 s2 + + Gn s2n

(44)

where Gi(s) are given as follows:

G0 = h20
G1 = h21 + 2h2 h0
..
.
Gi =

(1)i h2i

+ 2 h2i h0 +

i


j=2

!
(1)

j1

h j1 h2 ji+1
(45)

..
.
Gk = Gi |i=k + (1)k
..
.
Gn = (1)n h2n
Then, explicit factorization of Eq. (44) follows. Following the
factorization process, polynomial g(s) is formed on the left
plane zeros of g(s)g(s).
Hence, the scattering parameters of E are generated as in
Eq. (42) and T() is computed employing Eq. (40). The objective function generated by means of TPG calls for an optimization routine. As a result of optimization, the unknown coefficients hi are determined. Details of the numerical work can
be found in the Reading List. In brief, examination of Eq. (40)
together with Eq. (42) indicates that TPG is almost inverse
quadratic in the unknown coefficients hi. Furthermore, the
numerical stability of the computer algorithm written for
SRFT discussed above is excellent, since all the scattering parameters Eij and reflection coefficients G22 and L11 are

601

bounded real, that is, Eij, G22, L11 1. As is usually the

case, an intelligent initial guess is important in efficiently
running the program. It has been experienced that, for many
practical problems, an ad hoc direct choice for the coefficients
hi (e.g., hi 1 or hi 1) provides satisfactory initialization
to start the simplified real frequency technique algorithm.
As indicated previously, SRFT is naturally suited to design
microwave amplifiers since scattering parameters for all the
units to be matched are used. Several matching networks and
amplifiers have been designed and built employing the SRFT.
Laboratory performance measurements exhibit good agreement with theoretical computations.
Active Matching: Design of Microwave Amplifiers
One of the major problems of microwave engineers is to develop proper matching networks for active devices so that the
power generated with these devices can be pumped into dissipative terminations or transferred to another device to generate more microwave power. Typical examples are the negative
resistance amplifiers, constructed with impatt diodes, and
single- or multi-stage amplifiers, constructed with GaAs field
effect transistors (FET).
In fact, the problem of active matching is not any different
from single or double matching, as explained in the first section. However, slight modifications of the techniques may be
required, depending on the type of application.
Kuh and Rohrer extended analytic theory of single matching to design negative resistance amplifiers (30). Later, Ku
and his coworkers applied the single-matching theory to design GaAs MESFET amplifiers using the tapered gain concept
(31). These were the early works to design microwave amplifiers.
After the breakthroughs of real frequency techniques, the
design of microwave amplifiers became much more practical,
since the complicated gainbandwidth restrictions were omitted and the measured device data were processed without any
model. First, the line segment technique was expanded to design single-stage microwave amplifiers by Carlin and Komiak
(32). Later, Yarman and Carlin developed first interstage
equalizer design, in the literal sense, using the direct computational and simplified real frequency technique (33). Then,
utilizing SRFT, many single- or multi-stage amplifiers were
designed and different variants of the technique were developed and applied to practical problems (3437).
Therefore, in this presentation, the application of the
SRFT to design single- and multi-stage amplifiers will be outlined briefly.
Referring to Fig. 9, the design of a single-stage amplifier
can be implemented within two steps. First, the front-end
equalizer EF of the active device is constructed, while the
other end of the device is terminated in unit resistance. In
this case, transducer power gain T(1)() is given by
T (1) () =

|G21 |2 |E21F|2 |A21 |2

|1 G22 E11F|2 |1 E 22FA11 |2

(46)

where [Gij], [EijF] and [Aij] designate the unit (or real) normalized scattering parameters of the generator network, frontend equalizer, and the active device, respectively. Clearly,
T(1)() is generated from EijF, as described in SRFT, and all
the scattering parameters are determined from its numerator

602

BROADBAND NETWORKS

1
+
G

EG

EF
Ak
G22

G
(a)

1
+
G

EG

EF

EB

Ak
G22

22

22

22 B

(b)
Figure 9. (a) Single-stage amplifier with front-end equalizer EF. (b) Single-stage amplifier with
front-end EF and back-end EB equalizers.

22F is given by
polynomial hF(s). Here, E
E 22F = E22F +

2
G22
E21F
1 E11FG22

(47)

In the second step, the back-end equalizer EB is constructed

to optimize the overall transducer power gain T() given by

T () = T (1) ()

|E21B |2 |L21 |2

|1 A 22 E11B |2 |1 A22E11B |2 |1 E 22B L22 |2

(48)

where Lij and Eij are the unit normalized scattering parameters of the load network and the back-end equalizer EB, re 22, and E
22B are given as follows:
spectively. A

A A E
A 22 = A22 + 21 12 22
1 E 22FA11
2
A 22
E21B
E 22B = E22B +
1 E11BA22

(49a)

ring to Fig. 10, one can design an N-stage amplifier with field
effect transistors (FET), step by step. Assume that generator
G and load L are also complex. Let A(k)
ij designate the unit
normalized (50 normalized) scattering parameters of FETs.
The design algorithm can be described as follows: First, the
front-end equalizer E1 is constructed, while the output of the
first FET is terminated with its normalization resistance. In
the second step, resistive termination is removed and the second equalizer E2 and the new FET are placed into the design
with resistive termination. At the kth step, insert the kth interstage equalizer with the kth active device while it is terminated in its normalization resistance at the output. As this
process plays out, at the last step we introduce the back-end
equalizer is introduced in between the Nth device and the
load L. In other words, at each step a new interstage equalizer and an active device with resistive termination are inserted. At the last step, which corresponds to the (N 1)th
step, the back-end equalizer EN1 is designed.
At the kth step, TPG is given by

(49b)

As is customary for SRFT, the back-end equalizer is completely determined from its numerator polynomial hB(s) of the
input reflectance E11B(s).
Employing SRFT, several single-stage amplifiers were implemented by Yarman (38). The technique is also applied to
design power amplifiers. In this case, a modified version (A
Dynamic CAD Technique for Designing Microwave Amplifiers) was introduced by Yarman (39).
It is straightforward to extend the SRFT to design multistage microwave amplifiers by generating the TPG in a sequential manner, as was done for single-matching amplifier
design.

Tk () = Tk1 Ek ()

k = 1, 2, . . ., (N + 1)

(50a)

where
(k) 2
Ek () = |E21
|
(k)
(k)
L21
= A21
(k)
(k)
E 22
= E 22
+

(k)
(k)
G22
= A22
+

(k) 2
|L21
|

(k) G (k) |2 |1 E
(k) L(k) |2
|1 E11
22
22 11
(k)
(k)
L11
= A11
(k) 2 (k)
(E21
) G22
(k) E (k)
1 G22
11
(k1) (k1) (k1)
A12 A21 E22
(k) E (k)
1 G22
11

(50b)
(50c)
(50d)

k2

(50e)

with
Design of Multi-Stage Microwave Amplifiers. Multi-stage microwave amplifiers can be designed in a similar manner, described above using a step-by-step design algorithm. Refer-

(1)
G22
=

ZG 1
ZG + 1

(50f)

BROADBAND NETWORKS

603

1
+
G

E1

Ek

Ek + 1

Ak

Ak 1
G22(1)

22(1)

22(k)

22 B(k)

Figure 10. Multistage amplifier configuration with front-end, back-end, and interstage equalizers.

At the last step of the above process, overall transducer power

gain of the multistage will be computed in a sequential manner as
T () = (T1 .T2 . . . TN ).EN+1

(51)

In Eq. (51) the term E(N1)() provides the impedance matching to load ZL. In this case, parameters of Eq. (50b) are given
by
(N+1)
L11
=

ZL 1
ZL + 1

(N+1) 2
(N+1) 2
|L21
| = 1 |L11
|

(52a)
(52b)

At each step of the design, SRFT is accessed to construct the

lossless matching networks [Ek] and TPG is optimized over
the band of operation. In the course of the optimization process, the gain taper of each FET is compensated at the corresponding front-end equalizer. Furthermore, nonunilateral behavior of the active devices is taken into account. Eventually,
in order to improve the gain performance, the TPG of the
overall system can be reoptimized.
Practical Implementation of Matching Equalizers
In the above-presented techniques, the complex variable s
j was employed in the descriptive network functions,
which yields lumped element circuit components (inductors
and capacitors) in matching equalizers. Utilizing hybrid or
monolithic integrated circuit production technologies, it is
possible to build this type of lumped circuit elements up to 10
GHz. Beyond these frequencies, however, physical sizes must
be included in the design process. A straightforward method
to construct matching equalizers with physical sizes is to employ equal delay transmission lines throughout the design. In
this case, complex variable s j is replaced with the
Richard variable j. Here, transformed frequency
is given by tan, where specifies the equal delay
length of transmission lines employed in the designs. In this
case, all the computations are carried out in the transformed
frequency domain, but otherwise, all the analytic and real frequency solutions to matching problems remain unchanged.
Extension of the analytic and real frequency solutions with
equal length or commensurate transmission lines can be
found in Refs. 34 and 4044.
More sophisticated solutions to broadband matching problems can be given with mixed lumped and distributed elements. In these solutions, physical connection of lumped elements can be covered with transmission lines and parasitics
of the discontinuities can be imbeded into lumped elements.

In this case, it is necessary to carry out all the designs in at

least two variables, namely, s for lumped elements and for
equal delay transmission lines. Semi-analytic and real frequency solutions to matching problems with mixed lumped
and distributed elements can be found in the works of Yarman, Aksen, and Fettweis (28,4549).
BIBLIOGRAPHY
1. H. W. Bode, Network Analysis and Feedback Amplifier Design,
Princeton, NJ: Van Nostrand, 1945.
2. H. J. Carlin, A new approach to gain-bandwidth problems, IEEE
Trans. Circuits Syst., CS-23: 170175, 1977.
3. S. Darlington, Synthesis of rectance 4-poles, J. Math. Phys., 18:
257353, 1939.
4. R. M. Fano, Theoretical limitations on the broadband matching
of arbitrary impedances, J. Franklin Inst., 249: 5783, 1950.
5. D. C. Youla, A new theory of broadband matching, IEEE Trans.
Circuit Theory, CT-11: 3050, 1964.
6. B. S. Yarman, Broadband matching a complex generator to a complex load, Ph.D. thesis, Cornell University, Ithaca, NY, 1982.
7. D. C. Youla, H. J. Carlin, and B. S. Yarman, Double broadband
matching and the problem of reciprocal reactance 2n-port cascade
decomposition, Int. J. Circuit Theory Appl., 12: 269281, 1984.
8. H. J. Carlin and P. P. Civalleri, Electronic engineering systems
series, in J. K. Fidler (ed.), Wideband Circuit Design, Boca Raton,
FL: CRC Press, 1998.
9. W. K. Chen, Broadband Matching, Theory and Implementations,
2nd ed., Singapore: World Scientific, 1988.
10. B. S. Yarman, Modern approaches to broadband matching problems, Proc. Inst. Electr. Eng., 132: 8792, 1985.
11. V. Belevitch, Classical Network Theory, San Francisco: HoldenDay, 1968.
12. P. I. Richards, Resistor-transmission-line circuits, Proc. IRE, 36:
217220, 1948.
13. H. J. Carlin and A. B. Giordano, Network Theory. An Introduction
to Reciprocal and Nonreciprocal Circuits, Englewood Cliffs, NJ:
Prentice-Hall, 1964.
14. H. J. Carlin and P. Amstutz, On optimum broadband matching,
IEEE Trans. Circuits Syst., 28: 401405, 1981.
15. H. J. Carlin and P. P. Civalleri, On flat gain with frequency-dependent terminations, IEEE Trans. Circuits Syst., 32: 827839,
1985.
16. M. R. Wohlers, Complex normalization of scattering matrices and
the problem of compatible impedances, IEEE Trans. Circuit Theory, CT-12: 528535, 1965.
17. Chien, A theory of broadband matching of a frequency dependent
generator and load, J. Franklin Inst., 298 181221, 1974.
18. W. K. Chen and T. Chaisrakeo, Explicit formulas for the synthesis of optimum bandpass butterworth and chebyshev impedance-

604

BROADBAND NETWORKS
matching networks, IEEE Trans. Circuits Syst., CAS-27: 928
942, 1980.

19. W. K. Chen, Explicit formulas for the synthesis of optimum

broadband impedance matching networks, IEEE Trans. Circuits
Syst., 24: 157169, 1977.
20. Y. S. Zhu and W. K. Chen, Unified theory of compatibility impedances, IEEE Trans. Circuits Syst., 35: 667674, 1988.
21. Satyanaryana and W. K. Chen, Theory of broadband matching
and the problem of compatible impedances, J. Franklin Inst., 309:
267280, 1980.
22. H. J. Carlin and B. S. Yarman, The double matching problem:
Analytic and real frequency solutions, IEEE Trans. Circuits Syst.,
30: 1528, 1983.
23. C. M. Gewertz, Synthesis of a finite, four-terminal network from
its prescribed driving point functions and transfer functions, J.
Math. Phys., 12: 1257, 1933.
24. B. S. Yarman, Real frequency broadband matching using linear
programming, RCA Rev., 43: 626654, 1982.
25. A. Fettweis, Parametric representation of brune functions, Int. J.
Circuit Theory Appl., CTA-7: 113119, 1979.
26. J. Pandel and A. Fettweis, Broadband matching using parametric
representations, IEEE Int. Symp. Circuits Syst., 41, 143149,
1985.
27. B. S. Yarman and A. Fettweis, Computer-aided double matching
via parametric representation of brune functions, IEEE Trans.
Circuits Syst., 37: 212222, 1990.
28. A. Aksen, Design of lossless two-ports with lumped and distributed
elements for broadband matching, Ph.D. thesis, Ruhr University
at Bochum, 1994.
29. J. Pandel and A. Fettweis, Numerical solution to broadband
bmatching based on parametric representations, Arch. Elektr. U
ertragung., 41: 202209, 1987.
30. E. S. Kuh and J. D. Patterson, Design theory of optimum negative-resistance amplifiers, Proc. IRE, 49 (6): 10431050, 1961.
31. W. H. Ku et al., Microwave octave-band GaAs-FET amplifiers,
Proc. IEEE MTT-S Int. Microw. Symp., Palo Alto, CA, 1975, pp.
6972.
32. H. J. Carlin and J. J. Komiak, A new method of broadband equalization applied to microwave amplifiers, IEEE Trans. Microw.
Theory Tech., MTT-27: 9399, 1979.
33. B. S. Yarman and H. J. Carlin, A simplified real frequency technique applied to broadband multi-stage microwave amplifiers,
IEEE Trans. Microw. Theory Tech., 30: 22162222, 1982.
34. B. S. Yarman and A. K. Sharma, Extension of the simplified real
frequency technique and a dynamic design procedure for designing microwave amplifiers, IEEE Int. Symp. Circuits Syst., 3: 1984,
pp. 12271230.
35. L. Zhu, B. Wu, and C. Cheng, Real frequency technique applied
to synthesis of broadband matching networks with arbitrary nonuniform losses for MMICs, IEEE Trans. Microw. Theory Tech.,
36: 16141620, 1988.
36. P. Jarry and A. Perennec, Optimization of gain and vswr in
multistage microwave amplifier using real frequency method,
Eur. Conf. Circuit Theory Des., 23: 1987, pp. 203208.
37. A. Perennec et al., Computer-aided design of hybrid and monolithic broad-band amplifiers for optoelectronic receivers, IEEE
Trans. Microw. Theory Tech., 37: 14751478, 1989.
38. B. S. Yarman, A simplified real frequency technique for broadband matching complex generator to complex loads, RCA Rev.,
43: 529541, 1982.
39. B. S. Yarman, A dynamic CAD technique for designing broadband microwave amplifiers, RCA Rev., 44 (4): 551565, 1983.

40. L. Zhu, C. Sheng, and B. Wu, Lumped lossy circuit synthesis and
its application in broadband FET amplifier design in MMICs,
IEEE Trans. Microw. Theory Tech., 37: 14881491, 1989.
41. B. S. Yarman, A. Aksen, and A. Fettweis, An integrated design
tool to construct lossless matching networks with lumped and
distributed elements, Eur. Conf. Circuit Theory Des., 3 1991,
pp. 12801290.
42. C. Beccari, Broadband matching using the real frequency technique, IEEE Int. Symp. Circuits Syst., 3: 1984, pp. 12311234.
43. G. Pesch, Breitbandanpassung mit Leitungstransformatoren,
Ph.D. thesis, Technische Hochschule, Aachen, 1978.
44. R. Pauli, Breitbandanpassung Reeller und Komplexer Impedanzen
mit Leitungsschaltungen, Ph.D. thesis, Technische Universitat,
Munich, 1983.
45. B. S. Yarman and A. Aksen, An integrated design tool to construct lossless matching networks with mixed lumped and distributed elements, IEEE Trans. Circuits Syst., 39: 713723, 1992.
46. B. S. Yarman, A. Aksen, and A. Fettweis, An integrated design
tool to construct lossless two-ports with mixed lumped and distributed elements for matching problems, Int. Symp. Recent Adv.
Microw. Tech., 2: 1991, pp. 570573.
47. A. Aksen and B. S. Yarman, Construction of low-pass ladder networks with mixed lumped and distributed elements Eur. Conf.
Circuit Theory Des., 1: 1993, pp. 13891393.
48. A. Aksen and B. S. Yarman, A semi-analytical procedure to describe lossless two-ports with mixed lumped and distributed elements, ISCAS94, 56: 1994, pp. 205208.
49. A. Aksen and B. S. Yarman, Cascade synthesis of two-variable
lossless two-port networks of mixed lumped elements and transmission lines: A semi-analytic procedure, NDS-98, 1st Int. Workshop Multidimen. Syst., Poland, 1998.

Reading List
P. Abrie, The Design of Impedance Matching Networks, Dedham, MA:
Artech House, 1985.
A. Aksen and B. S. Yarman, A Brief Survey of the Modern Design
Techniques on Broadband Matching Networks, Workshop on Circuits and Systems at Isk University, Istanbul, 1997.
A. Aksen, E. G. C
imen, and B. S. Yarman, Saclma parametrelerinin
parametrik tanm ile bilgisayar destekli genis bandl empedans
uyumlastrma, Electron. Eng. 10th Anniv. Symp., C
ukurova University, 1998.
H. G. Ansell, On certain two-variable generalization of circuit theory
with applications to networks of transmission lines and lumped
reactances, IEEE Trans. Circuit Theory, CT-11: 214223, 1964.
N. K. Bose, Applied Multidimensional Systems Theory, New York: Van
Nostrand-Reinhold, 1982.
H. J. Carlin, Network theory without circuit elements, Proc. IEEE,
55: 482497, 1967.
H. J. Carlin, On the existence of a scattering representation of passive networks, IRE/IEEE Trans. Circuit Theory, CT-14: 418
419, 1967.
H. J. Carlin, Distributed circuit design with transmission line elements, Proc. IEEE, 3: 10591081, 1971.
H. J. Carlin, A new approach to broadbanding, Proc. 14th Annu. Allerton Conf. Circuits Syst. Theory, 1976, pp. 9399.
H. J. Carlin and P. P. Civalleri, A general theory for broadband
matching of two-ports with application to fet amplifiers with internal feedback, Int. J. Circuit Theory Appl., 19: 5164, 1991.
H. J. Carlin and R. A. Friedenson, Gain bandwidth properties of a
distributed parameter load, IEEE Trans. Circuit Theory, CT-15:
455464, 1968.

BROADBAND NETWORKS
H. J. Carlin and O. P. Gupta, Computer design of filters with lumpeddistributed elements or frequency variable terminations, IEEE
Trans. Microw. Theory Tech., MTT-8: 598604, 1969.
H. J. Carlin and W. Kohler, Direct synthesis of bandpass transmission line structures, IEEE Trans. Microw. Theory Tech., MTT-13:
283297, 1965.
H. Dedieu and J. Neirynck, A simplified real frequency computation
method for broadband matching, Proc. Eur. Conf. Circuit Theory
Des., 1993.
H. Dedieu et al., A new method for solving broadband matching problems, IEEE Trans. Circuits Syst., CAS-41: 561571, 1994.
C. Dehollain and J. Neirynck, Simplified impedance broadband
matching by the image parameter method: The RC case, Int. J.
Circuit Theory Appl., 23 (2): 91116, 1995.
C. Dehollain and J. Neirynck, Broadband matching of an RLC load
by optimal Chebyshev gain function, Proc. IEEE Int. Symp. Circuits Syst., 3: Seattle, WA, 1995, pp. 16481651.
A. Fettweis, Network theory, in R. Boite (ed.), Cascade Synthesis of
Lossless Two Ports by Transfer Matrix Factorization, New York:
Gordon and Breach, 1972, pp. 43103.
A. Fettweis, Scattering properties of real and complex lossless 2ports, Proc. Inst. Electr. Eng., 128: 147148, 1981.
A. Fettweis, On the scattering matrix and the scattering transfer ma bertratrix of multidimensional lossless two-ports, Arch. Elektr. U
gung., 36: 374381, 1982.
A. Fettweis, Multidimensional circuit and systems theory, IEEE Int.
Symp. Circuits Syst., 2: 1984, pp. 951957.
A. Fettweis, A new approach to hurwitz polynomials in several variables, Circuits Syst. Signal Process., 5: 405417, 1986.
W. T. Hatley, Computer Analysis of Wide-band Impedance Matching
Networks, Tech. Rep. No. 6657-2, Stanford, CA: Stanford University, Stanford Electronics Laboratories, 1967.
B. K. Kinariwala, Realization of Broadband Matching Networks for
Arbitrary Impedances, Electronics Res. Lab., Rep. No. 59 on Office
of Naval Res., Nronr-29529, Berkeley: University of California,
1957.
B. K. Kinariwala, Theory of cascaded structures: Lossless transmission lines, Bell Syst. Tech. J., 45: 631649, 1966.
T. Koga, Synthesis of a resistively terminated cascade of uniform lossless transmission lines and lumped passive lossless two-ports,
IEEE Trans. Circuit Theory, CT-18: 444455, 1971.
E. S. Kuh and R. A. Rohrer, Theory of Linear Active Networks, San
Francisco: Holden-Day, 1967.
A. Kummert, Beitrage zur Synthese Mehrdimensionaler Reaktanz
Mehrtore, Ph.D. thesis, Ruhr-Universitat, 1988.
A. Kummert, Synthesis of two-dimensional lossless m-ports with prescribed scattering matrix, Circuits Syst. Signal Process., 8: 97
119, 1989.
P. Landau and E. Zeheb, On solving broadband matching design
equations, Circuit Theory Appl., 13: 123132, 1985.
R. Levy, A general equivalent circuit transformation for distributed
networks, IEEE Trans. Circuit Theory, CT-12: 457458, 1965.
R. H. Levy and T. E. Rozzi, Precise design of coaxial low-pass filters,
IEEE Trans. Microw. Theory Tech., MTT-16: 142147, 1968.
L. Y. G. L. Matthaei and E. M. T. Jones, Microwave Filters, Impedance
Matching Networks, and Coupling Structures, New York: McGrawHill, 1964.
J. Neirynck and P. Thiran, Broadband matching as a scattering problem, Proc. Int. Symp. Circuits Syst., 1989, pp. 693696.
H. Ozaki and T. Kasami, Positive real functions of several variables
and their applications to variable networks, IEEE Trans. Circuit
Theory, 7: 251260, 1960.

605

R. Pauli, Darlingtons theorem and complex normalization, Int. J. Circuit Theory Appl., 17: 429446, 1989.
V. Ramachandran and A. S. Rao, A multivariable array and its application to ladder networks, IEEE Trans. Circuit Theory, 20: 511
518, 1973.
M. H. Reddy, P. Rajan, and M. N. S. Swammy, Realization of resistively terminated two variable lossless ladder networks, IEEE
Trans. Circuits Syst., 29: 827832, 1982.
G. Rhodes and H. Dedieu, A new method for solving broadband
matching problems, Proc. Eur. Conf. Circuit Theory Des., 1993.
L. A. Riederer and L. Weinberg, Synthesis of lumped-distributed networks: Lossless cascades, IEEE Trans. Circuits Syst., 27: 943
956, 1980.
R. A. Rohrer, Optimal matching: A new approach to the matching
problem for real linear time-invariant one-port networks, IRE/
IEEE Trans. Circuit Theory, CT-15: 118124, 1968.
M. Saito, Generalized Networks, in P. I. Brooklyn (ed.), Synthesis of
Transmission Line Networks by Multivariable Techniques, New
York: Polytechnic Press, 1966, pp. 353392.
S. O. Scanlan and H. Baher, Driving point synthesis of a resistor
terminated cascade composed of lumped lossless 2-ports and commensurate stubs, IEEE Trans. Circuits Syst., 26: 947955, 1979.
A. Sertbas, Genellestirilmis iki kapl iki degiskenli kaypsz merdiven
devrelerin tanmlanmas, Ph.D. thesis, Istanbul University at Istanbul, 1997.
A. Sertbas, B. S. Yarman, and A. Aksen, Explicit two-variable description of a class of band-pass lossless two-ports with mixed,
lumped elements and transmission lines, NDS-98, 1st Int. Workshop Multidimens. Syst., Poland, 1998.
G. Szentirmai, Band-pass matching filter in the form of polynomial
low-pass filter, IRE/IEEE Trans. Circuit Theory, CT-11: 177
178, 1964.
M. Uruski, Realizability conditions of non-reciprocal broadband
matching networks, Circuit Theory Appl., 12: 4767, 1984.
M. Uruski and M. S. Piekarski, Synthesis of a network containing a
cascade of commensurate transmission lines and lumped elements, Proc. Inst. Electr. Eng., 119: 153159, 1972.
Y. T. Vhan and E. S. Kuh, A general matching theory and its application to tunnel diode amplifiers, IEEE Trans. Circuit Theory, CT13: 618, 1966.
M. R. Wohlers, Lumped and Distributed Passive Networks, New York:
Academic Press, 1964.
M. R. Wohlers, On gain-bandwidth limitations for physically realizable systems, IRE/IEEE Trans. Circuit Theory, CT-12: 329333,
1965.
B. S. Yarman, A dynamic CAD technique for designing broadband
microwave amplifiers, IEEE David Sarnoff Symp. GaAs FET Circuits, 1983.
D. C. Youla, Generalized Networks, in P. I. Brooklyn (ed.), Synthesis
of n-Ports Containing Lumped and Distributed Elements, New
York: Polytechnic Press, 1966, pp. 289343.
D. C. Youla, L. J. Castriota, and H. J. Carlin, Bounded real scattering
matrices and the foundations of linear passive network theory,
IRE/IEEE Trans. Circuit Theory, CT-6: 102124, 1959.
D. C. Youla, J. D. Rhodes, and P. C. Marston, Driving point synthesis
of resistor terminated cascades composed of lumped lossless passive 2-ports and commensurate tem lines, IEEE Trans. Circuit
Theory, 19: 648664, 1972.
L. Zhu, Computer-aided synthesis of a lossy commensurate line network and its application in MMICs, IEEE Trans. Microw. Theory
Tech., MTT-39: 654659, 1991.

B. SIDDIK YARMAN
Isk University

606

BROADCASTING VIA INTERNET

BROADBAND NETWORKS. See CABLE TELEVISION.

BROADCAST ALGORITHMS. See GROUP COMMUNICATION.

BROADCASTING. See TRANSMITTERS FOR AMPLITUDE MODULATION BROADCASTING

BROADCASTING ANTENNAS. See ANTENNAS FOR

HIGH-FREQUENCY BROADCASTING; ANTENNAS FOR MEDIUM-FREQUENCY BROADCASTING.

BROADCASTING BY DIRECT SATELLITE. See DIRECT SATELLITE TELEVISION BROADCASTING.

BROADCASTING, TELEVISION. See TELEVISION TRANSMITTERS.

BROADCAST, RADIO STUDIO EQUIPMENT. See

RADIO BROADCAST STUDIO EQUIPMENT.

BROADCAST TELEVISION STANDARDS. See TELEVISION BROADCAST TRANSMISSION STANDARDS.

BROADCAST TRANSMISSIONS, PROPAGATION

OF. See PROPAGATION OF BROADCAST TRANSMISSIONS.
BROADCAST TRANSMITTERS. See TRANSMITTERS FOR
FM BROADCASTING.

ANALOG FILTERS
ACTIVE-RC FILTERS
INDUCTORLESS FILTERS
ANALOG ACTIVE-RC FILTERS
ACTIVE FILTERS
FILTERS, ANALOG
An electrical lter is a device, circuit, or system that transforms a given input signal into a desired output signal.
The transformation or ltering may be carried out in the
frequency or the time domain, and by a variety of physical means (electrical, mechanical, acoustical, etc.) depending on the frequency range of the signals, on the available
technology, and on the application in question. The most
commonly used electrical lters have traditionally been
wave or frequency lters, although with the development of
highly sophisticated digital signal processors on a silicon
integrated chip, ltering in the time domain has become
equally feasible. Because this article deals with analog ltering, we restrict ourselves to ltering issues in the frequency domain.

FILTER CATEGORIES
Electrical lters can be categorized in a number of
ways: for example, functionally (high-pass, low-pass, bandpass, etc.), technologically by component type or physical
medium [inductorcapacitorresistor (LCR), mechanical,
active RC, active gm C, monolithic crystal, quartz, etc.],
or by their operational features. Referring to Fig. 1, we
consider the last categorization here. The gure shows the
three main modes in which a lter can operate. Altogether
from input to output, we have an analog lter, that is, a lter that is continuous in amplitude and time. If we sample
the incoming signal in time [after bandlimiting the signal
with an antialiasing lter (AAF)] but leave the amplitude
continuous (nonquantized), we have a so-called sampleddata, or discrete-time, lter. If now we also quantize the
amplitude by passing the signal through an analog-todigital converter (ADC), we have a digital lter. In either
case, sampled-data or digital, if we require an analog signal at the output, we must add a digital-to-analog converter
(DAC) and a reconstruction lter to the processing chain.
Although lters operating in continuous time and amplitude, as well as those operating in discrete time but nonquantized amplitude (i.e., sampled-data lters) are sometimes referred to as analog lters, in this article we shall
include only the former in this category. Sampled-data lters, and in particular switched-capacitor lters, are dealt
with separately under Switched capacitor circuits. For

other categorizations of lters, see also Classical lter

synthesis.
TRANSFER FUNCTION AND FREQUENCY RESPONSE
Classical lters are made up of inductors (L), capacitors (C),
and terminating resistors (R); thus they are often referred
to as LCR lters. Ideally, the inductors and capacitors are
considered to be lossless, the only lossy components being the terminating resistors. The synthesis of such lters
is dealt with under Classical Filter Synthesis. Interestingly enough, most analog (and much digital) ltering can
be traced back to, and derived from, the foundations of classical LCR-based lter theory.
LCR lters belong to the family of linear, lumpedparameter, nite (LLF) networks. Those not falling into
this category typically are nonlinear, distributed (e.g., individual components such as resistors and capacitors cannot
be identied, but are distributed lmlike on a substrate),
nonnite, or any combination of these. The order of an LLF
lter is related to the number of reactive, or lossless, components in the network. For example, if a low-pass lter
comprises one inductor, one capacitor, and two resistors, it
is of second order.
The output signal of an nth-order LLF network can generally be found in terms of the input signal by solving a
linear nth-order differential equation of the form

where x(t) is the input signal, y(t) is the output signal, and
n m. Applying the Laplace transform to this equation,
we obtain the transfer function T(s) = Y(s)/X(s) as the ratio
of two polynomials N(s) and D(s), namely,

where s = + j is the complex frequency and N(s) and D(s)

are polynomials in s with real coefcients ai and bj . Expressing N(s) and D(s) in their factored form, we obtain
the poles and zeros of the transfer function:

As the coefcients ai and bj in Eq. (2) are real, the poles pj

and zeros zi must be either real or complex conjugate. The
factor K is a scaling factor whose dimension is such as to
render the transfer function T(s), when it is a voltage or a
current ratio, dimensionless. Combining a complex conjugate zero pair with a complex conjugate pole pair, we obtain
the special case of a second-order transfer function:

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Filters, Analog

Figure 1. Diagram of a generalized lter, demonstrating analog, sampled-data, and digital signal
processing: (a) block diagram including input sampler and output reconstruction lter; (b) typical
waveforms at points A through D.

response is obtained by letting s = j in Eq. (3); thus,

Taking the natural logarithm of T(j), we obtain

where () and () are the gain and phase response, given

in nepers and degrees, respectively. To obtain the gain response in decibels, we have

and to obtain the group delay,

Figure 2. The polezero diagram of a general second-order transfer function.

where

The poles and zeros can be displayed in the complex frequency, or s, plane as shown in Fig. 2. Note that

and

To obtain the frequency response of a lter described by

Eq. (1), we assume a sinusoidal input signal and, because
the network is linear, obtain a sinusoidal response. The

Typically frequency-selective lters are classied according to their frequency or phase response, and each response has its characteristic polezero pattern in the complex frequency, (s) plane. For reasons of stability, all poles
must be in the left half plane (LHP) excluding the j axis.
Thus, for example, the maximally at or Butterworth lowpass lter will have poles distributed on a semicircle centered at the origin in the left half s plane, and the equiripple
or Chebyshev low-pass lter will have its LHP poles on an
ellipse with center at the origin. In fact, it can generally be
stated that the poles of any practical frequency-selective
lter must have complex conjugate LHP poles. The only
other practical alternative is for the poles to lie on the negative real axis, which is the domain of inductorless, passive
RC networks. It can readily be shown that such lters, although perfectly stable and easily designable, are rarely
of any practical use because their in-band frequency se-

Filters, Analog

lectivity is extremely poor. Thus, for example, where the

center-frequency-to-3 dB-bandwidth ratio of a practical
LCR second-order bandpass lter can be arbitrarily high
(limited only by the nonideal characteristics of the inductors and capacitors), that same ratio of its passive RC counterpart will be less than 0.5. [An easy way to show this is as
follows: Referring to Eq. (1), assume that the two negativereal poles of a passive RC bandpass lter are at 1 and
2 on the negative-real axis in the complex-frequency
s-plane. Then we have (s + 1 )(s + 2 ) = s2 + ( 1 + 2 )s + 1 2
with 1 , 2 real and strictly positive. By identication with s2 + (p /qp )s + 2 p we then have p =
and p /qp = 1 + 2 , or 1/qp =

. Letting

x=
we therefore have 1/qp = x + 1/x, which is a
parabolic-like function whose minimum is equal to 2 for
x = 1, or 1 = 2 . Thus, (1/qp )min = 2, i.e., (qp )max = 0.5. However, because a passive RC network may have no multiple
poles (e.g., a double pole results in an innite spread of
the RC component values), it follows that 1 may not be
equal to 2 , i.e., 1 = 2 , and the RC pole qp , which we have
p , must be less than 0.5. Finally, because for
designated Q
a second-order band-pass lter, qp is identically equal to
the ratio of the center frequency to the 3 dB bandwidth, it
follows that for an RC band-pass lter this ratio must be
less than 0.5]. It is this characteristic feature of passive RC
networksnamely that their poles must lie on the negative real axis in the s plane, thereby drastically reducing
their capability of frequency selectionthat leads to the
basic problem of so-called inductorless lters.

The Problem of Inductorless Filters

We have indicated above that the transfer-function poles
of any practical frequency-selective lter (Butterworth,
Chebyshev, inverse Chebyshev, elliptic or Cauer, Bessel,
etc.) must be complex conjugate. In terms of the quantity
qp [the so-called pole Q, which is given by Eq. (7)], this
means that for any complex conjugate pole pair pi ,p i , the
corresponding qpi must be greater than 0.5. Note that with
the LCR lters of classical lter theory, we have no trouble realizing such complex conjugate pole pairs. However,
inductors are incompatible with integrated circuit technology, and with small-size hand-held equipment, at least at
frequencies below several megahertz. This is because the
needed inductance and hence the physical size of inductors
increases with decreasing operational frequencies. Consequently, the trend is to eliminate inductors from electronic
equipment wherever possible, leaving, in the case of LCR
lters, only RC circuits behind. As we have seen, however,
because the poles of RC circuits and lters are restricted
to the negative real axis, such inductorless RC lters, per
se, are useless for most practical lter design. In fact, denoting the pole Q of a second-order passive RC network by
p , it was shown above that Q
p < 0.5. As we shall see in
Q
what follows, with the inclusion of gain cells or ampliers,
this critical limitation can be readily overcome.

CASCADED ACTIVE RC BIQUADS

Cascaded biquad lter design is one of the oldest, and has
proved to be one of the most useful, of active RC lter design methods. This is mainly due (1) to their simplicity of
designviz., second-order (or third-order) lter sections,
or biquads, can be cascaded to provide any nth-order lter
functionand (2) to the excellent properties and low cost of
silicon integrated (CMOS and bipolar) voltage and current
ampliers.
Foremost among the voltage ampliers, the operational
amplier, or opamp, is ideally a differential-input, singleended, or differential-output amplier with innite gain,
innite bandwidth and input impedance, and zero output impedance and offset voltage. In practice the gain
may be anywhere between 60 dB and 100 dB, the bandwidth several tens to hundreds of megahertz, and the input
impedance several tens to hundreds of megohms. The offset
voltage may be several to tens of millivolts. These features
may be mutually exclusive; an opamp will be designed to
optimize one or more of them, and in addition numerous
others, such as dissipated power, noise, common-mode and
power-supply-rejection ratio, slew rate, and so on. As a network element, the idealized opamp can be considered to be
a voltage-controlled voltage source with innite gain and,
when used with negative feedback, a virtual ground at the
input.
More recently, current ampliers are also being used
in the form of operational transconductance ampliers
(OTAs), current feedback ampliers, and current conveyors. To a large extent these current-based ampliers are
duals of the voltage-based opamps. They have certain
technology-related advantages when built into CMOS or
BiCMOS technology, and are often advantageous with respect to required power and high-frequency operation. In
what follows the conventional opamp is assumed as the
basic gain element; the change to current-based ampliers
generally has very little consequence with respect to the
theoretical, and even to the practical, design aspects.
Recall from the above that the transfer function of an
nth-order lter network has the form given by Eq. (2),
where T(s) is a rational function in the complex frequency
variable s. The order of T(s) is determined by the order of
the denominator polynomial D(s). T(s) can be factored into
a product of second- or third-order functions Ti (s), according to n being even or odd. Thus, for n even,

and for n odd,

where is a negative real pole and the individual biquadratic functions Ti (s) have the general form

Filters, Analog

has negative real poles and consequently poor frequency

selectivity; an LCR network can, theoretically have poles
arbitrarily close to, but not on, the j axis, and therefore
its frequency selectivity is, theoretically, almost unlimited.
Thus, in an active RC network, the purpose of a gain element (whose gain we denote by ) is essentially to increase
p of each pole pair to a value qp that is larger than
the Q
0.5. This can be done in a number of different ways.
Single-Amplier Biquads (SallenKey Biquads)

Figure 3. Typical polezero pair: (a) of an elliptic LCR biquad

lter, qp = p /2 p ; (b) passive RC biquad lter, pi1 pi2 = 2 p ,
p = p /(pi1 + pi2 ), p = (pi1 + pi2 )/2.
Q

For most practical applications the poles of each biquad

function Ti (s) will be complex conjugate, as shown in Fig.
3(a). The location of the zeros is less signicant with regard
to their realization. Complex conjugate zeros are realizable
both with LCR and with passive RC networks. [Zeros on
the imaginary axis (as shown in Fig. 3) correspond to socalled elliptic or inverse Chebyshev lters.] The closer the
poles are to the j axis, the higher will be the selectivity of
the lter; the closer the zeros, the larger the lter attenuation at those frequencies. Referring to Eqs. 6 and 7, the
proximity to the j axis of the poles and zeros is indicated
by the quantities qp and qz , respectively; the closer they
are to the j axis, the higher the q values will be. If, on the
other hand, the critical frequencies (i.e., poles and zeros)
are on the negative real axis, that is, far from the j axis,
the corresponding q values will be less than 0.5; if they are
complex conjugate, the q values will be larger than 0.5 and,
in the limit (i.e., on the j axis), equal to innity. For the
pole Q (i.e., qp ) this latter case is forbidden, because poles
on, or to the right of, the j axis correspond to an unstable
network.
As pointed out above, it can be shown that the poles of
a passive RC network must be single and on the negative
real axis [see Fig. 3(b)], whereas there is no such limitation
on the location of the zeros. In terms of qp this means that
for a second-order RC network, that is, for a pole pair on
the negative real axis,

where we use the circumex on q, and on any other pertinent quantity describing the network, to indicate that
it is associated with a passive RC network. On the other
hand, we have seen that for any practical application, the
selectivity specications of the lter will require complex
conjugate poles:

As indicated in this expression, this condition is readily

satised by conventional LCR networks. Thus, the basic
difference between a passive RC and a passive LCR network is the location of the poles: a passive RC network

The biquad (biquadratic lter cell) is a building block

whose transfer function is given by Eq. (14), with the possible inclusion of a negative real pole as in Eq. (13). The negative real pole can be realized by a simple passive RC lowpass combination attached to the active biquad. Strictly
speaking, the biquad is then of third order, but the active
feedback part of the lter remains second-order and provides the complex conjugate pole pair.
Since power is generally at a premium in electronic
equipment, it is desirable, wherever possible, to realize the
biquad with as few ampliers or gain devices as possible.
For low-to-medium pole Qs, single-amplier biquads are
therefore not only feasible and, in most cases, adequate,
but also very desirable.
There are two basic categories of single-amplier biquads: those based on negative, and those based on positive feedback. The former can be grouped into three distinct classes, the latter into one. Because one of the earliest
publications on active biquads using single (vacuum-tube)
ampliers was by R. P. Sallen and E. L. Key (1), singleamplier biquads are often referred to as SallenKey biquads (even though modern single-amplier biquads have
little in common with those early units). The basic principles underlying these biquads are outlined in what follows.
Negative-Feedback Biquads (Q Multiplication). We start
out with the biquadratic transfer function T (s) of a passive
(no gain element) RC second-order network,

The poles of this function are, by denition, negative real,

p < 0.5. Multiplying Q
p by a quantity such that
i.e., Q

we obtain the same function as in Eq. (17), except that it

now has complex conjugate poles:

where

Note that must be selected to satisfy Eq. (20). It therefore

p , and on the required value qp .
depends on the value of Q
After some manipulation, and with the assumption that

Filters, Analog

> 1, Eq. (19) can be written as

where

Equation (21) corresponds to the transfer function of an

active RC biquad consisting of T (s), t 1 (s), and the amplier , connected in a negative-feedback loop as shown in
the block diagram of Fig. 4. A typical biquad with bandpass characteristics, which is based on Q multiplication, is
shown in Fig. 5.
Positive-Feedback Biquads (Sigma Reduction). Instead of
expressing the transfer function of the initial second-order
p as in Eq. (17), we can do so in
RC network in terms of Q
terms of the negative real quantity p , thus:

where

The inequality Eq. (24) indicates that the two poles of t (s)
are negative real. They can be made complex conjugate by
decreasing the quantity 2 p by some amount :

where

Equation (25) now corresponds to Eq. (19), since

meaning that T(s) in Eq. (25) now has complex conjugate

poles. T(s) can now be rewritten as

where

Equation (28) corresponds to an RC network consisting of

T (s) and t 2 (s) connected in a positive-feedback conguration with gain . This is shown in the block diagram of
Fig. 6. A low-pass biquad based on sigma reduction, that
is, positive feedback, is given in Fig. 7.
A Classication of Single-Amplier Biquads. It was shown
above that complex conjugate poles can be generated by Q
multiplication or sigma reduction applied to a second-order
passive RC lter network. The former method is based
on negative, the latter on positive feedback. Both can be

represented by the general feedback structure shown in

Fig. 8. Here the RC network in the forward path, t 12 (s),
determines the lter type (low-pass, high-pass, band-pass,
etc.). The RC network in the feedback path, t 32 (s), determines the necessary feedback polarity and the actual path
on the root locus with respect to , along which the initially negative-real poles of t 32 (s) move, to become the complex conjugate poles of T(s). It can be shown that there are
essentially three basic feedback functions t 32 (s) providing
complex conjugate poles with negative feedback, and one
basic feedback function t 32 (s) providing them with positive
feedback. The individual t 32 (s) functions are the transfer
functions of second-order passive RC networks providing
a low-pass, high-pass, and band-stop lter function in the
rst three classes, respectively, and a band-pass function
in the fourth class. This is the basis for the classication of
single-amplier biquads presented in Table 1.
Which of these biquads should be used to obtain a particular lter type depends on the application. More on this
and other practical design questions can be found in the
publications referred to in the reading list at the end of
this article.
Multiple-Amplier Biquads (State-Variable Biquads)
The biquads in the multiple-amplier category start out
from the nth-order transfer function given by Eq. (2), just
as the single-amplier biquads did. However, rather than
individually shifting the pole Qs of passive RC networks
into the complex-frequency plane with the help of negative or positive feedback, this method converts the transfer function into a function of interconnected integrators,
which can be graphically represented by a so-called statevariable signal-ow graph (hence the name state-variable
biquads). The method requires at least as many ampliers as the order of the transfer function (in the case of
a biquad it actually requires three opamps) and is therefore not economical of power. This disadvantage is compensated for by a exibility in terms of pole-frequency tuning, in that the pole frequency and Q can be adjusted, or
tuned, independently of one another. The method is not
restricted to biquads and can be directly applied to an nthorder transfer function (hence this method is often referred
to as the direct-form active lter design). Because of stability and sensitivity problems with higher than secondorder networks, the method is practically restricted to biquad design. In what follows we shall therefore illustrate
the method for a general second-order lter function, or
biquad.
Consider the general biquadratic function T(s) [which
corresponds to that given by Eq. (14)]:

Note that in the general case the coefcient B1 can be positive or negative, corresponding to nite zeros in the left
or right half plane, respectively. (Networks with left- and
right-half-plane zeros are often referred to as minimumphase and non-minimum-phase networks, respectively.) By

Filters, Analog

Figure 4. Block diagram, based on negative feedback, of an active RC biquad with complex conjugate poles.

Figure 5. A band-pass lter biquad based on negative feedback.

Figure 6. Block diagram, based on positive feedback, of an active RC biquad with complex conjugate poles.

Figure 7. A low-pass lter biquad based on positive feedback.

Filters, Analog

Figure 8. A general feedback conguration, which serves as

the basis for single-amplier active RC biquads.

contrast,A1 must be positive and greater than zero, because

the poles must lie in the left-half plane excluding the j
axis.
Dividing the numerator and denominator of T(s) by s2 ,
we obtain

This transfer function can now be represented by the statevariable signal-ow graph shown in Fig. 9(a). Using the
opamp realization for an integrator, lossy integrator, and
summer, we obtain the active opamp version of a general
biquad as shown in Fig. 9(b). The transfer function for this
circuit is

where Kb = R4 /R1 , K1 = R2 /R1 , R7 = R8 , and

With this general-purpose biquad, any arbitrary biquadratic lter function can be obtained by selecting the
resistors and capacitors to match the desired coefcients,
as in Eq. 33(a) to (e). Note, however, that at least three,
and in the general case four, opamps are required for its
realization. This is the penalty to be paid for the fact that
the complex-conjugate pole and zero pairs can be tuned independently of each other. Considering that pole and zero
tuning is in itself time-consuming and costly (and, in the
case of integrated circuits, only achievable by switching in
or out units of capacitor or resistor arrays), it follows that
multiple-amplier biquads are sometimes considered to be
impractical from the point of view of both cost and power
dissipation. On the other hand, in terms of integratedcircuit (IC) design, in which opamps take up less chip area
than capacitors of any practical size, multiple-amplier biquads are becoming increasingly useful and practical. One
reason for this is that pole and zero tuning can be accomplished individually by a single resistor or capacitor (designed especially in arrays of suitably small switchable
units) for a pole and zero pair, respectively. Furthermore
this biquad has other important advantages as far as IC
chip design is concerned. For one thing it uses opamps ex-

Filters, Analog

Figure 9. State-variable biquad: (a) signal-ow graph, (b) circuit diagram of the corresponding
general-purpose biquad.

clusively in the inverting mode, in which the input terminals are at virtual ground. This is a big advantage compared to the single-amplier biquads, in which opamps are
used with input terminals in common mode. The former,
compared to the latter, has advantages with respect to dynamic range, which becomes increasingly important as the
supply voltage is reduced. The trend in IC chip design is to
reduce the supply voltage as much as possible in order to
reduce power and chip size.
For another, the concept of modular cascades of biquads
in lter design provides a exibility not found in inductorless ladder simulations. In the case of high-selectivity
(high-pole-Q) and high-precision applications, the LC lter simulation method discussed below, in which inductors
are either directly replaced by gyratorcapacitor combinations (inductor simulation) or eliminated by the so-called
frequency-dependent negative resistor (FDNR) transfor-

mation, must also be considered. The reason for this is related to the extraordinary sensitivity properties of LCR
and simulated LCR ladder networks. These properties
must therefore be discussed rst, namely in the following
section, before the actual inductor simulation can be dealt
with.

SENSITIVITY PROPERTIES OF LC LADDER FILTERS

LC ladder lters, terminated at both ends by identical
resistors (which are selected according to the desired
impedance level of the lter), can be shown to have an
extraordinarily low sensitivity to variations of individual
component values. Thus, for example, if properly designed
and resistively terminated at both ends, the tolerances of
the individual components of an LC ladder lter may be

Filters, Analog

permitted to be orders of magnitude larger than the required tolerance of the resulting frequency response in the
passband. For example, it may be possible to guarantee a
0.1 dB ripple with components having no more than 1%
accuracy, if the order of the LCR ladder lter is sufciently
high. This remarkable feature of doubly resistively terminated LC ladder lters was rst pointed out by H. J. Orchard in 1968, decades after LC lters had rst come into
widespread use. Orchards theorem, as this low-sensitivity
property has come to be called, is the reason why lter designers using other than LCR components (e.g., active RC,
switched-capacitor, digital) attempt to maintain this excellent low-sensitivity property by simulating the behavior
and the properties of the equivalent LC ladder structure,
even though the actual components may be entirely different. Thus, the doubly terminated LC ladder structure
(real or simulated) plays a central role in lter theory and
design, no matter what the technology used for the actual
lter realization.
To understand the reason for the low-sensitivity property of LCR ladder lters it is interesting to quote Orchards
own words, namely (2):
If one designs a at-passband reactance ladder lter
to operate from a resistive source into a resistive load,
and arranges that, at the frequencies of minimum
loss over the passband, the source delivers its maximum available power into the load, one nds, to a
rst order of approximation, that, at every frequency
in the passband and for every component, the sensitivity of the loss to component tolerances is zero. This
is easily checked by noting that, when one has zero
loss in a reactance network, a component change, either up or down, can only cause the loss to increase;
in the neighbourhood of the correct value, the curve
relating loss to any component value must therefore
be quadratic, and consequently, d(loss)/d(component)
must be zero.
It follows from Orchards theorem that in any doubly
terminated passive LC ladder network, the transmission
sensitivity in the passband with respect to variations of the
components, will decrease with decreasing passband ripple
and with increasing lter order. This is counter intuitive
and in contrast to most other lter structures (and, indeed,
to linear systems), which generally become more prone to
instability and to high component sensitivity as the lter
complexity and order increase. Moreover, Orchards theorem explains why, in whatever technology (e.g., active RC,
digital, switched capacitor), the ladder structure simulating a doubly terminated LC ladder network is the preferred
structure when high performance is required. Here, performance, pertains to high selectivity and order of the lter,
as well as to low tolerance with respect to the passband
lter characteristics, and to a low sensitivity to component
variations in the passband.
Note that Orchards theorem does not make any claims
about insensitivity to component variations in the stop
band. Indeed, it can be shown that other structures, such
as biquad cascades, may well display a lower sensitivity

to component variations in the stop band. However, since

the specications in the passband generally have a higher
priority than those in the stop band, Orchards theorem
retains its importance. We should point out, however, that
since ladder networks are more difcult to manufacture, be
it as LC structures or in simulated form, economic considerations nevertheless often dictate the use of biquad cascades or variations thereof. In fact, it will depend on the
application and the overall requirements whether biquad
cascades or ladder structures (LC or simulated) constitute
the more appropriate realization. As so often in analog design, the choice of optimum lter circuits will depend on a
trade-off between performance characteristics (3). In this
case, the trade-off will be between tunability (in favor of
biquad cascades) and low sensitivity to component tolerances (in favor of indutorless LC ladder simulation).
ACTIVE INDUCTORLESS LADDER FILTERS
In the preceding section, the remarkable property of low
sensitivity to component variations in the passband of LC
ladder lters is discussed (Orchards theorem). It is this
property that has motivated the simulation of passive LC
ladder lters by active inductorless ladder lters, in those
cases in which real inductors may not be used. This is so
in most integrated circuit (IC) realizations, since inductors, being three-dimensional devices, are basically incompatible with IC manufacture. In order to understand the
principal methods of simulating inductors, we must rst
discuss some basic network elements that are required for
this purpose.
Basic Network Elements
The most important basic network elements necessary for
the description and analysis of active RC lters are the
following:
The Two-Port. The two-port, which represents one of the
most elementary concepts of network theory, is shown with
a load impedance ZL in Fig. 10. The two-port can be described by the equations

and

Here, the two-port equations, which fully dene the twoport, are given in terms of the elements of the so-called
[ABCD] or transmission matrix. The corresponding matrix
equation is then

To obtain the input impedance ZIN in terms of the [ABCD]

parameters, a simple calculation involving Eqs. (34) to (36)

10

Filters, Analog

Figure 10. A linear two-port with load ZL .

Figure 11. Idealized, physically nonrealizable network elements:

(a) nullator; (b) norator.

results in
Figure 12. Nullatornorator (nullor) equivalents of two commonly used active devices: (a) transistor, (b) operational amplier
(opamp).

This expression provides the basis for some of the ideal

network elements described further below.
The Nullator, Norator, and Nullor. The nullator and norator belong to a class of physically nonrealizable, idealized
network elements that have no conventional matrix representation. Nevertheless, they are very useful in the analysis and synthesis of idealized network elements. Naturally,
the idealized network must, at some point, give way to a
practical network with physically realizable components.
The description of the network with nullators and norators
then represents a sort of upper bound, whose idealized performance, due to nonideal effects, can only be approached,
but never actually reached.
The nullator [Fig. 11(a)] is dened by the condition

and the norator [Fig. 11(b)] by

where k1 and k2 are often said to be arbitrary. Actually

they are not, strictly speaking, arbitrary, but take on values imposed on them by the nullators and the remaining
circuitry in which they are embedded. Thus, when a norator is used in a circuit, the voltage V and the current I
take on the values needed to satisfy Kirchhoffs current
and voltage laws.
An idealized transistor can be represented by a
nullatornorator combination as in Fig. 12(a), an idealized
operational amplier (opamp) as in Fig. 12(b). In any given
circuit, nullators and norators always occur in pairs, also
called nullors. The step from an abstract, idealized, and
physically nonrealizable nullor circuit to a nonideal, physically realizable circuit is taken by replacing each nullor
either by a transistor (transistorization) or by an opamp.
Transistorization (in contrast to opamp design) requires

every nullor to have a common terminal, which corresponds

to the emitter of the transistor.
The Impedance Converter. The impedance converter is a
two-port whose [ABCD] matrix is given by

If A and D are frequency-dependent [i.e., A = A(s), D = D(s)],

then we have a general impedance converter (GIC). For the
case that A and D are constants, but of opposite polarity,
that is,

the impedance converter, loaded by ZL , has, according to

Eq. (38), the input impedance

We then speak of a negative-impedance converter (NIC),

because, for k1 > 0 and k2 > 0, and for a realizable (i.e., positive) ZL , the input impedance of the loaded two-port is
negative. Thus, for k1 = k2 = 1, we have ZIN = ZL .
A nullor realization of an NIC is shown in Fig. 13.
Straightforward application of the dening expressions of
the nullator and norator [Eqs. (39) and (40), respectively]
gives the input impedance as

Note that in Eq. (42) the pair A = k1 , D = +k1 2 corresponds to an NIC with voltage reversal, called a VNIC;
the pair A = +k1 , D = k1 2 corresponds to an NIC with current reversal, called a CNIC. The nullor conguration in

Filters, Analog

11

(see Fig. 15). The equivalent inductance is again given by

Eq. (48). An LC band-stop lter and its gyratorRC simulation are shown in Fig. 16. From Eq. (49) each gyrator
constant gi is given by

Figure 13. Nullatornorator (nullor) realization of a loaded

negative-impedance converter (NIC).

Fig. 13 corresponds to a CNIC; the nullor-dual circuit (i.e.,

nullator and norator exchanged) results in a VNIC. Note,
furthermore, that the conguration in Fig. 13 excludes a
one-transistor realization of an NIC because the nullor has
no common terminal. Using nullatornorator identities to
extend the circuit, a two-transistor realization can be obtained. Such nullatornorator extensions are based on the
fact that a nullator and norator in series is equivalent to
an open circuit; in parallel such a pair is equivalent to a
short circuit.
The Impedance Inverter. An impedance inverter is dened as a two-port whose [ABCD] matrix is given by

For the special case that

the input impedance to the loaded two-port becomes

This is the dening expression for the so-called gyrator,

whose symbolic representation is shown in Fig. 14. The
gyrator constants g1 = g2 have the dimensions of inverse
resistance, and a capacitively loaded gyrator (see Fig. 14)
has an inductive input impedance

An impedance inverter consisting of nullors and resistors that has gyrator characteristics is shown in Fig. 17.
Typically a gyrator-type impedance inverter requires three
nullors for its realization. For the nullor gyrator of Fig. 17
we have

Thus, with the load ZL = (sCL )1 , we have with Eq. (49)

Note that the nullators in Fig. 17 are designated ni , the

norators Ni , where i = 1, 2, 3; they are all identical, however,
and dened by Eq. (39) and Eq. (40), respectively.
The Frequency-Dependent Negative Resistor. The
frequency-dependent negative resistor (FDNR) is obtained by carrying out a so-called impedance-scaling
procedure on an LCR network, which is aimed at transforming all the inductors of the LCR network into
resistors. Impedance scaling implies multiplying all the
impedances of a network by a dimensionless constant k,
or by a frequency-dependent dimensionless factor k(s).
Signicantly, when carrying out an impedance-scaling
procedure on a network, the transfer function of the
network remains unchanged. Thus, letting

where 0 is arbitrary but often selected equal to the lter

cutoff frequency, and scaling each impedance associated
with Li , Cj , and Rv by k(s), the resulting scaled impedances
are

where the equivalent inductance Leq is given by

The gyratorcapacitor combination represents the oldest and most common method of simulating an inductance
without an actual electromagnetic inductive device being
used. The assumption that g1 = g2 = g very often holds in
practice, although if it does not, inductance simulation still
results.
To simulate a oating inductance we require two cascaded gyrators with a grounded capacitor in between them

Note that every inductor Li is transformed into a resistor



R i = 0 Li , every resistor Rv into a capacitor C v = (0 Rv )1 ,
and every capacitor Cj into a new element Dj = Cj /0 . The
last is known as a frequency-dependent negative resistor
(FDNR). The reason for this name is that for s = j (i.e., for a

sinusoidal signal) the impedance Z j is equal to (2 Dj )1 ,
and this negative, frequency-dependent quantity is real
and has the dimensions of resistance. The network symbol
for the FDNR is shown in Fig. 18(a). The FDNR transformation is most useful for low-pass-type lters comprising
numerous oating inductors and grounded capacitors, as

12

Filters, Analog

Figure 14. Simulation of a grounded inductor: (a)

the gyratorcapacitor combination where I1 = gV2 ,
I2 = gV1 ; (b) the equivalent inductor given in terms of
the capacitor C and the gyrator constant g.

Figure 15. Simulation of a oating inductor:

(a) the gyratorcapacitor combination; (b) the
equivalent inductor given in terms of the capacitor C and the gyrator constant g.

Figure 16. Inductor simulation of an LC band-stop lter: (a)

LC band-stop lter; (b) the gyratorC equivalent lter, where
g1 = (CL1 /L1 )1/2 , g2 = (CL2 /L2 )1/2 , and g3 = (CL3 /L3 )1/2 .

shown in the FDNR transformation of a fth-order elliptic low-pass LCR lter [Fig. 18(b)], into an equivalent inductorless FDNRRC lter [Fig. 18(c)]. Since in classical
lter synthesis every LCR network has a dual network,
one of which is a minimum-L and the other a minimum-C

network, the FDNR transformation is preferably applied

to the minimum-C version so that a maximum number of
inductors are transformed into resistors. The fact that the
resistive terminations become capacitive may be a problem
with the FDNR transformation; the problem can, however,

Filters, Analog

13

Figure 17. Nullatornorator realization of a gyrator

with load capacitor CL . The gyrator consists of two voltagecontrolled current sources (VCSS) connected in parallel
and in opposite directions. The upper VCS is positive, the
lower one is negative.

Figure 18. Inductor simulation based on the

frequency-dependent negative-resistor (FDNR)
transformation: (a) FDNR symbol; (b) fth-order
elliptic LCR low-pass lter; (c) FDNR-transformed
equivalent circuit.

generally be circumvented in a number of ways. One is to

connect a large-valued resistor in parallel with the terminating capacitors; another is based on so-called GIC embedding, the principles of which are outlined below under
Active RC Simulation of LCR Ladder Filters.
The nullor realization of an FDNR can be obtained by
cascading two NICs of the kind shown in Fig. 13, resulting
in the nullor conguration shown in Fig. 19. It follows from
Eq. (44) that the input impedance of this conguration is
given by

Depending on which of the ve impedances in this expression are resistive and which capacitive, either an FDNR or
a simulated inductor (equivalent to a gyratorC combina-

tion) can be obtained. Thus, if any one of the three pairs,

(Z1 , Z3 ), (Z1 , ZL ), and (Z3 , ZL ), is capacitive and the remaining three impedances are resistive, an FDNR is obtained.
Similarly, if either Z2 or Z4 is capacitive and the other four
impedances resistive, a simulated inductor results.
Using two opamps to replace the two nullors in the conguration of Fig. 19, a working circuit is obtained. Again,
there are various ways of combining the nullors (e.g., [n1 ,
N1 ] and [n2 , N2 ], or [n1 N2 ] and [n2 N1 ]), and for each combination, more than one method of connecting the opamps.
(Remember, in contrast to a transistor, a nullor being replaced by an opamp requires no common terminal.)
Figure 20 shows an opampRC realization of the fthorder FDNRRC low-pass lter of Fig. 18(c). The component selection in terms of resistors and capacitors, combined with the opamp connection to obtain the FDNRs

14

Filters, Analog

Figure 19. Two nullor-based negativeimpedance converters (NICs) in cascade,

with loading impedance ZL . This conguration serves as a basis for gyrator and FDNR
design.

Figure 20. FDNR-based opampRC realization of

the low-pass lter in Fig. 18(c).

shown in Fig. 20, has proved itself well in practice. Notice that in this realisation of the LCR lter, the source
resistor R1 in Fig. 18(b) was selected to be zero, in order
to guarantee a dc path from source to load. Although this
violates Orchards theorem, which requires equal resistive
terminations at the source and load, the penalty involved,
in terms of increased component sensitivity, is often acceptable and will generally still be better than it would be with
a cascaded-biquad design.
Active RC Simulation of LCR Ladder Filters
Under Sensitivity Properties of LC Ladder Filters the remarkable property of low sensitivity to component variations in the passband of LC ladder lter structures was discussed (Orchards theorem). This property has motivated
the simulation of LC ladder lters in those cases in which
high lter performance is required but inductors may not
be used, as in integrated-circuit realizations, both analog
and digital. It has been shown above that the two most important active elements used to build active-RC simulated
LC ladder lter networks are (1) the gyrator for inductor
simulation and (2) the frequency-dependent negative resistor (FDNR), as it occurs in conjunction with the FDNR

transformation of LCR lter networks. Which of these two

approaches is used depends on the LCR lter that is to
be rendered inductorless. Some illustrative examples will
demonstrate this in what follows.
Consider, for example, the fth-order elliptic low-pass
lter shown in Fig. 21. This is the minimum-L version of
the minimum-C lter shown in Fig. 18(b). Simulating the
inductors by gyratorC combinations, we obtain the active
RC simulated inductor circuit shown in Fig. 22. Note that
each oating inductor (i.e., L2 and L4 ) requires two gyrators, and each gyrator requires at least two opamps for its
realization. This is because, in practice, gyrators are realized by a nullor conguration as shown in Fig. 19, resulting in the two-opamp structures shown in Fig. 20. Thus
the gyratorC replacement of L2 and L4 will require eight
opamps, which for a fth-order lter is quite uneconomical,
with regard to both component cost and dissipated power.
Floating inductors are typical for a low-pass lter, because a true low-pass characteristic must also transmit
direct current (dc). The oating inductors could, of course,
be eliminated by an FDNR transformation. Carrying this
transformation out on the LCR lter of Fig. 21 would,
however, be counterproductive. L2 and L4 would indeed be
transformed into resistors, but each of the ve capacitors

Filters, Analog

15

Figure 21. The LC-dual, or minimum-L,

version of the fth-order elliptic LCR lowpass lter of Fig. 18(b).

would be transformed into an FDNR. A grounded FDNR

can be realized by two opamps; a oating FDNR requires
more. Thus, an FDNR transformation of the minimum-L
lter in Fig. 21 requires well over ten opamps, which is
even more extravagant in opamp count than the gyratorC
version of Fig. 22.
However, the situation looks quite different for the
equivalent minimum-C version of a lter. This is the lter shown in Fig. 18(b) and, after impedance scaling by
0 /s (where 0 is selected as the lter cutoff frequency c ),
corresponds to the FDNR-transformed lter in Fig. 18(c).
Here each impedance-scaled inductor Li becomes a resis

tor R i = 0 Li , each resistor Rj a capacitor C j = (0 Rj )1 ,

and each capacitor Cv an FDNR Z v = (s2 Dv )1 , where
Dv = Cv /0 . Note that there are now only two active elements in the lter: the two impedance-transformed capacitors, each of which becomes a grounded FDNR. With two
opamps required for each FDNR, the overall circuit now
comprises four opamps, in addition to numerous resistors
and capacitors, as shown in Fig. 23. Thus, compared to the
simulated inductor version of the lter using gyrators as
in Fig. 22, the number of opamps using the FDNR transformation has now been halved.
We now compare the simulated LC ladder lter of Fig.
23 with an equivalent cascade of single-ended biquads to
realize the same fth-order low-pass lter. Using typical biquads capable of realizing nite zeros for an elliptic lter,
we obtain the circuit conguration shown in Fig. 24. Here
the opamp count has been halved again, but this reduction comes at a price. Because the sensitivity to component
variations is higher with the biquads than with the simulated LCR ladder lter, the performance in the passband
of the biquad cascade, when subjected to ambient changes
involving temperature, humidity, or aging, will be signicantly worse for the biquads than for the simulated LCR
ladder lter. Furthermore, due to the higher sensitivity

Figure 25. Amplitude response of fth-order elliptic low-pass lter obtained by measurement of the lter shown in Fig. 23 and
in Fig. 24 (nominally, no difference between the two lters can be
distinguished).

of the biquads, to obtain an accurate nominal frequency

response, either the lter will have to be ne-tuned, or
very accurate, low-tolerance, and therefore expensive RC
components must be used. By contrast, because of its low
sensitivity, the FDNR-simulated ladder network of Fig. 23
can be built with less expensive components of reasonable
tolerance, while achieving a highly accurate frequency response, often with no ne tuning required. Nominally, however, with ideal components, the lter response of the two
lters (shown in Fig. 25) will be identical, and will satisfy
the intended specications.

16

Filters, Analog

Figure 23. FDNR-based opampRC realization of the fth-order elliptic low-pass lter in Fig. 18(c), with component values selected for
amplitude response shown in Fig. 25.

The FDNR transformation generally provides the most

efcient (in terms of opamp count) inductorless active RC
circuit for low-pass specications, because low-pass lters
contain oating coils in order to guarantee a dc path from
source to load. Simulated oating inductors require two
gyrators per inductor, and, as shown in the preceding example, this may result in twice as many opamps being
required as for the corresponding FDNR realization. The
FDNR preference will not necessarily hold for any general
lter application, however; for general lters a combination
of gyratorC, FDNR, and GIC embedding will more typically provide the most robust (with respect to component

tolerances) and economical inductorless lter. An example

to illustrate GIC embedding is shown next.
A general impedance converter, or GIC, was briey introduced above (under Basic Network Elements) as a twoport with a transmission, or ABCD, matrix given by

Filters, Analog

Loading a GIC with an impedance ZL at the output terminals, the input impedance results from Eq. (38) as

where A(s)/D(s) is a dimensionless but frequencydependent quantity designated k(s).

GIC embedding is based on the fact that a two-port,
which is characterized by its ABCD matrix and embedded between two GICs as shown in Fig. 26, has the overall
transmission matrix

For k1 (s) = k(s) = k1 2 (s) this simplies to

Since the dimensionless transfer parameters A and D

remain unaltered, and the impedance and admittance parameters are scaled by k(s) and [k(s)]1 , respectively, embedding between two GICs is identical with impedance
scaling of the embedded network by k(s). If k(s) = 0 /s, then
the embedded network undergoes an FDNR impedance
transformation. Thus, for example, a resistive network, embedded between two GICs with k1 (s) = s/0 and k2 (s) = 0 /s,
appears as an all-inductive network, as shown in Fig. 27.
In practice, GIC embedding and gyratorC substitution
of inductors can be applied within the same network, depending on the conguration. This is shown in Fig. 28,
where a relatively complex LCR band-pass lter is shown
in (a) and the equivalent inductorless ladder lter is shown
in (b). In the latter, GIC embedding and gyratorC inductor simulation alternate to provide the most efcient simulated active RC ladder lter. Note that the embedding is
introduced at the terminal end so as to leave the terminating resistor R (and also the rst capacitor C1 ) intact. This
is the most elegant way of avoiding the R-to-C transformation of the terminal resistors that would otherwise occur
in a straightforward FDNR transformation.
OTHER METHODS OF INDUCTORLESS FILTER DESIGN
There are numerous other methods of designing inductorless active RC lters which are developed hand in
hand with new emerging IC technologies. Many of these
are closely related to CMOS IC technology and use the
transconductance gm of CMOS transistors together with
CMOS-realized capacitors to provide both the RC time constants and the active gain in current-mode type circuits
used for the design of inductorless lters. The basic concepts are very similar to those dealt with above, i.e. they are
current-mode versions of the opamp-based voltage-mode
circuits described earlier.

17

Another design technique that has been successfully

used for inductorless IC lter chips is that of deriving a
signal-ow graph (sfg) equivalent of the original LCR ladder lter satisfying the desired lter specications. Thus,
instead of deriving the sfg from the transfer function as
in Fig. 9 above, it is derived from the LCR lter circuit.
As in Fig. 9, the sfg is then transformed and manipulated until it consists of branches with only integrators,
adders, and inverters. These can readily be realized with
CMOS-compatible circuits. In voltage-mode circuits, the
integrators consist of opamp-based circuits with a capacitor in the negative feedback path and a resistor connected
to the inverting input terminal. A signicant advantage
of such inverters is that the input terminal is at virtual
ground, which, as was pointed out above, is advantageous
with regard to maximizing the dynamic range of the lter.
Current-mode versions of the sfg integrators also exist, and
their use is mainly dictated by the IC technology available.

18

Filters, Analog

Figure 26. Embedding a network N between two general impedance converters (GICs), with converter constants k1 (s) and k2 (s), respectively.

Figure 27. (a) A resistive network embedded between two GICs; (b) the equivalent inductive network.

Figure 28. Inductorless simulation of an LC band-pass lter using GIC embedding and gyratorC
substitution of inductors.

Filters, Analog

BIBLIOGRAPHY
1. R. P. Sallen, E. L. Key, A practical method of designing RC
active lters, IRE Trans. Circuit Theory, CT-2: 7885, 1955.
2. H. J. Orchard, Inductorless lters, Electron. Lett., 2 (6):
224225, 1968.
3. C. Toumazou, G. S. Moschytz, and B. Gilbert, Trade-Offs in
Analog Circuit Design, The Designers Companion, Kluwer
Academic Publishers, 2002.

Reading List
L. T. Bruton, RC Active Circuits, Theory and Design, Englewood
Cliffs, NJ: Prentice-Hall, 1980.
M. G. Ellis, Sr., Electronic Filter Analysis and Synthesis, Norwood,
MA: Artech House, 1994.
W. E. Heinlein, W. H. Holmes, Active Filters for Integrated Circuits,
New York: Springer-Verlag, 1974.
M. Herpy, J. C. Berka, Active RC Filter Design, Amsterdam: Elsevier, 1986.
L. P. Huelsman (ed.), Active RC Filters: Theory and Application,
Stroudsburg, PA: Dowden, Hutchinson and Ross, 1976.
D. E. Johnson, J. L. Hilburn, Rapid Practical Designs of Active
Filters, Long Beach, CA: Wiley, 1975.
H. Y.-F. Lam, Analog and Digital Filters: Design and Realization,
Englewood Cliffs, NJ: Prentice-Hall, 1979.
C. S. Lindquist, Active Network Design with Signal Filtering Applications, Long Beach, CA: Stewart and Sons, 1977.
S. K. Mitra, Analysis and Synthesis of Linear Active Networks, New
York: Wiley, 1969.
S. K. Mitra, C. F. Kurth, Miniaturized and Integrated Filters, New
York: Wiley, 1989.
G. S. Moschytz, Linear Integrated Networks: Fundamentals, New
York: Van Nostrand Reinhold, 1974.
G. S. Moschytz, Linear Integrated Networks: Design, New York:
Van Nostrand Reinhold, 1975.
G. S. Moschytz, P. Horn, Active Filter Design Handbook: For Use
with Programmable Pocket Calculators and Minicomputers,
Chichester: Wiley, 1981.
R. Schaumann, M. S. Ghausi, K. R. Laker, Design of Analog Filters:
Passive, Active RC, and Switched Capacitor, Englewood Cliffs,
NJ: Prentice-Hall, 1990.
A. S. Sedra, P. O. Brackett, Filter Theory and Design: Active and
Passive, Portland, OR: Matrix Publishers, 1978.
M. E. Van Valkenburg, Analog Filter Design, New York: Holt, Rinehart and Winston, 1982.
A. B. Williams, Active Filter Design, Dedham, MA: Artech House,
1975.
A. B. Williams, F. J. Taylor, Electronic Filter Design Handbook, 3rd
ed, New York: McGraw-Hill, 1995.

GEORGE S. MOSCHYTZ
Swiss Federal Institute of
Technology (ETH), Zurich,

Switzerland

19

NONLINEAR NETWORK ELEMENTS

NETWORK, NONLINEAR
Most of the natural laws of physics can be stated in terms
of partial differential equations (PDE) since they describe
physical phenomena by relating space and time derivatives
and these operations represent natural things such as velocity, acceleration, force, magnetic ux, currents.
From a theoretical point of view, the electrical behavior
of semiconductor devices can be described solving a set of
nonlinear partial differential equations given by the combination of Maxwells equations and continuity equations
for electrons and holes.
However, as for practically all modern microelectronic
devices the wavelength associated with the maximum operating frequency is signicantly longer than device dimensions, the set of equations can be restricted to Poissons
equation and to continuity equations for the free carriers.
Nonetheless, even the terminal behavior of a quite simple device like a pn junction can be achieved only through a
cumbersome and very time-consuming numerical analysis.
For purposes of analysis and design, most modern nonlinear semiconductor devices and electronic systems can be
replaced by models made of basic nonlinear circuit elements
such as two terminal, multi-terminal and multi-port resistors, inductors, capacitors and independent voltage and
current sources.
The interconnection of these elements is called electric
circuit, whereas physical circuit is a collection of interconnected electrical devices.
In a physical circuit the current I(t) through any device
terminal and the voltage V(t) across any pair of terminals
at any time are well dened.
Additionally, if the electrical charges into the device can
be considered function of the instantaneously values of the
voltages applied to device terminal only, (quasistatic hypothesis (1, 2)), the device may be approximated by the
connection of several lumped circuit elements, i.e. can be
modeled by a nite number of equation involving only algebraic, ordinary differentiation and integration operations
on the terminal variable at any time.
For example, in a one-port this means that the current entering one terminal appears instantaneously at the
other.
The assumption of no spatial variables implies that all
voltages V(t) and currents I(t) are functions of only one
independent variable, namely, the time t.
In addition, all circuit elements are assumed to be ideal
with perfectly conducting terminals, and without any parasitic effects.
There is no less of generality in this assumption, since
any important parasitic effect may be modeled by introducing additional circuit elements.
Finally, we assume that each circuit element is dened
for all voltage and current waveform for all frequencies.
In other words, there are no time-rate dependent circuit
parameters because such elements would produce a lack of
predictability under arbitrary external interconnections.

A model is a representation of a device by using a set

of basic components under a series of constraints and assumptions.
Models to be used in circuit simulators for the analysis
and design of integrated circuits must be analytical and
simple enough to enable simulations lasting not more than
some tens of minutes even in the extreme case of transient
analysis.
Thus, several hypothesis and limitations must be introduced.
Analytical models are often derived for a prototype
device with a very simplied physical description (onedimensional structure, regional approach, abrupt doping
variations from one region to another).
The physical effects associated to the two- or threedimensional nature of real geometries and proles are
subsequently introduced by simply performing semiempirical manipulations to basic models and to some parameters denition.
By doing so, for a given device one can nd in circuit
simulators a set of models (called compact models) with
several degrees of complexity.
This result, which could appear strange at the rst
glance, is very useful from a practical point of view, as
the designer can validate new ideas on circuit topologies
by making simulations with simple (and thus low timeconsuming) models, turning to the adoption of higher-order
modelling when the basic circuit really works.
Additionally, in model derivation for computer-aideddesign (CAD) purposes it is supposed that device currentvoltage and charge-voltage relationships can be written in
such a way that device networks associated with mathematical models can be implemented by a suitable connection of one-port or multi-terminal devices.
The estimation of values of the several parameters in
the models are left to detailed comparisons with experimental data; in such a way, several of the parameters do
not maintain a real physical meaning but acquire just the
meaning of tting or semi-empirical parameters.
Moreover, models for transient analysis are obtained by
simply adding to dc models nonlinear reactive one-port elements which are automatically skipped from circuit simulators during dc analysis.
Hence, on the basis of the above observations, in this
work we will rstly briey review the models of basic nonlinear one-port and multi-terminal devices and then we
will present models used in circuit simulators for some of
the more important semiconductor devices.

BASIC IDEAL ELEMENTS

Network Theory is a series of denitions, methods and assumptions used to analyse the properties of any electrical
circuit, in both its quantitative (i.e. values of the electrical variables) and qualitative (i.e. properties of the circuit)
behaviours.
All the electrical variables are unambiguously dened
and the basic laws of the Theory are Kirchhoff s current
and voltage laws.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Network, Nonlinear

In Linear Circuit Theory (3, 4), elementary one-port

(resistors, capacitors, inductors, independent current and
voltage sources), basic two-ports (ideal transformer, gyrator, controlled sources, ideal operational amplier) and
complex N-ports, obtained by connecting the basic elements, are constructed.
For nonlinear circuits one can proceed in a similar way,
both introducing nonlinear versions of the above elements,
and considering a wider range of basic elements (12, 14).
To characterize a nonlinear device, one can refer to the
terminal voltage V and current I that may be readily measured externally, together with the charge Q and the magnetic ux
that can be either measured by appropriate
instruments or indirectly obtained by integrating I(t) and
V(t) functions:

Considering all possible pairwise combinations of the four

variable (V, I, Q,
), the four unrelated combinations (V, I),
(
, I), (Q, V) and (
, Q) dene the four basic two-terminal
network elements named resistor, inductor, capacitor and
memristor, respectively.
Moreover, a two-terminal element is said to be timeinvariant iff its constitutive relation does not depend explicitly on time, otherwise it is time-varying.
Figure 1 shows typical symbols used to denote these
nonlinear elements and the links between the different
variables involved in the denitions.
It is worthwhile to note that the dark band in each symbol necessarily distinguishes the two terminals when the
element characteristic is not symmetric.
Obviously, if the element is linear, its characteristic remains unchanged after swapping the terminal and standard symbols can be used.
The nonlinear element shown in Figure 1 are truly basic not only because they include the three classical circuit elements as special cases but also because the value
of their associated small-signal resistance, inductance, capacitance and memristance are frequency independent, i.e
they do not change with the frequency of an innitesimally small sinusoidal testing signal about any xed operating point.
It is possible to generalize the above denitions to introduce an innity variety of higher order basic circuit elements by means of the complementary signal pair (V() ,
I() ) (5).
In this general case, the constitutive relation consists
of a system of nonlinear, algebraic, ordinary differential
and/or integral equations involving both the terminal variables V and I and their higher order derivatives:
d V (t)
dt
d I(t)
()
I (t)

dt
V () (t)

Z.
Z.

Assuming negative values to indicate integration, using

this notation, one can classify resistor (0,0) and memristor
(1,1) as zeroth-order elements while inductor (1,0) and
capacitor (0,1) as rst-order element.

It is worth to notice that given V(t) and I(t), we can generate the corresponding kth-order voltage signal V(k ) (t) or
the hth-order current signal I(h) (t).
By doing so, the complementary signal pair (V(k ) (t),
I(h) (t)) represents physical signals and can therefore be
measured by appropriate instrumentations.
Nonlinear Resistor and Sources
A nonlinear resistor is a one-port device dened by a constitutive relation denoted by the algebraic relationship

Obviously, a resistor is said to be linear iff its constitutive relation is a straight line through the origin in the V
I plane with a constant slope equal to R.
Relation (2) denes the so-called autonomous resistor,
whereas if time is explicitly involved the resistor is said to
be time dependent.
If, as often happens for real devices, an explicit singlevalued relationship for the current versus voltage can be
derived, previous equation can be rewritten as:

where function g is dened for the set of the admissible

voltages for the resistor.
In this case, the resistor is said to be voltage-controlled.
In the particular case in which current is independent of
voltage, Eq. (4) becomes I = Io and describes a constant
current source, and if the constant Io is equal to zero one
models an open circuit.
Alternatively, if the voltage can be written as a singlevalued function of the current:

where function h is dened for the set of the admissible currents for the resistor, the resistor is said current-controlled.
In the particular case in which voltage is independent
of current, i.e. V = Eo , one gets a constant voltage source,
and if the constant Eo is equal to zero one describes a short
circuit.
When relation (2) depends on some independent variable x one has a controlled resistor characterized by a family of V I curves, each of which corresponds to a specic
value of the controlling variable.
A special class of controlled resistors includes the xcontrolled voltage source and the x-controlled current
source represented by V I curves that are independent
of the terminal current Ix or voltage Vx , respectively.
If the controlling variable x is non electrical, the controlled source is usually called transducer, while when the
controlling variable x is electrical, four type of nonlinear dependent sources extending the linear denitions are possible: voltage controlled voltage source (VCVS) V = f(Vx ),
current controlled voltage source (CCVS) V = f(Ix ), current
controlled current source I = f(Ix ) (CCCS) and voltage controlled current source I = f(Vx ) (VCCS).
These elements can be modelled using only nonlinear
resistor and linear controlled sources. As an example, Fig.
2 shows two possible equivalent circuit models for a VCVS
and CCCS nonlinear controlled source described by f1 and

Network, Nonlinear

Figure 1. The four basic nonlinear elements and their symbols. Out of the possible pairings of the four basic variables V, I, Q and
, two

are related by I = Q and V =
.

Figure 2. (a) A nonlinear Voltage Controlled Voltage Source (VCVS) (a) and (b) a nonlinear Current Controlled Current Source (CCCS)
(b) together with two possible equivalent realization using linear controlled sources and nonlinear resistors.

f2 functions and using nonlinear resistors with Iy = k1 f1

(Vy ) and Vy = k1 f2 (Iy ). Dually for the other two sources.
As well known (3), only a strictly monotonically increasing resistor is both voltage-controlled and currentcontrolled and can therefore be described by Eqs. (4)(5).
Another interesting nonlinear resistor is the ideal diode
shown in Fig. 3(a), having a constitutive relation expressed
by:

If the diode is reverse biased (V < 0) the current is zero,

i.e. the diode acts as an open circuit, while if it is conducting
(I > 0) the voltage is zero, i.e. the diode acts as a short
circuit.
In this case, as the resistor is controlled by neither current nor voltage, the general relation (2) must be used. The
model for a physical junction diode Fig. 3(b) will be presented in the Subsection Semiconductor Diode.
Nonlinear Capacitors
A nonlinear autonomous capacitor is a one port device dened by a constitutive relation denoted by the algebraic

Network, Nonlinear

Figure 3. Symbols adopted for an ideal (a) and for a pn semiconductor junction diode (b) and their corresponding I V characteristics.

Nonlinear Inductors

relationship

A nonlinear inductor can be dened as a one-port device

establishing a nonlinear relationship:
A capacitor is said to be linear iff its constitutive relation
is a straight line through the origin in the plane Q V with
a constant slope equal to C.
As for the resistor, it is possible to dene a timedependent capacitor and a controlled-capacitor, characterized by a family of Q V curves, each of which corresponds
to a specic value of the controlling variable.
As, it often happens, one can give an explicit analytic
form for the constitutive relation of the type

Eq. (13) denes the so-called autonomous inductor, but it

is possible to dene a time-dependent inductor and a controlled inductor, characterized by a family of
I curves,
each of which corresponds to a specic value of the controlling variable. An inductor is said to be linear iff its constitutive relation is a straight line through the origin in the

I plane with a constant slope equal to L.
Often, magnetic ux can be explicitly expressed as a
function of the current:

a nonlinear voltage-controlled capacitor results, while if

one has
so the nonlinear inductor is said current-controlled,
whereas it is ux controlled if
the capacitor is charge controlled. In particular, starting
from Eq. (8), the current can be expressed in term of an
incremental capacitance C(V(t))
dq(V (t)) dV (t)
dV (t)
I(t) =
= C(V (t))
dV
dt
dt

In the rst case Eq. (14) can be expressed in term of an

incremental inductance L(I(t))

(9)

It is worth notice that the incremental capacitance is

a function of the capacitor voltage and become a constant
only in the case of a linear capacitor.
As an example of nonlinear capacitor (see Fig. 8) one
can consider the following simplied formulation between
the depletion region charge Q and junction voltage V for a
reverse-biased pn junction diode (varactor):

V (t) =

d(I(t)) dI(t)
dI(t)
= L(I(t))
dI
dt
dt

For a linear inductor, the incremental inductance coincides

with the inductance.
Two superconductors separated by a thin insulating
layer such as oxide form a Josephson junction (6). A physical study proves that when contacts are built with the same
metal, the current I varies sinusoidally with
, namely
I = I0 sin k

where V is the operating voltage, while Qo , VJ and m are

suitable constant parameters. Because the relation (10) is
dened for V < VJ , this capacitor is not voltage-controlled
for all values of voltage.
In a similar way, for a two-terminal MOS structure, one
achieves the following relation between charge and applied
gate bias (1):

where the surface potential s is a strongly nonlinear function of V, while Cox , VFB and are constant parameters.

(14)

(15)

where I0 is a device parameter and k = 2e/
a fundamental constant. This device is an example of a not currentcontrolled element, so its small-signal inductance is not
uniquely dened. However, the Josephson junction is a
ux-controlled device and can be classically modeled with
a parallel connection of a linear capacitor C, a linear resistor R, and a nonlinear inductor L with the constitutive
relation shown in Eq. (17).
A device made of a conducting wire wound around a
ferromagnetic material shows a nonlinear measured
I
characteristic. In this case (see Fig. 5), the nonlinear behavior is due to the variation of the permeability of ferromagnetic materials with the applied magnetic eld intensity.

Network, Nonlinear

Figure 4. Nonlinear Q V characteristic referring to a depletion region charge Q as a function of junction voltage V.

The multi-valued function obtained applying a sinusoidal

current excitation is commonly referred to as an hysteresis loop. A simple model describing this device operating
under periodic excitation is mathematically dened by (7)

= g[I f (
)]

(16)

and can be synthesized by connecting a nonlinear inductor

described by IL = f(
L ) in parallel with a nonlinear resistor characterized by VR = g(IR ) as shown in Fig. 6. In this
case, g and f are continuous monotone increasing functions
determined directly from the hysteresis loop.
Hysteretic phenomena are also deliberately introduced
in circuits and systems. Generally speaking, one refers to
hysteresis every time the value of the output depends on
both the present and past value of the input. Usually one
exploits this feature to build oscillators and noise rejection
circuits such as comparators, Schmitt triggers and multivibrator circuits (8, 9) which nd applications both in pulse
and digital systems and have been recently used also in
neural-type microsistems and to generate chaos (10). For
this reason, only if parasitic energy storage elements such
as lead inductance and capacitance of the interconnecting
wires are included in the circuit model one can readily explain the jumps which occur measuring the physical circuit. In particular, a non monotone voltage-controlled resistor needs a small parasitic capacitor in parallel with it,
while a model of a non monotone current-controlled resistor needs a series parasitic inductance to be complete (11).
Memristor
Finally, the memristor is a one port dened by a constitutive relation denoted by
f M (
, Q) = 0

(17)

It is a component similar to a resistor but with memory

capabilities (12).
In the Linear Circuit Theory, there is no need to introduce this element since it is equivalent to a linear resistor.
In fact, derivating with respect to the time of the constitutive relation for a linear memristor
= RQ simply gives
V = RI. A memristor is said to be linear iff its constitutive
relation is a straight line through the origin in the
Q
plane with a slope equal to M. Differently, deriving with
respect to time the nonlinear relation

leads to
V =

d
I = M(Q)I
dQ

that can be understood as a linear resistor described by

Ohms law, except that its small-signal resistance M(Q) is
not constant, but
varies with the instantaneous value of
t
the charge Q(t) = I()d.
Examples of physical devices showing a qualitative
memristor-like behavior are thermistors, amorphous devices, some biological systems and, in general, switching
and time-delay phenomena. Considering a negative temperature coefcient thermistor that can be described by

one can model this device as current-controlled memristive

one-port

where R(T0 ) is the resistance measured at some reference

temperature T = T0 , is the dissipation constant, C is the
heat capacitance and is a material constant (13).
Finally, this important element can be favorably use to
model many quantum mechanical phenomena (tunneling,
Coulomb blockade, ion-membrane dynamics) which are essential to the nonlinear dynamics of many modern (molecular and nano) devices.
MULTI-TERMINAL ELEMENTS
By means of the same approach used in the previous section, the concept of two-terminal element can be extended
to characterize multi-terminal devices. In particular, one
can select a set of measurable independent variables and
take a series of external measurements to derive consistent relationships among the variables. Kirchhoff s current
and voltage laws show that one terminal can be arbitrarily
chosen to be the common, so that voltages of the remaining
ones are measured with respect to it.
In this way, among the N currents entering the terminals and the N voltages between terminals, only (N 1)
currents and (N 1) voltages are independent. In general,
N 1 distinct laboratory setups are required to completely

Network, Nonlinear

Figure 5. A nonlinear inductor driven by a periodic voltage signal (a) and the hysteresis loop associated with the steady-state waveform

(t) and I(t).

Figure 6. A simple lumped circuit model of hysteretic inductor operating under periodic excitation.

characterize an Nterminal element: each setup could involve as many sets of interesting variables (Vj , Ij , Qj or
j )
curves as are necessary to include all desired combinations
of parameter values of the controlling variables. Any independent combinations of these variables constitutes a valid
set of measurements.
Similarly to the classication of two terminal elements,
one can consider: Nterminal resistors, Nterminal capacitors, Nterminal inductors if the relationship involves only
(Vj , Ij ), (Vj , Qj ) (Ij ,
j ), j = 1 (N 1), respectively.
For example, ideal multi-terminal elements such as gyrators, ideal transformers, controlled sources and opamps
are four-terminal resistors (3). Finally, there is another
important class of networks called two-port resistors that

transforms a given V I curve into a new V I one.
According to the type of transformation performed, they
are called scalors, rotators and reectors, together with
mutators, i.e. linear algebric two-ports that are able to
transform a basic network element (R, C, L, M) into an
element of different type. These can be usefully adopted to
generate many new nonlinear components (14).

Example 1
Under some simplifying assumption a three-terminal resistor is representative of many practical devices, such as
bipolar, eld-effect transistors and silicon-controlled rectiers (SCR) (15).
A three-terminal resistor can be characterized by two
separate sets of measurements: for example, the input and
output characteristic curves. The rst set is obtained by
applying an independent source S2 (which may be a voltage
source or a current source) across terminals bc as show in
Fig. 7(a) and measuring the V1 I1 curve across terminals
ac of the resulting two-terminal controlled element. For
each value of the independent source S2 , a corresponding

V I curve is obtained forming a whole family of V1 I1

curves.
In a similar way, the second set is obtained by applying another independent source S1 (which can be either
a voltage source or a current source) across terminals ac
as shown in Fig. 7(b) and measuring the V2 I2 curve
across terminals bc of the resulting two-terminal resistor.
An analogous set of V2 I2 curves can be plotted with
the value of S1 as a parameter. Additionally, any two sets
of measurements which are independent of one another
would be suitable forms of representation. As an example, Fig. 8 shows typical common-emitter input and output
characterization for a npn bipolar transistor.
Of course, different choices of the independent variables
and of the common terminal lead to different circuit descriptions. With four scalar variable V1 , V2 , I1 , I2 and two
equations, there are six different representations to characterize a resistive two-port that are summarized in Table
1 according to independent and dependent variables. These
are current-controlled, voltage-controlled, hybrid and transition type representations that generalize the corresponding linear cases (3, 4). From a measurement accuracy point
of view, it is desirable to choose a representation which involves only smoothly varying curve.

Table 1. Equations for the six possible representations of a nonlinear resistive two-port.

V1 = Z1 (I1 , I2 )
V2 = Z2 (I1 , I2 )
V1 = H1 (I1 , V2 )
I2 = H2 (I1 , V2 )
V1 = T1 (V2 , I2 )
I1 = T2 (V2 , I2 )

I1 = Y1 (V1 , V2 )
I2 = Y2 (V1 , V2 )
I1 = H1 (V1 , I2 )
V2 = H2 (V1 , I2 )
V2 = T1 (V1 , I1 )
I2 = T1 (V1 , I1 )

Network, Nonlinear

Figure 7. Typical setup for measuring the characteristic curves of a three-terminal resistor. Each set of curves can be interpreted as the
I V curves of a two-terminal controlled resistor. In gure, terminal c is arbitrarily chosen to the common (ground) terminal

Figure 8. (a) The common-emitter conguration of a npn bipolar transistor. (b) Input Ib Vbe characteristic with Vce as a parameter and
(c) output Ic Vce characteristic with Ib as a parameter.

Figure 9. Typical characterization of a n-channel MOS transistor: (a) output characteristic Id

Vds and (b) transcaracteristic Id Vgs .

Network, Nonlinear

It is worth notice that any N-terminal (N > 3) resistor

can be considered as a three-terminal controlled resistor
by connecting a voltage (or current) source between the remaining N 3 terminal and the common reference. With
these terminal voltages (or currents) xed the resulting
device can be characterized by the above described procedure. For example, the most important four-terminal resistor commercially available is the MOS transistor which
when operates as a three-terminal device, is usually characterized by the two sets of I V characteristic curves
shown in Fig. 9. With the source terminal xed as common,
the drain current Id has been plotted against the drain and
the gate voltages Vds and Vgs respectively, considered bulk
and drain biased with a constant voltage.
Example 2
A widely used example of four-terminal resistor is the operational amplier (opamp) (see Fig. 10). This nonlinear resistor can be characterized by a nite gain model described
by the three following relationships:
I1
I2

=
=

Vo

0
0
A(V2 V1 )
{ AE
AE

if |V2 V1 | < E
if (V2 V1 ) E
if (V2 V1 ) E

(18)

where parameters A and E are called voltage gain and saturation voltage, respectively.
Thus, an operational amplier acts as a nonlinear element if the magnitude of the input differential voltage exceeds the saturation voltage E (voltage comparator, threshold detector), while it operates as a linear device in the
opposite case. In practice, operational ampliers are built
by a suitable connection of several devices such as bipolar,
MOS or FET transistors, resistors and capacitors (16).
However, as in several applications there is no need of a
detailed knowledge of the current and voltage behavior in
all branches the amplier, analog ICs manufacturers usually provide extremely simplied models for the entire circuits, called circuit macromodels (see the Subsection titled
Circuit Macromodelling).
DEVICE MODELS AND EQUIVALENT CIRCUIT MODELS
By denition, a circuit is equivalent to a given element iff
they are indistinguishable when measured from their external terminals. This is a very strong requirement that, in
most practical cases, forces to consider circuit model as approximately equivalent circuits. For this reason a model of
an electronic device should ideally reproduce the same electrical behavior of the real device when connected with an
appropriate excitation network and the results predicted
from the model should represent a good approximation of
the validating data constituted by the set of measured admissible voltage-current pairs. Depending on the applications, the acceptable error may be rather small (less than
5%) as in many analog signal processing applications or
it may be quite large if one is interested only in the device models qualitative performance. Additionally, a device
model must avoid non-physical situations when it is used

together with other models and should be able to predict

previously unknown operating modes.
Two main different approaches are usually adopted in
the derivation of device models: (1) the black-box approach
and (2) the physical approach. Black-box modelling is useful when device physics or device operating mechanisms
are not well understood, or when the device is very complex
and a physical approach would be impractical, as for VLSI
circuits with billion of components. Experimental observations, mathematical modeling, model validation and implementation by suitably connection of nonlinear elements
(nonlinear network synthesis) are the basic four steps involved in this approach. Thus, the black-box method uses
analytical expressions that have a curve tting nature,
poor forecasting abilities and correlation between parameters but requires a shorter development time than physical
modelling.
Conversely, the analytical modelling approach starts
from a study of the physics and operating mechanisms of
the device, so its accuracy depends on the validity of the hypothesis and of the approximations made in its derivation.
For this approach, physical study, introduction of suitably
simplied equations and solutions, and nonlinear network
synthesis are the typical steps. Frequently, the correspondence with internal operating mechanism is used to build
a rough circuit model that subsequently is completed with
the inclusion of essential parasitic elements. The advantages of physical-based models are the ability to foresee
new phenomena, the adoption of physical parameters and
the possibility of use the correlation between model parameter to dene realistic statistical or mismatch models
(17). On the contrary, the long developing time, the poor
re-usability and the limited accuracy associated to the approximations used in the analytical expressions are their
main drawbacks.
Once a device model is derived, the associated parameters must be identied before a meaningful computer simulation of any real circuit can be carried out. This important
task, known as model parameter identication problem,
generally involves both ad hoc measurements and computer optimization techniques which may be rather expensive in terms of computer time. In fact, most model parameters are not independent from each other so the value given
to one may inuence the value of others. Moreover, the set
of values may not be unique with respect to the same tting
to measured data because the phenomena described by certain parameters cannot be distinguished clearly from each
other in the measured characteristics (f.i. Early effect and
avalanche multiplications in bipolar and MOS transistors).
One of the most widespread parameter extraction
method consists of simplifying model equations considering a particular device bias to eliminate neglectable equation factors. This direct method nds parameters by using either graphical procedures or simple numerical techniques such as linear regression.
Global methods adopt a different approach since they
try to nd most parameters at the same time starting from
some typical values and then to use computer optimization techniques to optimize these parameters by minimizing the error between the measured and predicted results.

Network, Nonlinear

Figure 10. (a) Standard symbol of an operational amplier and (b) the simple three-segment piecewise-linear relationship between the
output voltage Vo and the differential input voltage Vd = V1 V2 (transfer characteristic). The terminal voltages are measured with respect
to the ground terminal.

The problem of model parameter extraction can be seen

as an optimization task: a nonlinear function F (D, S; P)
is minimized with respect to a set of parameters P constrained by a set of bonds C. Function F describes the tness between simulated (or computed) results S and a set
of experimental data D. This procedure leads to a set of
parameter values that minimizes differences between simulation and validation data. In general, it is very difcult
to nd generally efcient methods for identifying model
parameters, even for simpler models (37).
In the following Subsections, some analytical models for
real devices often used in circuit simulators are presented
and briey discussed.
Semiconductor Diode
The electrical topology of a two-terminal semiconductor
diode is shown in Fig. 11(a). The device can be modelled
through the connection of three one-port components: a
nonlinear resistor representing the voltage drops in the
quasi-neutral regions and on ohmic contacts, a nonlinear
capacitors representing both charge transit-time effects
and depletion charge variations with voltage, and a nonlinear resistor (diode) representing the physical effects associated with charge transport from one region to another
of the device. Thus, the constitutive equations for the diode
model can be written as

Ic =

I = Id + Ic

(19)

V = V1 + Vd = f 1 (I) + Vd

(20)

Id = Is [exp(Vd /nVt ) 1] + Ib (Vd )

(21)

dQj (Vd )
dId
dId
Vd
dVd
+
=
+ Cj (Vd )
= C(Vd )
(22)
dt
dt
dt
dt
dt

where V1 represents the voltage drop in the nonlinear series resistor, Vd is the voltage applied to the intrinsic diode,
Vt the thermal voltage, the effective transit time, Is the socalled diode saturation current, n the diode grading factor,
while Qj and Cj are the charge and depletion capacitance,
respectively. Besides, Ib (Vd ) is a term that takes into account generation current in the space-charge region and
breakdown phenomena for reverse-bias operation and is
negligible for forward bias. The presence of a grading factor
n always greater than 1 in real devices enables to model
in a simple manner for non ideal effects. Additionally, to
account for the nite physical dimensions of the junction,
the depletion capacitance Cj can be expressed in the following way as a function of both area (bottom) and perimeter

(sidewall):
Cj = Cjb

As
Psw
m + Cjsw
m
(1
Vo ) b
(1
Vs ) sw

(23)

where As and Psw are area and perimeter of the junction respectively. The two grading factors mb and msw , due to the
signicant differences between the doping shapes in the direction of the main current ux and along the borders of the
junction, differ from each other and are strongly processdependent. Finally, the experimental current-voltage characteristic shows that the V1 drop is signicant only at high
current levels; in this region, for the sake of easy modelling
Eq. (25) can be substituted by V1 = RI, where the series resistance Rs represents an average or effective value for
the ohmic effects at high voltages.
Bipolar Transistor
The basic dc model for a three-terminal bipolar semiconductor transistor (BJT) can simply be represented through
the so-called Ebers-Moll (EM) injection model (18, 19) reported in Fig. 12(a). Here the two diodes account for the direct injection of the carriers from the emitter (e) to the base
(b) and from the collector (c) to the base, respectively. Only
npn transistors will be considered here, since the same
models would apply to pnp transistor with minor modications. The two voltage-dependent current sources represent the fraction of the free carriers injected from the
emitter reaching the quasi-neutral region of the collector,
and the fraction of the free carriers injected from the collector reaching the quasi-neutral region of the emitter, respectively. With reference to a npn structure, the equations
relating currents and voltages are simply given by:
Ie = Ibe (Vbe ) + Ir (Vbc )

(24)

Ic = Ibc (Vbc ) + If (Vbe )

(25)

By exploiting the voltage-dependence associated with

device physics one gets:
Ie = Ies (exp(Vbe /ne Vt ) 1) R Ibc

(26)

Ic = Ics (exp(Vbc /nc Vt ) 1) F Ibe

(27)

where Ies and Ics are the direct and reverse saturation currents (which depend on doping and junction areas), while
ne and nc are called forward and reverse grading coefcients, and account for non ideal effects. Parameters F
and R are the forward and reverse current-gains in the
common-base conguration. Of course, in the normal forward operation mode, where the be-junction is forward bi-

10

Network, Nonlinear

Figure 11. (a) Diode lumped model and (b) experimental V I characteristic.

Figure 12. (a) Bipolar injection model and (b) transport model.

ased and the bc-junction is reversed biased, the current

owing through diode Ibc and current-generator Ir are negligible low so that device behavior can be represented only
with diode current Ibe and current source If . Similar, but
opposite, considerations can be developed for the normal
reverse mode of operation. By considering that the sum of
the emitter, base and collector currents must equal zero, a
suitable rearrangement of Eqs. (31)(32) leads to the following relationships
Ib

Ic

Ie

Is [exp(Vbe /ne Vt ) 1] Is [exp(Vbc /nc Vt ) 1]

Icc
Iec
+


+
F
R
F
R
1
Iec
Icc (1 +
)Iec
Ict
R
R
1
Icc
Icc (1 +
)Iec
Ict
F
F

(28)

where the transport saturation current Is has been dened

through the so-called reciprocity condition (Is = F Ies =
R Ics ) and the forward and reverse current gains in the
common emitter conguration
F = F /(1 F )

R = R /(1 R )

(29)

have been introduced. The equivalent circuit model corresponding to Eqs. (33), known as transport version of the
Ebers-Moll model, is shown in Fig. 12(b) and has been implemented in most circuit simulators. The main differences
between the two approaches lies in the reference currents
used: (1) the injection model is based on the diode currents
injected at the junction while (2) the transport model is
based on the currents traversing the base region. Considering the approximations inherent in the model derivation,
it turns on that the functional dependencies of model pa-

rameter in the case (2) are both more realistic from a physical point of view and simplify measurements procedures
required for parameter determination.
It clearly appears that the device is completely modelled
once the ve (constant) parameters Is , F , R , ne and nc are
known. Both the injection and transport model of Fig. 12
do not consider base-width modulation with bias and predict a constant collector (emitter) current Ic (Ie ) against bc
(be) voltage for a device biased in the normal forward (reverse) mode. On the contrary, base-with modulation has a
complex dependence on Vbe and Vbc . However, it has been
experimentally found that for forward (reverse) operation
the reduction in base-width strongly depends on Vbc (Vbe )
and is practically independent of Vbe (Vbc ) and induces an
almost linearly increase in collector (emitter) current with
respect to Vbc (or Vbe ); in particular, Eqs. (33) can still be
assumed valid by considering F and R simple function
of Vbc and Vbe , respectively. Additionally, experimental results show that, as a rst approximation, F and R can be
substituted with the following simple expressions:
F = FO (1

Vbc
);
VAF

R = RO (1

Vbe
)
VAR

(30)

where FO an RO can be interpreted as zero-bias forward

and reverse common-emitter current gains, while parameters VAF and VAR represent the forward and reverse effective Early voltages.
Turning now to capacitive effects, one can notice that in
a transistor, charge storage can be divided into two types:
(1) voltage-dependent xed charge in depletion regions and
(2) current-dependent mobile charge. With reference to Fig.

Network, Nonlinear

12 the currents owing through the two nonlinear capacitors Cbe and Cbc represent both the effect of the effective transit time of injected carriers and of the depletion
charges in the be-junction and in the bc-junction, respectively. Thus, similarly to capacitive currents in semiconductor diodes (see Eq. (27)), currents associated to charge
variations can be expressed as:
Icbe

vice (i.e. a device in which electrons are the carriers owing

from source to drain), Id can simply be expressed as:

2
[2(Vgs VT )Vds Vds
] for Vds > Vgs VT , Vgs VT
2

Id = {
(36)
for Vds > Vgs VT , Vgs VT
(Vgs VT )2
2
0
for Vgs VT


dIec
dQjbe (Vbe )
dVbe
dIec
= F
+
= F
+ Cjbe (Vbe )
dt
dt
dt
dt

(31)

dQjbc (Vbc )
dVbc
dIcc
dIcc
+
= R
+ Cjbc (Vbc )
dt
dt
dt
dt

(32)

Icbc = R

11

where F and R are the forward and reverse effective

transit-time, respectively, while Cjbe and Cjbc , each of
which has an area and a perimeter contribution (associated
with the area and perimeter of be- and bc-junctions, respectively), are called base-emitter and base-collector depletion
capacitance. It seems useful to notice that in practice for
integrated circuits in which electrically isolation from one
device to another is mandatory, most of the bipolar transistors have an additional (substrate) terminal. For standard
operating conditions, the presence of the substrate does
not alter circuit behavior; however, the substrate can inuence circuit performance or can induce circuit failures
during transients.
MOS Transistor
Unlike bipolar transistors, metal-oxide-semiconductor
(MOS) transistors (often called MOSFETs) are intrinsically four-terminal components (1, 29). The simplest dc
model for these devices can be represented as in Fig. 13
and is described by the following set of equations:
Ig = 0

(33)

Id = f m (Vgs , Vds , Vbs ) f d (Vdb )

(34)

Ib = f d (Vdb ) + f d (Vsb )

(35)

in which, as usual, the gate current Ig owing through the

dielectric gate oxide has been assumed equal to zero. Current fm (Vgs , Vds , Vbs ) represents the main carrier (minority) ow from source to drain, while the two terms fd (Vdb )
and fd (Vsb ) are associated with currents owing through
the drain-bulk (Ddb ) and source-bulk (Dbs ) junctions, respectively, which must be reversed biased for the correct
operation of the MOSFET.
Several relationships for fm (Vgs , Vds , Vbs ) have been presented in the literature, depending on the degree of approximation requested to the model and to the maximum
acceptable computer time. However, in principle, even for
prototype transistors with dimensions signically larger
than those encountered in standard CMOS VLSI technologies, analytical expressions for fm (Vgs , Vds , Vbs ) can be derived only if strong hypothesis are assumed for the behavior of some physical variables, such as electric eld, quasiFermi potentials and carrier distribution in the depletion
layer. In particular, by assuming the so-called charge-sheet
hypothesis (1), considering only the drift component of the
channel current, and a constant surface potential as far as
bulk charge distribution is concerned, for a n-channel de-

where VT is the threshold voltage, = (W/L) is the extrinsic conduction factor, W and L represent channel with and

length respectively and = Cox = ox /tox is a physical
parameter depending on effective carrier mobility , oxide
permittivity ox and gate oxide thickness tox .
The rst two Eqs. (42) express the drain current in the
above-threshold regime; in particular, the rst one refers
to the linear or triode regime, while the second one corresat
sponds to the saturation region, being Vds
= Vgs VT (saturation voltage) the Vds value corresponding to the transition point from triode to saturation. Besides, the third
relationship means a zero drain current for a device in the
sub-threshold regime. The threshold voltage VT depends
on source-substrate voltage Vsb and on device technology.
For example, for a n-channel MOSFET one can write:

VT = VT 0 + (

Vsb 2
F

2
F )

(37)

where VT0 is the zero-bias threshold voltage and and

2
F are physical-technological parameters called body coefcient and inversion potential. In particular, 2
F depends
 only on substrate doping and temperature, while
= 2si qNA tox /ox depends on both gate oxide thickness
and substrate doping concentration NA (si is the silicon
permettivity). Thus, the device behavior is completely de
ned once the four model parameters , VT0 , and 2
F
and device dimensions W and L are known. In particular,
for given values of gate-source and bulk-source voltages,
Eq. (41) predicts a constant drain current for high values
of Vds .
However, measured output characteristics show that Id
is not exactly constant, but almost linearly increasing with
Vds in the saturation region. This effects is physically due
to a reduction in the electrical channel length with Vds
(channel length modulation) when the device operates in
saturation and, similarly to what happens in bipolar devices through the F dependence on Early voltage, it could
be modelled by introducing a dependence of the extrinsic
conduction factor on drain voltage. However, to maintain
continuity in both drain current and in its derivates in the
transition point from triode to saturation, in compact MOSFET models for circuit simulation it is assumed that channel modulation holds also in the triode region, even though
this in incorrect from a physical point of view. By so doing one can get for Id the following simplied model (often
called Level 1 MOSFET model in circuit simulators):
Id =

2
[2(Vgs VT )Vds Vds
](1 + Vds ) if Vds > Vgs VT , Vgs VT
2
{ (Vgs VT )2 (1 + Vds )
if Vds < Vgs VT , Vgs VT
0
0
if Vgs VT

(38)

where is another tting model parameter, calledchannel length modulation parameter, which can be considered (apart a minus sign) as the reciprocal of the Early
voltage for MOS transistors. Often, to take into account

12

Network, Nonlinear

Figure 13. Large-signal circuit representation of the MOS transistor model.

also mobility reduction with electric eld and, thus, to better t experimental data, it is usual to render the intrinsic

conduction factor a suitable function of both Vgs and Vds
(1).
Depending on the magnitude of the time-varying voltages, the dynamic operation can be classied as large signal operation or small signal operation. If the variation in
voltages is sufciently small, the device can be modeled
with linear resistors, capacitors, current sources. Such a
model is call a small-signal model. Otherwise, the device
must represented by an analytical, nonlinear large-signal
model. Both types of dynamic operation are inuenced by
devices capacitive effects. Thus, a capacitive model describing the intrinsic and extrinsic components of the device capacitance is an essential part of a compact MOSFET model
for circuit simulation.
Turning now to capacitive effects, in a MOS transistors
one has to consider both capacitive couplings associated
with channel, substrate and gate charges in the intrinsic
device, and capacitive effects associated with the non ideal
fabrication processes. In the simple Meyer model (20), one
assumes that: (1) capacitances in a MOSFET are reciprocal, that is Cgb = Cbg , Cgd = Cdg , Cgs = Csg ; (2) the change
rate of gate charge Qg is equal to change rate of channel
charge when gate, source and drain bias changes. By so
doing, one can introduce in the model (see Fig. 14) three
interelectrodic capacitances Cgs , Cgd and Cgb (each of which
is constituted by an intrinsic (nonlinear) and an extrinsic
(linear) or overlap contribution) and two junction capacitances Cjs (Vsb ) and Cjd (Vdb ) whose voltage dependence is
the same as the second term in Eq. (27). For the intrin
sic components Cgj
( j = s, d, b) of the interelectrodic capacitances, one can refer for example to the following usual
denitions (1,19):

Cgs
=

Qg
|V ,V
Vgs gd gb


Cgd
=

Qg
|V ,V
Vgd gs gb


Cgb
=

Qg
|V ,V
Vgb gs gd

where Qg is the total gate charge. Within the same degree

of approximation used to derive
Eqs. (61), once dened the
bulk charge as Qb = Cox WL 2
F + Vbs , for a device in the
linear regime one has the following expression for QG :

so we have:
Cgs

Cgd

Cgb

2
(Vgd VT )2
WLCox [1
]
3
(Vgs VT + Vgd VT )2
2
2
(Vgs VT )
WLCox [1
]
3
(Vgs VT + Vgd VT )2
0

It is to be expected that Cgb is zero in strong inversion

since the inversion layer in the channel from the drain to
the source shields the gate from the bulk and prevents any
response of the gate charge to a change in the substrate
bias.
For a device in saturation (Vds > Vdssat ) the gate charge
results:
2
Qg = WLCox (Vgs VT ) Qb
3
and it is easy to obtain
Cgs =

2
WLCox
3

Cgd = Cgb = 0

Circuit Macromodelling: Operational Ampliers

In principle, detailed electrical performances of complex integrated circuit or systems can be correctly predicted only if
each device (whatever desired or parasitic) is represented
by a proper device model. However, different degrees of
approximation are required for the analysis and design
of analog and digital ICs. The electrical performances to
be simulated for the latter are usually logic levels, noise
margins and delay time, while for the former one must
correctly predict frequency response, phase margin, distortion, noise . . . , and to do this it is extremely important
to simulate several device details. In particular, designers
of analog integrated circuits (whatever bipolar, CMOS and
mixed bipolar-CMOS or BiCMOS (21)) must be very condent with device and circuit behavior and able to model
with great accuracy the nuances in device and circuit performance and variations of these nuances with parameter
variations. Conversely, quite different is the approach to
circuit simulation of analog designers of circuits and systems which implement projects by simply interconnecting
existing ICs and/or components or by interconnecting predesigned integrated building blocks (called macro-cells).
The goal to reach with circuit simulation in these applications is a cheap and very fast prediction of circuit perfor-

Network, Nonlinear

13

Figure 14. MOS transistor model complete with interelectrodic (Cgs , Cgd , Cgb ) and junction (Cjs (Vsb ), Cjd (Vdb )) capacitances.

mance (f.i. the cut-off frequency of a lter), without the need

of a detailed knowledge of the current and voltage behavior in all branches and nodes. Therefore, most of analog ICs
factories render available to the users extremely simplied
models for the entire circuits, called circuit macromodels,
which neither model exactly device performance under all
conditions nor fully replace bread-boarding for nal verication. In fact, the aim of macromodelling is to obtain
a circuit model of an IC, or a portion of an IC, which has
a signicantly reduced complexity to provide for smaller,
less costly simulation time, or to allow the simulation of
larger ICs or IC systems for the same time and cost. Thus,
by using these macromodels one can obtain, within a given
degree of approximation, the main pin-to-pin or pad-to-pad
circuit performance.
Macromodels pose particularly difcult problems during circuit simulations. In particular: (1) if not all macromodels equations are continuous, one can generate extremely large internal currents or voltages so that convergence problems arise, and (2) if some negative component
values are used the solution can grow causing the simulator to fail if the time constant of the unstable mode is small
compared to the transient analysis interval. Of course, as
a priori not all circuit performance are considered, most of
the elements in the macromodel are linear while the very
few key nonlinear devices still present are usually modelled with basic device models discussed in Section Device
and equivalent circuit models.
Operation ampliers are common circuits that are suitably described by macromodels in order to simulate their
non ideal characteristics. Advantages of this approach is
evident considering that a typical IC opamp consists of
about twenty transistors which, once simulated even by
the simple Ebers-Moll model, would lead to over 160 components and 40 pn junctions.
Unlike the ideal opamp previously described, a real
opamp is characterized by some particular features such
as (1) nite input and output resistance (Ri = , Ro = 0),
(2) frequency-dependent open-loop voltage gain and phase
shift, (3) output voltage limiting behavior and (4) nite limited slew-rate Sr dening the maximum time rate of change
of the output voltage that can be attained under the worst
case feedback conguration (usually unity-gain voltage follower).
Two most widely basic macromodeling techniques used
are (1) simplication and (2) build-up (22). The former technique simplies representative portions of the system circuitry by using simple ideal elements to replace numerous

real elements. By so doing, the nal model bears a strong

resemblance to the real circuit. The latter technique implements circuit specications by using composition of ideal
elements, with no regard to resemble a portion of the actual
circuit.
As an example, Figs. 15 and 16 show a full-transistor
schematic and the macromodel circuit for a generalpurpose typical FET-bipolar opamp (23). As can be seen,
the macromodel (developed using both the aforementioned
methodologies) represents the real opamp as a suitable
connection of three stages: the input stage, the intermediate stage and the output buffer.
The input stage is an example of the simplication technique and in this case models the nonlinear input transfer
characteristic and the input offset voltage. It includes a
JFET input differential stage loaded with non ideal current sources which model the two active loads of the real
circuit, while the current bias source of the stage is represented by the pair 2I0 , RS. The voltage-dependent current source Gk draws a suitable current from the common
source of the differential couple J1-J2 to give rise to an effect similar to that due to collector current of transistor Q12
that depends on the common mode voltage of the intermediate stage. The intermediate stage provides for open-loop
gain, gain-bandwidth product, poles and zero frequency response and, together with the rst stage, slew-rate. In particular, its single-ended part has been represented with a
voltage dependent current source.
Finally, the output stage is modelled using the build-up
technique and is devoted to the modelling of power dissipation, output impedance and maximum output voltage
swing. The gain and the output resistance of such a stage
have been modelled through GFOLL, Rout while diodes and
the voltage sources VDCC and VDEE enable to achieve saturation values of the output voltage very close to those measured in the real opamp. Performance examples for this
macromodel are summarized in Figs. 17 and 18.
Figure 17 refers to the common mode gain behavior
showing comparison between full-circuit simulation and
the simplication/build-up technique macromodel. Following Fig. 18 shows comparison between experimental and
simulated slew performance of the opamp connected in the
voltage-follower conguration. Of course, the macromodel
proves itself useful to reduce computing time and essential
to describe and control the main opamp behaviours.
Finally, let us notice that when non-frequently asked
features of the opamp must be macromodelled, one has to
refer to specically devoted topologies (2227).

14

Network, Nonlinear

Figure 15. Schematic diagram of the LF355 operational amplier.

Figure 16. Macromodel circuit diagram for the LF355 operational amplier in Fig. 15.

ADVANCED MODELS
Modern IC design is based on circuit simulation, the effectiveness of which depends on the accuracy and completeness of the compact models and characterization of the circuit elements and parasitics that comprise the IC.
In modern microelectronics VLSI technologies the channel length of MOSFETs and the base width of BJTs have
very reduced physical dimensions; thus analytical models
for these devices must be able to describe, at least in an
approximate manner, several second-order physical phenomena associated with two- or three-dimensional effects.
Compact model should be formulated physically, as functions of both the fundamental process parameters that con-

trol device electrical behaviour and the geometric layout

parameter associated with a device.
The nonlinear equation solved in SPICE-like simulators generally require compact models to be formulated as
equivalent networks. As already stated, this can be done by
making voltage-controlled current and charge expressions
more complex and by introducing in the models several additional pseudo-physical parameters and additional components. Although these empirical parameters, as much as
possible a model and its parameters should be linked to
the small number of physical parameters (junction depths,
sheet resistance,doping levels) that control device electrical behaviour.

Network, Nonlinear

15

Figure 17. Common mode gain behaviour for the LF355 operational amplier; comparison between full-circuit simulation (continuous
line) and macromodel (dashed line).

Figure 18. Experimental (line) and simulated (dots) slew performance of the LF355 operational amplier connected in the voltage follower
conguration for a 5V/5V input voltage step.

Advanced Bipolar Models

The rst advanced model presented for the bipolar transistor was the very popular Gummel-Poon model (GP), which
is implemented in practically all circuit simulators (19, 28).
Starting from an original interpretation of the current ux
in the transistor, based on the concept of an effective basecharge, the GP model was naturally able to describe several important physical effects. The model has the same
topology of the transport Ebers-Moll shown in Fig. 12(b),
so model equations are formally equal to Eqs. (33) with
a suitable new denition of the saturation current. By so
doing, current expressions are given by
Ict
Ib

Iss
Vbe
Vbc
[exp(
) exp(
)]
qb
Vt
Vt
Icc Iec
Vbe
=
+
+C2 Iss [exp(
) 1]
F R
ne Vt
Vbc
) 1]
+C4 Iss [exp(
nc Vt
=

(39)

where the normalized base charge qb can be expressed as:

q
qb = +
2

q1 2
) + q2
2

(40)

and where
q1 = 1 +

Vbe
Vbc
+
VAR
VAF

(41)

accounts for the Early effects associated with bias of both

junctions, while
q2 = B

Iss [exp(Vbe /Vt ) 1] Iss [exp(Vbc /Vt ) 1]

+
Ikf
Ikr

(42)

models, through parameters Ikf and Ikr , high-level charge

injection in both collector and emitter. The parameter B
accounts for a larger transit time at high current density
due to the increase of neutral base region (kirk effect) (29,
30). Base current expression is completed with two non
ideal additional components which model, through parameters C1 , C2 , ne and nc , recombination in the space-charge
regions (see Fig. 20), and series resistances between the internal nodes and the terminals account for the differences
between internal and applied voltages, obtaining a signicant improvement with respect to the previous EM model.
Recently, further improvements and modications to
the basic GP model have been introduced in some very advanced compact models for the BJT (3135) implemented
in public or proprietary circuit simulators. These new approaches model also the presence of the substrate terminal,
series resistances associated to the nite conductance of
the semiconductor layers, voltage-dependence of the buried
layer conductance, avalanche breakdown, advanced modelling of base push-out and temperature dependence. Additionally, by adopting a different physical approach, new
expressions for the base charge qb have been developed.

16

Network, Nonlinear

Figure 19. Circuit representation of the Gummel Poon model for a vertical npn bipolar transistor.

Figure 20. Plot of Ic and Ib versus Vbe for Vbc = 0 showing the denitions of main parameters introduced with the Gummel Poon model.

For example, in Mextram model (34) one has

qb = q1 (1 + q2 )

q1 = 1 +

QTE + QTC
QB0

q2 = 1 +

QBE + QBC
QB0

where QTE , QTC , represent the depletion charges, QBE , QBC

represent the diffusion charges directly obtained solving
the differential equation for the majority carriers in the
neutral base and QB0 in the integral of the base charge. Unlike the Gummel Poon relation (40) that models the Early
effect by using constant VAF and VAR parameters, this approach involves bias-dependent depletion charges which
increase description of the Early voltage. Moreover, the
model makes use of both constant (RE , RCC , RBC ) and variable (Rb2 , Repi ) series resistance. The variable part of the
base resistance is modulated by the base charges taking
into account the base current crowding, while the epilayer
resistance describes both current spreading in the epilayer
and the decrease in resistance due to carrier injected from

the base when internal base-collector junction is forward

biased. Additionally, as at high frequencies and for steep
transients the quasi-static hypothesis does not still apply,
an excess phase shift, obtained by a suitable partitioning of
the stored base charge and by introducing additional delay
times, was implemented. This leads to both complex equivalent circuit models and current-voltage relationships: f.i.
MEXTRAM equivalent circuit model shown in Fig. 21 have
about 40 effective model parameters.
Another recent advanced model for high-speed/highfrequency bipolar applications is the HIgh CUrrent Model
(HiCUM (35)). This model addressed some major disadvantages of the GP such as the poor descriptions of base resistance and junction capacitances in the regions of interest
and inadequate description of both Si- and III-V materialbased HBTs.
Among the major features of HiCUM we can mention
the accurate description of the high-current operating re-

Network, Nonlinear

17

Figure 21. Mextram equivalent circuit for a vertical npn transistor. Current generator Iavl models avalanche multiplication current due
to the high eld in the space-charge region.

gion (including quasi-saturation and saturation), the distributed modelling of external base-collector region, self
heating effects and sufciently physical model equations
allowing predictions of temperature and process variations, as well as scalability, even at high current densities.
Advanced MOSFET Models
The rst attempt to ameliorate current-voltage behavior in
MOSFET model was given by the so-called Level 2 model.
This model copes with several short-channel effects such
as the velocity saturation or the variation of the depletion
charge along the length of the channel. This results in a
more accurate but complex expression for the drain current
Id , leading to many convergence problems. For example, for
a device in the triode region one has (20, 29)
Id =

Weff Cox
{(Vgs (VFB + 2F ))Vds
Leff

2
2
Vds
f s [(Vds + 2F Vbs )3/2 (2F Vbs )3/2 ]
2
3

f n[

2
Vds
+ (2F Vbs )Vds ]}
2

(43)

where fs and fn are two suitable parameters associated

with two different phenomena: the decrease in the total
depletion charge due to depletion region around source
and drain (important in short-channel devices) and the
increase in the depletion charge due to the spreading of
the gate-induced depletion outside the channel edges and
under the isolation (important in narrow-channel transistors). Additionally, to take into account carrier velocity
against electrical eld behavior and to have continuity in
the drain current expression in the transition point from
triode to saturation regime, a complex expression for the
sat
saturation voltage Vds
is adopted as well. A simplied version of Level 2 model based on semi-empirical considerations led to Level 3, a robust and popular model particularly suited for digital circuit design, but not very scalable

and with discontinuities in the rst derivative of the drain

current (20).
The basic model formulation introduced in Subsection
MOS Transistor revealed useful for devices with dimensions not lower than 5 m. However, low-voltage highspeed VLSI CMOS circuits and systems require the availability of devices with very small geometry, so that advanced MOSFET models including several two- and threedimensional effects are demanded from circuit designers.
From a topological point of view, compact models implemented in circuit simulators for these applications have
the same topology of the basic circuit in Fig. 13, but with a
quite different expression for the fm (Vgs , Vds , Vbs ) currentvoltage relationship.
It is easy to understand that advanced models have become heavily empirical, with extensive mathematical conditioning. The number of model parameters has become
very large, and most of these are basically empirical in
character. Today, a general-purpose state of-the-art compact model consists of more than 300 equations and about
200 parameters containing both physical information such
as oxide thickness or doping level and simplied descriptions of the physical effects such as mobility models. Often,
the focus is mainly on the circuit simulation use of the device model, rather than on a physical description of the
MOSFET and, therefore, mathematical tness overrides
physical understanding in the description of the device.
Compact models should be C -continuous to enhance
modeling accuracy and numerical performance, by avoiding problem, such as square roots or logarithms of negative
numbers, exponential overows. As a matter of fact, nonsmooth models cause problems for dc convergence and parameter extraction and limit the order of integration that
can be used for transient analysis.
In order to have continuity in the rst derivatives of
current equations with respect to voltages for the whole
range of gate and drain biases, an extensive use of polynomial equations and other mathematical functions has
been sometimes made, while in the more robust circuit

18

Network, Nonlinear

simulators and models smoothing functions have been implemented. The use of smoothing functions is particularly
useful as it serves two interrelated purposes: (1) it eliminates the need to change equations at particular points
sat
(e.g. the Vds voltage crosses the saturation voltage Vds
),
which allows for the use of a single equation for all regions
of device operation (e.g. one unique expression for Id rather
than separate equations for weak-inversion, triode and saturation regions), and (2) it allows smooth and continuous
derivatives to also be guaranteed, a very useful property
in the development of the expressions for the device conductances and transconductances.
With the growth of both the number and empirical character of model parameters, increasing emphasis must be
placed on parameter extraction; for examples, in the BSIM
model (20) each parameter is made dependent on both effective channel length Leff and width Weff as
X = X0 +

XL
XW
+
Leff
Weff

(44)

through suitable tting parameters X0 , XL and XW .

To model sub-threshold operation, in weak-inversion
and moderate inversion Eq. (42) is substituted by a suitable exponential relation (similar to the one found in bipolar transistor) of the type:
(Vgs VT )
Vds
Id = I0 exp[
](1 exp[
])
nVt
VT

j = g, s, d, b

Moreover, the capacitances in a MOSFET cannot be arbitrary functions and the charge neutrality relationship
Qg + Qs + Qd + Qb = 0

Ij =

dQj
=
dt


i {g, s, d, b}
i = j

(45)

must be assured. Different capacitance models have been

developed to solve the charge non-conservation problem.
In order to ensure charge conservation, it can be shown
that the reciprocity of the Meyer model requires Qs to be
independent of Vds and Vbs and Qd to be independent of Vgs
and Vbs .

dQj dVji
dVji dt

j = g, s, d, b;

(46)

By dening the following capacitances

dQi
,
dVj
{
dQi
,
Cij =
dVj
Cij =

i = j, i, j = g, s, d, b;
(47)
i = j.

and substituting Eq. (61) into Eq. (60) we can derive


i = j

where I0 and n are tting parameters. In particular, the

slope factor n can be made a suitable linear function of
both Vbs and Vds , and ad hoc tting expressions can be introduced to link the weak inversion current expression to
the strong inversion expression. Of course, as most of the
dependence are constructed on a semi-empirical basis, parameters provide little physical information, for example
regarding the process technology.
Additionally, advanced models adopt a more robust and
accurate charge approach to satisfy charge conservation
and for a better efciency in circuit simulations. The Meyer
model described in Section MOS Transistor is simple and
sufciently accurate for many circuit applications but it
has been found to yield non-physical results when used to
simulate circuits that have charge storage nodes (such as
MOS charge pumps, static RAM, switched-capacitor circuits, silicon-on-sapphire circuits) since charge built-up
on these nodes is incorrectly predicted by the simulation
(charge non-conservation problem). With the quasi-static
assumption, all charges at each time t only depend on the
values of terminal voltages at the same time, so we have
Qj = Qj (Vgs , Vgd , Vgb ),

Another approach is the charge-based model in which

the emphasis is put on the charge rather than the capacitance, from derivation through model implementation. The
approach is to determine the charges in the drain, gate,
source and bulk of a MOSFET and use them as state variables in the circuit simulation. Both the transient currents
and the capacitances are obtained through mathematical
differentiation of the charge with respect to time or voltage,
respectively.
The charge-based capacitance model automatically ensures the charge conservation, as long as Eq. (59) is satised. The capacitive currents can be rewritten as

Cij =

Cji

(48)

i = j

so only 9 of the 16 capacitances are independent according

to Eq. (62). The charge-based capacitance model needs the
charge equations for all four terminals: Qg and Qb can be
obtained directly by integrating the corresponding charge
density over the channel. However it is difcult to model
the charges on the source and drain terminals because only
the total mobile channel charge Qi = Qs + Qd is known and
a partition is needed. At Vds = 0 the partition should be Qs
= Qd = Qi /2 due to symmetry, but several charge partition
approaches have been suggested for the saturation region
(50/50, 40/60, 0/100) that can be selected with a model parameter called. As an example, when >0.5, the 0/100 charge
partition is chosen so Qs = Qi and Qd = 0 is assumed in the
saturation region. Differently, = 0.5 and <0.5 assumes the
50/50 and 40/60 charge partition respectively. The latter
choice is physically correct under the quasi-static condition as proven by 2D device simulation and experiments.
Among the tens of models proposed in the literature
those which have reached a more assessed formulations
and which are usually implemented in circuit simulators
to analyze modern CMOS VLSI circuits are the BSIM3/4,
MM9/11 and EKV models (20, 36). Their basic structure is
similar to that of the previously described models but they
make extensive use of smoothing functions to guarantee
continuous and smooth expressions also for the charges.
Moreover, in these last generation models one can also nd
dependencies that have been ignored in the past. Among
these are threshold-voltage dependence on substrate and
drain voltages, modelling of the breakdown for source-bulk
and drain bulk-junctions, a sophisticated formulation for
carrier mobility dependence on electric eld components,
advanced modelling for channel length modulation, gateoxide leakage current due to traps in oxide, and tunneling
current through oxide due to quantum-mechanical effect,

Network, Nonlinear

and non-quasistatic effects.

With the help of smoothing functions BSIM3 adopts a
single-equation to describe device characteristics in various operating region (38). This eliminates the discontinuity
in the IV and CV characteristics.
Id =

W
(1 + )VDS,eff

VGST,eff [1
n Cox
]VDS,eff
L
2VGST,eff + 4kT/q

(49)

where VGST,eff is a suitable smoothing function given by

2nkT/q ln[1+exp(Vgs VT
2nkT/q
1+2n exp(Vgs VT 2Voff
,
2nkT/q)

VGST,eff =

)]

(50)

that gradually changes the overdrive voltage Vgs VT between two extreme values: when Vgs > VT then VGST,eff
Vgs VT and when Vgs < VT then VGST,eff kT/q exp[q(Vgs
VT Voff )/nkT]. Similarly,
VDS,eff = VDS,sat


+

1
(VDS,sat Vds 
2

(VDS,sat Vds )2 + 4VDS,sat )

(51)

where the exact value of the parameter  determines

the degree of smoothness in the transition between triode
and saturation region. BSIM4 offers several improvements
over BSIM3 in the transistors noise modeling and in the
incorporation of extrinsic parasitics (38).
MOS Model 9 employs simple smoothing functions similar to (65) to achieve continuity in device characteristics.
It is accurate for sub-quarter micron technologies and exhibits good behaviours in circuit simulation. Recently, MOS
Model 11 has been developed as the successor of Model 9.
This new physics based model is particular suitable for digital, analog and RF CMOS technologies, and allows for a
simple parameter extraction procedure, and it represent
one of the rst surface-potential based models (32).
While all other cited models employs source-referencing,
the EKV (36) is the rst one that uses the bulk-referencing
method, so source and drain can be treated symmetrically,
a particularly useful feature in analog circuits where the
MOSFET is used bidirectionally. By developing a pichVp = Vg VT
off voltage
which applies independently to the
n
source and drain terminals, the weak-to-strong inversion
transition and the linear-to-saturation transition (which
are treated separately in other models) are both describes
by the same weak-to-strong inversion model.
This fundamental philosophical change allows the
EKV model a greater hope of fundamentally eliminating the asymmetry problems unavoidable in the sourcereferencing models. The normalized current in weak and
in strong inversion can be expressed as
id

ID
= i f ir = F (v p vs ) F (v p vd )
IS

where if IF /IS is the forward normalized current which

is also dened as the inversion coefcient and ir IR /IS is
the reverse normalized current. The function F(v) = [ln (1 +
ev /2 )]2 is an interpolation function, which guarantees that
the current equations and their derivatives are continuous
and smooth.

19

The rapidly decreasing minimum channel-lengths in

CMOS process leads to a drastic improvement of the high
frequency performance that, combined with low-noise gures and low power consumption, make CMOS more suited
for RF and high frequency applications, for which a good
accuracy modelling of impedance, transconductance, circuit and voltage gain must be included in the model. As
the device dimensions approach their fundamental limits, new physical phenomena become essential for the accurate reproduction of the device characteristics. Today,
the threshold voltage-based MOSFET compact models (VT based model) are considered standard but they proved to be
inadequate for modeling future RF, mixed signal and lowvoltage circuits. Some of the fundamental structural aws
of VT -based models include the use of source-referenced
threshold voltage producing a singularity in the IV characteristic, nonphysical description of the moderate inversion region leading to erroneous results for the Gm /Id ratio, (an important gure of merit for analog designers)
and inconsistent modeling of charges and currents producing negative transcapacitances. For these reasons, there
is the need to replace VT -based models with either inversion charge (Qi ) based or surface potential-based models
(s -based model).
Recent advances in this direction have brought both
qualitative and quantitative improvement in the ability
to simulate modern CMOS circuits. Moreover, surfacepotential-based model includes both threshold-based and
Qi -based methods as special cases that follow from the general approach under additional assumption. For all these
regions, s -based formulation seems to be the only viable
foundation for the next generation of MOSFET compact
models.

BIBLIOGRAPHY
1. Y. P. Tsividis, The MOS Transistor, New York: McGraw-Hill,
1988.
2. R. Beaufoy, J. J. Sparkes The Junction Transistor as a Charge
Controlled Device ATE Journal, 13: 310327,October 1957.
3. L. O. Chua, C. A. Desoer and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.
4. C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York:
McGraw-Hill, 1969.
5. L. O. Chua, Nonlinear Circuits IEEE Trans. Circuits Syst.
CAS-31, 1984.
6. L. D. Landau, E. M. Lifshitz Statistical Physics Oxford: Pergamon, 1969.
7. L. O. Chua, K. A. Stromsmoe Lumped circuit models for nonlinear inductors exhibiting hysteresis loops IEEE Trans. on
Circuit Theory 17: 564574,Nov 1970.
8. J. Millman, A. Grabel, Microelectronics, New York: McGrawHill, 1987.
9. D. A. Hodges, H. G. Jackson, R. A. Saleh Analysis and Design
of Digital Integrated Circuits in Deep Submicron Technology,
New York: McGraw-Hill, 2004.
10. K. Mitsubori and T. Saito, A four-dimensional plus hysteresis chaotic generator, IEEE Trans. Circuits Syst. I, Fundam.
Theory Appl. 41: 782789, 1994.

20

Network, Nonlinear

11. M. P. Kennedy, L. O. Chua Hysteresis in Electronic Circuits:

a circuit theorists perspective, Int. Journal of Circuit Theory
and Application, 19: 471515, 1991.
12. M. Hasler and J. Neirynck, Nonlinear Circuits, Norwood:
Arthech House, 1986.
13. L. O. Chua S. M. Kang Memristive Devices and Systems Proc.
IEEEvol64pp. 209223Feb. 1976.
14. L. O. Chua Introduction to Nonlinear Network Theory New
York: McGraw-Hill, 1969.
15. S. Sze, K. K. Ng Physics of Semiconductor Devices 3rd ed., New
York: John Wiley & Sons, 2006.
16. K. R. Laker and W. M. C. Sansen, Design of Analog Integrated
Circuits and Systems, New York: McGraw-Hill, 1996.
17. S. W. Director, P. Feldmann, and K. Krishna, Statistical integrated circuit design IEEE J. Solid-State Circuits 28: 193202,
1993.
18. J. J. Ebers, J. L. Moll Large-Signal Behavior of Junction Transistors, Proc. IRE, 42: 1761, 1954.
19. I. E. Getreu, Modeling the Bipolar Transistor, Amsterdam: Elsevier, 1976.
20. D. Foty MOSFET Modeling with SPICE New York: Prentice
Hall, 1997.
21. P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Mayer Analysis and
design of Analog Integrated Circuits, New York: John Wiley &
Sons, 2001.
22. R. G. Meyer (ed.) Integrated-Circuit Operational Ampliers
IEEE Press, 1978.
23. G. R. Boyle, B. M. Cohn, D. O. Peterson, Macromodeling of
Integrated Circuit Operational Amplier, IEEE J. Solid-State
Circuits, SC-9: 353363, 1974.
24. D. Golzio, S. Graf, Zs. M. V. Kovacs,
G. Masetti, Circuit Macromodels and Large-Signal Behaviour of FET-Input Operational
Ampliers Int. Journal of Circuit Theory and applications, 20:
7585 1992.
25. C. Hu, D. P. Leach, S.-P. Chan, An Improved Macromodel for
Operational Ampliers Int. Journal of Circuit Theory and applications, 18: 189203, 1990.
26. D. Golzio, S. Graf, G. Masetti, New Macromodel and Measurements for the Analysis of EMI effects in 741 opamp Circuits
IEEE Trans. Electromagn. Compat., 33: 2534 1991.
27. G. Masetti et al., Failures induced on analog integrated circuits from conveyed electromagnetic interferences: A review,
Microelectron. Rel., vol.38,p. 995, 1996.

28. H. K. Gummel, H. C. Poon, An Integral Charge Control Model

of Bipolar Transistors Bell Syst. Techn. J, 49: 827851, 1970.
29. P. Antognetti, G. Massobrio Semiconductor device Modeling
with SPICE, New York: McGraw-Hill, 1988.
30. R. S. Muller and T. I. Kamins, Device Electronics for Integrated
Circuits, New York: John Wiley & Sons, 1986.
31. H. C. de Graaff and F. M. Klaassen, Compact Transistor Modelling for Circuit Design, Wien: Springer-Verlag, 1990.
32. R. van Langevelde, A. J. Scholten, D. B. Klaassen, MOS11
Compact MOSFET Model Summary.
33. C. McAndrew, J. A. Seitchik, D. F. Bowers, M. Dunn, M. Foisy,
I. Getreu, M. McSwain, S. Moinian, J. Parker, D. J. Roulston,
M. Schroter, P. van Wijnen, L. F. Wagner, VBIC95, The Vertical
Bipolar Inter-Company Model IEEE J. Solid State Circuit 31:
14761483, 1996.
34. H. Stubing,

H-M. Rein A Compact Physical Large-Signal

Model for High-Speed Bipolar Transistors at High Current
Densities Part I and II IEEE Trans Elect Dev ED 34, 1987.
35. A. Koldehoff, M. Schroter, and H.-M. Rein, A compact bipolar transistor model for very high-frequency applications with
special regard to narrow stripes and high current densities,
Solid-State Electron., Vol.36,pp. 10351048, 1993.
36. C. Enz, F. Krummenacher, E. Vittoz An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to
Low Voltage and Low Current Applications, Analog Int. Circ.
and Signal Proc. 8: 83114, 1995.
37. F. Franz`e, N. Speciale A Tabu Search Based Algorithm for Continuous Multiminima Problems, International Journal for Numerical Methods in Engineering 50: 665680, 2001.
38. W. Liu MOSFET models for SPICE Simulation including
BSIM3v3 and BSIM4, John Wiley & Sons, Inc. 2001.
39. C. Galup-Montoro, M. C. Schneider MOSFET Modeling for
Circuit Analysis and Design, World Scientic Publishing Co.,
2007.

GUIDO MASETTI
NICOLO` SPECIALE
D.E.I.S.-Universita` di
Bologna-Viale, Risorgimento
2, 40136, Bologna, Italy

154

NETWORK EQUATIONS
YSIS.

NETWORK EQUATIONS
In an electrical network or an electrical circuit, the operation
of every single element is determined at each moment by the
interaction between the element itself and the rest of the network. In other words, we can say it results from the action
due to different requirements: (1) that the element behaves
in a manner compatible with its specific nature; and (2) that
such behavior is in turn compatible with the behavior of all
other elements present in the network. The constitutive relations describe the operation of the single elements and Kirchhoff s laws regulate the interaction. The equations that derive
from them are the network equations and are the subject of
this article.
Within the limits of the circuit model approximation, the
operating conditions of the single elements are identified by
the voltages and currents at their terminals; these are the
unknowns of the circuit equations. They are linked by the
constitutive relations, which are expressions of the nature of
the elements and, as a whole, describe their operations. The
constitutive relations do not depend on the way in which the
elements are connected to one another. For the sake of simplicity, we will refer here to a network of one-ports only, that
is, elements with two terminals. Its extension to the case
where there are also n-terminal elements does not involve
any conceptual difficulty and will be considered later.
Voltages and currents are algebraic variables, and so it is
necessary to choose a reference direction in advance for every
single one-port. In this context the concepts of voltage and
current are introduced axiomatically; thus, it may be difficult
to understand fully the need for the choice of a reference direction for them. However, if one remembers that the current
is nothing but the intensity of the electric charge flow crossing
the one-port, one readily understands why it is necessary to
indicate the reference direction in advance in order to assess
the intensity of the flow charge indicated by the symbol i(t).
Similarly, for the voltage it is sufficient to recall that it is the
work done by the electric field to bring a unit charge from one
terminal to another. Therefore, it is necessary here to indicate
also the starting and ending terminals in advance to evaluate
the work indicated by the symbol v(t). These concepts, which
are the basis of the circuit theory, would merit a more profound discussion. However, due to space limitations we cannot develop them in this article. We therefore refer the reader
to LINEAR NETWORK ELEMENTS and TIME-DOMAIN NETWORK ANAL-

There the problems implicit in the previous simple definitions, and their connections with the general theory of the
electromagnetic fields, are dealt with in greater depth.
Returning to the circuit model, if we represent the one-port
as a closed box with two terminals, as shown in Fig. 1a, we
can indicate the chosen reference directions with an arrow
placed on one of the two terminals for the current and with
the signs and placed near the terminals for the voltage.
Suppose that a current reference direction is chosen from the
two available. Then the voltage reference direction can be
chosen with either the sign or the sign at the terminal
where the current arrow enters the element. The former
choice is called the normal convention, which we will always
adopt here. In the general case, one thinks, for example, of
the pn junction diode; the four possible alternatives give rise
to different expressions of the constitutive equations.
One-ports can be classified as dynamic and nondynamic.
For nondynamic one-ports, which we will call resistive oneports, the relations between the voltage and the current are
of the algebraic type, that is, the value assumed by the voltage at any time depends only on the value of the current at
that time and vice versa. Resistors, diodes, voltage and current sources are examples of resistive one-ports. By contrast,
the operations of dynamic one-ports are described by means
of differential or integral-type equations. Thus the value of
the voltage or of the current at any time depends also on their
past histories. Capacitors and inductors are examples of dynamic one-ports. For now and for the sake of simplicity, we
will refer only to resistive one-ports.
The voltage and the current of a resistive one-port, therefore, identify its operating point. This expression derives from
the fact that, as the one-port constitutive relation is of an
algebraic type, f(v, i) 0, and thus is graphically representable in the plane (v, i), a given voltage and a given current
identify a point on the characteristic curve f(v, i) 0. If one
considers, for example, the linear resistor, the characteristic
v Ri is representable in the plane (v, i) by a straight line
passing through the origin. The points on this straight line
represent the possible operating conditions that the one-port
in question can allow. What the effective operating point of
the one-port is at a given time is determined by the operating
conditions of the remaining part of the network into which it
is inserted. The laws governing this interaction are the two
Kirchhoff laws, which we will briefly recall after the introduction of some simple definitions.
Let us call node the connecting point of at least two terminals of distinct elements. Between two nodes effectively connected to one-ports we will say that the network has
branchesone branch for each one-port. The set of branches

i
+

v1

+
i1

i3

v
Figure 1. Graphic representation for (a)
two-terminal elements; (b) three-terminal
elements or three-poles; (c) four-terminal
elements operating as two-ports. The normal convention is used.

i2
+

(a)

+
v1

i1

i2

i1

i2

v2
(b)

(c)

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

+
v2

NETWORK EQUATIONS

and nodes of the network constitute the graph of the circuit.

Finally, we will call loop any closed path starting from any
node, traversing different branches and nodes of the network
itself and ending at the same node, where precisely two
branches are incident with each node. The graph of the network and its topologic properties are considered in TIME-DOMAIN NETWORK ANALYSIS. With this premise one can state
Kirchhoff s two laws.
Kirchhoff s Current Law (node law). The algebraic sum of
all the currents at any node is equal to zero.
Kirchhoff s Voltage Law (loop law). The algebraic sum of
all the voltages along any loop is equal to zero.
In this context, and because of the way in which they have
been introduced, Kirchhoff s laws appear as postulates or experimental laws. In effect they can be derived, in a more general model of the electromagnetic field, from Maxwells equations and are strictly exact in the stationary regime, that is,
when voltages and currents do not vary with time. However,
they are only approximate, but generally closely so, in a dynamic regime (see LINEAR NETWORK ELEMENTS).
The equations obtained by applying Kirchhoff s laws do
not depend on the nature of the single elements, but only on
the way in which they are connected. For greater clarity, let
us assume that the network consists of b branches and n
nodes. Kirchhoff s current law allows us to write n equations
for the currents, while Kirchhoff s voltage law allows us to
write an imprecise number m of equations for the voltages,
where m is in fact the number of possible loops present in the
network. To analyze a circuit it is not necessary to consider
all these equations. In reality, it is easy to show (see TIMEDOMAIN NETWORK ANALYSIS) that only (n 1) equations for the
nodes and [b (n 1)] equations for the loops are in effect
independent of each other. Every other additional equation
would result in a linear combination of them and would not
provide any additional information. Thus Kirchhoff s laws
allow independent b equations to be written in the 2b unknowns i1, i2, . . ., ib and v1, v2, . . ., vb.
It is important to emphasize that Kirchhoff s equations are
linear, algebraic and homogeneous; hence the interaction that
they describe is linear and instantaneous, and time derivatives and integrals do not appear in them. Every dependence
on the past history of the circuit, every nonlinearity, as every
source term, can only derive from the constitutive relations
of the network elements. This is a point of extreme importance that is at the origin of many important properties of the
circuit equations.
If we now join the b equations that express the constitutive
relations and the independent b equations derived by
applying Kirchhoff s laws, we obtain 2b equations in 2b unknowns. Naturally, such a system of equations will still be
algebraic and linear only if the equations introduced from the
constitutive relations are such. If this is so, the solution of the
circuit equations does not present any particular problems,
provided we ignore those deriving from the dimension of the
resulting system of linear algebraic equations and thus from
the number of branches of the network. Ultimately, it is only
necessary to invert the coefficient matrix of the equation system that, because of the way in which it has formed, is certainly not singular in significant cases.

155

Naturally, it is not generally convenient to deal directly

with the system of 2b equations in 2b unknowns. An immediate reduction of the equation system can be obtained by eliminating the currents or the voltages from the Kirchhoff b equations, making use of the constitutive relations. In this way,
one obtains a system of b equations in b unknownsvoltages
or currents.
A more significant reduction can be obtained by exploiting
the fact that the sets of Kirchhoff equations for voltages and
that for currents are independent of each other. Thus, it is
possible to introduce new unknowns that by definition make
it possible to satisfy one of the two sets of equations. This way
of dealing with the problem leads to the introduction of the
method of node potentials, where the n 1 unknowns are the
node potentials, and to the method of loop currents, where the
b (n 1) unknowns are, in fact, the loop currents (see TIMEDOMAIN NETWORK ANALYSIS, where these methods are dealt
with in detail). Naturally, one can resort to the method of the
node potentials or loop currents even when the one-ports are
neither resistive nor linear, because they are based on a particular technique of reformulating the node and loop equations, which, we recall, are not dependent on the nature of
the elements present in the network.
Where the one-ports of the network (even if they are still
linear) are not all resistive, the overall system of circuit equations becomes of the algebraic-differential type. This is because the constitutive relations of the dynamic elements contain differential equations. For such networks, circuit
equations alone are not sufficient to determine the solution of
the circuit starting from a given time t0. This is due to the
fact that the behavior of a dynamic one-port for t t0 depends
also on the state of the one-port at t t0: The state contains
all the information of the one-port past history necessary to
determine its future behavior. For example, the state variable
of linear capacitors is the voltage, while that of linear inductors is the current. As a result the mathematical model of a
circuit generally consists of the circuit equations and the initial state of all the dynamic elements. This aspect will be
dealt with in detail later. However, even here, searching for
the unknown functions i1(t), i2(t), . . ., ib(t) and v1(t), v2(t),
. . ., vb(t) for t0 t does not present particular problems for linear circuits, as it falls within the well consolidated
field of solving a system of linear algebraic-differential equations.
The whole system of circuit equations can be reduced to a
system of linear ordinary differential equations of the first
order, where the state variables of the circuit are the only
unknowns; these are the state equations of the circuit. The
possibility of effecting such a reduction has an important significance: The first-order time derivative of each state variable and all the other circuit variables at any time t depend
only on the values that all the state variables and the sources
of the circuit have at the same time t. By means of the state
equations it is possible to study many of the properties of linear circuits without having necessarily to solve them.
The study of circuit equations is considerably complicated
when the circuit contains nonlinear elements (for example,
diodes, nonlinear inductor, nonlinear capacitors). This is because it is no longer possible to apply the superposition property, a property that is the basis of the whole analysis of linear circuits (see NETWORK THEOREMS).

156

NETWORK EQUATIONS

In the case of nonlinear circuits with only resistive elements, the circuit equations are still algebraic, but a part of
them is nonlinear. The properties of these equations can be
very different from those of linear circuits. For example, it is
possible to have several solutions that are compatible with
the same sources. In general, the problem of their solution is
very complicated and there are still many unsolved questions.
The analysis is further complicated (and considerably so)
if the nonlinear circuit contains dynamic elements. Because
many results can be found in the literature on nonlinear ordinary differential equations having the normal form dx/dt
H(x; t), where x is a vector whose components are the state
variables of the circuit and H is a single-valued vectorial function, much attention has been given to determining when is
it possible to reduce the equations of nonlinear dynamic circuits to a system of differential equations in normal form for
the state variables.
In general, for nonlinear circuits it is not always possible
to reduce the system of circuit equations to a system of state
equations in normal form. It can happen that the first derivative of some state variables depends on the state variables of
the circuit through multivalued functions. As we will then
see, if this happens, it means that the circuit equations and
the initial state alone are not sufficient by themselves to determine the circuit evolution. That is, the circuit model under
consideration is incomplete; essential phenomena for an adequate representation of the physical circuit are absent in
the circuit model because of the approximations introduced in
the modeling phase.

CONSTITUTIVE AND KIRCHHOFF EQUATIONS

Every circuit element is described by a mathematical model
that approximates the behavior of a physical device. It may
happen that, depending on the application, the same physical
device can be represented by different models. Generally,
complex circuit elements are obtained by interconnecting several basic elements. First, we will consider the general features of constitutive relations of basic circuit elements to
show how they affect the network equation structures. Later,
we will deal with Kirchhoff s equations, which describe the
interaction between single elements.
The first basic classification divides one-ports, and, more
generally, circuit elements with several terminals, into resistive and dynamic.

and the resistance R is a constant. If the relation between the

voltage and the current is not linear, we say that the one-port
is nonlinear. Examples of nonlinear resistive one-ports are diodes and varistors. For example, the exponential model of the
junction diodes is described by the equation i Is[exp(v/
nVT) 1] where I, VT and n are characteristic parameters and
a varistor model is described by v i, with and constant. Also, ideal voltage and current sources are resistive
one-ports, respectively, imposing the voltage and current.
Generally, it is not always possible to express the constitutive relation of a nonlinear resistive one-port by combinations
of elementary functions. This difficulty can be overcome by
observing that Eq. (1) can be represented graphically in the
(v, i) plane. The curve thus obtained is the characteristic curve
of the one-port. The points on such a curve represent the possible operating conditions of the one-port. A graphic representation allows the effective operating point to be easily determined for simple circuits of the type shown in Fig. 2(a).
Figure 2(b) shows the characteristic curves of two one-ports.
In this case the only operating point compatible with the two
characteristics and Kirchhoff s laws (which in this simple
case are reduced to i1 i2 and v1 v2) is given by the intersection of the two curves. It is to be noted that the normal convention has not been adopted for the second one-port. Naturally, there can be cases, which we will examine later, where
the characteristic curves do not meetor meet at more than
one point. There are one-ports that have characteristic curves
that are variable in the time; they are called time-varying
one-ports. The function f s for these one-ports depends also on
time as a parameter. When the characteristic of the one-ports
does not vary in time, they are said to be time-invariant. The
resistor with a time-independent resistance and diodes are
examples of time-invariant one-ports, while the switches are
examples of time-variant one-ports.
A voltage (current) value is called admissible voltage (current) if there is at least one current (voltage) value such that
Eq. (1) is satisfied. It can happen that not all the current and
voltage values are admissible for a static one-port. It is sufficient to consider the characteristic of an ideal voltage or current source, or of the ideal diode. This is possible since Eq. (1)
is only the representation of a physical device in the context
of the circuit model that we are adopting. The presence of
elements with characteristics of this type can give rise to
problems of incongruency of the circuit model. For example,
for the ideal diode, positive voltages and negative currents
are inadmissible (appropriate references having been chosen).

Resistive One-Ports
A resistive one-port is a two-terminal circuit element described by a constitutive relation of the type

i1 = i2 = i
+

+
i1

f s (v, i) = 0

i2 = i2 (v2)

(1)
v1

Equation (1) defines an instant type relation between the current i and the voltage v, that is, the value of the voltage at
any time t depends only on the value that the current assumes at that time and vice versa.
The linear resistor is a particular type of resistive one-port
where
v = Ri

i2

(2)

2 v2

v1 = v2 = v

(a)

i1 = i1 (v1)
(b)

Figure 2. (a) Simple resistive circuit used to illustrate the graphic

solution method; (b) the two one-port characteristic curves are superimposed on the same (v,i) plane.

NETWORK EQUATIONS

rent source will admit more than one solution; see Fig. 4. This
is a further example of an inadequate circuit model. In this
case to obtain a circuit that admits one and only one solution,
it is sufficient to add a capacitor with an arbitrary small capacitance in parallel to the tunnel diode.

i
+

+
i
+

i = i (v)

Dynamic One-Ports
v

(a)

(b)

Figure 3. Example of an unsolvable resistive circuit for E 0 [i

(v) is the characteristic of an ideal diode].

The voltage and the current in dynamic one-ports are related

through differential equations. Thus, the value of the voltage
or of the current also depends at every instant on their time
history. Basic dynamic one-ports are the capacitor and the inductor.
The constitutive relation of the capacitor is
f c (v, q) = 0

Consequently, a circuit consisting of an ideal diode connected

to an ideal voltage source may not admit solution as in the
case shown in Fig. 3, where the two characteristic curves do
not intersect each other. That is, the circuit model in question
does not adequately describe the physical circuit it represents. To obtain a circuit model that admits one and only one
solution, it would be sufficient to add a resistor with an arbitrarily small resistance in series to the voltage source.
If for any admissible voltage value there exists one current
value that verifies Eq. (1), then this can be rewritten as
i = (v)

(3)

where ( ) is a single-valued function defined for the admissible voltage values. These one-ports are called voltage controlled. If, however, for any admissible current value there is
one voltage value that verifies Eq. (1), it can be rewritten as
v = v(i)

157

(4)

where v( ) is a single-valued function defined for the admissible current values. These one-ports are called current controlled. Naturally, if the one-ports are time-varying, then the
functions and v depend on the time.
There are static one-ports that are voltage and current
controlled at the same time; for example, linear resistors
(with R 0 and R ), junction diodes, zener diodes and
varistors. In these cases the characteristic curves are strictly
increasing, Eq. (1) can be rewritten indifferently as either Eq.
(3) or Eq. (4) and the function g is the inverse of the function
r and vice versa. One-ports that are only voltage or only current controlled have characteristic curves that are not strictly
increasing. Therefore, it is clear that in the case where a oneport is voltage controlled only, the function g is not wholly
invertible with respect to the voltage; in the case where a oneport is current controlled only, the function r is not wholly
invertible with respect to the current.
The ideal current source, the open circuit and the tunnel
diode, are examples of voltage-controlled one-ports. The ideal
voltage source, the short-circuit and the thyristor with disconnected gate are examples of current-controlled one-ports. The
ideal switch is current controlled when it is on and voltage
controlled when it is off. A circuit consisting of a voltage-controlled one-port (such as the tunnel diode) connected to a cur-

(5)

where q is the capacitor charge related to the current of the

capacitor by the differential equation
i=

dq
dt

(6)

or the integral equation

q(t) =
t0

i( ) d + q(t0 ),

t t0

(7)

Equation (5) is an instantaneous relation between the charge

and the voltage of the capacitor, that is, the charge at any
time t depends only on the voltage value at the same time t
and vice versa. By contrast, the relation between the voltage
and the current, because of Eq. (6) or (7), is not instantaneous; the charge, and hence the voltage, at any time t t0
depends on the charge value at t t0 and on the entire time
history of the current on the interval [t0, t]. The value of the
charge q(t0) summarizes the whole electric history of the capacitor for t t0. Therefore, capacitors have memory. In general, Eq. (5) can be represented graphically in the (v, q) plane.
This defines the characteristic curve of the capacitor; for this
reason Eq. (5) is called the characteristic equation of the capacitor.
For linear capacitors we obtain
q = Cv

(8)

i
+

+
i

i = i (v)
J

v
v

(a)

(b)

Figure 4. Example of a resistive circuit with three solutions [i

(v) is the characteristic of a tunnel diode].

158

NETWORK EQUATIONS

with C constant, and thus

i=C

dv
dt

(9)

or, equivalently,

v(t) =

1
C

t0

i( ) d + v(t0 )

t t0

(10)

From Eq. (10), it is more evident that v(t) depends on the time
history of the current in the time interval (t0, t) and on the
voltage value at t t0. A capacitor having a constitutive relation that is nonlinear is called nonlinear. As an example of a
nonlinear capacitor, we can consider the model of the varactor
diode described by the equation q 3/2 C0V0(1 v/V0)2/3 for
v V, where C0 and V0 are two constants.
The other fundamental dynamic one-port, which, with respect to the capacitor has a dual operation, is the inductor,
defined by the constitutive relation
f i (i, ) = 0

(11)

where is the inductor flux, connected to the voltage v by the

differential equation
v=

d
dt

(12)

or, equivalently, by the integral equation

From Eq. (16), it is evident that i(t) depends on the time history of the voltage in the interval (t0, t) and on the current
value at t t0. An inductor whose characteristic is nonlinear
is called nonlinear. For example, the behavior of an inductor
realized on a ferromagnetic core can be described by the nonlinear constitutive equation i a b3 if the hysteresis
phenomena are negligible, and a Josephson junction can be
represented by the equation i I0 sin( /0); a, b, I0 , and 0
are characteristic constants.
It is possible to extend all the concepts introduced for static
one-ports to the characteristic curves of capacitors and inductors (time-variant capacitors, time-variant inductors, voltage
and charge admissible values, charge and voltage-controlled
capacitors, current and flux admissible values, flux and current-controlled inductor. For example, the varactor diode
model given in the foregoing describes a voltage-controlled capacitor with v V0 admissible voltages. For more details on
linear and nonlinear one-ports we refer the reader to LINEAR
NETWORK ELEMENTS and to NONLINEAR NETWORK ELEMENTS.
Circuit Elements With More Than Two Terminals
An element with M 1 terminals is characterized by M 1
currents i1, i2, . . . and (M 1)M/2 voltages v12, v13, . . .; the
current ik is associated with the kth terminal and the voltage
vkh is associated with the two terminals k and h. The reference
directions of the currents are those entering the element, and
for the voltages those going from the terminal k to the terminal h. An example is shown in Fig. 1(b), where (M 1) 3,
and in Fig. 1(c), where (M 1) 4.
In agreement with Kirchhoff s law for currents, at any
time the following equation has to be verified:

(t) =
t0

v( ) d + (t0 )

t t0

(13)

M+1


ih = 0

(17)

h=1

Equation (9) is an instantaneous relation between the flux

and current of the inductor, that is the inductor flux at any
time t depends only on the current at that time t and vice
versa, while the relation between the current and the voltage
is not of an instantaneous type: the flux, and hence the current, at any time t t0 depends on the flux value at t t0
and on the entire time history of the voltage on the interval
[t0, t]. For the inductor the value of the flux (t0) summarizes
the whole electric history for t t0. Therefore the inductors
have memory like the capacitors. In general, Eq. (9) can be
represented graphically in the (i, ) plane and it defines the
characteristic curve of the inductor; it is called the characteristic equation of the inductor.
For linear inductors we have
= Li

(14)

di
dt

(15)

with L constant, and thus

v=L
or, equivalently,

i(t) =

1
L

t
t0

v( ) d + i(t0 )

t t0

(16)

Therefore, only M currents are independent. Similarly, in

agreement with Kirchhoff s law for voltages, it has to be
vkh = vkp vph

(18)

and, thus, as for currents, only M voltages are independent.

To identify a set of independent currents and voltages one
may choose a reference terminal, for example, the terminal
labeled M 1, and consider the currents of the first M terminals i1, i2, . . ., iM and the voltages v1, v2, . . ., vM between
the first M terminals and the reference terminal (in Fig. 1(b)
an element with three terminals is considered, M 2; the
terminal labeled 3 is chosen as reference terminal). The
variables thus obtained are all independent of each other and
any other electrical variable of the element under consideration can be expressed as a linear combination of them by
means of Eqs. (17) and (18). They are called descriptive variables of the element. In general, the constitutive relations
link the descriptive currents and the descriptive voltages of
the single elements of a circuit. This method is one among
many other possible methods for identifying a set of independent currents and voltages of a multi-terminal element (see
MULTIPOLE AND MULTIPORT ANALYSIS).
The one-port is an element with two terminals (M 1
2) and is characterized by a single descriptive current and a
single descriptive voltage [Fig. 1(a)]. The three-pole is an ele-

NETWORK EQUATIONS

ment with three terminals (M 1 3) and is characterized

by two descriptive currents and two descriptive voltages [Fig.
1(b)]. The four-pole is an element with four terminals, and so
on. Examples of three-poles are transistors and three-phase
voltage sources, while among four-poles there are voltageand current-controlled sources, ideal transformers, operational amplifiers, gyrators, and mutual inductances.
Typological analysis undertaken for the constitutive relations of one-ports can be extended to constitutive relations of
elements with M 1 terminals without any problem of principle. Consider, for example, a resistive three-pole and let i1,
i2 and v1, v2 be, respectively, the descriptive currents and voltages [Fig. 1(b)]. The constitutive relation is of the type
f 1 (v1 , v2 , i1 , i2 ) = 0
f 2 (v1 , v2 , i1 , i2 ) = 0

(19)

where f 1 and f 2 are two functions, generally nonlinear. For

resistive linear three-poles the relations between the descriptive variables are linear. In general, as Eq. (19) may not be
described by means of a finite combination of elementary
functions, it might be useful to represent them graphically,
considering some of the descriptive variables as parameters.
An appropriate choice of reference terminals can simplify the
representation of the characteristic curves considerably. As
with the one-port, the possibility of making Eq. (19) explicit
with reference to two descriptive variables depends on the
control variables of the element.
For dynamic n-terminal elements, however, only the relations between fluxes and currents or charges and voltages are
of instantaneous kind. For example, the generic descriptive
voltage vk of a multi-terminal element of inductive type (e.g.,
coupled inductors), is equal to the time derivative of the flux
k. Besides, k is related to all the descriptive currents of the
element through an algebraic relation.
The operation of an element with more than two terminals
may be conditioned by the topology of the circuit into which
it is inserted. The simplest and at the same time the most
significant example is that in which an element with 2M terminals is connected to M distinct circuits, each of which is
representable as a one-port [in Fig. 1(c) an example with
M 2 is considered]. In this case the current that enters a
given terminal is equal to the current that exits from another
terminal. Each terminal couple having this property is called
a port of the element, and the element in this operating state
is called an M-port. Each port of an M-port is characterized
by the current circulating in one of the two terminals and by
the voltage between the two terminals (for every port we can
adopt the normal convention). It is clear that in this operating
condition the constitutive relations must be taken as those
that relate the currents and voltages of the single ports of the
element. We should remember that there are also elements
with 2M terminals that can operate only as M-ports. The
ideal transformer and the ideal operational amplifier are two
examples of elements with four terminals that can operate
only as two ports. For more details on linear and nonlinear
multi-terminal elements we refer the reader to LINEAR NETWORK ELEMENTS and to NONLINEAR NETWORK ELEMENTS.
Kirchhoff s Equations
In the beginning of this article Kirchhoff s laws were recalled
in reference to a circuit consisting of only one-ports. Their

159

extension to a circuit with more than two terminals is

straightforward if one is referring to the circuit graph. Such
a circuit graph can be formed by associating N nodes and
(N 1) branches with elements with N terminals, for as
many descriptive variables as there are (a reference node having previously been chosen for each element), and to each
M-port 2M nodes and M branches, for as many ports as extant. Then, let us consider a circuit with b branches n nodes
and let vk, ik, k 1, . . ., b be the unknowns of the circuit. As
we have mentioned earlier, only (n 1) equations at the
nodes and (b n 1) equations at the loops are linearly
independent. To simplify the discussion we are implicitly assuming that the circuit graph is connected. Where this is not
so, what has been said holds true for every single connected
part of the whole graph.
To determine (n 1) linear-independent equations at the
nodes one need only consider any (n 1) nodes of the circuit,
but determining (b n 1) linear-independent equations at
the loops is not as easy as it is for the nodes. In general, (b
n 1) linearly independent equations at the loops can be determined by applying Kirchhoff s law for voltages at a set of
fundamental loops of the circuit.
The concept of the fundamental loop, which we will recall
briefly here, is linked to the tree and the co-tree of a circuit.
We recall that a tree is a subset of branches that pass through
all the nodes of the circuit without forming loops. Even if a
circuit has different trees, each tree consists always of (n
1) branches; the remaining (b n 1) branches of the graph
constitute the co-tree. Therefore, each branch of the co-tree
belongs to a loop consisting of itself and branches of the corresponding tree. Such a loop is called a fundamental loop. Thus
for every choice of the tree there exist (b n 1) fundamental loops. It is evident that equations obtained by applying
Kirchhoff s loop law to (b n 1) fundamental loops are
linearly independent because each of them exclusively contains the voltage of the corresponding co-tree branch.
Thus Kirchhoff s laws allow independent b equations to be
written in 2b unknown voltages and currents. These equations can be written in compact form using the vector notation. To this end we define the column vectors

i = [i1 , . . ., ib ]T
v = [v1 , . . ., vb ]T

(20)

representing, respectively, the circuit currents and voltages.

Then the linearly independent Kirchhoff b equations can be
rewritten using two matrices A and B whose elements are 0,
1, or 1
Ai = 0

(21)

Bv = 0

(22)

The (n 1) b matrix A is a reduced incidence matrix of the

circuit and the (b n 1) b matrix B is a fundamental
loop matrix (for more details see TIME-DOMAIN NETWORK ANALYSIS). The system of Eqs. (21) and (22) is a maximal independent set of Kirchhoff equations. The (n 1) independent
equations for the currents can also be obtained with a fundamental cut set of the circuit; in this case A is a fundamental
cut set matrix.

160

NETWORK EQUATIONS

THE SYSTEM OF CIRCUIT EQUATIONS

the circuit equations and it is compatible with the initial conditions for the state variables.

As we have seen, the dynamics of a circuit is described by a

maximal set of Kirchhoff independent equations and by the
constitutive relations of the single circuit elements, which by
their very nature are independent of each other. The Kirchhoff equations are linear, algebraic and homogeneous and
thus the interaction they describe is always instantaneous
and linear. By contrast, the constitutive relations of the circuit elements can radically modify the nature of the overall
system of equations by transforming it into algebraic-differential and nonlinear. From this viewpoint the most interesting
classifications are resistive elements and dynamic elements,
linear elements, and nonlinear elements.
Let us, for the moment, consider a circuit consisting of linear and time-invariant capacitors and inductors and resistive
one-ports that can, instead, be nonlinear and time variant.
Later, we will refer to a circuit consisting of nc capacitors and
ni inductors, as well as ns resistive one-ports. The number of
circuit branches will then be b nc ni ns. For the sake of
simplicity, we will number the circuit branches in the following order: the capacitor branches are numbered from 1 to nc;
those corresponding to the inductors from nc 1 to nc ni;
and, finally, those corresponding to the resistive one-ports
from nc ni 1 to nc ni ns b. For this type of circuit
the system of circuit equations is made up of the b Kirchhoff
Eqs. (21) and (22), nc first-order differential equations of the
type of Eq. (9), ni first-order differential equations of the type
of Eq. (15), and ns algebraic equations of the type of Eq. (1).
The presence of linear and time-invariant dynamic oneports in the network introduces first-order differential equations, and, therefore, it is necessary to know the initial values
of the variables that appear in them under the derivative operations. In fact, from the integral form Eq. (10) of the capacitor constitutive relation, it is clearly seen that, in order to
know the voltage value at any given time t, it is not enough
to know the current in the interval (t0, t); one also needs to
know the voltage or the charge at t t0. The initial condition
v(t0) summarizes the effects of the entire past history of the
capacitor (from t to t t0) on the present value of v(t)
for t t0. From the physical viewpoint this is due to the fact
that capacitor voltage determines the energy value EC stored
in the one-port at every instant throughout the relation (see
NETWORK THEOREMS).
Ec (t) =

1 2
1 2
Cv (t) =
q (t)
2
2C

(23)

Similarly, for the inductor, it is necessary to know the current

value or the flux at the initial instant. We will call the capacitor voltages and the inductor currents state variables of the
circuit under examination insofar as they describe the initial
state. Naturally, the same role can be played by the capacitor
charge and the inductor flux, respectively.
In the final analysis the state of the circuit at the generic
instant t1 summarizes the whole electric history of the circuit.
No matter how the circuit has been brought to its state at the
instant t1, its subsequent behavior will depend only on the
state value at t t1 and on the independent sources (see TIMEDOMAIN NETWORK ANALYSIS). The set of functions vk(t), ik(t);
k 1, . . ., b defined in the interval t0 t , is called the
circuit solution in the interval t0 t if it is a solution of

Resistive Circuits
Even if circuits without inductors and capacitors are a particular case, their study is of fundamental importance in circuit
theory. In fact, as we will see, in the study of dynamic circuits
one often resorts to auxiliary circuits consisting of resistive
elements related to the dynamic circuits being studied. When
an electric network is without dynamic elements, that is,
nc ni 0, the circuit is said to be resistive and the circuit
equations are algebraic and generally nonlinear. Even if the
sources present are time variant, the solution at each instant
has no memory of its operating point at preceding instants.
For these circuits the time appears as a parameter in the
equations. Therefore the relations between the overall circuit
variables and the voltages and currents imposed by the independent sources are instant type relations. If the nonlinearities of the one-ports present allow it, the values of the 2b
unknowns can be determined univocally by solving the relative system of algebraic equations instant by instant. In the
case of linear one-portsapart from pathological cases, which
we will refer to shortlythis is always possible. In the presence of nonlinearities, the circuit may have no solutions, one
solution or several solutions.
The pathological situations in which a resistive network,
even linear, may not admit solutions, are those where there
is incongruency or dependence between the constitutive relations of some circuit elements and the Kirchhoff equations
regulating the interaction. In general, bearing in mind what
has been said in the introduction to this article about the interaction between each single element and the rest of the network, we may say that cases of incompatibility between
Kirchhoff s equations and the constitutive relations may occur when there are elements for which there are inadmissible
voltages and/or currents. The case of two ideal sources of voltage e1(t) and e2(t) connected in parallel is emblematic. It is
evident that no solution is possible when there is incongruency [i.e., e1(t) e2(t)], while the number of solutions is infinite, at least so far as the currents of the sources are concerned, when there is dependence [i.e., e1(t) e2(t)]. Naturally,
the incongruency or the dependence is entirely in the model
used to represent the real circuit; a more realistic model that
includes the internal resistance of the sources would resolve
every problem of incongruency or dependence. In general, the
existence and the uniqueness of the solution of a linear resistive one-port network are guaranteed if there are no loops
consisting of voltage sources only, no cut-sets consisting of
current sources only, and the resistances of the circuit resistors are strictly positive. If controlled sources, ideal transformers, gyrators, nullators, and norators are also present in
the circuit, further pathological situations of a different nature may be present. There can also be cases where solutions
do not exist because of the presence of nonlinear elements. A
typical case is that of an ideal current or voltage source that
feeds an ideal diode, as we have seen in the foregoing. In this
case the incongruency disappears if more realistic models of
source or diode are also adopted. Hereafter we will assume
that such situations are absent. Finally, it should be said that
even where the system of circuit equations admits more than
one solution, such behavior can be attributed to a weakness

NETWORK EQUATIONS

161

of the model. In reality, it is not possible to determine which

of the solutions is the one for the real circuit if other factors,
able to provide a single solution, are not forthcoming. For
nonlinear resistive networks the existence and uniqueness of
the solution are certainly guaranteed if, besides the topological hypotheses on sources made for the linear case, all the
current and voltage values are admissible for the nonlinear
resistors, and their characteristic curves are strictly increasing. If the first hypothesis is not satisfied, there can be no
solution; if the second one is not satisfied, the solution may
not be unique. However, the question of existence and uniqueness of the solution for nonlinear resistive circuit requires further discussion which we cannot undertake here. See Ref. 1
where the problem is considered in detail.
To solve nonlinear resistive circuit equations it is generally
necessary to resort to approximate methods. Only for linear
circuits is it possible to determine the solution by analytical
methods, as, for example, Gausss method. However, many
properties of the solution of nonlinear resistive circuits may
be determined without necessarily having to resolve the circuit equations.

expressing the 2b (nc ni) nonstate variables of the circuit

as function of the nc ni state variables. Then the expressions
of the capacitor currents ic and the inductor voltages vi so
obtained are substituted in Eqs. (24).
To clarify the matter it is useful to refer to a concrete example of the type shown in Fig. 5. All the voltages and currents have been ordered in accordance with the convention
we have previously adopted. The equations that describe the
dynamics of the circuit are

dv1

= i1
C
dt
(26)
di

L 2 = v2
dt

0 = i1 + i2 i3

0
= i3 + i4

0 = v v
1
2
(27)
0 = v2 + v3 v4

0 = v 3 R3 i 3

0 = v4 e(t)

Dynamic Circuits and Global State Equations

The system of circuit Eqs. (26) and (27) consists of 8 equations

in 8 unknowns; Eq. (26) expresses, respectively, the constitutive relations of the capacitor and the inductor. The first four
equations of Eq. (27) constitute the maximal set of linearly
independent Kirchhoff equations and the remaining two
equations are the constitutive relations of the resistive oneports present in the circuitthe resistor and the voltage
source.
To reduce the differential algebraic Eqs. (26) and (27) into
canonical form, one need only determine the expression of the
capacitor current i1 and the inductor voltage v2, from Eq. (27),
as function of the sole state variables v1, i2 and the voltage
source e(t). To this end it is sufficient to consider the voltage
v1 and the current i2 as assigned, and interpret Eq. (27) as a
system of 6 equations in the 6 unknowns i1, v2, i3, v3, i4, v4.
The solution of this system is

Returning to circuits with dynamic one-ports, we observe

that, in general, the system of 2b circuit equations of the network is of the algebraic-differential type

vc
dv

= ic
C
dt
(24)

dii

L i = v i
dt
0 = F (vv, i ; t)

(25)

where vc (v1, . . ., vnc)T, ii (inc1, . . ., incni)T are the vectors

that represent, respectively, the capacitor voltages and the
inductor currents, that is, the state variables of the circuit,
C diag(C1, . . ., Cnc), L diag(Lnc1, . . ., Lncni) are two
diagonal matrices, respectively, representative of the capacitances and inductances of the circuit, ic (i1, . . ., inc)T, vi
(vnc1, . . ., vncni)T are the vectors that represent, respectively,
the capacitor currents and the inductor voltages, and v, i are
representative of all the network voltages and currents. The
system of algebraic equations (25) consists of the b Kirchhoff
equations (21) and (22) and b (nc ni) characteristic equations of the resistive one-ports, that is, b (nc ni) equations
of the type of Eq. (1).
The system of 2b Eqs. (24) and (25) can be reduced to the
canonical form wherein only the state variables appear as unknowns. That this is possible is evident from the following
considerations. If we assign the state variables at a given
time, that is, nc ni circuit variables, the overall system of
Eqs. (24) and (25) can be interpreted as a system of 2b equations, which still has 2b unknowns, where now the derivatives
of the state variables have assumed the role of unknowns instead of the state variables themselves. Such a system can be
resolved to furnish the values of the derivatives of the state
variables at that given time. In other words, it is possible to
express the state variable derivatives as function of the state
variables themselves, and this constitutes the canonical form
to which we referred. Operatively, this result can be obtained
as follows: the system of algebraic Eqs. (25) is resolved by

e(t) v1 (t)
i2 (t)
R
v2 (t) = v1 (t)
i1 (t) =

(28)

and

i3 (t) = i4 (t)
v3 (t) = e(t) v1 (t)
v1 (t) e(t)
R
v4 (t) = e(t)

(29)

i4 (t) =

i3 +
i4

R
+
+

e(t)

v3

v4

i2
i1
C

+
v1

v2

Figure 5. Simple dynamic circuit used to illustrate the determination of the state equations in normal form.

162

NETWORK EQUATIONS

The result obtained is very significant; the nonstate variables can be expressed at each instant as function of the sole
state variables and the voltage source. The result further justifies the name of state variables given to v1 and i2; their
knowledge at a given time in fact implies the knowledge of all
the other circuit variables at the same time and thus univocally determines the state of the circuit. Substituting Eq.
(28) in the differential Eqs. (26), the equations for the state
variables are obtained

v = v (i)

v
i
e(t)
dv1
= 1 2 +
dt
RC C
RC
di2
v1
=
dt
L

Figure 6. Characteristic curve of a current-controlled one-port.

(30)

This is a system of two first-order ordinary differential equations in normal form, that is, in general, of the type

dx1
= H1 (x1 , . . ., xN ; t)
dt
....................

(31)

dxN
= HN (x1 , . . ., xN ; t)
dt
where xk is the generic state variable, the value of which is
known at instant t t0, and H1, . . ., HN are single-valued
functions defined for every x1, . . ., xN, where N nc ni.
The differential equations that regulate the dynamics of the
circuit state variables, written in the normal form of Eq. (31),
are called global state equations of the circuit. Global state
Eqs. (30) are linear and with constant coefficients because the
circuit under examination consists of linear and time invariant one-ports.
Naturally, the presence of a nonlinear one-port of particular nature can hinder the reduction of the circuit equation to
a system of normal form state equations. Let us again consider the circuit in Fig. 5 where, however, we have substituted the linear resistor with a nonlinear one. If the nonlinear
resistor is both voltage and current controlled (for example, a
junction diode) or only voltage controlled [for example, a tunnel diode; see Fig. 4(b)], its constitutive relation is of type
i3 (v3), where the function (v3) is a single-valued function.
Here, too, it is possible to express the circuit variables as
functions of the state variables by means of a univocal relation of instantaneous type, resolving the algebraic part of the
circuit in respect to the nonstate variables. In this case the
global state equations are nonlinear and are

[e(t) v1 (t)] i2
dv1
=

dt
C
C
v2
di2
=
dt
L

(32)

If, instead, the nonlinear resistor is controllable only in the

current (for example, a thyristor with disconnected gate) the
constitutive relation is of the type v3 v(i3), where the function v(i3) is not globally invertible, that is, it is not invertible

for every value of i3 (see Fig. 6). In this case the capacitor
current i1 can be expressed as a function of the state variables
only in the implicit form through the nonlinear equation
v[i
1 (t) + i2 (t)] + v1 (t) e(t) = 0
Thus the state equations are


dv
v C 1 + i2 (t) = v1 (t) + e(t)
dt
v
di2
= 2
dt
L

(33)

(34)

As the function v(i3) is not globally invertible, the first equation of the system in Eq. (34) cannot be rewritten in normal
form. This is a direct consequence of the fact that in this circuit even though all the nonstate circuit variables are linked
to the state by means of the instantaneous relations imposed
by the algebraic part of the circuit equations, the state does
not determine them univocally. From Eq. (34) it is evident
that the capacitor current can be expressed in general as
function of the state variable and the voltage source only
through multivalued functions. In this case, starting from the
assigned initial conditions, the solution of the state equations
cannot be unique because the time derivative of the capacitor
voltage is a multivalued function of the state variables and
the voltage source. From the physical point of view this is
another very interesting example of an incomplete model. The
incongruency can be resolved by adding an inductor with an
arbitrary small inductance in series with the nonlinear resistor. In this way the current i3 also becomes a state variable.
It is clear, then, that to reduce the circuit equations to a
system of global state equations, one needs to be able to express the nonstate circuit variables, and in particular the capacitor currents and the inductor voltages, as functions of the
state and source variables by means of single-valued functions. This is the same as resolving a resistive circuit obtained
from the actual circuit by substituting each capacitor with a
voltage source whose voltage is equal to that of the capacitor
and each inductor with a current source whose current is
equal to that of the inductor. We call this circuit associated
resistive circuit; interested readers may refer to Ref. 1. Thus
it is evident that the necessary and sufficient condition to express the nonstate circuit variables of a dynamic circuit as
functions of the state variables by means of single-valued
functions is that the associated resistive circuit admits one
and only one solution for every admissible state value. In this
way the possibility of reducing the circuit equations to a sys-

NETWORK EQUATIONS

163

tem of global state equations is brought back to the study of

the existence and uniqueness of the solution for a resistive
circuit.
If the dynamic circuit is linear the associated resistive circuit also is linear. In this case, in agreement with what has
been said about linear resistive circuits, it is possible to reduce the circuit equations to a system of global state equations if: (1) the dynamic circuit does not have loops consisting
of only capacitors and independent voltage sources and cutsets consisting of only inductors and independent current
sources; and (2) all the circuit resistances are strictly positive.
Naturally the presence of controlled sources (or elements that
can be returned to the controlled sources) of norators or nullators in the associated resistive circuit implies that the very
difficulties that we mentioned previously regarding the existence and the uniqueness of solutions are reflected in the possibility of writing the state equations in normal form. Even if
the nonlinear case does not lend itself to a systematic general
treatment, the preceding criterion continues to be valid if the
characteristics of the nonlinear resistors are defined for all
voltage and current values and are strictly increasing. By contrast, if the dynamic circuit also contains resistors with nonmonotone characteristics, nonlinear multi-terminal elements
as transistors, and operational amplifiers, then the associated
resistive circuit can have more than one solution, as we have
demonstrated in the example; thus, a global state equation
system may not exist.
Reference 2 proposes algorithms for the formulation of circuit state equations relevant to linear circuits that can easily
be implemented by a computer, based on the solution of the
associated resistive circuits. Again Ref. 2 indicates a criterion
that allows the verification of the existence or nonexistence of
global state equations dx/dt H(x; t) for a nonlinear dynamic
circuit and proposes an algorithm for the numerical evaluation of the vector-valued function H.
Once the global state equations are obtained it is necessary
first to ascertain the existence and uniqueness of the solution
for fixed initial conditions. The problems connected with the
existence and uniqueness of the solution of the global state
equations are also dealt with in detail in NONLINEAR DYNAMIC
PHENOMENA IN CIRCUITS. Here, we limit ourselves to recalling
that in the case of linear state equations the solution exists
and is unique regardless of the initial conditions for the state.
The existence and uniqueness of the solution in the nonlinear
case are ensured if the characteristics of the nonlinear oneports are regular and every resistive element absorbs electrical power as soon as the current or the voltage exceeds a certain value; interested readers may refer to Refs. 13.
The solution of the state equations can be determined analytically only in the case of linear and time-invariant circuits.
In this case the circuit state equations are of the type

ables are annulled, which is called free evolution, and one that
is annulled if the sources are all turned off, which is called
forced evolution. Each of these can be represented through
the nc ni natural modes of the circuits eit, where i i 1,
. . ., nc ni are the natural, generally complex, frequencies
of the circuit (we have implicitly assumed that the natural
frequencies are all distinct); the natural circuit frequencies
are the eigenvalues of the dynamic matrix A. For dissipative
circuits the free evolution tends to zero when t , while
the forced one will depend on the waveforms of the independent sources of the network. For example, when all the circuit
sources are constant, the forced evolution term for every variable tends towards a constant function for t . Where all
the sources are sinusoidal and isofrequential, the forced evolution term of each variable tends towards a sinusoidal waveform with the same frequency as the sources for t . By
contrast, for time-variant and/or nonlinear circuits the solution cannot be determined in closed form. In these cases one
has to use approximate solution methods, such as perturbative techniques (see NETWORK ANALYSIS USING LINEARIZATION)
and more generally numerical methods (see CIRCUIT ANALYSIS
COMPUTING and PERIODIC NONLINEAR CIRCUITS). The general
properties of the solutions of circuit state equations, even
nonlinear, can be determined without having to resolve them.
In the last thirty years many analysis techniques have been
developed for predicting the qualitative behavior of the solutions of state equations of a circuit merely starting from their
structures and properties (see NONLINEAR DYNAMIC PHENOMENA
IN CIRCUITS, QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS, and
Refs. 13).

dxx
= Axx + d (t)
dt

H N (x1 , . . ., xN ) = 0

(35)

where A is the so-called dynamic matrix and d(t) is a known

term dependent on the sources. The properties and the solution techniques of linear time-invariant dynamic circuits are
also illustrated in TRANSIENT ANALYSIS. Here, we will limit ourselves to recalling that two different terms can be distinguished for each circuit variable because of the linearity; one
that goes to zero if all the initial conditions for the state vari-

Dc Operating Points
Let us now consider time-invariant dynamic circuits with only
stationary sources. These circuits are called autonomous circuits. An autonomous circuit generally admits stationary solutions. These solutions are called dc operating points of the
circuit. The fundamental characteristic of these solutions is
that the current in the capacitors and the voltage across the
inductors are zero at each instant. The dc operating points of
an autonomous circuit can be determined in various ways. It
is possible to determine the stationary solutions of the state
equations first, and then determine the remaining variables
through their instantaneous relations with the state variables. The stationary solutions of the state equations are obtained by making all the system derivatives in Eqs. (31) zero,
and thus they are the solutions of the algebraic equation system

H 1 (x1 , . . ., xN ) = 0
.................

(36)

The dc operating points of an autonomous circuit are also the

solutions of the resistive circuit, obtained by substituting an
open circuit for each capacitor and a short-circuit for each inductor that can be considered as current and voltage sources
turned off, respectively.
In general, except for the cases of model incongruency,
which we have already discussed for resistive circuits, an autonomous circuit will admit one or more dc operating points.

164

NETWORK EQUATIONS

If the resistors of the autonomous circuit have strictly increasing characteristics and topological hypotheses on sources
are verified, then there is only one dc operating point. By contrast, there can be more than one dc operating point if the
circuit also contains resistors that are only voltage or current
controlled. The possibility of having more than one dc operating point in a dynamic circuit does not mean, in fact, that
the circuit model is ill-posed. Which of the dc operating points
is effectively reached depends on the stability of the corresponding stationary solution of the state equations and on the
initial value of the state (see QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS).
The determination of dc operating points assumes particular significance when besides stationary sources the network
also contains variable sources with small amplitudes. In such
cases nonlinear characteristic curves of the network can be
approximated with straight lines passing through the dc operating points of the elements and tangent to the characteristic curves. In this way it is possible to determine the circuit
solution by superimposing the solution of two distinct problems, the first nonlinear but static, and the second, dynamic
but linear.

It is evident that the trajectory of the operating point in

the configuration space is univocally determined if, for every
value of the state circuit variables vc and ii, there is one and
only one operating point P compatible with it. In other words,
the projection of the circuit configuration space onto the
state space of the circuit determines a one-to-one correspondence. This means that the resistive circuit associated with
the dynamic circuit admits one and only one solution, and
thus it is possible to express the nonstate variables as functions of state variables by means of a single-valued function.
If the projection of the circuit configuration space onto the
state space does not determine a one-to-one correspondence,
there may be more than one trajectory of the circuit operating
point compatible with the initial conditions for the state; thus
the circuit model is ill-posed. As an example let us consider
the circuit illustrated in Fig. 7. For the sake of simplicity, this
consists of a sole dynamic element. The resistor N is described
by the constitutive relation f(v4, i4) 0. The circuit equations
are then
L

(37)

0 = i1 i3

0
= i2 + i3

0
= i1 i4
0 = v1 v2 + v3 + v4

0 = v2 E

0
= v 3 R3 i 3

0 = f (v , i )
4 4

GEOMETRIC DESCRIPTION OF THE EVOLUTION

OF A DYNAMIC CIRCUITS
The structure of circuit Eqs. (24) and (25) clearly shows
that dynamic and resistive one-ports play two different
roles in the mechanism determining the circuit time evolution. In particular, the constitutive relations of resistive
one-ports play a role similar to that played by the Kirchhoff
equations. In analogy with mechanics, algebraic Eqs. (25)
can be considered as holonomic constraints, generally time
variant, on the voltages and currents of the circuit, while
differential Eqs. (24) recall the motion equations (see Refs.
1 and 4). To understand this parallel better we will use a
geometric approach. The voltages and currents of the circuit
elements identify a point of coordinates (v1, . . ., vb,
i1, . . ., ib) in a space of 2b dimensions. Because the voltages and currents must be compatible with the holonomic
constraints given by Eqs. (25), consisting of the Kirchhoff
equations and the constitutive relations of the resistive elements, the point (v1, . . ., vb, i1, . . ., ib) is forced to move
on a surface of the space R2b. Let us call a point P
(v1, . . ., vb, i1, . . ., ib), compatible with the holonomic
constraints (25), the circuit operating point, and in analogy
with mechanics, let us call the set of all circuit operating
points the configuration space of the circuit, which we will
indicate with . Normally, if there is no dependence or
contradiction between the Kirchhoff equations and the constitutive relations of the resistive one-ports, the dimension
of the configuration space is N nc ni. In such cases
the circuit solution is represented by the motion of the
operating point P(t) on the surface ; the motion laws are
given by the system of differential Eqs. (24) which describe
the operation of the dynamic one-ports. Returning to the
analogy of mechanics once again and to understand these
definitions better, one may imagine a body sliding along an
inclined plane under the action of gravity. In this case the
configuration space is a plane of the three-dimensional
space.

di1
= v1
dt

(38)

An operating point P (v1, v2, v3, v4, i1, i2, i3, i4) of this circuit
is a point of the eight-dimensional space R8, compatible with
the holonomic constraints determined by the algebraic equations (38). The set of Eqs. (38) consists of 7 independent and
compatible equations, and thus has infinite solutions. The solutions of these equations form a surface of dimension N
8 7 1, that is, a curve of the space R8. This is the configuration space of the circuit under examination.
The only way to visualize this configuration space is to
project it onto two-dimensional planes. The projection of
onto planes with two currents or two voltages as coordinates
is a straight line, as is evident from the first 4 equations of
system [Eq. (38)]. If the projection is made, for example, onto
the plane with coordinates (i1, i3), the straight line is the bisector of the first and third quadrants, while if the projection
is made onto the plane (v1, v3), the straight line does not generally pass through the origin. If is projected onto the

i3 +
i2
+
E

v2

v3
R3

i4

v4

+
L

v1

i1
Figure 7. Circuit used to highlight the problems arising in the writing of the state equations due to nonlinear elements.

NETWORK EQUATIONS
v1

v1

Q(t0)

165

v1

Q(t1)
Q

Q(t2)
Q1

I1
Q(t)
(a)

Q3
Q2

i1

i1

i1

(b)

(c)

planes (v2, i2), (v3, i3) and (v4, i4), we obtain the characteristic
curves of the circuit resistive one-ports. In particular, the projection onto the plane (v2, i2) is a straight line, which moves
parallel to the i2 axis. The projection of onto the plane (v1,
i1), which we will denote with , is the most interesting one,
since it involves all the constitutive relations of the resistive
elements. Combining the equations of system [Eq. (38)] we
obtain the equation for the curve

Figure 8. Projections of the configuration

space of the circuit shown in Fig. 7 onto
the (v1,i1) plane for different types of resistor N.

Let us consider first the case where resistor N is linear, that

is, f(v4, i4) v4 R4i4 0. In this case Eq. (39) becomes

erating point. Therefore, once assigned, the initial state univocally determines the motion of the circuit operating point.
For the case described by a curve of the type illustrated in
Fig. 8(b), three dc operating points are possible, Q1, Q2 and
Q3. One can easily see that the point Q2 is unstable, whereas
Q1 and Q3 are stable. The operating point reaches equilibrium
points Q1 or Q3 according to its initial position as indicated by
the arrows in the figure.
Finally, let us consider the case where the resistor is only
voltage controlled, i4 (v4) [for example, a tunnel diode; in
Fig. 4(b) the characteristic of a tunnel diode is represented],
where (v4) is a single-valued function but not globally invertible. The equation of curve is given by

v1 + i1 (R3 + R4 ) E = 0

i1 (v1 R3 i1 + E) = 0

f (v1 + E R3 i1 , i1 ) = 0

(39)

(40)

and thus is a straight line with a slope constant in time

[Fig. 8(a) reports the case wherein E 0]. The projection of
the operating point P onto the plane (v1, i1), marked Q in Fig.
8(a), moves along the straight line with the law of motion
specified by the differential Eq. (37). In this case at every
value of the state variable i1 corresponds a single point Q and
thus a single operating point P and vice versa. Therefore, once
the initial state i1(t0) is assigned, the initial point Q(t0) is univocally determined, and thus the initial operating point P(t0) of
the circuit. The projection of point Q(t0) onto the v1 axis gives
the inductor voltage at that time, which, by means of Eq. (37),
determines the increase per unit of time of the current i1, and
thus the elementary displacement of the point Q, and hence
of the circuit operating point P. Proceeding, then, the trajectory of the operating point for t t0 can be determined. In
the case we are examining, the circuit has a single dc operating point. This is represented by the intersection of the
configuration space with the hyperplane v1 0. The projection of the dc operating point onto the plane (v1, i1) is represented by Q(t). The operating point, irrespective of its initial
position, tends asymptotically towards the dc operating point
for t .
If the resistor is nonlinear and both voltage and current
controlled (for example, a junction diode) or only current controlled (for example, a thyristor with disconnected gate; see
Fig. 6), its constitutive relation is of the type v4 v(i4), where
v(i4) is a single-valued function. Then Eq. (39) becomes
v1 + R3 i1 + v(i
1) E = 0

(41)

and a possible curve is shown in Fig. 8(b). In this case too,

the projection of curve onto the i1 axis determines a one-toone correspondence between the circuit state and the op-

(42)

and a possible curve is illustrated in Fig. 8(c). In this case, as

the function (v4) is not globally invertible, the projection of
curve onto the i1 axis does not determine a one-to-one correspondence, that is, more than one circuit operating point can
correspond to the same state value [see Fig. 8(c)]. Hence, the
motion of the operating point in the configuration space,
starting from an assigned initial condition, might be undetermined. This is another example of an ill-posed dynamic circuit
model. To obtain a well-posed model it is sufficient to add an
arbitrary small capacitance in parallel to the voltage-controlled resistor. In this way the voltage across the nonlinear
resistor also becomes a state variable.
For the dynamic circuit reported in Fig. 5, which we examined in the previous section, the configuration space determined by Eqs. (27), has dimensions N 8 6 2 and it is
the hyperplane defined by Eqs. (28). The motion of the circuit
operating point on is described by the differential Eqs. (26).
FINAL CONSIDERATIONS
So far, we have considered dynamic circuits consisting of linear and time-invariant capacitors and inductors and generally time-variant and nonlinear resistive one-ports. The analysis made can readily be extended to time-variant linear and/
or nonlinear dynamic one-ports. In such cases, generally, one
has to consider the capacitor charges and the inductor fluxes
as circuit state variables and thus the unknowns of the problem become (nc ni) 2b; nc charges, which we denote with
the vector q (q1, . . ., qnc)T, ni fluxes, which we denote with
the vector (nc1, . . ., ncni)T, and b (nc ni ns)
currents and voltages. The circuit always consists of nc capacitors, ni inductors, and ns resistive one-ports. The circuit equa-

166

NETWORK EQUATIONS

tions also become (nc ni) 2b; the b linearly independent

Kirchhoff Eqs. (21) and (22); the nc characteristic capacitor
equations type [Eq. (5)], which express the voltages of the single capacitors as functions of the respective charges; the ni
characteristic inductor equations type [Eq. (11)], which express the single inductor currents as functions of the respective fluxes; the ns characteristic resistive one-ports type [Eqs.
(1) and (9)], the nc first-order differential equations type [Eq.
(6)], which link the single capacitor currents to the respective
charges; and the ni first-order differential equations type [Eq.
(12)] which link the single inductor voltages to the respective
fluxes. Therefore, the system of circuit equations in these
cases is of the following type:

q
dq
= ic
dt

d
= vi
dt

(43)

q, , v , i ; t)
0 = F (q

(44)

Now algebraic equation system Eq. (44), besides the b Kirchhoff equations and the ns characteristic resistive one-port
equations, also includes the (nc ni) characteristic equations
of circuit dynamic one-ports. In this case too the circuit equation system can be reduced to the canonic form wherein only
the circuit state variables q and appear as unknowns. By
means of algebraic equations (44) it is possible to express the
capacitor currents ic and the inductor voltages vi as functions
of the sole state variables and sources
q, , i , v ; t)
i c = H c (q
q, , i , v; t)
v i = H i (q

(45)

In fact if one considers the charge q and the fluxes as assigned, it is possible to interpret system [Eq. (44)] as a system
of 2b equations in the 2b unknowns i and v. If the solution of
this system exists and is unique, then Hc and Hi are singlevalued functions defined for every value of the state variables
q and . When this is so, the system of state equations

q
dq
q, , i , v ; t)
= H c (q
dt
d
q, , i , v; t)
= H i (q
dt

(46)

is in normal form.
Only if the capacitors are charge controlled and the inductors flux controlled does the state circuit at a given time determine the capacitor voltages vc and the inductor currents ii
univocally at that time, and thus it is possible to define an
associated resistive circuit as for circuits consisting of linear
and time-invariant dynamic one-ports. Otherwise it is evident
that it will never be possible to build a system of global state
equations. If all the capacitors are at least charge controlled
and the inductors at least flux controlled, and the resistive
circuit associated with the dynamic circuit admits one and
only one solution, then it is possible to reduce the systems of
circuit Eqs. (43) and (44) to a system of global state Eqs. (46).
Similar results can naturally be extended to a circuit containing elements with more than two terminals. In such cases
the algebraic equation system in Eq. (44) will also contain the

characteristic equations of resistive and dynamic elements

with several terminals (i.e., controlled sources, gyrators, ideal
transformers, operational amplifiers, mutual inductances,
and transistors), and the associated resistive circuit will contains static n-poles and multiports as well as simple oneports. The more general approach to the problem of the existence of a system of normal form differential equations for
circuit state variables is therefore that of bringing the problem back to the study of the existence and uniqueness of the
solution of the resistive circuit associated with the dynamic
circuit under examination. In this way it is possible to use
everything that is known regarding nonlinear resistive circuits (see, e.g., Ref. 1 and CIRCUIT STABILITY OF DC OPERATING
POINTS). There are many reports in the literature that deal
with the problem of constructing global state equations for
certain classes of circuits without explicitly referring to the
associated resistive circuits. The results of these works are
summarized clearly and fully in Willsons review (3) of 1973.
However, it should be mentioned here that to solve a circuit it is not necessary to determine the state equations in
normal form previously, but it is possible to resolve the algebraic-differential equations of the circuit directly by using, for
example, difference methods (see, for example, Ref. 2). Nonetheless the problem of the existence of normal form state
equations remains a fundamental question. If the circuit does
not admit a system of global state equations the circuit model
would be incomplete and thus could have more than one solution. In such cases numerical methods would still produce a
set of numbers, which, of course, would be meaningless.
As we tried to show, and as is also described in more
detail in other articles (see, for example, CHAOTIC CIRCUIT
BEHAVIOR and TRANSMISSION USING CHAOTIC SYSTEMS), the circuit equations regulate the dynamics of a very rich and
complex model, which is common to other different dynamic
systems. This richness and complexity can be verified experimentally in a very simple way because electric circuits
are generally very easy to build. For these reasons the
research in this field has developed remarkably in recent
years, not only for the intrinsic practical interest but also
at a speculative level.

BIBLIOGRAPHY
1. M. Hasler and J. Neirynck, Nonlinear Circuits, Norwood, MA: Artech House, 1986.
2. L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronic
Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1975.
3. A. N. Willson, Some aspects of the theory of nonlinear networks,
Proc. IEEE, 61: 10921113, 1973.
4. C. A. Desoer and F. F. Wu, Trajectories of nonlinear RLC networks: a geometric approach, IEEE Trans. Circuit Theory, CT-19:
562571, 1972.
Reading List
L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits, New York: McGraw-Hill, 1987.

LUCIANO DE MENNA
GIOVANNI MIANO
Universita` di Napoli Federico II

NETWORK ANALYSIS USING LINEARIZATION

107

(b) linear or nonlinear nondifferential equations which

model the relationships among the variables associated
to the physical phenomena taking place in the devices
and which are referred to as the devices constitutive
laws;
(c) linear first-order differential equations which express
some currents as time derivatives of electric charges
and some voltages as time derivatives of magnetic
fluxes.

NETWORK ANALYSIS USING LINEARIZATION

Generally speaking, the term linearization indicates the substitution of a nonlinear relationship by a linear one which,
according to some criterion, is approximately equivalent to it.
However, the subject considered in this contribution should
not be confused with the concept of piecewise linearization
(see PIECEWISE LINEAR TECHNIQUES). In fact, linearization is intended here to be equivalent to small-signal linearization,
which is a useful procedure in the analysis of physical systems and which is, in particular, widely employed for the
analysis and the design of lumped electronic circuits.
As is well known from Circuit Theory (1 3) (see also NETWORK EQUATIONS), a lumped circuit is a model of a physical
circuit composed by a suitable interconnection of electric and
electronic devices, which applies whenever the size of the
physical circuit is sufficiently smaller than the wavelength of
the electromagnetic field associated with the electric phenomena. Nevertheless, the term circuit is also practically employed to indicate a circuit schematic and any graphical representation of a circuit mathematical model. However, notice
that these two ways of using the same term may be considered equivalent whenever the circuit schematic is completed
by sets of equations representing the models associated with
the device symbols. In the following, the term circuit will be
used with both meanings.
A circuit can thus be considered as composed of (ideal) circuit elements such as resistors, capacitors, inductors, independent voltage and current sources, voltage-controlled voltage sources (VCVS), voltage-controlled current sources
(VCCS), current-controlled voltage sources (CCVS), and current-controlled current sources (CCCS). In fact, the model of
more complex elements such as bipolar junction or MOS transistors can be suitably expressed by using the former elements. Therefore, the mathematical model of a circuit consists of a set of time-dependent variables (voltages, currents,
electric charges, and magnetic fluxes) linked by a set of equations composed of:
(a) Kirchhoff s equations, namely linear algebraic equations deriving either from Kirchhoff s current law
(KCL), stating that the sum of branch currents entering a circuit node is zero, or from Kirchhoff s voltage
law (KVL), stating the vanishing of the sum of branch
voltages along a closed node sequence;

In particular, circuit topology determines equations (a), while

the structure of the constitutive laws (b) may considerably
vary, depending on the kind of the device. Typical examples
of independent branches constitutive laws are V V for an
independent voltage source, I I for an independent current
source, V RI for a linear resistor, and I IS exp (V/VT 1)
for a nonlinear resistor representing a junction diode model.
Examples of controlled branches constitutive laws are Vj
Vi for a linear VCVS, the voltage at branch j being controlled
by the voltage at branch i, or Ij (Vi) for a nonlinear VCCS.
In order to model the storage of energy in the electric and
the magnetic field, reactive branches, namely capacitors and
inductors, have also to be considered. They are described by
constitutive laws of type (b) like LI (which links magnetic
flux and current in a linear inductor) or f(Q, V) 0 (which
links electric charge and voltage in a nonlinear capacitor) together with, respectively, the auxiliary equations of type (c)
V d/dt and I dQ/dt. Although not completely general,
we will preliminarily assume that a circuit may include only
the above-mentioned elements and that the corresponding
constitutive laws link only two variables. These assumptions
will be relaxed in the section entitled A More General Approach to Linearization.
Because the constitutive laws of electronic devices are usually nonlinear, electronic circuits perform, in the most general
case, nonlinear signal transformations. On the other hand,
since such circuits are often employed to achieve linear information processing, like for instance in amplifiers or active filters (4,5), a question naturally arises about the way of obtaining such a goal.
To answer this question, first remember that in any information processing device, the information support is the variation of some physical quantity with respect to a reference
value, which, although potentially variable in time, is often
assumed to be constant [with the exception of the so-called
parametric circuits (6) or parametric amplifiers]. In the following, we shall therefore consider the latter case only, and
we shall define as quiescent values the constant reference values of the physical quantities used to carry information. In
this context, a signal is defined as the difference between the
physical quantity and its quiescent value. An electronic circuit intended for linear signal processing must therefore, first
of all, ensure that, in the absence of signals, all physical
quantities have an appropriate constant value. For this purpose any nontrivial circuit comprises a set of devices which is
specifically devoted to establish suitable quiescent values and
which is usually called a bias circuit. In particular, a bias
circuit includes one or more bias sources which are independent voltage or current sources constant with time.
A set of quiescent values which satisfy the circuit equations when all capacitors have been replaced by open cir-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

108

NETWORK ANALYSIS USING LINEARIZATION

cuits, all inductors have been replaced by short circuits, and

all independent sources have been set to their quiescent
value is called a quiescent operating point or dc operating
point (DCOP). A circuit may possess several DCOPs, some
stable and others unstable, but, in order to allow linear signal
processing, the existence of a stable and usually unique
DCOP must be ensured by a proper design. Moreover, as
shown in the following section, the use of sufficiently small
signals around a DCOP allows us to replace the circuit nonlinear equations by linear ones which are approximately
equivalent to them as far as the relationships among small
signals are concerned. These linear equations can be interpreted as referring to a small-signal equivalent circuit composed
by linear elements only, which may then be analyzed by using
the well-known powerful techniques applicable to linear circuits (3). In particular, linear differential equations theory
from Calculus or Laplace transform-based methods can be
used for transient analyses, while complex numbers representation of sinusoidal functions or Fourier transform can be
used for alternating current (ac) analyses and lead to very
useful concepts as driving-point immittances and transfer
functions (see LINEAR SYSTEMS).
Finally, it is important to stress that linearization is additionally involved in other important topics such as stability
analysis of a DCOP, sensitivity analysis, and determining the
DCOP(s) of a circuit. In fact, this amounts to solving a nonlinear system of equations, which is often numerically accomplished by using circuit analysis programs like SPICE (7,8).
The numerical algorithm typically employed is iterative and
gradually converges toward the solution by repeatedly solving
linear equations systems obtained by suitable linearizations
of the circuit equations.
A SIMPLE APPROACH TO LINEARIZATION
Consider a circuit element characterized by the constitutive
law
Y = f (X )

In other terms, the problem is to determine whether a best

choice exists between all the possible linear functions (3) approximating the device constitutive law (1) in a neighborhood
of X0. Consider a small displacement x of X with respect to
X0. Since f is differentiable, the dependent variable value corresponding to X X0 x can be expressed as
Y = f (X ) = f (X0 ) +

#
d f ##
x + O(|x|2 )
dX #0

(5)

where the subscript 0 in df /dX means that this quantity must

be evaluated at X X0. By employing Eqs. (3) and (5), one
obtains that Eq. (4) is satisfied if and only if
p=

#
d f ##
dX #0

(6)

On the basis of the above considerations, the linearization

procedure of a nonlinear circuit may be summarized as
follows:
1. The DCOP of the circuit, and therefore of all its devices,
is suitably chosen during the design or computed during
an analysis step.
2. For each nonlinear device, the constitutive law (1) is
substituted by Eq. (3) satisfying Eq. (6). This corresponds to changing each element into its small-signal
equivalent device whose constitutive law can be recast
in terms of small signals only as
y = px

(7)

The parameter p is called differential parameter and is

indicated by several different terms according to the
physical dimensions of the variables X and Y and to the
nature of the circuit element to which it refers, as
shown in Table 1.

(1)

with p . Since from Eq. (2) it follows that f(X) l(X) is at

least first-order infinitesimal for X X0, one could wonder if
a suitable choice of p allows the above difference to be infinitesimal of order greater than one with X X0, namely

It is important to stress that the whole linearization procedure applies whenever the signal x X X0 (and hence y
Y Y0) is small in the sense that it can be considered as
infinitesimal without introducing unacceptable errors. In order to verify this condition, circuit topology, devices characteristics, and DCOP have to be considered, as well as the maximum tolerable distortion in the circuit. Typically, this
amounts to subsequently performing a suitable (nonlinear)
distortion analysis (9).
Figure 1 shows a simple geometrical interpretation of the
linearization process. Given the diagram of the function Y
f(X) and the operating point P0 (X0, Y0), then the diagram
of Y l(X) with p chosen according to Eq. (6) is represented
by the straight line tangent to f in P0. If the coordinate axes
are shifted so that the new origin coincides with P0, then the
tangent equation in the new reference system is expressed by
Eq. (7).
It is worthwhile to note that the above considerations remain valid, under suitable assumptions, even when the circuit element constitutive law is provided in implicit form as

f (X ) l(X ) = O(|X X0 |2 ) for X X0

g(X , Y ) = 0

where f : is a differentiable function. The two variables

X and Y may stand, for instance, for the voltage across a voltage-controlled resistor and the current flowing in it, or for the
electric charge of a charge-controlled capacitor and the voltage across it, or even for the input and output voltages of
an amplifier.
Let X0 be a reference value of the independent variable and
consider the class of first-degree polynomials Y l(X) such
that
l(X0 ) = f (X0 ) = Y0

(2)

l(X ) = f (X0 ) + p(X X0 )

(3)

namely

(4)

(8)

NETWORK ANALYSIS USING LINEARIZATION

109

Table 1. Different Terms Used to Indicate the Differential

Parameter p in Eq. (7), Depending on the Physical Dimension
of X and Y in the Circuit Element Constitutive Law Expressed
by Eq. (1)
Circuit element
Resistor
Resistor
Capacitor
Inductor
VCVS
VCCS
CCVS
CCCS

X, x

Y, y

Current
Voltage
Voltage
Current
Voltage
Voltage
Current
Current

Voltage
Current
Charge
Magnetic flux
Voltage
Current
Voltage
Current

Differential resistance
Differential conductance
Differential capacitance
Differential inductance
Voltage gain
Transconductance
Transresistance
Current gain

with g : 2 . In fact, consider a DCOP P0 satisfying Eq. (8)

and suppose that a neighborhood U of P0 exists such that g is
differentiable in U with nonvanishing partial derivative
g/Y0 in P0. Then, by the implicit function theorem (10), a
neighborhood V of X0 and a differentiable function f : V
exist such that g(X, f(X)) 0 and df /dX (g/X)/(g/Y).
In this way the previously considered procedure still holds in
V with p (g/X)0 /(g/Y)0.

in P0 is given by
rd =

#
dV ##
nVT
=
dI #0
I0 + IS

and the small signals v V V0, i I I0 are linked

by the simple relationship
v = rd i

Examples
1. Consider a pn junction diode whose dc voltage
current relationship in the forward bias region (I 0)
is expressed as (11)



I
V = nVT ln 1 +
IS
where IS is the reverse saturation current, VT is the
thermal voltage, and n the emission coefficient. If one
indicates with P0 (I0, V0 nVT ln (1 I0 /IS)) the diode
operating point, the differential resistance of the diode

Y = f (X)
Y = Y 0 + p ( X X 0)

P0
x
X0

"




VBE
IC = IS exp
1 ,
VT

Figure 1. Geometrical interpretation of the basic linearization procedure: in a small neighborhood of a DCOP P0, the curve Y f(X) is
approximated by its tangent straight line Y Y0 p(X X0) whose
slope is p (df /dX)0. The small signals x and y px are measured
in the coordinate system with origin in P0.

IB =

"




IS
VBE
exp
1
F
VT

where IC and IB are the transistor collector and base

currents, IS is the transport saturation current, VBE is
the base-emitter voltage, and F is the large signal forward current gain of the common emitter configuration.
The associated small-signal relationships are expressed by
iC = gm vBE ,

Y0

Since the last equation represents Ohms law, as far as

dc, small-signal relationships are concerned, the diode
can be substituted by its small-signal equivalent oneport that is, a linear resistor whose resistance is rd.
2. Figure 2(a) shows a two-port representing a bipolar
junction transistor (BJT), whose elementary model
when operating in the forward normal region can be formulated as (11)

iB =

vBE
rBE

(9)

where gm IC /VBE0 (IC0 IS)/VT is the BJT transconductance and where rBE F /gm. By using a VCCS,
Eqs. (9) can be considered as referring to the small-signal equivalent two-port shown in Fig. 2(b).
3. As a last example, consider a reverse-biased p/n junction diode. If one neglects the reverse current, its model
reduces to a nonlinear capacitor having a voltage
charge relationship given by


1m
V
Q = Q0 1 + R
VJ

110

NETWORK ANALYSIS USING LINEARIZATION

IB
Figure 2. Basic BJT model, where
f(VBE) IS[exp (VBE /VT) 1]: (a) A linearization procedure applied to (a) gives rise
to the linear constitutive laws of the small
signal equivalent two-port represented in
(b).

VBE

IC

f(VBE)
F

VBE

rBE

where VR0 is the dc operating voltage and Cj0 (1

m)Q0 /VJ. The small-signal charge q Q Q0 and the
small-signal voltage vR VR VR0 are related by q
CjvR.
The material developed so far shows that circuit elements
characterized by means of two-variable constitutive laws have
linear counterparts which are described in terms of the corresponding two-variable increments. Moreover, substituting increments for variables also in Kirchhoff s and auxiliary differential equations yields a linear mathematical model whose
graphical representations are called small-signal equivalent
circuits of the original nonlinear circuit.

A MORE GENERAL APPROACH TO LINEARIZATION

Consider a lumped circuit and express Kirchhoff s equations
in vector form as (1,2)
(10)

where A and B are matrices whose elements are 0, 1, and

1 and whose structure depends on the network topology, I
is the nb-dimensional vector of branch currents, and V is the
nb-dimensional vector of branch voltages. If the circuits possess nc capacitor and nl inductors, let Vc (Vl) and Ic (Il) be the
nc(nl)-dimensional vectors of voltages and currents at capacitive (inductive) branches and let Vr and Ir be the voltage and
current vectors for the nr nb nc nl resistive branches,
which include also dependent and independent sources. Then,
by suitably ordering the vector components, one has V
[VtcVtlVtr]t and I [ItcItlItr]t, where t denotes transposition.
The nb (generally nonlinear) constitutive laws of the circuit
elements may be expressed in the form
Fc (Qc , Vc ) = 0

(11)

 l , Il ) = 0
Fl (

(12)

Fr (Vr , Ir , E) = 0

(13)

gm VBE

VCE

(b)

where E is the vector of circuit excitations, while Qc and t

are the vectors of capacitors charges and inductors fluxes, respectively, which also satisfy the auxiliary differential equations
dQc
= Ic ,
dt

#
Cj0
dQ ##
Cj =
=

m
#
dVR 0
V
1 + R0
VJ

BV = 0

VCE

iC

(a)

where VR is the reverse voltage across the junction, Q0

is the charge at VR 0, VJ is the built-in potential, and
m 1 is the junction grading coefficient (11). The smallsignal equivalent one-port is readily found to be a linear
capacitor whose capacitance is

AI = 0,

f(VBE)

iB

l
d
= Vl
dt

(14)

Notice also that with the above notation, a DCOP is defined

as a set of time-independent variables (V0, I0, Qc0, l0) such
that Eqs. (10) (13) are satisfied with the dc values E0 replacing the original excitations E(t) and with Ic 0 and Vl 0.
The small-signal linearization procedure relies on assuming
the existence of the total differential of the functions Fc, Fl,
Fr in Eqs. (11) (13) and on substituting, for each vector X, its
differential dX by the small increment x, while the linear
equations (10) and (14) hold for x as for X. By applying this
procedure one gets
Ai = 0,
Bv = 0
#
#
Fc ##
Fc ##
q
+
vc = 0
c
Qc #0
Vc #0
#
#
Fl ##
Fl ##

+
i =0
l
 l #0

Il #0 l
#
#
#
Fr ##
Fr ##
Fr ##
v
+
i
+
e=0
r
r
Vr #0
Ir #0
E #0

(15)
(16)
(17)
(18)

dqc
= ic
dt

(19)

l
d
= vl
dt

(20)

where Fc /Qc0, Fc /Vc0, . . ., Fr /E0 are the Jacoby matrices of the functions Fc, . . ., Fr with respect to Qc, Vc, . . .,
E at the DCOP.
Small-Signal Equivalent Circuits
A small-signal equivalent circuit can be defined as a graphical
representation of Eqs. (15) (20) constructed by means of linear ideal circuit components which, in addition to those considered in the section entitled A Simple Approach to Linearization, may include, for instance, dependent voltage and
current sources controlled by any number of variables. Moreover, if the derivative with respect to time of Eqs. (16) and
(17) is considered and Eqs. (19) and (20) are used, dependent
branches controlled by time derivatives of voltages and currents may also appear. By simple inspection of Eqs. (10) (14)
and (15) (20) it can be observed that, since Kirchhoff s equations sets (10) and (15) have an identical structure, a smallsignal equivalent circuit having the same topology as the orig-

NETWORK ANALYSIS USING LINEARIZATION

rB'C

rBB'

CB'C

B'

vB'E
vBE

CB'E

rB'E

vCE
gmbvB'E rCE

E
Figure 3. Hybrid- equivalent circuit of a BJT which is widely used
for small-signal analysis of bipolar and BiCMOS circuits.

inal nonlinear one may be obtained by substituting small-signal increments for the corresponding circuit variables and a
linear component for each corresponding nonlinear one. In
practice, however, the topological correspondence between the
nonlinear and the linearized circuit models is often not perfect. This is due, on one hand, to the common practice of rearranging the equations to simplify the associated equivalent
circuit or, conversely, of performing transformations which
modify the topology of the small-signal circuit to simplify the
associated equations and, on the other hand, to the presence
of bias sources. In fact, a voltage bias source is, by its very
definition, an independent voltage source whose value is unaffected by the signals. Therefore, its small-signal equivalent
one-port is an independent voltage source of zero voltage
that is, a short-circuit. Dually, the small-signal equivalent
one-port of a current bias source is an open-circuit. So, the
small signal equivalent sources corresponding to bias sources
do not explicitly appear in equivalent circuits.
As simple but important examples, commonly used equivalent circuits of a bipolar junction transistor operating in normal region and of a MOS field-effect transistor are reported
in Figs. 3 and 4, respectively (11,12). In addition to the components in Fig. 2(b), the well-known hybrid- equivalent circuit for a BJT shown in Fig. 3 accounts for the base resistance (rBB), the junction capacitances (CBE and CBC), an
internal resistive feedback (rBC), and the Early effect (rCE). Notice that in a BJT nonlinear model the Early effect is accounted for by a dependence of the transport current on the
base-collector voltage and the corresponding equivalent circuit should have a current source controlled by vBC connected

CGD

v GS

gd
CGS

CGB

gmvB'E gmbvB'E

vDS
CDB

S
CSB

vBS

B
Figure 4. Small-signal equivalent circuit of a MOSFET which is
widely employed for small-signal analysis of MOS circuits.

111

between the collector node and the emitter node. However,

simple algebraic transformations allow us to use vBE and vCE
as controlling voltages so that the considered VCCS may be
equivalently replaced by adding a resistor of resistance rCE
and by considering a slightly different expression for the
transconductance (11). In this way one obtains a circuit characterized by a different topology, but described by an equivalent equations set.
Finally, it should also be noted that the knowledge of a
nonlinear model is not compulsory in order to obtain a smallsignal equivalent circuit. In fact, this one can also arise, especially when high-frequency behavior is of interest, from an
empirical or semiempirical procedure, namely by using a set
of experimental values possibly integrated by physical considerations. For instance, let a three-terminal model of an electronic device like a BJT be represented as a two-port having
one of the terminals shared by the ports. Its small-signal ac
behavior around a fixed DCOP and at a fixed frequency can
be described by the results of a suitable set of measurements
which allow the four complex parameters of the 2 2 admittance or scattering matrix to be identified (see MULTIPOLE AND
MULTIPORT ANALYSIS). By repeating the measurements at different frequencies, an approximate characterization of the device in a limited frequency range may be obtained. For an
ac analysis of the circuit, one could employ look-up tables or
functions obtained by interpolating the measured data, but
computational efficiency may often be improved if a linear
two-port circuit having the same matrix and a relatively
small number of parameters, compared to the data set, can
be devised. This corresponds to considering a small-signal
equivalent circuit of the device in the considered frequency
range.
While a nonlinear model would still be necessary for dc
and for (nonlinear) transient analyses, this empirically identified linear equivalent circuit does not have to be strictly related to it; so more so as the desired approximations for the
different types of analyses may be somewhat different, and
the ease of linear analyses allows us to use equivalent circuits
with many more parameters than desirable in a nonlinear
model. Therefore, it may be more practical to consider both
nonlinear and linear models as independently associated to
the physical device or circuit, with not too tight a relationship
each to the other.
An Example of Small-Signal ac Analysis
As is well known from basic Circuit Theory (3), a stable linear
circuit excited by a sinusoidal signal reaches, after a transient
phase, a steady state characterized by sinusoidal signals having the same frequency, but in general different amplitudes
and nonzero phase shifts, with respect to the excitation.
These signals represent the circuit ac response, whose derivation is defined as ac analysis. In nonlinear circuits with ac
sources of a given frequency, the same effect arises in practice
when excitation amplitudes are small enough to obtain a negligibly nonlinear response of circuit elements in a neighborhood of the bias point. In this case one has the so-called
small-signal ac response. Hence, performing a small-signal ac
analysis requires the solution in the frequency domain of the
small-signal equivalent circuit equations.
As an application example, consider the MOSFET common
source amplifier M1 with active load M2 shown in Fig. 5. The

112

NETWORK ANALYSIS USING LINEARIZATION

where Gs 1/Rs and where VGS1, Vi and V0 indicate the Fourier transform of the voltages vGS1(t), vi(t) and v0(t), respectively. By solving Eqs. (21) and (22) for Vi( j) and V0( j), one
easily obtains

VDD

M2

M3

C
1 j GD1
V0 ( j)
gm1
= Av0
,
Av ( j) =
Vi ( j)
1 + j 2

Voo + vo(t)
Ib

Rs

(23)

where Av0 gm1 /GL is the dc voltage gain and

CL

M1

Rs
[C (C
+ Cg ) + CgCGD1 ]
GL L GD1
Rs
=
[G (C
+ Cg ) + Gs (CL + CGD1 ) + gm1CGD1 ]
GL L GD1
=

v i(t)
Vio

Figure 5. A MOSFET common source amplifier with active load. The

transistor M3 and the current bias source Ib are employed to bias the
gate of transistor M2 to a suitable voltage.

circuit including the supply voltage generator VDD, the transistor M3, and the constant current source Ib is used to bias
the gate of M2 to a suitable voltage, thus establishing, together with the bias source Vio, the circuit DCOP. Moreover,
vi(t) represents a small-signal input source with internal resistance Rs, and CL is a load capacitance. Substituting the
equivalent circuit shown in Fig. 4 for M1 and M2 yields the
small-signal equivalent circuit reported in Fig. 6, where Cg
CGS1 CGB1, CL CL CDB1 CDB2 CGD2, and GL gd1
gd2. In order to characterize the circuit behavior, a very meaningful quantity to be computed is the amplifier voltage gain,
namely the transfer function Av V0 /Vi, where V0 and Vi represent the Laplace or Fourier transform of the small signals
v0(t) and vi(t). By applying the KCL to the nodes M and N of
the circuit in Fig. 6, one gets
(VGS1 Vi )GS + jCgVGS1 + jCGD1 (VGS1 V0 ) = 0

(21)

jCGD1 (V0 VGS1 ) + gm1VGS1 + V0 (GL + jCL ) = 0

(22)

Rs

Vi

Cg

CGD1

Vo

VGS1
gm1V GS1

GL

CL

Figure 6. Small-signal equivalent circuit of the amplifier shown in

Fig. 5, obtained by substituting the equivalent circuit of Fig. 4 for
transistors M1 and M2.

The voltage gain (23) is then characterized by a real positive

zero at the angular frequency z gm1 /CGD1 and by two real
negative poles corresponding to angular frequencies p1 and
p2. By assuming, as verified in practice, that p1 p2, Eq.
(23) can be recast in a more useful form as

Av ( j) Av0

1 j

2
1+ j

p1
p1 p2

(24)

where p1 GL /CL CGD1 RsGL[Cg CGD1(1 Av0)] and

p2 [GL(CGD1 Cg) Gs(CL CGD1) gm1CGD1]/[CL(CGD1
Cg) CgCGD1]. Since the voltage gain (24) is a complex function, it is usually represented in terms of magnitude response
Av( j) and phase response ( j) arg Av( j), which are
commonly represented as Bode diagrams and from which several meaningful quantities, like the amplifier gain-bandwidth
product or phase margin, can be computed (4,5) (see also SIGNAL AMPLIFIERS).
Linearization and Sensitivity
By recalling that the (relative, small-change) sensitivity of a
function H with respect to a parameter is defined as (1)
SH
=

H/H
H
=
H
/

and observing that its expression may be interpreted as the

ratio of the fractional change in H due to a unit fractional
change in provided that all variations are sufficiently small,
it is not surprising that sensitivity can be related to the concepts of linearization and small-signal equivalent circuit. This
quantity is of course a valuable information for any electronic
circuit designer. For instance, if the output voltage of a filter
is very sensitive to the resistance value of a resistor, a circuit
VLSI implementation would probably fail to meet one or more
constraints, due to the unavoidable spreading introduced by
the devices physical realization or to temperature changes
and aging.
In the following, we restrict our considerations to the case
of a purely resistive circuit, which is formally simpler because
its model includes only nondifferential equations (for the

NETWORK ANALYSIS USING LINEARIZATION

iC

iB

VCC

113

vBE

RC

rBE

ICo iS
ISo F

F iB

Vo

vi

RC

vo

REo
Vi

RE

(a)

IEorE

(b)

Figure 7. Sensitivity calculations may be included in a general linearization procedure. Parameters changes in the circuit (a) are accounted
for in the small-signal equivalent circuit (b) by suitable independent sources.

more general case of nonlinear reactive circuits see Ref. 13).

In this case, the circuit is described by the system
AIr = 0,

BVr = 0,

Fr (Vr , Ir , E,  ) = 0

(25)

where, with respect to Eq. (13), the dependence on the parameters vector has been accounted for. By applying a linearization procedure to Eqs. (25), one obtains

Air = 0,
Bvr = 0,
#
#
#
#
Fr ##
Fr ##
Fr ##
Fr ##
v
+
i
+
e
+
=0
r
r
 #0
Vr #0
Ir #0
E #0

where indicates the small changes parameters vector with
respect to the nominal parameter values 0. Note that only
vr and ir are unknown variables and therefore may be dealt
with as e; that is, the effects of small parameter changes may
be accounted for by suitable independent sources. Once vr, ir
are expressed as functions of e and , any desired sensitivity
is readily obtained.
As a simple example, consider the amplifier stage of Fig.
7(a) and suppose that small spreads or changes of the BJT
transport saturation current IS and of the resistance RE must
be considered. Assume that IS has nominal value IS0 and variation iS, while RE has nominal value RE0 and variation rE. The
equations describing the circuit behavior may be written as

Vi = VBE + RE IE
VCC = RC IC + VCE + RE IE
VCE = VCB + VBE
Vo = VCC RC IC

$
%V &
'
IC = IS exp VBE 1
T

IE = IC + IB
$
%V &
'
I
IB = S exp VBE 1
F

The corresponding linearized equations may be recast in the

form

vi = vBE + RE0 iE + IE0 rE

i C = F i B

0 = RC iC + vCE + RE0 iE + IE0 rE

iE = iC + iB

vCE = vCB + vBE

iB =

v BE
r BE

I C0
F I S0 iS

vo = RC iC
and may be interpreted by the small-signal equivalent circuit
of Fig. 7(b), where the changes of RE and of IS are accounted
for by a voltage source IE0rE and a current source (IC0 /FIS0)iS,
respectively. In this way, sensitivities such as
#
IS0 v0 ##
R I
rBE
V0
SI =
= C C0
V00 iS # v i =0
V00 rBE + RE0 (F + 1)
S
r E =0

can then be computed from the equivalent circuit by means

of standard linear circuit analysis.
BIBLIOGRAPHY
1. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.
2. M. Hasler and J. Neirynck, Nonlinear Circuits, Norwood, MA:
Artech House, 1986.
3. C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York:
McGraw-Hill, 1969.
4. K. R. Laker and W. M. C. Sansen, Design of Analog Integrated
Circuits and Systems, New York: McGraw-Hill, 1994.
5. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits
for Signal Processing, New York: Wiley, 1986.
6. D. G. Fink and D. Christiansen, Electronics Engineers Handbook,
New York: McGraw-Hill, 1982.

114

NETWORK COMPUTING

7. P. W. Tuinenga, SPICE: A Guide to Circuit Simulation & Analysis

Using PSpice, Englewood Cliffs, NJ: Prentice Hall, 1988.
8. W. Banzhaf, Computer-Aided Circuit Analysis Using SPICE, Englewood Cliffs, NJ: Prentice Hall, 1989.
9. J. Millman and A. Grabel, Microelectronics, New York: McGrawHill, 1987.
10. W. Flemming, Functions of Several Variables, New York:
Springer, 1977.
11. R. S. Muller and T. I. Kamins, Device Electronics for Integrated
Circuits, New York: Wiley, 1986.
12. Y. P. Tsividis, The MOS Transistor, New York: McGraw-Hill,
1988.
13. J. Ogrodzki, Circuit Simulation Methods and Algorithms, Boca
Raton, FL: CRC Press, 1994.

SERGIO GRAFFI
GIANLUCA SETTI
Universita` di Bologna

NETWORK ANALYZERS. See STANDING WAVE METERS

AND NETWORK ANALYZERS.

NETWORK AVAILABILITY. See NETWORK RELIABILITY

AND FAULT-TOLERANCE.

408

CIRCUIT STABILITY OF DC OPERATING POINTS

CIRCUIT STABILITY OF DC OPERATING POINTS

To some readers it might seem incongruous that we refer to

the notion of stability in the context of dc circuits, but that is
exactly what this article is about. Numerous observations
have been made, dating back at least to the turn of the century (1,2), that stability related properties seem to be embodied in dc circuits. In 1965 Stern (3) wrote:

+ 5V

Only during the past few years has the issue been formulated in a manner that permits adequate insight into its character such that a rigorous theory has begun to emerge. A major stride forward was announced in (4), and subsequent work
has yielded further results. The problem of assessing the stability of each operating point of a nonlinear dc circuit is still
not completely solved. Much basic understanding has been
attained, however, and this article is intended as a survey of
that knowledge. We begin with several important definitions.

FUNDAMENTAL DEFINITIONS
Equilibrium Points vs. Operating Points
We will first make a clear distinction between a circuits equilibrium point and its operating point. In any dynamic system
described by a set of differential equations
dx
= f (x)
dt

(1)

where x Rn and f : Rn Rn, the set of equilibrium (or singular) points is defined to be x : f(x) 0. When we refer to an
equilibrium point it is within this context of a given dynamic
system. When the dynamic system is an electric circuit the
derivative terms in Eq. (1) will necessarily arise from the
presence of capacitors and inductors.
A natural starting point when analyzing a dc circuit is to
solve for its operating point. This entails ignoring all capacitors and inductors while solving for the voltages and currents
across all branches of the static elements (e.g., transistors
and resistors). In such an analysis there are no state variables defined, hence the concept of an equilibrium point has
no meaning. This set of dc branch voltages and currents constitutes the operating point, defined independently of any dynamic system; in others words, an operating point is independent of the vaue or location of any capacitor or inductor in
the circuit.
As a simple example, the circuit in Fig. 1(a) has its equilibrium point given by vc 10 V, while the circuit in Fig. 1(b)
has its equilibrium point given by iL 5 A. Although these
equilibrium points are different, since they correspond to different dynamic systems [indeed, the equilibrium point of Fig.
1(a) is unstable, while the Fig. 1(b) circuit is stable], they both
correspond to the same dc operating point, defined by the

+
vc

5V

(a)

(b)

5A
Mathematically speaking, there is no basis for discussing stability
in resistive networks, since they are not described by differential
equations. Physically, however, it is well known that in a resistive
network with multiple states of equilibrium some of these states
are usually unstable. Thus some dynamic mechanism of instability must exist in the network.

iL

+ 5 V

5 A
1

+ 5V

5A
+
10 V

(c)
Figure 1. Illustration of equilibrium point versus operating point.

branch voltages and currents of the static elements shown in

Fig. 1(c).
For circuits having isolated (but perhaps multiple) equilibrium points there is a unique correspondence from any equilibrium point to an operating point. In fact, the two terms
are often used interchangeably in the literature and many
textbooks, since there is usually no need for the distinction.
Throughout this article, however, we will maintain the distinction between an equilibrium point and an operating point,
since this is crucial to the discussion of the concepts presented.
Stability of Equilibrium Points and Operating Points
It is well known what is meant by the stability of an equilibrium point possessed by an autonomous circuit. (An autonomous circuit has no time-varying independent sources, only
dc sources.) A general definition can be formulated as follows (5):
Definition 1. An equilibrium point x* is said to be stable if,
for each 0, there exists a 0 such that x(t) x* ,
for all t t0, whenever x(t0) x* . Otherwise, the equilibrium point is said to be unstable.
There are many methods to ascertain whether a given
equilibrium point is stable or unstable; two well-known methods are Lyapunovs first and second methods (6). We will use
Lyapunovs first method, which entails linearizing the circuit
around the equilibrium point in question and then examining
the natural frequencies there. If all natural frequencies are
located in the open left half-plane then the equilibrium point
is stable. If at least one natural frequency is in the open right
half-plane then the equilibrium point is unstable.
We now turn our attention from equilibrium points to operating points, and we make the following operating point
stability definitions; notice that these definitions do not depend on the location or value of any capacitors or inductors
(except that we, of course, assume they are positive since this
is how they occur in nature).
Definition 2. A dc circuits operating point is said to be potentially stable if, by inserting some set of positive-valued

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CIRCUIT STABILITY OF DC OPERATING POINTS

shunt capacitors and series inductors into the circuit, the corresponding equilibrium point of the resulting dynamic circuit
is stable, even in the presence of parasitic capacitors and inductors.
In the above definition we use the term parasitic to mean
arbitrarily small values of capacitors and inductors that are,
as in real circuits, placed anywhere throughout the circuit. In
the next section we will give an example illustrating why such
elements must be mentioned in this definition.
Definition 3. An operating point that is not potentially stable is said to be unstable.
We emphasize that if an equilibrium point is unstable this
means with respect to a particular set of capacitor and inductor values. If an operating point is unstable, this means it is
unstable for any set of positive-valued capacitors or inductors.
Since there is an infinite number of possible dynamic circuits
(and, therefore, an infinite number of resulting equilibrium
points) that could be constructed from a given operating
point, the above definitions are unsuitable for directly testing
for an operating points instability. A more practical method
is required. Such a method is given in the next section.
HOW TO IDENTIFY UNSTABLE DC OPERATING POINTS
Consider the linear dynamic circuit shown in Fig. 2(a). We
presume that this has come from the linearization, around a
particular operating point, of some nonlinear circuit. The linear n-port N contains only positive-valued resistors. Ports 1

Ck + 1

yk+1

y1

+
xk+1

+
x1

.
.
.

Outside
ports
Ln

xn

a 1x i

.
.
.

xk

+
yn

+
yk

C1

Dependent
source ports

Lk
+

a kx j

(a)
y1
+
x1

a 1x i

.
.
.

xk
+
yk
N

.
.
.

through k, called dependent-source ports, are each terminated

by either a dependent current source in parallel with a positive-valued capacitor or a dependent voltage source in series
with a positive-valued inductor. A controlling signal, shown
in Fig. 2(a) as xi or xj, is the voltage across a dependent current source or the current through a dependent voltage
source. The value of a dependent source gain ai may be zero.
(This is useful when a port i corresponds to an open-circuit
voltage or a short-circuit current that is used as a controlling
signal, but is not connected to an actual, nonzero dependent
source.) Ports k 1 through n, called outside ports, are terminated with positive-valued capacitors and inductors, called
outside capacitors and outside inductors, as shown. These
model other capacitors and inductors that may be present in
the linearized circuit.
The class of nonlinear circuits from which this linear circuit can be derived is quite general. We assume that all capacitors and inductors in the original circuit are uncoupled
and have strictly monotone-increasing charge-voltage or fluxcurrent characterizations. We assume that the resistive elements (e.g., resistors and transistors) can be expressed in a
very general representation (7). In general, any circuit consisting of positive-valued resistors, diodes, transistors of any
kind, and capacitors and inductors with strictly monotone-increasing charge-voltage or flux-current characteristics, respectively, linearized at a given operating point, can be modeled by the circuit in Fig. 2(a).
We also assume that no set of dependent current (voltage)
source ports forms a cut set (loop) by itself or with any set of
outside capacitors (inductors). Otherwise the circuit in Fig.
2(b), derived from Fig. 2(a), when analyzed at dc, could be illposed, in that it could contain cut sets of dependent current
sources and/or loops of dependent voltage sources.
In addition, let us assume (these assumptions can be relaxed; see the appendix of Ref. 4) that there exist no cut sets
(loops) made up exclusively of outside capacitors (inductors).
Then the resistive n-port N in Fig. 2(a) can be characterized
(8) at its ports by



QA QB
yd
xd
+
=0
(2)
QC QD
yo
xo




where the vector x consists of the usual state variables (capacitor voltages and inductor currents), and is partitioned
into xd, a vector whose components are the state variables
appearing at the dependent source ports, and xo, a vector of
state variables appearing at the outside ports. Vectors yd and
yo are the respective port-variable complements of xd and xo.
The n n matrix Q, shown partitioned in Eq. (2), has a nonnegative determinant, since N contains only passive reciprocal elements.
The port constraints of the circuit in Fig. 2(a) are given by

y 

yd
yo

a kx j

(b)
Figure 2. Generalized linear circuits.

409

d
=K
dt

x 
xd
xo

AA
+
0




0
xd
0
xo

(3)

where K is a diagonal n n matrix whose diagonal elements

specify the positive linearized capacitor and inductor values.
Matrix A, shown partitioned in Eq. (3), is the n n matrix
whose elements specify the appropriate dependent source coefficients. Notice that its entries are nonzero only in the upper

410

CIRCUIT STABILITY OF DC OPERATING POINTS

left-hand k k submatrix, since all controlling variables and

dependent sources are, by assumption, confined to ports 1,
. . ., k. Combining Eq. (2) and Eq. (3) we have the dynamic
equations of the circuit:
d
QK
dt


xd
xo



x
+ (QA + In ) d
xo

=0

(4)

where In denotes the n n identity matrix. From this, the

natural frequencies of the circuit can be found; they are the
values of s that satisfy
det[sQK + (QA + In )] = 0

(5)

We define the constant as follows:

Theorem 1. Given an operating point of a circuit which can

be linearized as in Fig. 2(a) with its dynamic equations written as in Eq. (4), if 0 then the operating point is unstable.
Remark. Notice that QA and AA, from Eqs. (2) and (3), are
associated with the dc equations of the circuit that results
when yo is set to zerothat is, when all outside capacitors
are replaced with open circuits and all outside inductors are
replaced with short circuits. Thus, can be derived from the
linearized operating point of the dc circuit; in order to use
Theorem 1 for any given circuit, we need only define a port for
each dependent source and ignore the presence of any outside
capacitors and inductors. This, of course, is consistent with
the definition of an unstable operating point.
The proof of Theorem 1 can be found in Ref. 4.
We will now give an example of the use of Theorem 1. Consider the circuits in Fig. 3(a) and Fig. 3(b). These circuits are
used to generate a current that is independent of the supply
voltage.

det(QA AA + Ik )
We can now state the following theorem:

ib

e1 10 V
100
2
M1

100
2

3.51 k

M2
e3

I1

I2

Q4

Q3

+
vb

ia

e2

ic

dc node voltages
e1 = 10
e2 = 9.01
e3 = 0.691
e4 = 0.041

285 Sva

id

+
vc

1.57 mS vd

e4

+
va

+
vd

64 k

641 k

R = 1 k
1 k

(a)

(a)

e1 10 V

ia

e2

100
2
M1

M2
e3

I1
Q3
5

+
va

100
2

I2

Q4
1

dc node
e1 =
e2 =
e3 =
e4 =

voltages
10
9.01
0.693
0.042

ib
292 mS vb
ic

602 k

62 k

+
vc

+
vb

3.42 k
id
+
vd

e4

R = 1 k
1 k

(b)

(b)
Figure 3. Two versions of a current reference circuit.

1.61 mSvc

CIRCUIT STABILITY OF DC OPERATING POINTS

The operation of these circuits is explained as follows: A

pair of currents I1 and I2 are set up subject to two sets of
constraints. The first constraint, imposed by the current mirror made up of M1 and M2, sets I1 I2. The second constraint
is a consequence of the combination of Q3, Q4, and R and is
given by
I1 = I2 =

Vt
ln 5
1000

where Vt is a parameter proportional to absolute temperature,

approximately 26 mV at room temperature. Details of this
circuits operation can be found in Ref. 9. Both Fig. 3 circuits
realize the desired operating point at which I1 I2 42 A,
as is verified by the results of the SPICE dc operating point
analysis shown along with the circuits. However, this operating point is unobservable in one of these circuits. We will
use Theorem 1 to identify which one. The Fig. 3(a) and Fig.
3(b) circuits are shown, linearized at the operating point in
question, in Fig. 3(a) and Fig. 3(b), respectively. These linear
circuits are presented in the form of four-ports.
For the Fig. 3(a) circuit we can write the following equation in the form of Eq. (2):

3510
0
3510
0

0
635
10
625

3510
10
4495
975

0
625
975
1600



ia
ib
ic
id

va
vb
vc
vd

=0
(6)

For the Fig. 3(b) circuit we can write:

1562
0
1562
0

1562
0
1562
0

0
3420
0
3420

0
3420
0
3420



ia
ib
ic
id

va
vb
vc
vd

=0

411

Since 0 for the Fig. 3(b) circuit, the operating point indicated in the Fig. 3(b) circuit must be unstable.
Recall that Theorem 1 specifies a sufficient condition for
operating point instability, but not a necessary one. The
above analysis does not prove that the operating point shown
in Fig. 3(a) is potentially stable, but it can be verified that
this is the case simply by building this circuit and observing
the dc node voltages shown in Fig. 3(a).
The instability criterion 0 given in Theorem 1 has been
incorporated into the dc operating point analysis of SPICE
(10). A discussion of that topic will be given in the section
titled Identifying Unstable Operating Points Using SPICE.
MODELING REQUIREMENTS FOR REACTIVE ELEMENTS
How capacitors and inductors are appropriately modeled was
addressed in another result, which was derived as a by-product of the development of the stability criterion. In particular,
Theorem 2 in (4) states that any dependent current (voltage)
source must have a capacitor (inductor) placed in parallel (series) with it. This requirement holds even if the value of a
dependent source gain is zero. (Such zero-valued dependent
sources are needed when a port corresponds to an open-circuit
voltage or a short-circuit current that is used as a controlling
signal but is not directly connected to an actual, nonzero dependent source.) This result is important because there are
locations in certain circuits where capacitors and inductors
must be modeled in order to observe unstable natural frequencies. The dangers of leaving out such critical capacitors
and inductors are illustrated in the following example. Consider the circuit shown in Fig. 4. This circuit has been designed to be a second-order low-pass gm C filter using the
pseudodifferential technique (11). The capacitors C1 and C2
determine the filters desired transfer function. The capacitor

(7)

VDD

The AA matrix, as defined in Eq. (3), is given, for the Fig. 3(a)
circuit, by

AA =

0
.000285
0
0

0
0
0
0

0
0
0
0

0
0
.00157
0

C2
C1

(8)

M2

AA =

0
0
0
0

.000292
0
0
0

0
0
0
.00161

0
0
0
0

M2

M3 M3

and, for the Fig. 3(b) circuit, is given by

Cp

(9)
VCM(out) +

M1

vout
2

M1
VCM(out)

We now evaluate for each circuit. For the Fig. 3(a) circuit,

= 1.55

(10)

VCM(in) +

vin
2

M1

M1
VCM(in)

and for the Fig. 3(b) circuit,

= 1.51

(11)

Figure 4. Second-order low-pass gm C filter.

vin
2

vout
2

412

CIRCUIT STABILITY OF DC OPERATING POINTS

Cp is considered to be parasitic and we will initially assume

it to be small enough so that its effect is insignificant at the
filters frequencies of interest.
Setting Cp 0, this circuits natural frequencies (i.e., the
filters poles) are given by the values of s that satisfy the following characteristic equation:
C1C2 s2 +

V2
RC = 1 k

RC = 1 k

10 k

10 k

V2 V1
C

gm2
g g
C s + m1 m3 = 0
2 2
4

V1

Since both solutions to the above equation lie in the left halfplane, we could then conclude that the filter is stable. Unfortunately, this conclusion is incorrect, as we will now show.
Let us now assume Cp 0. The resulting (now third-order)
characteristic equation is:

g g
g g
g
C1C2C p s + 2C1C2 m1 m3 C1C p m1 m3 + C2C p m2
gm2
2gm2
2
3

C2 gm1 gm3 s

(a)

RC = 90
10 k

(b)

V2

RC = 90
10 k

C
V2 V1

s2

( gm1 gm3 )2
=0
2gm2

Note that, for any value of Cp 0, no matter how small, the

s3 term in the above equation is positive and the s0 term is
negative. Thus we can conclude that there is at least one realvalued natural frequency that lies in the right half-plane,
thereby making the circuit unstable. Since any real MOS
transistor will always have some nonzero capacitance between its gate and source (indeed, the correct operation of any
transistor hinges upon the presence of such a capacitance),
then any analysis that does not take this capacitance into account would be prone to error, as illustrated above. From the
viewpoint of a circuit designer, this circuit is said to have positive feedback for common-mode signals, thereby resulting in
instability. As explained in (11), this problem is typically
overcome by adding circuitry to cancel out the common-mode
signals between stages. The resulting circuit would then possess a potentially stable operating point.
The above example illustrates that there are certain locations in a circuit where capacitances (and inductances), no
matter how small, must be modeled. A sharper result concerning such locations was later given in (12):
Theorem 2. Given the linear dynamic circuit shown in Fig.
2(a), let a capacitor be modeled in parallel with each pair of
terminals whose voltage is the controlling signal for some dependent source, and let an inductor be modeled in series with
each branch whose current is the controlling signal for some
dependent source. If 0 then, regardless of whether or not
any additional capacitors and inductors are modeled, the resulting characteristic polynomial will have its highest- and
lowest-order nonzero coefficients of opposite signs, making it
apparent that the corresponding operating point is unstable.

V1
(c)

(d)

Figure 5. Latch circuits with different loop gains.

circuit may possess; the stability of each operating point is

assessed separately.
One may question whether the existence of multiple operating points and the stability of the various operating
points are really separate issues. Might there be some connection between the presence of multiple operating points for a
circuit and the stability of the operating points? This question
is motivated by the following examples.
Figure 5(a) shows a simple latch circuit. It is shown in (4)
that operating points A and B in Fig. 5(b) are potentially stable, and that operating point C is unstable. Let us now change
the circuit slightly to the circuit shown in Fig. 5(c), where RC
has been reduced from 1 k to 90 . This circuits unique
operating point C in Fig. 5(d) can be shown to be potentially
stable. It happens, in fact, that as the value of RC is reduced
from 1 k to 90 , operating points A and B disappear exactly
when operating point C changes from unstable to potentially
stable.
Now consider the nonlinear one-port shown in Fig. 6(a)
(13). If this one-port is driven by a 24 V voltage source, then it

Is (mA)
Is

+
100 k

GENERAL PROPERTIES OF OPERATING POINT

STABILITY IN EVENTUALLY PASSIVE CIRCUITS

Vs

Thus far we have addressed only the stability of each of a

circuits specific operating points, one at a time. Once the stability of an operating point is determined there is nothing
that can be inferred, on the basis of Theorems 1 and 2, regarding the stability of any other operating points that the

200 k
3

6.8

3 k
14
(a)

24

453

(b)

Figure 6. Nonlinear one-port with driving-point characteristic.

Vs

CIRCUIT STABILITY OF DC OPERATING POINTS

can be shown that operating point P in Fig. 6(b) is the unique,

potentially stable operating point of the circuit. If the oneport is driven instead by a 6.8 mA current source, it then
happens that this circuit possesses, in addition to P, which is
now unstable, two more operating points, Q and R, both of
which are potentially stable.
Notice that in both of these examples, an unstable operating point occurred only in the presence of two other, potentially stable operating points. Furthermore, in analyzing
the latch we saw that the stability of operating point C
changed at the bifurcation point (brought about by changing
some of the resistor values) at which the circuit changed from
possessing three operating points to possessing only one. In
this section we will show how all of these issues are connected
in a natural way.
Two Classes of Unstable Operating Points
Although Theorem 1 gives a sufficient condition for an operating point to be unstable, it is not a necessary condition;
there may exist unstable operating points where 0 holds.
To show why this is true, consider the following characteristic
equation, assumed to have been derived from an augmentation with capacitors and inductors of the circuit in Fig. 2:
an sn + an1 sn1 + + a1 s +
= an

(s k ) = 0

where an 0 and each k is a natural frequency. Clearly,

n
/an k1(k) and, in general, this product can be factored
into three parts, corresponding to positive real roots, negative
real roots, and complex roots:

r=1

l=1

(13)

c=1

Here we assume that there are R positive real roots, implying

that each r is negative; L negative real roots, implying that
each l is positive; and C pairs of complex conjugate roots.
Since all but the r terms must be positive and an 0, Eq.
(13) implies
sgn
= (1)R

At this point perhaps it is natural to question whether circuits exist which, when the dc biasing is appropriate, possess
operating points having an even number of positive real natural frequencies. Such circuits do exist (14) and such operating
points would also be unstable, but they would not be identified as such by Theorem 1, since the constant term in any
corresponding characteristic polynomial would be positive.
The following definition identifies such operating points.
Definition 5. Given an operating point O of a dc circuit, if
every robust dynamic circuit that can be constructed around
O has an even nonzero number of natural frequencies in the
open right half-plane, then we say that O U e.
Although a special class of U e operating points has been
identified in Ref. 14, finding definitive criteria that identify
such operating points is still an open problem.
(Almost) Half of All Dc Operating Points Are Unstable
We will now prove some general results for the number of
unstable operating points that a circuit must possess. We begin by stating the following result from Ref. 15:

(12)

k=1








R
L
C





=
r
l
(c + jc )(c jc )
an
r=1
c=1
l=1







R
L
C



2
2
r
l
(c + c )
=

413

(14)

which shows that 0 if and only if there is an odd number

of positive real roots for the capacitor/inductor augmentation
at issue. This leads to the following definition:
Definition 4. If an operating point O of a dc circuit satisfies
Theorem 1 and, equivalently, if every robust dynamic circuit
(i.e., all capacitor/inductor-augmented circuits with a sufficient number of arbitrarily small, but positive, capacitors
and/or inductors included) that can be constructed around O
has an odd number of natural frequencies in the open right
half-plane, then we say that O U o.
(Notice that a circuit possesses an odd number of open right
half-plane roots if and only if it possesses an odd number of
positive real roots.)

Theorem 3. Let a dc circuit contain positive-valued resistors,

independent sources, and passive, voltage-controlled nonlinear elements whose ports form neither loops nor cut sets. If
the circuit has a finite number of operating points, all of
which are isolated, then it possesses an odd number of structurally stable operating points.
The circuit description in the above theorem covers any
circuit that can be built or fabricated out of real electrical
components. A structurally stable operating point is one that
does not disappear or split into a pair of operating points
when any of the circuits parameters are varied slightly.
Theorem 3 is proved in (15) using the degree of a mapping.
In particular, it is shown there that any structurally stable
operating point can be assigned an index of 1 or 1, and
that the sum of the indices of all of a circuits operating points
must add up to 1. Hence, the total number of operating
points of any circuit must be odd.
From this we can also conclude that if a circuit possesses
n operating points, then (n 1)/2 of these operating points
must have index of 1. In (14) it is proved that the index of
any operating point is identical with the sign of the corresponding value of . Since 0 implies that the operating
point is U o, we have the following result:
Theorem 4. If a dc circuit as specified in Theorem 3 has n
structurally stable operating points, then (n 1)/2 of them
must be U o and therefore must be unstable.
It is not necessarily true that the remaining (n 1)/2 operating points, all of which have an index 1, will be potentially stable; a U e unstable operating point also has an index
of 1. As an illustration of Theorems 3 and 4, consider the

414

CIRCUIT STABILITY OF DC OPERATING POINTS

12 V
4 k

4 k

4 k

4 k

30 k

30 k

V1

V2

10.1 k

10.1 k

2.5 V

1 mA

1 mA

V1

V2

Index

1.8
1.8
2.7
2.7
2.5
1.8
2.7
2.5
2.5

1.8
2.7
1.8
2.7
2.5
2.5
2.5
1.8
2.7

+1
+1
+1
+1
+1
1
1
1
1

Stability type
Potentially
Potentially
Potentially
Potentially
ue
uo
uo
uo
uo

stable
stable
stable
stable

Figure 7. An illustration of Theorems 3 and 4.

circuit in Fig. 7. The entire circuit possesses nine operating

points which are listed in the figure. As Theorem 4 predicts,
four of these operating points are U o. Of the remaining five
operating points that are not U o, four are potentially stable;
the fifth can be shown to be U e using results given in (14).
Results similar to those given in this section have been
applied in other scientific fields as well. For example, degree
theory has been used to obtain results regarding the number
and stability of equilibrium states in chemically reacting systems (16,17).
IDENTIFYING UNSTABLE OPERATING POINTS USING SPICE
Background
Designers of integrated circuits have commonly looked to the
SPICE dc operating point analysis to give an accurate solution to the dc circuit being simulated. Although SPICE does
generally give an accurate solution to the static equations
that describe the dc circuit, the solution may not be an observable operating point of the physical circuit itself. Since it has
been shown that there exist circuits with operating points
that are inherently unstable (no insertion of capacitors or inductors can make the resulting dynamic circuits corresponding equilibrium point stable), these unstable operating points
are physically unobservable. As a result, one might conjecture
that an unstable operating point is also unobservable from
the standpoint of dc circuit simulation. In other words, one
might infer that, when using an iterative algorithm to solve
the nonlinear equations describing a dc circuit, the iterates
would tend to be driven away from an unstable solution in
the same way that the actual circuit, during operation, would
drive itself away from the unstable operating point. This conjecture is false. As a counterexample, consider the circuit

shown in Fig. 8, which is well known to possess an unstable

operating point.
For this circuit the SPICE dc operating point analysis was
found to converge to the unstable operating point, as indicated in Fig. 8, when no .nodeset commands were specified
in the SPICE input file. (SPICE will use a zero voltage value
at each node as an initial guess, unless a .nodeset command
specifies otherwise. The .nodeset command is normally used
when there are convergence problems or when more than one
dc operating point is desired.) It is evident that the numerical
stability of the NewtonRaphson (or some similar) algorithm
used in SPICE is not necessarily related to the physical stability of the operating point that is being simulated. In fact,
provided that the starting point is close enough, the Newton
Raphson algorithm is guaranteed to converge to any operating point of a circuit, stable or unstable (18). In the example of Fig. 8, setting all node voltages to zero in the initial
guess (the default) led to convergence to the unstable operating point shown.
We now show how a certain class of unstable operating
points can be identified as a by-product of the SPICE dc operating point analysis. The following section then discusses
two practical examples showing how this addition to the
SPICE dc operating point analysis can be useful to a circuit
designer. Recall that, from Definition 4, any operating point
of a circuit that satisfies Theorem 1 is said to be a U o operating point. U e operating points (which are not identified
by Theorem 1) are rare in most practical circuits.
In most versions of SPICE the dc circuit equations are expressed in modified nodal analysis (MNA) form (19):



v
i
(15)
=F
i
v





Let the circuit contain p nodes and m independent and dependent voltage sources. Then in Eq. (15), v Rp is a vector each
of whose components is a node voltage; Rp is a vector
whose components are the sums of independent current
source values entering each node; v Rm is a vector each of
whose components is either an independent voltage source
value, or zero if the component corresponds to a dependent
voltage source; Rm is a vector whose components are the
currents flowing through each independent or dependent voltage source; F : Rpm Rpm is a smooth mapping. The jth
equation, j 1, . . ., p, of Eq. (15) is the KCL constraint that
equates the sum of all independent current sources entering
node j with the sum of the rest of the currents leaving node

5V

1 k

1 k
10 k

2
4

10 k
5

V(1)
V(2)
V(3)
V(4)
V(5)

=
=
=
=
=

5.000000e+00
1.186180e+00
1.186180e+00
8.085736e01
8.085736e01

Figure 8. An example of an unstable operating point.

CIRCUIT STABILITY OF DC OPERATING POINTS

j. The (k p)th equation, k 1, . . ., m, sets the value of

the kth voltage source equal to the voltage difference between
the two nodes (one of them may be ground) across which the
source is connected.
Once SPICE has converged to a solution

+15
+
741

+15

741
+

Vout

Vout

v 

15

15

Vout = 710.2999e6

Vout = 710.3210e6

of Eq. (15), the elements of the Jacobian matrix


v

F
i

******************************
Warning: This operating point
is unstable.
******************************



evaluated at the solution are available, since these will have

been computed and used by SPICE in the course of its normal
iterative solution process. The following simple relationship
between this Jacobian and operating point stability was given
in (10):
Theorem 5. For any operating point, sgn (1)m sgn[det F],
where m is the total number of dependent and independent voltage sources contained in the circuit.
In SPICE it happens that F is stored in its LU decomposed form after the dc solution has been obtained. Thus det
F is given simply by the product of the diagonal terms in the
LU matrix. Since we are interested only in the sign of this
determinant, we need only count the number r of negative
terms along the diagonal. If (m r) is odd (where, as mentioned in Theorem 5, m is the number of dependent and independent voltage sources contained in the circuit), then (1)m
det F 0, so 0, indicating that the operating point is unstable.
Using this algorithm, a very simple modification of SPICE
has been made that delivers a warning to the user, along with
the operating point information, whenever a U o operating
point is encountered. Since the algorithm only requires counting the voltage sources and counting the negative entries
along the diagonal of the final LU Jacobian matrix, this extra analysis requires a negligible increase of memory and
CPU time.

(a)

(b)

Figure 9. Op-amp circuits connected with (a) positive and (b) negative feedback. Warning message is automatically printed out by modified SPICE algorithm.

circuits equilibrium pointthat is, the instability of an equilibrium point of a dynamic circuit with a specific set of capacitors and inductors specifiedand the instability of a dc circuits operating point, as discussed in the section titled How
to Identify Unstable Dc Operating Points, and in Ref. 4. The
pole-zero and ac analyses cannot be used to determine a circuits dc operating point stability because such analyses must
be performed on a circuit with specific capacitors and inductors prescribed.
Bandgap Voltage Regulator. The fact that SPICE can converge to an unstable operating point is undesirable for two
reasons. First, SPICE can find an operating point that looks
correct, but is worthless in that it is actually unstable and
hence physically unobservable. As mentioned previously, the
instability of the operating points indicated in Fig. 8 and Fig.
9(b) is well known to most circuit designers. There are other
circuits, however, where it is not as obvious that an unstable
operating point has been encountered. Consider, for example,
the design of a circuit commonly used as a bandgap reference
voltage. The design concept, as illustrated in Fig. 10, is based
on the placing of two sets of constraints on a pair of branch
currents I1 and I2. The first, imposed by the connection shown
of Q1, Q2, and R1, gives
VT ln

Two Examples
Op-Amps Connected with Positive and Negative Feedback. To
illustrate the use of the above algorithm in SPICE, consider
the SPICE dc analysis of the two op-amp circuits shown in
Fig. 9. The model of the 741 op-amp used in our simulations
is the one shown in Ref. 9, p. 424. In both circuits, the SPICE
simulations converged to the operating point shown in Fig. 9.
Our modified SPICE algorithm automatically shows the Fig.
9(b) operating point to be unstable. It may be argued that
such instability can be determined by performing an ac or
pole-zero analysis, both of which are available in most circuit
simulators. However, the Fig. 9(a) circuit that we simulated
was not properly internally compensated; a pole-zero analysis
on this circuit would show that, in fact, both circuits are unstable for the particular capacitor values used.
While the Fig. 9(a) circuit can be stabilized by adjusting
the value of an internal capacitor; the Fig. 9(b) circuit cannot.
This is the essence of the difference between instability of a

415

nI2
= I1 R1
I1

(16)

Current mirror
I1

I2
Q1

Q2
K

nx

Vout

1x VB

R1

R2

Figure 10. Design concept of bandgap voltage reference.

416

CIRCUIT STABILITY OF DC OPERATING POINTS

The second, from the current mirror, simply gives

I1 = I2

(17)

Combining Eq. (16) and Eq. (17), we have

I1 = I2 =

VT
ln n
R1

(18)

The output Vout is then given by

K VB = K[Vbe (Q2 ) + 2I2 R2 ]

(19)

10 V

This gives a voltage with very low dependence on temperature. Further details on the operation of this circuit can be
found in (9). The Fig. 10 block diagram can be implemented
in the two different ways shown in Fig. 11(a) and Fig. 11(b).
Both circuits correctly realize the Fig. 10 design, where the
output voltage at node 4 is approximately 5 V. The SPICE dc
operating point analysis, whose results are shown in Fig.
11(c) and Fig. 11(d), confirms this. (The difference between
the output voltages of the two circuits is due to second-order
effects, such as nonzero base currents.) It happens that the dc
operating point in the Fig. 11(a) circuit is potentially stable,
whereas in Fig. 11(b) it is unstable. This fundamental prop-

10 V

4
3

Vout

8 k

8
8 k

5X

5X
6

10 k

1 k

10 k

1 k

26 k

26 k

(a)
V(1)
V(2)
V(3)
V(4)
V(5)
V(6)
V(7)
V(8)

=
=
=
=
=
=
=
=

(b)

1.000000e+01
9.309432e+00
5.585356e+00
4.845284e+00
2.688440e+00
2.039494e+00
1.999687e+00
8.720304e+00

V(1)
V(2)
V(3)
V(4)
V(5)
V(6)
V(7)
V(8)

i(vs) = 3.46535e04

=
=
=
=
=
=
=
=

1.000000e+01
9.305452e+00
6.203722e+00
5.460580e+00
3.029703e+00
2.378533e+00
2.335150e+00
8.712343e+00

i(vs) = 3.92694e04
*****************************
Warning: This operating point
is unstable.
******************************

(c)

(d)
V(1)
V(2)
V(3)
V(4)
V(5)
V(6)
V(7)
V(8)

=
=
=
=
=
=
=
=

1.000000e+01
9.413378e+00
1.722498e+00
1.022720e+00
5.681401e01
2.314104e02
2.242561e02
8.928227e+00

i(vs) = 5.76906e05

Figure 11. Two realizations of a bandgap voltage regulator circuit. Warning

message is automatically printed out by
modified SPICE algorithm.

******************************
Warning: This operating point
is unstable.
******************************
(e)

Vout

CIRCUIT STABILITY OF DC OPERATING POINTS

erty distinguishing the two circuits in Fig. 11 is well known;

however, it is not always obvious using a simple hand calculation to determine the dc behavior. Since the SPICE dc operating point analysis converges to the desired operating
point in both cases, it is impossible to tell solely from its results which circuit functions correctly. Moreover, it is proved
in (14) that if a circuits operating point is found to be unstable, then the circuit must possess at least two additional operating points. Hence another important by-product of identifying an unstable operating point is knowledge of the
existence of other, possibly potentially stable operating
points. This information could alert the designer to possible
latch-up conditions that would otherwise have gone undetected.
In the example of Fig. 11(b), we have a circuit that, on the
basis of its dc operating point analysis, looks correct, but in
fact is incorrect for the desired application. We will now consider an example of a circuit that looks incorrect on the basis
of its dc operating point analysis, but which actually operates
correctly. Consider again the circuit shown in Fig. 11(a). If no
.nodeset command is given for its dc operating point analysis, SPICE will converge to the different operating point
shown in Fig. 11(e), where the output voltage at node 4 is
approximately 1 V. This result might well cause the circuit
designer to consider taking steps to prevent possible latch-up
into the unwanted Fig. 11(e) state. If, however, the designer
could be warned that that operating point is unstable, no such
concern would be necessary since the circuit could not possibly latch-up into the unstable operating point. (The designer
would, however, be well advised to find the circuits third dc
operating point and examine its stability and latch-up potential.)
Designers familiar with bandgap circuits can easily identify instability in the Fig. 11(b) circuit by recognizing the
presence of positive feedback. We urge the reader to review
the discussion given in Section I of (4), however, to better appreciate the heuristic, nonrigorous character of the arguments that usually form the basis for such positive feedback
criteria for assessing dc operating point instability. See also
Section 8-3.2 of (3). Nonetheless, the SPICE algorithm discussed in the Background of this section does not rely on such
experience-based insights; it is perfectly general, applies to
all circuits, and does not require the use of heuristic analytical methods.

APPLICATION OF OPERATING POINT

STABILITY TO NONLINEAR ONE-PORTS
A number of results concerning the presence of negative differential resistance (NDR) have been reported in the literature, including (2022). These papers deal rigorously with
finding sufficient conditions for the presence of NDR. Very
little has been said, however, regarding the relationship between NDR and stability, except that it is usually assumed
that the presence of NDR automatically implies instability.
This assumption is not always true. A counterexample is
shown in Fig. 12. This one-port, constructed by terminating a
current conveyor (23) with a 2 k resistor, exhibits a resistance of 2 k for I [500 A, 2 mA], where all transistors
are biased in the forward-active region. However, it can be
shown that if this one-port is driven by a current source, then

417

+5

I
+
V

2 k
500 A

5
Figure 12. Transistor one-port with NDR.

the resulting equilibrium point can be made stable, even in

the presence of a capacitor connected across the port. This
somewhat surprising behavior is due to the inevitable presence of other parasitic capacitors across each transistor junction. However, if we were instead to drive this one-port with
a voltage source, then, as we will subsequently prove, the resulting circuit would be unstable independent of the location
or values of any capacitors that may be present at the input
or at any other location in the circuit.
The qualitative difference between the current sourcedriven and voltage source-driven one-port in Fig. 12 is discussed in (4). The operating point of the circuit created by
driving the Fig. 12 one-port with a current source is potentially stable, even though the one-port exhibits negative differential resistance, while the operating point of the circuit
created by driving the Fig. 12 one-port with a voltage source
is unstable.
We will now extend the circuit-related stability results to
the stability of dc one-ports. An operating point of a one-port
is defined by its port voltage, port current, and internal
branch voltages and currents, but the port termination is not
specified. Given an operating point O of a one-port, let O s
denote the operating point of the circuit formed by the voltage
source termination of the port that realizes O , and let O o denote the operating point of the circuit formed by the current
source termination of the port that realizes O .
Definition 6. An operating point O of a nonlinear one-port
is said to be open-circuit (short-circuit) unstable if O o (O s) is
unstable. Otherwise it is said to be open-circuit (short-circuit)
potentially stable.
We now develop results that give a fundamental relationship between a nonlinear one-ports open-circuit operating
point stability, its short-circuit operating point stability, and
its driving-point characteristic. We will also show how we can
use the results presented in this article to identify, by inspection, unstable regions of a nonlinear one-ports driving-point
characteristic.
Assume that at dc a one-port, linearized at any operating
point, does not contain any cut set consisting exclusively of
dependent current sources, or of dependent current sources
and the port; we also disallow any loop consisting of depen-

418

CIRCUIT STABILITY OF DC OPERATING POINTS

y1

xk

.
.
.

ak x j

x1

x1

a1 x i

+
+

y1

xk

ak x j

N
ik+1

.
.
.

yk

N
ik+1

+ vk+1

+ vk+1

No
Figure 13. General linear active oneports.

Ns

(a)

dent voltage sources, or of dependent voltage sources and the

port. We will model this linearized circuit as the passive (k
1)-port N, terminated by dependent sources, shown in Fig.
13(a) and Fig. 13(b), where the first k ports are defined by the
location of the dependent sources and the (k 1)th port is
the location of the original one-port. Define No as the k-port
that results when the (k 1)th port is open-circuited, as
shown in Fig. 13(a), and define Ns as the k-port that results
when the (k 1)th port is short-circuited, as shown in Fig.
13(b). Define Qo as the hybrid matrix of k-port No such that
x Qo y 0, where vectors x and y are defined in Fig. 13.
Likewise, define Qs as the corresponding hybrid matrix of kport Ns. Notice that Qo and Qs will, in general, be different
because No and Ns differ topologically. While, in general,
Qo Qs, the above loop and cut set assumptions do guarantee
that the same kind of hybrid matrix exists in both cases (8).
Define the k k matrix A to give the port constraints of No
and Ns; that is, y Ax. The entries of A will be the appropriate dependent source coefficients. Ik is defined as the k
k identity matrix. We now define the following stability-indicating constants for each of the two Fig. 13 circuits:

o det(Qo A + Ik )

(20)

s det(Qs A + Ik )

(21)

(b)

Let gp(A) denote the linearized port conductance of the oneport biased at a given operating point, and let gp(0) denote
the port conductance of the same linearized one-port under
the condition that all of the dependent sources have been set
to zero. This notation is illustrated in Fig. 14. The following
theorem is presented in (24):
Theorem 6.
g p (A) = g p (0)

o

s

(22)

The following example shows how one can infer operating

point stability information from a one-ports driving-point
characteristic. Consider again the nonlinear one-port shown
in Fig. 12. We have established that O o is potentially stable.
Hence O o U o and therefore o 0. Since the slope of the
driving-point characteristic at the operating point of interest is negative, gp(A) 0 at O . Furthermore, we know that
gp(0) 0 since the linearized one-port is passive in the absence of controlled sources. Therefore, it follows from Theorem 1 that s 0. Hence O s U o, and we can conclude that
the one-port is short-circuit unstable at O . This result is generalized in the following theorem:

y1
+
x1

.
.
.

xk

.
.
.

+
ak x j

yk

N
ik+1

Figure 14. Illustration of gp(A) and gp(0).

a 1x i

.
.
.

yk

.
.
.

+ vk+1

gp(A)

y1
+
x1

.
.
.

a 1x i

xk

.
.
.

+
yk

N
ik+1

+ vk+1

gp(0)

CIRCUIT STABILITY OF DC OPERATING POINTS

B
i
i2

+
v

i1

v1

R
+
v

v2

(a)

(b)

i
B

i2

i1

E
v

v1

v2

Voltage-controlled

Current-controlled

(c)

(d)

Figure 15. C-Type NDR circuit with driving-point characteristic.

Theorem 7. Let O be an operating point of a nonlinear oneport whose topology satisfies the loop and cut set assumptions
stated above, and let gp(A) be the linearized port conductance
at O . The following statements are true:
(i) If gp(A) 0 then O s U o if and only if O o U o.
(ii) If gp(A) 0 then O s U o if and only if O o U o.
Proof. By the assumptions on the topology of the one-port,
gp(0) 0 only if gp(A) 0, and gp(0) only if gp(A) .
The proof is now immediate from inspection of the sign of
each term of Eq. (22).
We can use Theorem 7 to identify regions of stability on a
one-ports driving-point characteristic for both open-circuit
and short-circuit terminations of the one-port as follows.
In Fig. 15(a) we show a one-port with a C-type drivingpoint characteristic, constructed by placing a positive resistor
in series with an N-type circuit, as shown in Fig. 15(b) (23).
The charactristic has been divided into five curve segments in
Fig. 15(a), each of which is bounded on at least one end by a
point at which the characteristic has either zero or infinite
slope. We assume that all components in this one-port are
described by C 2 functions that are, along with their derivatives, bounded on any compact set. Also, let us assume for
this example that the origin of the characteristic in Fig. 15(a)
is known to be potentially stable when the one-port is terminated with either a short circuit or an open circuit. These
assumptions imply that s and o are continuous and finite
everywhere on the characteristic and that they are both positive at the origin.
As we proceed from the origin along segment A to the
boundary between segments A and B, the slope changes from

419

positive to negative through zero, which implies by Theorem

6 that either o changes from positive to negative through
zero, or s changes from positive to negative discontinuously
and without bound. But because s and o must vary continuously with all circuit parameters, it can only be true that o
passes through zero. Thus we can conclude that all operating
points on segment B are open-circuit unstable. As we move
from segment B to segment C, the slope becomes infinite and
then positive, implying that o remains negative and s
changes from positive to negative. This means that all operating points on segment C are both open-circuit and shortcircuit unstable. Similarly, all operating points on segment D
are open-circuit unstable. In Fig. 15(c) and Fig. 15(d), we
show the possibly observable operating points on the drivingpoint characteristic for a voltage source input and a current
source input, respectively. We say possibly here because an
operating point that is not U o may still be unstable (i.e., if it
is U e). The methods given in this section can only identify
U o operating points as being unstable. Notice that both
curves show hysteresis from the point of view of the controlling signal. Furthermore, at any value of the controlling signal for which hysteresis is present, it can be seen by comparing Fig. 15(a) with Fig. 15(c) and Fig. 15(d) that there is
another operating point present (between the two possibly observable operating points) that is unstable for the given termination. This is in agreement with the relationship between
the number of U o operating points and the number of other
operating points that any eventually passive circuit must
possess.

CONCLUSION
This article has surveyed a variety of results on the stability
of dc operating points. In contrast to techniques often found
in the literature, which are based on heuristic methods or
overly simplified assumptions and consequently can be misleading, these results provide an analysis of operating point
stability in a more rigorous context. We first made clear the
difference between an operating point and an equilibrium
point and then defined rigorously, based on the actual circuit
dynamics, what it means for an operating point to be either
potentially stable or unstable. We found a simple criterion,
based only on the dc circuits linearized equations, that can
identify an operating point as being unstable. As a by-product
of the derivation of this criterion we showed that, in order to
correctly determine operating point stability, it suffices to
model stray capacitance and inductance in a few specific locations, even though parasitic reactances might exist virtually
everywhere in a physical circuit. Practical examples were
given which used this criterion to identify unstable operating points.
Our attention then turned to the classes of U 0 and U e operating points, and we established that U 0 operating points
are quite prevalentcomprising approximately half of all operating points in circuits having multiple operating points.
The modification of SPICE to permit it to identify U 0 operating points was treated next. The stability results were
extended to operating ports of nonlinear one-ports, where the
relationship between negative differential resistance at an operating point and open- and short-circuit stability was described.

420

CIRCUIT TUNING

BIBLIOGRAPHY
1. W. Duddel, On rapid variations in the current through the directcurrent arc, The Electrician, 46: 269310, 1900.

24. M. M. Green and A. N. Willson, Jr., On the relationship between

negative differential resistance and stability for nonlinear oneports, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 43:
407410, 1996.

2. T. Simon, On the dynamics of electrical arcs and its hysteresis,

in German, Phys. Z., 6 (10): 818839, 1905.

M. M. GREEN

3. T. E. Stern, Theory of Nonlinear Networks and Systems, Reading,

MA: Addison-Wesley, 1965, pp. 319320.

A. N. WILLSON, JR.

4. M. M. Green and A. N. Willson, Jr., How to identify unstable dc

operating points, IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., 39: 820832, 1992.
5. M. Vidyasagar, Nonlinear Systems Analysis, Englewood Cliffs,
NJ: Prentice-Hall, 1978.
6. J. P. LaSalle and S. Lefschetz, Stability by Liapunovs Direct
Method; with Applications, New York: Academic Press, 1966.
7. L. O. Chua and D. N. Green, Graph-theoretic properties of dynamic nonlinear networks, IEEE Trans. Circuits Syst., CAS-23:
292312, 1976.
8. H. C. So, On the hybrid description of a linear n-port resulting
from the extraction of arbitrarily specified elements, IEEE Trans.
Circuit Theory, CT-12: 381387, 1965.
9. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1993.
10. M. M. Green and A. N. Willson, Jr., An algorithm for identifying
unstable operating points using SPICE, IEEE Trans. Comput.Aided Des. Integr. Circuits Syst., 14: 360370, 1995.
11. F. Rezzi, A. Baschirotto, and R. Castello, A 3 V 1255 MHz
BiCMOS pseudo-differential continuous-time filter, IEEE Trans.
Circuits Syst., 42: 896903, 1995.
12. M. M. Green, Comment on How to identify unstable dc operating
points, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 43:
705707, 1996.
13. L. Trajkovic and A. N. Willson, Jr., Negative differential resistance in two-transistor one-ports with no internal sources, Proc.
IEEE Int. Symp. Circuits Syst., Espoo, Finland, June 1988, pp.
747750.
14. M. M. Green and A. N. Willson, Jr., (Almost) half of any circuits
operating points are unstable, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 41: 286293, 1994.
15. L. O. Chua and N. N. Wang, On the application of degree theory
to the analysis of resistive nonlinear networks, Int. J. Circuit Theory Applic., 5 (1): 3568, 1977.
16. G. R. Gavalas, Nonlinear Differential Equations of Chemically Reacting Systems, New York: Springer-Verlag, 1968, pp. 2428.
17. D. Luss, The influence of capacitance terms on the stability of
lumped and distributed parameter systems, Chem. Eng. Sci., 29
(8): 18321836, 1974.
18. J. M. Ortega and W. C. Rheinboldt, Iterative Solution of Nonlinear
Equations in Several Variables, New York: Academic Press, 1970,
chap. 6.
19. C. W. Ho, A. E. Ruehli, and P. A. Brennan, The modified nodal
approach to network analysis, IEEE Trans. Circuits Syst., CAS22: 504509, 1975.
20. L. O. Chua, J. Yu, and Y. Yu, Negative resistance devices, Int. J.
Circuit Theory Appl., 11: 161186, 1983.
21. L. Trajkovic and A. N. Willson, Jr., Circuit parameters and the
occurrence of negative differential resistance, Proc. IEEE Int.
Symp. Circuits Syst., San Jose, CA, May 1986, pp. 277280.
22. L. Trajkovic and A. N. Willson, Jr., Theory of dc operating points
of transistor networks, Int. J. Electron. Commun., 46 (4): 228
241, 1992.
23. K. C. Smith and A. S. Sedra, The current conveyera new circuit
building block, Proc. IEEE, 56: 13681369, 1968.

University of CaliforniaIrvine
University of CaliforniaLos
Angeles

CIRCUIT THEORY. See NETWORK EQUATIONS.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

529

NONLINEAR DYNAMIC PHENOMENA

IN CIRCUITS
When we look at the behavior of the state in a nonlinear circuit, its long-term time response is sometimes remarkably different from that of a linear circuit. In some cases we come
across phenomena that never occur in linear circuits. These
are termed nonlinear phenomena. The existence of multistable states, self-excited oscillation, nonlinear resonances, synJ. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

530

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

chronizations, and chaotic states, all of which occur naturally

in simple nonlinear circuits, illustrate typically these particular phenomena. In a linear circuit or system, there exists only
one steady state and all transient states die out after appropriately long time duration. Linear systems have a nice property such that we can always analyze the steady and transient states separately by the principle of superposition.
Hence we know all the properties of linear systems by analytical treatment. In nonlinear systems, on the other hand, besides the local property of linear systems there may appear
some combined or mixed states that have qualitatively different features, and this fact causes some complicated behavior
of states in time. Because there is no general analytical solution for these nonlinear phenomena, the problem is difficult.
Much attention has been paid to the problem, however, in the
last two decades, and the progress of theoretical and applied
study in the field of nonlinear dynamics has developed
rapidly.
Apart from the circuit dynamics, these nonlinear phenomena are very commonly observed in many other disciplines,
such as mechanics, physical systems, chemical reactions, optics, fluid dynamics, and population dynamics. The mathematical model of these systems is expressed by a system of
ordinary differential equations which defines a deterministic
process, called a dynamical system. The theory of dynamical
systems is then concerned primarily with making qualitative
investigations into the behavior of states which evolve in
time, as the initial state and parameter of the system are
varied. Most of the models derived from practical problems
cannot be solved by analytic method, so that the topological
or geometrical approach (called the qualitative method) and
numerical analyses are of fundamental importance in understanding of various phenomena observed in dynamical systems. Fortunately, among many nonlinear systems, electrical
circuits are considered simple and convenient physical systems to implement real nonlinear phenomena. They are
themselves widely used in various fields of electrical engineering.
Dynamical Process, State, State Space, and Attractor
Now we proceed with a little more detailed overview of some
typical nonlinear phenomena, some of which will also be discussed in later sections. Mathematically, the dynamic process
of a circuit is formulated as a set of ordinary differential equations, where the time is the independent variable and states
of the circuit are dependent variables in time. The equations,
say circuit dynamics, give a law of the evolution of the state
and determine the time evolution of all states of the circuit.
All possible states are then characterized by the points of
some point set or space, called a state space. The state space is
also called a phase space, borrowing from classical mechanics.
Actually, the specification of a point in the state space is sufficient to describe the initial or current state, as well as to
determine its future evolution. Then, for a given initial point
in the state space, the state evolves by the circuit dynamics.
One of the salient features of circuit dynamics is its dissipative property, which is achieved by resistors. Usually a circuit
consists of energy-storing elements (i.e., inductors and capacitors) and energy dissipative elements (i.e., resistors). Hence
along the time evolution of state the energy stored in the circuit will be lost at resistors and its state will approach some

stable steady state in the state space. The steady state works
as if it absorbs every neighboring state into itself. Such a
steady state is called an attractor, and the existence of attractors is the most significant property of a dissipative system
such as the circuit dynamics. On the other hand, a lossless circuit containing only inductors and capacitors is formulated as
an energy conservative system similar to classical mechanics.
In this case we have no attractors and the distinction between
transient state and steady state becomes difficult.
Examples of Steady State and Attractor
Among all possible states in the state space, some particular
states have a special property such that they are invariant in
some sense during the time evolution. They are candidates to
be attractors or steady states of the system. Equilibrium
point, periodic state, quasiperiodic state, and a more complicated state, called chaotic state, are typical invariant sets of
the system. An equilibrium point, also called a rest point, is a
single point in the state space which always rests at the same
point during the time evolution. This is the simplest steady
state and corresponds to a dc operating point in a real circuit.
Periodic state is a periodically repeated state with a definite
period or frequency. This state is commonly observed in
forced circuits driven by an ac voltage or current source. An
oscillator also produces a periodic state. Many biological
rhythms are also modeled as periodic states generated by biological oscillators. A state containing several distinct frequencies is called a quasiperiodic state. It appears sometimes in a
forced oscillator with periodic input signal. When the difference of free and driving frequencies is appropriately large,
both frequencies can survive and doubly periodic oscillation
becomes possible. In this case the time response is a beat or
quasi-periodic oscillation. Chaotic state is the most complicated state whose long-term time response looks like a noisy
or random nature. Later we will discuss this state more precisely. The concept of stability of the above invariant sets is
also important. Roughly speaking, a steady state is stable if
every neighboring state always stays in the neighborhood of
the steady state in future evolution. If a steady state satisfies
a stronger condition such that all neighbors approach the
steady state, then we say that the state is asymptotically stable. An attractor is an asymptotically stable steady state. In
a real system a physically observable state is an attractor. In
the theory of dynamical systems the above invariant sets are
called nonwandering sets. On the other hand, a transient
state corresponds to a wandering set. Figure 1 shows schematic diagram of states of dynamical systems and their bifurcations.
Role of System Parameters
A steady state of a circuit depends also on parameters contained in circuit dynamics. Associated with the change of parameters, the qualitative property of a steady state may
change at some particular value of the parameters. For example, the appearance of a couple of steady states, stability
change of a steady state, or the creation of a new type of
steady state, and so on, may occur under the variation of parameters. We may imagine the parameters as a controlling
device of the qualitative property of states. That is, by changing system parameters we can see a morphological process of
steady states, which is referred to as a bifurcation of state or

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Transient states

periodic inputs or periodic forces. But a dc operating point

(i.e., an equilibrium point) becomes unstable because of the
negative resistance and a periodic state appears. The oscillatory state is then represented as a closed curve in the phase
plane and is called a limit cycle. A small initial state grows
up and approaches the closed curve, whereas a large initial
state shrinks asymptotically into the same closed curve.
Hence the limit cycle is a unique attractor of the circuit. This
is a simplest mechanism of self-excited oscillatory process. A
sinusoidal time response is obtained for a weak nonlinear system, called a nearly harmonic oscillator. On the other hand,
if the nonlinear characteristics is strong, we may observe a
nearly square wave response, called a relaxation oscillation.

Steady states (invariant set)

Nonwandering states
Equilibrium states
HB

Wandering
states

Periodic states
TB

PDB

NS
Quasiperiodic
states

PDB

Regular states

531

Complex
and
composed
states
Homoclinic
states

Chaotic states

Figure 1. Schematic diagram of states of dynamical systems and

their bifurcations. TB, HB, NS, and PDB indicate tangent bifurcation,
Hopf bifurcation, NeimarkSacker bifurcation, and period doubling
bifurcation, respectively.

a bifurcation phenomenon. Bifurcations indicated by arrows

in Fig. 1 will be discussed in later sections.
Typical Nonlinear Phenomena
In the following we will present a short review of typical nonlinear phenomena. More concrete examples will be given in
subsequent sections. Figure 2 shows a schematic diagram of
nonlinear phenomena and related bifurcations.
Multistable States. Several stable steady states can coexist
in nonlinear systems. The simplest example is a flip-flop action with two stable equilibrium points as attractors. Depending on a given initial state, the state starts to evolve and
falls into one of the attractors. Which attractor is finally realized is uniquely determined by the choice of the initial state.
Self-Excited Oscillation. An LC resonant circuit with a negative resistance is a simple sinusoidal oscillator which generates a stable periodic state in two-dimensional state space,
called a phase plane. The circuit has only a dc source and no

Nonlinear Resonance. This phenomenon occurs mainly in a

nonlinear resonant circuit driven by a periodic input signal.
A ferro-resonant circuit forced by an ac voltage source is a
typical example of this type of circuit. As the system is forced
by a periodic external input signal, the steady state may be
realized by a periodic, quasiperiodic, or chaotic state. For a
moment we consider only the case where the steady state oscillates with the same frequency as that of the injected periodic signal. Keeping the amplitude of the forcing function constant and also changing the frequency of the input signal, we
observe a range of frequencies for which several possible stable periodic states coexist. Under the gradual change of frequency a hysteretic effect between the stable steady states
occurs for increasing and decreasing frequencies. This is
called a jump phenomenon of nonlinear resonance. Other periodic states can be also observed such as subharmonic or
higher-harmonic oscillations, whose frequency is a fraction or
an integral multiple of that of the input signal, respectively.
Therefore by nonlinear resonances there may appear multistable states of periodic oscillations with various frequencies.
Bifurcations of steady states occur by changing external injected frequency. The same phenomenon is also observed by
changing the amplitude of the external signal whereas the
frequency is held constant. Note also that a driven nonlinear
resonant circuit exhibits many other phenomena, such as the
period doubling bifurcation, the appearance of quasiperiodic
states, chaotic states, and so on.

Phase space
Attractor
Mutual
interaction

Stabilize or
destabilize

Selforganization
Synchronization

Tangent
period-doubling
Neimark-Sacker

Jump
hysteresis

Self-excited
oscillation

Nonlinear
resonance

Hopf

Tangent
Bifurcation

Parameter space

Parametric
excitation

Period doubling
Figure 2. Schematic diagram of typical nonlinear
phenomena: synchronization, self-excited oscillation, nonlinear resonance, and parametric excitation.

532

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Period Doubling Bifurcation. In a periodically driven circuit

we may observe that a stable periodic state becomes unstable
and there appears another stable periodic state with half-frequency under the variation of system parameters. That is, the
new periodic state has a period that is exactly twice as long.
This is a period doubling bifurcation and is one of the general
bifurcation processes of the periodic state. In many cases under the finite change of parameters, this doubling process repeats successively infinitely many times. At every doubling
process a new periodic state with half-frequency is produced.
Hence after this cascade of period doubling bifurcations we
observe a strange and complicated oscillatory state possibly
with very low frequencies, called a chaotic state. The cascade
is thus considered one of the routes to produce a chaotic
state.
Chaotic State. A chaotic state is a set of bounded composite
steady states composed of infinitely many unstable periodic
and nonperiodic states. Hence the long time response of the
state looks like a noisy or random oscillation. In a chaotic
attractor every state is unstable in one direction and stable
in another direction so that the neighboring states diverge at
some instant and converge at another instant during the time
evolution. All states in the attractor are thus mixing each
other according to the nonlinear property of the dynamics.
Thus two states starting from slightly different initial states
diverge rapidly so that the initial information of states will
be violated. This property is referred to as a sensitive dependence of intial states. A chaotic state is commonly observed
after a cascade of period doubling bifurcation stated above.
Because we cannot explicitly solve the circuit dynamics, the
complexity of the attractor is still mathematically unsolved.
We can see, however, some qualitative properties by topological and/or numerical approaches.
Synchronization. A synchronization effect can readily be
realized by a sinusoidal oscillator driven by an external sinusoidal signal. When the frequency difference of the free oscillator and driving input signal is appropriately large, quasiperiodic states appear. At a certain difference of the frequencies
the quasiperiodic states suddenly disappear and there remains an entrained periodic state with single external frequency. Similar entrainment can occur when we couple two
or more oscillators with nearly equal frequencies. The former

is called a frequency entrainment or phase locked phenomenon,

whereas the latter is called a mutual synchronization. Human
circadian rhythms being entrained by the earth rotation clock
is a former example. For the latter example, we see that despite many power stations being connected, a power network
operates at a single frequency.
Parametric Excitation. Parametric excitation or parametric
resonance is an oscillatory phenomenon observed in a system
with periodically varying parameters. A periodic external signal is injected into a system parameter in this case. An RLC
parallel circuit with a mechanically varying capacitance is a
simple example of this type of circuit, called a parametric amplifier. Applying a sinusoidal signal, the pump signal, to the
mechanical part, we can realize a periodically varying capacitance. In this circuit under appropriate setting of parameters
there appears a period doubling bifurcation of state; that is,
a stable equilibrium point becomes unstable and there appears a periodic state with half-frequency of the external mechanical input. The vertically pumping of a swing by a child
is another example of a parametrically excited system. In an
oscillatory regime the horizontal frequency is approximately
half that of the body of the child.
Method of Analysis
For understanding dynamical processes we have to know
many mathematical objects: the geometry of phase portrait,
approximation methods of periodic states, time series analysis for chaotic responses, mechanism of bifurcation process,
and so on (see Fig. 3). Various methods of analyses have been
proposed to this end. Here we point out briefly three different
approaches as follows.
Analytical Method. The method of analyzing periodic states
is well developed for weakly nonlinear systems. Various perturbation methods and averaging methods are classically applied to determine the periodic states of free and forced electrical circuits. For systems with strong nonlinearity, little is
known. Galerkins method of combining numerical analysis is
one of the methods for obtaining periodic states for such
strong nonlinear systems. Probability theory or ergodic theory
will be applied to the analysis of chaotic state in order to
know the long-term behavior.

Equilibrium points
Limit cycles
Invariant sets
Phase portrait
Parameter family
of dynamical systems

Calculus, analysis

Bifurcation diagram

Dynamical
systems

Probability

Figure 3. Schematic diagram of the analysis of

dynamical systems.

Time response
Frequency spectrum
Lyapunov exponent
Fractal dimension of attractor

Topology

Global structure
of phase portrait

Basin of attractor
Geometry

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Geometrical or Topological Method. Although nonlinear ordinary differential equations cannot generally be solved explicitly by quadrature, we can know the existence of a solution with a given initial condition, the uniqueness property of
the solution, extendability of the solution in long time interval, asymptotic property of solution, stability of the solution,
and so on. These properties depend upon the geometrical or
mainly topological property of dynamical systems. A qualitative approach is then directed to the study of phase portraits,
stability theory, and bifurcation processes.
Numerical Method or Simulation. Many numerical integration methods are now available. Combining these integration
methods and the qualitative approach, we can calculate any
type of steady state, stability condition, bifurcation condition,
statistical test condition for chaotic states, and so on. Newtons method and other root finding methods are effectively
used for the numerical computations.
References in This Section
The theory of dynamical systems, especially classical mechanics, has a long history and has developed many useful techniques to study the time evolution of state. During the early
part of the twentieth century, the theory of nonlinear oscillations arose in electrical and mechanical engineering and has
been developed also in parallel with that of dynamical systems. After discovering the chaotic state in many applied
fields, the nonlinear dynamics has become popular during the
last two decades. Many books and references are now available. We refer to only classical books (19) about nonlinear
oscillations in circuit dynamics and dynamical systems.
BASIC MATHEMATICAL FACTS
In this section we review minimal mathematical tools for understanding the circuit dynamics as a time-evolving process
called a dynamical system. We also mainly treat a smooth
system; that is, the functions or maps defining the system will
be differentiable as many times as we want. In the remainder
of the article the term dynamical system refers to a differentiable dynamical system or simply a smooth dynamical system.
Circuit Dynamics, State and State Equation
Every lumped electrical circuit obeys two basic physical laws:
(1) Kirchhoff s voltage and current laws and (2) the element
characteristics derived from the constitutive relation of circuit
element. Combining these two constraint relations and eliminating auxiliary variables, we can obtain a system of firstorder ordinary differential equations in normal form as the
state equation or circuit dynamics of the circuit:
x = f(t, x, )

(1)

are the state vector and the system parameter, respectively,

and the dot over x denotes differentiation with respect to the
time: x dx/dt. In most cases the voltages across capacitors
(or charges stored in capacitors) and the currents through inductors (or magnetic flux linkages in inductors) will constitute
the set of state variables x1, x2, . . ., xn. The state x is then
considered as a point of n-dimensional Euclidean space: x
Rn, where n is the sum of the number of capacitors and inductors in the circuit. The function f of the right-hand side of Eq.
(1) gives the velocity vector at each point in the state space
and determines the dynamics of the circuit. That is, Eq. (1)
defines a vector field in the state space. If f does not contain
the time explicitly, then Eq. (1) is called autonomous. Otherwise, Eq. (1) is called nonautonomous. An autonomous equation defines a time-invariant vector field in the state space
Rn, whereas a nonautonomous equation defines a time varying vector field in Rn. In circuit dynamics an autonomous system arises mainly from a circuit containing only dc sources.
A typical example of a nonautonomous system is a circuit
driven by an ac source.
Remark 1. 1. In the above definition we assume that the
state space of Eq. (1) is an entire n-dimensional Euclidean
space Rn. In some cases it may happen that the vector field
(1) is defined only some bounded region or some subset of
Rn. The same situation occurs for other variables: time and
parameters. For convenience we assume that the state space
is simply the whole Rn. In our circuit application, however,
we interest the time evolution of the state within the
bounded region.
2. The function f in Eq. (1) reveals the element characteristics and the connection of the circuit elements. Hence, if the
element characteristics are defined by continuous or differentiable functions, then f becomes continuous or differentiable functions, respectively. If the characteristics is assumed
as a piecewise linear function, then f is expressed by a
piecewise linear function. In the following we will mainly consider the case where f is defined everywhere and differentiable with all variables t, x and .
3. For the nonlinear circuit with weakly nonlinear characteristics, Eq. (1) may be expressed by the form
x = Ax + g(t) +
f(t, x)

Example 1. 1. An RLC resonant circuit. Consider the RLC

resonant circuit with a negative conductor shown in Fig. 4(a).

iG
iG

iC
vC

(a)

i
iG = g(v)

iL

L
R
E

1
2

= . Rm
..
m

(2)

where A is an n n constant matrix and is a small parameter of real number. In this case we say Eq. (2) a quasilinear
system or a weakly nonlinear system.

where t is the time: t R,

x1
x2

x = . Rn ,
..
xn

533

iG = I

vC
vC = V

(b)

Figure 4. (a) RLC resonant oscillator and (b) characteristics of the

nonlinear conductor.

534

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

We assume that the capacitor and inductor have linear characteristics whereas the conductor G has a nonlinear characteristics with voltage controlled type [see Fig. 4(b)]. For convenience we assume the nonlinear characteristics as a cubic
polynomial. Then the constitutive relations are written as

dvC
,
dt
di
vL = L L ,
dt
iG = g(vG ) = IG G1 vG G2 v2G + G3 v3G ;
iC = C

(3)

By choosing the capacitors voltage and the inductors current

as the state variables we have the state equations:

(4)

If we put the system in vector normal form, we have Eq. (1)

with

1
1

i
g(v

)
L
C
C

v
C

f=
x= C ,
(5)
1
R
E
iL
vC iL +
L
L
L
This gives an autonomous vector field in two-dimensional
state space (vC, iL).
By using the coordinate translation
vC = v + V,

iL = i + I,

iG = ig + I


1 = g1

L
,
C

g
3 = 3
C

L
,
C

k=R

C
,
L

B=e C
(12)

In the case where R 0 and E 0 (i.e., k 0 and B 0),

by eliminating the state y from Eq. (11) we have the following
second-order equation, called the van der Pol equation:

(13)

Equation (13) exhibits a typical self-oscillatory process of the

circuit as we shall see later. Note also that if we eliminate
the variable x, then we have the Rayleigh equation:

2 
d 2y
3 dy
dy
+y=0
1 1
2
d
1 d
d

(14)

Both Eqs. (13) and (14) are expressed by the first-order form
as Eq. (11), hence they are equivalent.
2. A forced resonant circuit. Figure 5 shows another resonant circuit with a saturable nonlinear inductor driven by an
alternating voltage source E sin t. As shown in the figure,
the linear resistor R is placed in parallel with the linear capacitor C, so that the circuit is dissipative. With the notation
of Fig. 5, we have

(6)

Eq. (4) becomes more compact form:

dv
= i + g1 v g3 v 3
dt
di
= v Ri + e
L
dt


3 2 dx
d 2x
+x=0
1 1 3 x
d 2
1
d

G1 , G2 , G3 > 0

dvC
= iL iG = iL g(vC )
dt
di
L L = vC RiL + E
dt

where we put the parameters as

v
dvC
+ C = iL
dt
R

(15)

d
+ vC = E sin t
dt

(7)

where we put
g1 = G1 + 2G2V 3G3V 2 ,

g3 = G3 ,

e = V RI + E
(8)

where n is the number of turns of the coil and denotes the

magnetic flux of the inductor. The saturable reactor has a secondary coil which only supplies a biasing direct current. Neglecting hysteresis, we assume the nonlinear characteristics
of the inductor to be
niL = f () = a1 + a2 2 + a3 3

(16)

and V and I are determined by the following relation:

G2 3G3V = 0,

I = IG G1V G2V 2 + G3V 3

(9)
R

For some purposes, it is convenient to renormalize the variables as

x=

Cv,

y=

Li,

1
= t
LC

(10)

C
E sin t

Equation (7) is then rewritten as

dx
= y + 1 x 3 x3
d
dy
= x ky + B
d

iL

E0

(11)
Figure 5. Forced resonant circuit with a nonlinear saturable inductor.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

where a1, a2, and a3 are positive constants. Substituting Eq.

(16) into Eq. (15), we have the state equation:

v
dvC
1
= C +
f ()
dt
RC nC

(17)

d
1
E
= vC + sin t
dt
n
n
for the state variables (vC, ). This gives a nonautonomous
system. By eliminating vC, we have the following second-order
equation:
d
d 2
+ b1 + b2 2 + b3 3 = B cos
+k
d 2
d

(18)

where

1
,
k=
RC

= t tan1 k,
E 
1 + k2
B=
n

a
bl = 2 l2 (l = 1, 2, 3),
n C
(19)

Equation (19) can be transformed to the alternative form as

dx
d 2x
+ c1 x + c3 x3 = B0 + B cos
+k
2
d
d

(20)

where x b2 /3b3 and c1, c3, B0 are constants determined

by b1, b2, and b3. Equations (19) and (20) are called Duffings
equations and exhibit various resonant phenomena as well as
jump and hysteresis of these responses.
Local Existence and Uniqueness Theorem
of the Solutions of Circuit Dynamics
By returning to dynamical problems, let us consider the following initial value problem of Eq. (1). Suppose that an initial
state x0 and an initial instant t0 is given. We say the function
x(t) = (t, x0 , )

(21)

is a solution of Eq. (1) on a time interval I R containing t0,

if Eq. (21) satisfies Eq. (1), that is,
(t,
x0 ) = f(t, (t, x0 , ), )

(22)

An initial value problem for Eq. (1) consists of finding the

interval I and the solution (21) satisfying the initial condition:
x(t0 ) = (t0 , x0 , ) = x0

(23)

x(t0 ) = (t0 , x0 , ) = x0 ,

ant under any translation of time. Hence without loss of generality we can choose the initial instance t0 0.
Hence the questions arise. For a given initial value problem, does Eq. (1) has a solution for all t I R? If Eq. (1)
has a solution, is such a solution unique and does it extend to
the entire time interval R? The answer is the following theorem on the local existence and uniqueness of the solution of
Eq. (1).
Theorem 1. Suppose that in Eq. (1) the function f(t, x, ) is
differentiable in all variables t, x, , then there exists an interval I R containing t0 and the solution (21) also exists for
all initial conditions (t0, x0) I Rn. Moreover, this solution
is unique.
Remark 2. 1. The initial value problem (24) can be equivalently rewritten as the integral equation of the form:

x(t) = x0 +

f(s, x, )ds

(25)

t0

Existence and uniqueness property is then discussed by posing an appropriate condition on f. One of the sufficient conditions to guarantee the property is known as a local Lipschitz
condition. Because the differentiability is stronger than the
Lipschitz condition, we never worry about the existence and
uniqueness problem if f is differentiable. Note that the solution to Eq. (21) exists only in a short time interval I so that
the theorem asserts a local existence property.
2. Extendability of the solution to the entire time interval
R depends on f(t, x, ). Usually the function f(t, x, ) is defined in a bounded region of state space Rn. Starting with an
initial state in the region, the state may reach the boundary
of this region after a finite time, and the solution could no
longer be extended to rest in the region. The simplest example
of such behavior is a blow-up situation where a state approaches to infinity within a finite time. In most circuit applications, however, the solution can be extended to the entire
time interval R.
3. In circuit dynamics, under some particular connection of
elements, the normal form of the state equation (1) may break
at some points or in some subset in the state space as the
next example shows. This pathological situation occurs by
making an oversimplified model for a real physical circuit. It
can be remedied, however, by an appropriate normalization
technique, such as inserting stray reactance elements into
suitable positions of the circuit.
Example 2. In Eq. (7), if we remove the capacitor (i.e., C
0), then we have

Thus we write the problem symbolically as

x(t)

= f(t, x(t), ),

535

tIR
(24)

If such a solution exists, we refer to Eq. (21) as a solution

passing through x0 at the instant t0. The solution (21) is also
called a trajectory starting from x0 at t t0. It corresponds to
a time response of the state in the state space Rn. Note that
the solution is not only a function of time but also a function
of the initial value as well as the system parameters. In an
autonomous system the time evolution of the state is invari-

i = g1 v + g3 v3
L

(26)

di
= v
dt

By eliminating i, we have the state equation:

L(g1 3g3 v2 )

dv
=v
dt

(27)

536

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

or equivalently
dv
v
=
dt
L(g1 3g3 v2 )

tion of the solution Eq. (21). By considering a small variation

(t) from Eq. (21) as
(28)

Hence at the point v2 g1 /3g3, Eq. (27) or (28) becomes singular; that is, the circuit dynamics could not be defined. Note
that, instead of the inductors current i, the conductors voltage is used for describing Eq. (27). The inductor is connected
in series with the voltage-controlled conductor with noninvertible characteristics. Hence even if the element characteristics are differentiable, the state equation can never be described by the normal form of Eq. (1). The above points are
called impasse points and generally appear by making an
oversimplification of a mathematical model of the circuit. Indeed if we consider a small stray capacitance C in parallel
with the nonlinear conductor, then the state equation is written in the form of Eq. (4).
Continuous Dependence on Initial Condition
and Parameters at a Finite Time
Knowing that the solution Eq. (21) exists for any initial state
and parameters, we can regard the solution Eq. (21) as the
following function:
(t, , ) :

Rn Rm Rn ;

(x0 , )
(t, x0 , )

(29)

Hence we can find the continuity and the differentiability of

the solution with respect to x0 and . Roughly speaking, the
dependence of the solution Eq. (29) on (x0, ) is as continuous
as the function f. Hence we have the following result.
Theorem 2. Suppose the function f(t, x, ) of Eq. (1) is differentiable, then the solution Eq. (21) is also differentiable with
respect to the initial state x0 and system parameter . In fact
the matrices (t, x0, )/x0 and (t, x0, )/ exist and they
satisfy the linear matrix differential equations:
d (t, x0 , )
f(t, (t, x0 , ), ) (t, x0 , )
=
dt
x0
x
x0

(30)

d (t, x0 , ) f(t, (t, x0 , ), ) (t, x0 , )

=
dt

f(t, (t, x0 , ), )
+

(31)

x(t) = (t, x0 , ) + (t)

(34)

and substituting this into Eq. (1), we have

(t,
x0 , ) + (t) = f(t, (t, x0 , ) + (t), )
= f(t, (t, x0 , ), )
+

f(t, (t, x0 , ), )
(t) +
x

where . . . denotes the higher-order terms of (t). Comparing

both sides of this equation and neglecting the higher-order
terms, we have a linear equation
f(t, (t, x0 , ), )
(t)
(t) =
x

(35)

The initial value (t0) 0 at t t0 is the initial variation

from the initial state x0. The same argument is applied to Eq.
(31) for the system parameter .
3. Second- and higher-order derivatives with respect to x0
and can be obtained similarly by differentiating Eqs. (30)
(33). These higher-order derivatives give useful information
when we will consider the bifurcation problem of a specific
steady state.
Structure of Circuit Dynamics
As stated earlier, a circuit usually consists of three kinds of
circuit elements: capacitors, inductors, and resistors. If one of
these types of circuit elements is never used in a circuit, the
circuit dynamics becomes a particular type of dynamical system. For example, dynamics of a circuit containing only capacitors and resistors has a special form called a gradient system. A similar situation occurs in a circuit with another
combination of circuit elements. We illustrate some types of
dynamical systems which arise also in other physical
systems.
Gradient System. A gradient system is a system whose vector field is defined by the gradient of a scalar function of state.
Let F be a scalar function, also called a potential or dissipative function:
Rn R; x
F (x)

F:
with the initial conditions

(36)

A system of the form

(t0 , x0 , )
= In
x0

(32)

(t0 , x0 , )
=0

(33)

respectively, where In is the n n identity matrix. Equations

(30) and (31) are called the linear variational equations with
respect to the initial condition and the system parameters, respectively.
Remark 3. 1. This result can be easily proved by differentiating Eqs. (22) and (23) with respect to x0 and .
2. The variational equation Eq. (30) is derived another way
as follows. Suppose that we want to know a neighboring solu-

x = gradF (x)

(37)

is called a gradient system, where

gradF (x) =

F
x

F
F
, ,
x1
xn

T
(38)

and ( )T denotes the transpose of the derivative vector F/x.

In gradient system, F always decreases along a trajectory
x(t). That is the total time derivative of F is negative or zero:
F dx
F
dF
=
=
dt
x dt
x

F
x

T
0

(39)

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Hamiltonian System, Conservative System, or Lossless System. In classical mechanics we study mainly Hamiltonian
systems. In circuit application, a lossless circuit is described
by this type of equation. Let an energy function H be defined
as
R R R; (x, y)
H(x, y)
n

H:

x =

Following the notation in the figure, we have the state equation:

C1

H
y

H
y =
x

H dx H dy
H
dH
=
+
=
dt
x dt
y dt
x

T
(41)

H
y

H
y

H
x

F (v1 , v2 ) =

R R R; (x, y)
F (x, y)
n

(43)

and let H be an energy function of the form Eq. (40).

A system of the form

H
y

F
x

y =

H
x

F
y

(l = 1, 2)

(45)

v2

C2

Figure 6. RC circuit with nonlinear resistors.

(49)

R2 R2 ;

(v1 , v2 )
1 (v1 , v2 ) = (v2 , v1 )

(50)

R2 R2 ;

(v1 , v2 )
(v1 , v2 ) = (v1 , v2 )

(51)

Hence Eq. (46) is invariant under the composition of the

above transformations:
R2 R2 ;

(v1 , v2 )
2 (v1 , v2 ) = (v2 , v1 )
(52)

Thus the above three linear transformations are expressed by

the following matrices:

1 =

0
1


1
,
0

1
0


0
,
1

2 =

0
1


1
0

(53)

With the identity matrix I2, they form a transformation

group. Under these transformations we have two invariant
subspaces:

ig2
v1

(48)

More generally we can prove that any RC circuit, similarly

any RL circuit, is a dissipative system. In the case of C1
C2 C, Eq. (46) becomes a symmetrical system. That is, Eq.
(46) is invariant under the linear coordinate transformations:

C1

g(v2 )dv2 (47)

and

Example 3. 1. An RC circuit. Consider the circuit shown in

Fig. 6. We assume that the nonlinear conductors g1 and g2 are
voltage-controlled and have the same characteristics as

g1

dF
F dv1
F dv2
=
+
dt
v1 dt
v2 dt


2 
1 F
1 F
+
50
=
C1 v1
C2 v2

2 = 1 :

ig1

v2

(44)

is called a dissipative system. Here for simplicity we define a

typical dissipative system by assuming two states variables
x and y have the same dimension n.

igl = g(vl ) = g1 vl + g3 v3l

g(v1 )dv1 +

Hence Eq. (48) is a kind of gradient system. In fact, F decreases along a trajectory, that is,

1 :

v1

F (v1 , v2 )
dv1
=
dt
v1
F (v1 , v2 )
dv
C2 2 =
dt
v2

=0
(42)

C1

Dissipative System. A dissipative system is a combined system of the above two systems. Let F be a dissipative scalar
function:
n

1
G(v1 v2 )2 +
2

Eq. (46) can be rewritten as

Thus, H is constant along any solution curve of Eq. (41) and

the trajectories lie on the surfaces H constant. This property is called the conservation of energy.

x =

(46)

Defining the dissipative function

is called a Hamiltonian system with n degrees of freedom. In

Hamiltonian system H remains constant along a trajectory of
Eq. (41).

F:

dv1
= g(v1 ) G(v1 v2 )
dt

dv
C2 2 = g(v2 ) G(v2 v1 )
dt

(40)

A system of the form

537

g2

E1 = {(v1 , v2 ) R2 | v1 = v2 }
E2 = {(v1 , v2 ) R2 | v1 = v2 }

(54)

In these subspaces, each solution of Eq. (48) remains in the

same subspace and the dynamics becomes one-dimensional

538

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

References in This Section

systems, that is,

dv
= g(v),
v E1
dt
dv
= g(v) 2Gv,
v E2
C
dt
C

(55)

2. An LC circuit. Consider the circuit discussed in Example

1(2) with R 0. The circuit becomes a lossless circuit, so that
it becomes a Hamiltonian system. In fact we define the Hamiltonian:
H(vC , ) =

v E
1 2
1
v +
F () C sin t
2n C nC
n

(56)

where

F () =
0

LOCAL PROPERTIES OF CIRCUIT DYNAMICS

1
1
1
f () d = a1 2 + a2 3 + a3 4
2
3
4

(57)

then we have Eq. (17) as

dvC
H
1
=
=
f ()
dt

nC
d
H
1
E
=
= vC + sin t
dt
vC
n
n

(58)

1 2 1
1
y + c1 x2 + c3 x4 x(B0 + B cos )
2
2
4

(59)

then we obtain Eq. (20) as

dx
H
=
=y
d
y
dy
H
=
= c1 x c3 x3 + B0 + B cos
d
x

(60)

In both cases, the Hamiltonian is a periodic function in time.

3. An RLC circuit. Equation (11) in Example 1(1) is a dissipative system. To see this, define the energy function:
1
1
H(x, y) = y2 + x2
2
2

The qualitative, geometrical, or topological approach of nonlinear ordinary differential equations is a powerful tool for
understanding the nonlinear phenomena of circuit dynamics.
In this and the following sections we introduce some basic
examples from this approach. For now we consider an autonomous system
x = f(x, ),

On the other hand, if we define

H(x, y) =

For ordinary differential equations there are many excellent

books. We refer to only some of them (1012). For the normal
form of general nonlinear circuits, see Refs. 5 and 13. The
circuit shown in Example 1(1) is found in Refs. 11 and 14,
where in the latter the circuit dynamics Eq. (11) is called the
Bonhoeffer van der Pol equation (BVP equation). The circuit
shown in Example 1(2) is found in Ref. 3. For the impasse
points and related topics, see Refs. 15 and 16. Similar circuit
shown in Example 3(a) is found in Ref. 1 as two dynamos
working in parallel on a common load. For the gradient system, see Ref. 12, and for the Hamiltonian systems, see Refs.
7 and 8.

(61)

x Rn , Rm

(65)

where x Rn is a state vector and Rm is a system parameter. Usually the terms state and phase have the same
meaning. Hence the state space Rn is also called the phase
space. In the two-dimensional case, we say the phase plane
instead of the state plane. Note that Eq. (65) defines the
phase velocity vector field at every point in the phase space.
The phase portrait of Eq. (65) is the set of all trajectories in
the phase space Rn. The phase portrait contains useful information of the behavior of trajectories. We see the number and
types of equilibrium points, their asymptotic behavior when
t , and so on. In practice, only typical trajectories are
illustrated in the portrait to show the behavior schematically.
Equilibrium Point and its Topological Classification
A point at which the phase velocity becomes zero is called an
equilibrium point. The point corresponds to a dc operating
point of a circuit. Hence an equilibrium point x0 Rn is given
by the relation

and the dissipative function:

1
1
1
F (x, y) = 1 x2 + 4 x4 + ky2 By
2
4
2

f(x0 , ) = 0
(62)

then, we have Eq. (17) as

H
F
dx
=

d
y
x
H
F
dy
=

d
x
y

which will be negative for sufficiently large (x, y) R2.

For every equilibrium point the solution

x(t) = x0

(67)

gives a stationary solution of Eq. (65).

(63)
Example 4. 1. Consider Eq. (11) in Example 1(1). Equation
(66) is given by

Hence the energy dissipation along a trajectory is

dH
H dx
H dy
=
+
= (1 x2 + 3 x4 By + ky2 )
d
x d
y d

(66)

f 1 (x0 , y0 ) = y0 + 1 x0 3 x30 = 0
(64)

f 2 (x0 , y0 ) = x0 ky0 + B = 0

(68)

The intersection of these two curves gives a solution of Eq.

(68). Hence by choosing parameters appropriately we see that

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

at most three equilibria exist in Eq. (68). Substituting the

first equation into the second, we find
(1 k1 )x0 + k3 x30 = B

(69)

Hence, if 1 k1, then for B (k1 1) (k1 1)/3k3 Eq.

(69) has three roots. For example, if B 0, then we have
three equilibria:

 

k1 1 1
,
k3
k

k1 1
,
k3

(0, 0),


1
k1 1
,
k3
k

k1 1
k3

(70)

For 1 k1 Eq. (69) has only one equilibrium point.

2. Consider Eq. (13) or Eq. (14) in Example 1(1). If 1 and
3 are positive, then the origin (x, x) (0, 0) in Eq. (13), or
(y, y) (0, 0) in Eq. (14) is the unique equilibrium point of
the systems.
3. Consider the circuit shown in Fig. 7. Using the notation
in the figure we have the circuit equation:

di1
= E 1 R1 i 1 v
dt
di
L 2 2 = E 2 R2 i 2 v
dt
dv
= i1 + i2 g(v)
C
dt

L1

(71)

where the nonlinear characteristics of the conductor G is assumed as

iG (vG ) = g1 vG + g3 v3G ,

g1 , g3 > 0

(72)

Hence the equilibrium point is given by

f 1 (i1 , i2 , v) = E1 R1 i1 v = 0
f 2 (i1 , i2 , v) = E2 R2 i2 v = 0

(73)

f 3 (i1 , i2 , v) = i1 + i2 g(v) = 0
Substituting the first and second equations into the third
equation, we have the following cubic function of v:
f (v) =

E1
E
+ 2
R1
R2


1
1
+
g1 v g3 v 3 = 0
R1
R2

(74)

Hence Eq. (73) has at most three equilibria under appropriate

parameter values.

iG
G

x(t) = x0 + (t)

L2

L1
i1

i2
R1
E1

R2
E2

Figure 7. A three-dimensional oscillatory circuit.

(75)

Substituting Eq. (75) into Eq. (65), we have the linear variational equation as
(76)

where A Df(x0, ) is the Jacobian matrix with respect to x

at x0. Equation (76) gives also the linear approximation of the
original system (65) in the neighborhood of the equilibrium
point x0. Indeed by Taylors expansion we have
f(x0 + , ) = Df(x0 , ) +

1 2
D f(x0 , )( , ) +
2

(77)

It follows that the linear part A Df(x0, ) is a good approximation to the nonlinear function f( , ) near the equilibrium point x x0, and it is reasonable to expect that the
qualitative behavior of Eq. (65) near x x0 will be approximated by the behavior of Eq. (76). This is indeed the case if
the matrix A Df(x0, ) has no zero or pure imaginary eigenvalues. Hence we define an equilibrium point with this condition as a hyperbolic equilibrium point. That is, an equilibrium
point is hyperbolic if none of the eigenvalues of the matrix
A Df(x0, ) have zero real part. The HartmanGrobman
theorem shows that near a hyperbolic equilibrium point, the
nonlinear system of Eq. (65) has the same qualitative structure as the linear system of Eq. (76). That is, by a homeomorphism (continuous mapping with its inverse) h from an open
set U containing x0 of Eq. (65) onto an open set V containing
the origin of Eq. (76), trajectories of Eq. (65) in U map onto
trajectories of Eq. (76) while preserving their orientation by
time. Here qualitative structure, topological property, or
topological type has the same meaning.
Using this result, we can classify topologically hyperbolic
equilibrium point. Let
() = det[In Df(x0 , )] = 0

(78)

be the characteristic equation and let

{1 , 2 , , n } = {i C | det[i In Df(x0 , )] = 0}

(79)

be the eigenvalues, also called the characteristic roots, of

A Df(x0, ). Then the hyperbolic condition is given by
Re(i ) = 0

iC

Once we have an equilibrium point x0, our interest turns

into its stability or the qualitative property of the behavior of
trajectories near x0. To do this let be a small variation from
the equilibrium point:

(t) = A (t)

539

(80)

for all i 1, 2, . . ., n. Now let Eu be the intersection of Rn

and the direct sum of generalized eigenspace of A corresponding to the eigenvalues i such that Re(i) 0. Similarly, let
Es be the intersection of Rn and the direct sum of generalized
eigenspace of A corresponding to the eigenvalues i such that
Re(i) 0. Eu or Es is called the unstable or stable subspace
of A. The HartmanGrobman theorem shows that Eu and Es

540

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

have the following properties:

(a) Rn = Eu Es ,

is called the orbit of Eq. (65) through the initial state x0. Asymptotic behavior in the future or in the past is also defined
as

A(Eu ) = Eu , A(Es ) = Es

(b) dim Eu = #{i | Re(i ) > 0},

(81)

dim Es = #{i | Re(i ) < 0}

(x0 ) = (Orb(x0 )) = lim(x0 ) =


(t, x0 , )
0 t


(t, x0 , )
(x0 ) = (Orb(x0 )) = lim(x0 ) =

(86)

where # indicates the number of the elements contained in

the set . The topological type of a hyperbolic equilibrium
point is then determined by the dim Eu or dim Es. Let kO
denotes the topological type of a hyperbolic equilibrium point
with dim Eu k. That is, kO denotes the type of a k-dimensionally unstable hyperbolic equilibrium point. Then for the
n-dimensional autonomous system Eq. (65) we have n 1
topologically different kinds of hyperbolic equilibria. Their
types are as follows:

They are called the limit set and the limit set of x0 or
Orb(x0), respectively. Now suppose that p Rn be a sink.
Then the set of all point x0 whose limit set is p is called the
basin of attraction or the domain of attraction of the attractor p:

{0 O, 1 O, , n O}

Basin(p) = {x Rn | lim(x) = p}

(82)

Usually a completely stable equilibrium point 0O is called a

sink, a completely unstable equilibrium point nO is called a
source, and others are called saddles.
Remark 4. 1. Stability of equilibrium point. The stability of
any hyperbolic equilibrium point x0 Rn is determined by the
signs of the real parts of the characteristic roots Eq. (79). A
hyperbolic equilibrium point x0 Rn is called asymptotically
stable if and only if it is a sink: Re(i) 0 for all i 1, 2,
. . ., n. A hyperbolic equilibrium point is unstable if it is a
source or a saddle. The stability of nonhyperbolic equilibrium
point is more difficult to determine. The definition of the stability due to Lyapunov is useful for this purpose. Let (t, u,
) be a solution of Eq. (65) with (0, u, ) u. An equilibrium
point x0 is stable (in the sense of Lyapunov) if for every 0
there exists a 0 such that for every u B(, x0) we have
(t, x0, ) B(, x0) for all t 0, where B(d, x0) denotes an
open disk with the radius d: B(d, x0) u Rn u x0
d. An equilibrium point x0 is unstable if it is not stable. And
x0 is asymptotically stable if it is stable and limt (t, x0, )
x0. An asymptotic stable equilibrium point is the simplest
attractor of dynamical systems.
2. Stable and unstable manifolds of a hyperbolic equilibrium
point. The subsets leaving from and approaching to a hyperbolic equilibrium point x0 are called the unstable manifold
Ws(x0) and the stable manifold Wu(x0), respectively. They are
defined as
t

(87)

If a system has several stable equilibria as attractors, then

each attractor has its own basin of attraction. The state space
considered as the set of initial states is divided into their basins of attractors. Hence the final steady state realized is completely determined by the basin in which we specify an initial
state. This is the simplest nonlinear phenomenon of the existence of multistable states.
Example 5. 1. Two-dimensional hyperbolic equilibria. We
have three different types of hyperbolic equilibria: 0O, 1O, 2O.
Assume that the characteristic equation Eq. (78) is given by
() = det[I2 Df(x0 , )] = 2 + a1 + a2 = 0

(88)

Then we have the following result:

(a) If a1 0 and a2 0, then the equilibrium point x0
R2 is a sink 0O.
(b) If a2 0, then the equilibrium point x0 R2 is a saddle 1O.
(c) If a1 0 and a2 0, then the equilibrium point x0
R2 is a source 2O.
These relations are illustrated in Fig. 8. Each type of hyperbolic equilibrium point is also classified by the location of its

W u (x0 ) = {u Rn | lim (t, u, ) = x0 }

W s (x0 ) = {u Rn | lim (t, u, ) = x0 }

0 t

(83)

Eu and Es defined in Eq. (81) are tangent spaces to Wu(x0) and

Ws(x0) at x0, and
dimEu = dimW u (x0 ),

dimEs = dimW s (x0 ),

W u (x0 ) W s (x0 ) = x0

(84)

3. Let (t, x0, ) be a solution of Eq. (65) with (0, x0, )

x0. The curve traced out the trajectory (t, x0, ):
Orb(x0 ) = {x Rn | x = (t, x0 , ), t R}

(85)

a2

2O

0O

a1

1O

Figure 8. Topological classification of equilibria: two-dimensional

case.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Im

Im

541

y2

Im

Im

Re

2 1

Re

(a)

Re

(b)

y1

Re

(c)

Figure 9. Distribution of the characteristic roots for a sink.

(a)

(b)

Figure 11. Distribution of the characteristic roots for (a) a saddle

and (b) a phase portrait of a saddle.

characteristic roots in the plane of complex numbers. Figure

9 shows the typical locations of a sink. Corresponding to these
roots, we have the phase portraits shown in Fig. 10. The equilibrium point of each case is called a node in Fig. 9(a), a spiral
or a focus in Fig. 9(b), and a degenerate focus in Fig. 9(c).
Note that for the multiple roots, we have two types of degenerate focuses shown in (c-1) and (c-2) in Fig. 10. Figure 11
shows the location of characteristic roots for a saddle point (a)
and its phase portrait (b). In a two-dimensional system, two
cases occur for a nonhyperbolic equilibrium point: (a) characteristic roots are pure imaginary numbers, and (b) one root
is zero. These nonhyperbolic equilibria are called center and
degenerate node, respectively, (see Fig. 12).
2. Consider the van der Pol equation in Example 1(1). Equation (13) is rewritten as

The only equilibrium point is the origin. The characteristic

equation of the origin is given by




() = 
 1


1 
 = 2
+ 1 = 0

Hence the origin is a source 2O, that is, a two-dimensionally

unstable hyperbolic equilibrium point.
3. The existence of multistable states. Consider Eq. (46)
with C1 C2 C:

x = x x3 (x y)

(92)

y = y y3 (y x)

x = y

(89)

y = x +
(1 x2 )y

where we put

where

= 1 > 0,

y2

v1 =

=3 3 >0
1

(90)

C
x,
g3


v2 =

C
y,
g3

y1


A = Df(x0 , y0 ) =

(a)

(b)

y2

y2

y1

g1
> 0,
C

G
>0
C

(93)

These two equations have the mirror reflection symmetry

with respect to the invariant subspaces given by Eq. (54), that
is, x y and x y. In the case of 4, 1 we have nine
equilibria as shown in Fig. 13. Note that the stationary points
of the dissipative function in Eq. (47) give these equilibria
(see Fig. 14). The Jacobian matrix at an equilibrium point
(x0, y0) is given by

y2

y1

(c-1)

(91)

3x20

3y20

(c-2)

y1

Figure 10. Phase portrait of a sink. (a) Node, (b) focus, (c) degenerate focus.

(a)

(94)

y2

y2

y1

y1

(b)

Figure 12. Phase portrait of nonhyperbolic equilibrium point. (a)

Center, (b) degenerate node.

542

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

2
0O

1O

1O

0O

0O

1O

0O

2O

1
2

0O

2O

1O

1O

0O

1O

1 1O

0
1

0O

3 x

0O

1O

Figure 13. Equilibria for Eq. (92) with 4 and 1.

All equilibria are hyperbolic and their types are easily calculated from Eq. (94). The phase portrait is illustrated in Fig.
15. Stable manifolds approaching four saddle points separate
the phase plane into four regions in which one sink is situated. That is, the phase plane is divided into four basins of
attractions whose boundaries are stable manifolds of the saddle points.

Figure 15. Phase portrait of Eq. (92) with 4 and 1.

Periodic State of Autonomous Systems

Consider an autonomous system
x = f(x, ),

References in This Section

A qualitative approach of ordinary differential equations or
dynamical systems is found in Refs. 1, 4, 7, and 9. We recommend Ref. 9 as a good source for this topic. Topological classification of equilibria is found in Refs. 1012.
PERIODIC STATE AND ITS STABILITY
Periodic state plays the central role in nonlinear circuit dynamics. A basic tool for studying periodic state and its related
property is the Poincare map by which a continuous time dynamical system reduces to a discrete time dynamical system.
A periodic state is then transformed to a fixed point of the
Poincare map. Hence a similar argument to equilibria will be
developed for fixed points.

x Rn , Rm

(95)

where x Rn is a state vector and Rm is a system parameter. Suppose that Eq. (95) have a periodic solution (t, x0, )
with period L. The orbit
C = Orb(x0 ) = {x Rn | x = (t, x0 , ), t [0, L]}

(96)

forms a closed curve in the state space Rn. This is an invariant set of Eq. (95). That is,
(t, C, ) = C

(97)

A small perturbation or variation (t) from the periodic solution obeys the following variational equation:
(t) = A(t) (t)

(98)

where
A(t) = Df((t, x0 , ), ) =

f
((t, x0 , ), )
x

(99)

is the Jacobian matrix with respect to x. By the periodicity

of (t, x0, ), the matrix A(t) becomes a periodic matrix with
the same period L:
F(x, y)

A(t) = A(t + L),

x
Figure 14. Surface of the dissipative function, Eq. (47). Each stationary point corresponds to the equilibrium point in Fig. 13.

tR

(100)

Hence Eq. (98) is a linear equation with periodic coefficients.

Similar to the hyperbolic equilibrium point, we can discuss
the hyperbolicity of periodic solution. We will study this by
example.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

2O

Figure 16. Phase portrait of the van der Pol equation, Eq. (89), with
0.5 and 1. The closed curve C indicates a stable limit cycle.

Example 6. 1. Self-excited oscillation. Consider the van der

Pol equation [Eq. (89)] in Example 5(2). Figure 16 shows the
phase portrait of Eq. (89) with 0.5, 1.0. We see that
the origin is a source and a closed curve C which is the
limit set of any point in the phase plane except the origin.
The closed curve C is the orbit of the periodic solution with
an initial state in C. As we will see later, the periodic solution
is orbitally stable. In a two-dimensional autonomous system,
an isolated closed orbit is called a limit cycle. Thus the van
der Pol equation has a unique stable limit cycle. This corresponds to a self-excited oscillatory phenomenon in circuit dynamics. Note that we could not solve Eq. (89) explicitly so
that an appropriate numerical algorithm, such as the fourthorder RungeKutta method, is used to accomplish the phase
portrait.
2. Hard oscillation. Consider the equation
x = y

(101)

y = x
(1 x2 + x4 )y

Equation (101) is the van der Pol equation with a hard characteristic. That is, the nonlinear characteristic is assumed to

543

be a fifth-order polynomial. Figure 17 shows the phase portrait for 0.2, 3.5. Two limit cycles C1 and C2, one of
which is stable and another unstable, exist and the origin is
a sink 0O in this case. Hence we have two attractors: a stable
limit cycle C1 and a stable equilibrium point 0O. The basin of
the latter equilibrium point is the region surrounded by the
unstable limit cycle cycle C2. The outer region of the unstable
limit cycle C2 is then the basin of the stable limit cycle C1.
According to the initial state we specify, the final steady state
becomes the sink 0O or the stable limit cycle C1. This shows
an example of the existence of multistable states. In the circuit, if the initial state is small, then the oscillatory state is
never realized. To observe an oscillatory state corresponding
to the stable limit cycle we must give an initial state large
enough to enter the basin of the limit cycle C1. This oscillatory
process is called a hard oscillation. On the other hand, the
process stated in Example 6, item 1, is called a soft oscillation.
Poincare Map for Autonomous Systems
The definition of a Poincare map, or first return map, for a
periodic solution is quite simple. Suppose that Eq. (95) has a
periodic solution (t, x0, ) through the point x0. We choose a
hypersurface Rn to intersect transversally the periodic
orbit at x0, Then for each point x1 sufficiently near x0,
the solution through x1 will return to again at a point x2
near x0 (see Fig. 18). The mapping x1 x2 is called the
Poincare map T. That is, T is defined as
T:

 ;

x1
x2 = T (x1 ) = ( , x1 , )

(102)

where is the return time and depends on the initial point

x1. The hypersurface is locally defined and is called a local
cross section or a Poincare section. Assume that is described as
 = {x Rn | q(x) = 0}

(103)

where q is a scalar function from Rn to R. The transversality

condition is then expressed by
q(x0 )
f(x0 , ) = f(x0 , ) grad q(x0 ) = 0
x

(104)

Note that dim n 1. Once the Poincare map T is defined,

we have a recurrent formula or difference equation of the

Rn
C1

(t, x1, )
0O

x2

x2 = ( (x1), x1, )

C2

x0
x1

x2 = (L, x0, )

(t, x0, )

Figure 17. Phase portrait of a hard oscillator equation, Eq. (101),

with 0.2 and 3.5. Closed curves C1 and C2 indicate a stable
and an unstable limit cycle, respectively.

Figure 18. Periodic orbit and Poincare map. Local cross section is
the hypersurface .

544

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

form
xk+1 = T (xk ),

xk ,

k = 1, 2, . . .

(105)

By the uniqueness theorem of differential equations the map

T has a unique inverse map T1. Moreover, if the vector field
(95) is differentiable, T and T1 is also differentiable; that is,
T is a diffeomorphism on near x0. Because x0 is on the periodic orbit, we have
T (x0 ) = x0

(106)

That is, x0 is a fixed point of T. If L is the period of the periodic solution, then the return time becomes (x0) L.
Stroboscopic Mapping: Poincare Map
for Periodic Nonautonomous Systems

x = f(t, x, ), x Rn , Rm

(107)

where x Rn is a state vector and Rm is a system parameter. We assume that f is periodic in t with period 2:
f(t, x, ) = f(t + 2, x, )

(108)

for all t R. Equation (107) describes a class of dynamic nonlinear circuits with a periodic forcing term. A nonlinear circuit with an ac operation is a typical example of this class.
Without loss of generality, we assume that the period of the
external forcing is 2. Suppose that Eq. (107) has a solution
x(t) (t, x0, ) with x(0) (0, x0, ) x0. This time we
have the periodic property equation, Eq. (108). Hence for every 2 instance the vector field equation, Eq. (107), returns
the same value so that a stroboscopic sampling of the solution
can be achieved under the fixed vector field. That is, we can
define the stroboscopic mapping as the Poincare map (see Fig.
19):
T:

R R ;
n

x0
x1 = T (x0 ) = (2, x0 , )

(109)

If a solution x(t) (t, x0, ) is periodic with period 2, then

the intial state x0 is a fixed point of T:
T (x0 ) = x0

(110)

Rn
x0

(t, x0, )

Hyperbolic Fixed Point and Its Stability

Now we consider the qualitative property of a fixed point of
the Poincare map T. In the following for the notational convenience we consider T defined by Eq. (109). The same discussion is applied to Eq. (102). Suppose that x0 Rn is a fixed
of T. The characteristic equation of the fixed point x0 is defined by
() = det(In DT (x0 )) = 0

Consider a nonautonomous system

If x(t) is a periodic solution with period 2k, then the point

x0 is a periodic point of T with period k such that Tk(x0) x0
and Tj(x0) x0 for j 1, 2, . . ., k 1. Hence there are always k points x0, x1 T(x0), . . ., xk1 Tk1(x0) which are
all fixed points of Tk. Thus the behavior of periodic solution of
Eq. (107) is reduced to the behavior of fixed or periodic points
of the map T.

Rn

where DT(x0)) T(x0)/x0 denotes the derivative of T. Near

x0 the map T is approximated by its derivative DT(x0). This
is indeed possible if the fixed point is hyperbolic. Here we call
x0 a hyperbolic fixed point of T, if DT(x0) is hyperbolic, that
is, all the absolute values of the eigenvalues of DT(x0) are
different from unity. Let x0 be a hyperbolic fixed point of T
and let Eu be the intersection of Rn and the direct sum of
generalized eigenspace of DT(x0) corresponding to the eigenvalues i such that i 1. Similarly, let Es be the intersection of Rn and the direct sum of generalized eigenspace of
DT(x0) corresponding to the eigenvalues i such that i 1.
Eu or Es is called the unstable or stable subspace of DT(x0).
The map version of the HartmanGrobman theorem shows
that Eu and Es have the following properties:

(a) Rn = Eu Es ,

DT (Eu ) = Eu ,

(b) dim Eu = #{i | |i | > 1},

x1

DT (Es ) = Es

dim Es = #{i | |i | < 1}

(112)

Let Lu DT(x0)Eu and Ls DT(x0)Es). Then the topological

type of a hyperbolic fixed point is determined by (1) the dim
Eu (or dim Es) and (2) the orientation preserving or reversing
property of Lu (or Ls). The latter condition is equivalent to the
positive or negative sign of det Lu (or det Ls) and is the additional condition comparing with a hyperbolic equilibrium
point. We refer a hyperbolic fixed point with det Lu 0 to a
direct type (i.e., D-type) and refer a hyperbolic fixed point
with det Lu 0 to an inverse type (i.e., I-type). Note
that DT(x0) is an orientation preserving map, that is, det
DT(x0) 0. Combining the dimensionality, we have 2n topologically different types of hyperbolic fixed points. These types
are
{0 D, 1 D, . . . , n D; 1 I, 2 I, . . . ,

t=0

(111)

n1 I}

(113)

where D and I denote the type of the fixed point and the subscript integer indicates the dimension of the unstable subspace: k dim Eu. Usually a completely stable fixed point 0D
is called a sink, a completely unstable fixed point nD is called
a source, and others are called saddles.

t = 2
Figure 19. Stroboscopic mapping. Poincare map for a periodic nonautonomous system.

Remark 5. 1. The classification stated above is also obtained

from the distribution of the eigenvalues, also called the characteristic multipliers, of Eq. (111). That is, D and I correspond

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

to the even and odd number of characteristic multipliers on

the real axis (, 1), and k indicates the number of characteristic multipliers outside the unit circle in the complex
plane. The distribution can be checked by the coefficients of
Eq. (111).
2. The derivative DT(x0) T(x0)/x is obtained from the
solution of the variational equation with respect to the initial
state of the periodic solution x(t) (t, x0, ) with x(0) (0,
x0, ) x0. Consider the nonautonomous case, Eq. (107). We
have the identity relation:
(t,
x0 , ) = f(t, (t, x0 , ), )
(0, x0 , ) = x0

(114)

Differentiating these relations with respect to the initial

state, we have

d (t, x0 , )
f(t, (t, x0 , ), ) (t, x0 , )
=
dt
x0
x
x0
(0, x0 , )
= In
x0

(t, x0 , )
,
x0

(115)

(122)

This means that (L) has the unity multiplier with the eigenvector:
(0,

x0 , ) = f(x0 , )

(123)

From this property the derivative of the Poincare map defined

by Eq. (102) has at least one unity multiplier.
4. Stable and unstable manifolds of a hyperbolic fixed point.
The subsets leaving from and approaching a hyperbolic fixed
point x0 are called the unstable manifold, Ws(x0), and the stable manifold, Wu(x0), respectively. They are defined as

W s (x0 ) = {u Rn | lim T k (u) = x0 }

(124)

Eu and Es defined in Eq. (112) are tangent spaces to Wu(x0)

and Ws(x0) at x0, and

dim Eu = dimW u (x0 ),

dim Es = dimW s (x0 ),

(125)

W u (x0 ) W s (x0 ) = x0
(0) = In

(116)

T (x0 )
(2, x0 , )
=
= (2 )
x0
x0

(117)

From Liouvilles theorem we have

det DT (x0 ) = det(2 )

= det(0)exp

 

L
f( , ( , x0 , ), )
d
trace
(118)
x
0




L
f( , ( , x0 , ), )
d > 0
= exp
trace
x
0
Thus T is an orientation preserving diffeomorphism.
3. In an autonomous system, Eq. (95), a periodic solution
always has at least one characteristic multiplier that is equal
to unity. Indeed, a periodic solution satisfies the relation
(t,
x0 , ) = f((t, x0 , ), )

(119)

Differentiating by t yields
(t,
x0 , ) =

(L,

x0 , ) = (L)(0,

x0 , ) = (0,

x0 , )

From the definition of the Poincare map, we obtain

DT (x0 ) =

Hence, using Eq. (121) and the periodicity of the solution, we

have

W u (x0 ) = {u Rn | lim T k (u) = x0 }

This is the matrix version of the variational equation with

respect to the initial state. We call the solution the principal
fundamental matrix solution and write
(t) =

545

f((t, x0 , ), )
(t,
x0 , ) = A(t)(t,
x0 , ) (120)
x

Hence (t, x0, ) is a solution of the variational equation, Eq.

(98). Let the principal fundamental matrix solution be (t),
then (t, x0, ) is expressed by
(t,
x0 , ) = (t)(0,

x0 , )

(121)

Thus stable and unstable manifolds have global information

of the phase portrait of the Poincare map T. In the two-dimensional case a 1D or 1I fixed point has a stable invariant
curve and an unstable invariant curve, which are also called
branch and branch of the fixed point, respectively.
5. Phase portrait for the Poincare map, Eq. (109). Similar
to the phase portrait of an autonomous system, we can define
the phase portrait of the Poincare map. Suppose that a discrete time dynamical system is defined by Eq. (109). We define the point set, called the orbit, through x0:
Orb(x0 ) = {xk Rn | xk = T k (x0 ), k = , 1, 0, 1, }
(126)
A fixed point x0 T(x0) has a single-point orbit Orb(x0)
x0. Similarly, a k-periodic point x0 Tk(x0) has the orbit
Orb(x0) x0, x1, , xk1. An orbit is an invariant set in
Rn:
T (Orb(x0 )) = Orb(x0 )

(127)

The stable and unstable manifolds defined by Eq. (124) are

other examples of an invariant set of T. A phase portrait of
the Poincare map T is then the set of all orbits in the phase
space Rn. We illustrate schematically some typical orbits and
invariant sets to show the global structure of the phase space.
6. Numerical computation of hyperbolic fixed point. A hyperbolic fixed point can be found by Newtons method as follows.
Let Eq. (110) be the form
F(x) = x T (x) = 0

(128)

Then from Eq. (117) the Jacobian matrix becomes

DF(x) = In DT (x) = In (2 )

(129)

546

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

This matrix is nonsingular if a fixed point is hyperbolic.

Hence Newtons iteration

x(k+1) = x(k) + h,
DF(x

(k)

)h = F(x

k = 0, 1, 2,
(k)

(130)

S2

1D

works well from an appropriate initial guess x(0).

Example 7. 1. Two-dimensional hyperbolic fixed points. We

have four different types of hyperbolic fixed points: 0D, 1D, 1I,
2D; they are called a completely stable, a directly unstable, an
inversely unstable, and a completely unstable fixed point, respectively. They are obtained under the following conditions.
Let Eq. (111) be given by
() = det[I2 DT (x0 , )] = 2 + a1 + a2 = 0

S1

(131)
2

Then we have:
(a) If 0 a2 1, 0 (1), 0 (1), then the hyperbolic
fixed point is 0D,
(b) If 0 a2, 0 (1), then the hyperbolic fixed point is
1D,
(c) If 0 a2, 0 (1), then the hyperbolic fixed point is
1I,
(d) If 1 a2, 0 (1), 0 (1), then the hyperbolic fixed
point is 2D.
These relations are illustrated in Fig. 20.
2. Periodic solutions of Duffings equation. Consider the following Duffings equation [cf. Eq. (20)]:
x = y

(132)

y = 0.1y x3 + 0.3 cos t

Figure 21 shows the phase portrait of the Poincare map T.

Equation (132) has three periodic solutions: a nonresonant solution S1, a resonant solution S2, and an unstable solution
1D. The former two solutions are sinks, and the latter a directly unstable saddle. These periodic trajectories are shown
by closed dotted curves. Two curves indicated and show
the unstable invariant curve Wu(1D) and the stable invariant
curves Ws(1D) of the saddle fixed point 1D. The branch is the
boundary curve of two basins of the attractors S1 and S2. By
the numerical computation in Remark 5(6), the location (x, y)
of the three fixed points is found to be S1(0.3228, 0.0360),
S2(1.1381, 0.7446), and 1D(0.9170, 0.3812).

(1) = 0

(1) = 0
2D

1
0D

Harmonic Resonance in Duffings Equation

Nonlinear resonance occurs typically in Duffings equation.
The simplest resonant phenomenon is a harmonic resonance.
It is observed when the frequency of a free harmonic oscillator
is nearly equal to that of an injected external periodic signal.
In the following we will discuss this phenomenon by using an
analytical approach: the perturbation method and the averaging method.
Perturbation Method. Let us consider the periodic solution
of Duffings equation:
x +
x + 2 x +
cx3 = B cos t

(133)

where is a small parameter. Rewriting this equation as

x + 2 x = B cos t
( x + cx3 )

(134)

we see that Eq. (133) is a quasilinear system. Hence we will

find periodic solutions by the standard perturbation method.
Assume that a periodic solution is expressed in the formal
power series of as
x(t) = x0 (t) +
x1 (t) +
2 x2 (t) +
3 x3 (t) +

(135)

Substituting Eq. (135) into Eq. (134) and equating the same
power of , we have

a2

1D

Figure 21. Phase portrait of the Poincare map defined by Eq. (132).
Closed dotted curves indicate periodic solutions.

0:

x0 + 2 x0 = B cos t

1:

x1 + 2 x1 = x0 cx30

x2 +  x2 =

1I

a1

Figure 20. Topological classification of fixed points: two-dimensional case.

3cx20 x1

(136)

x1

From perturbation theory, if Eq. (136) has an isolated periodic

solution, then for sufficiently small there exists the periodic
solution in Eq. (134). Hence to find the periodic solution we
will consider two cases: a nonresonant case and a resonant
case, separately.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Nonresonant Case Where 1. Solving Eq. (136) consecutively, we have

B
cos t
2 1
B
3cB3
sin
t

cos t
x1 (t) = 2
( 1)2
4(2 1)4
cB3
cos 3t

2
4( 1)3 (2 9)

is nonsingular at this root, then Eq. (142) has a periodic solution

x1 (t) =M1 cos t + N1 sin t

x0 (t) =

(138)

Note that a indicates a measure of the frequency difference

between free and external frequencies. Hence the resonant
case Eq. (134) becomes
x + x =
(b cos t + ax x cx3 )

0 : x0 + x0 = 0
(140)

By solving the first equation of Eq. (140), we have

x0 (t) = M0 cos t + N0 sin t

(141)

where M0 and N0 are unknown coefficients. They are determined as follows: Substituting Eq. (141) into the second equation of Eq. (140), we have
 !

3
x1 + x1 = M0 + a cr2 N0 sin t
4


!
3 2
+
a cr M0 N0 + b cos t
4
(142)
1
2
2
+ c(N0 3M0 )N0 sin 3t
4
1
+ c(3N02 M02 )M0 cos 3t
4
where r2 M02 N02. Equation (142) has a periodic solution if
and only if the following conditions are satisfied:


3
P(M0 , N0 ) = M0 + a cr2 N0 = 0
4


(143)
3
Q(M0 , N0 ) = a cr2 M0 N0 + b = 0
4
When a solution (M0, N0) of Eq. (143) is an isolate root, i.e.,
the Jacobian matrix:

P
M
0

Q
M0

P
N0

Q
N0

3
a cr2
4

2
+

r2 = b 2

(146)

(139)

Now we will try to find the periodic solution in the form of

Eq. (135). Substituting Eq. (135) into Eq. (139), we find

1 : x1 + x1 = b cos t + ax0 x0 cx30

(145)

where M1 and N1 are still unknown coefficients. Thus Eq.

(143) determines the first term of Eq. (135), called the generating solution of the first equation of Eq. (140). Although
higher-order terms of of Eq. (135) have little effect on this
solution, the generating solution (i.e., the zeroth order approximate solution) determines the behavior of the periodic
solution, Eq. (135). From Eq. (143) we find the relation

This simple relation gives then the amplitude relationship or

frequency relationship of the harmonic resonance. Figure 22
shows an amplitude characteristic of Eq. (146)that is, the
relationship between b and rin the case where a c 1.0.
Also plotted in Fig. 23 is a frequency response of the harmonic
oscillationthat is, the relationship between a and r in the
case where c 1.0 and 0.2. Thus we see that there are
three kinds of periodic solutions under certain values of b, a,
and r. We will return these characteristics after the discussion of their stability.
Stability Analysis. After finding a periodic solution of the
form Eq. (135), we will study the stability of the periodic solution. Let the periodic solution be
x(t) = x0 (t) +
x1 (t) +
2 x2 (t) +
3 x3 (t) + = (t)

x(t) = (t) + (t)

(148)

0O

1.4

= 0

1.2

0.1 0.2 0.3 0.4 .5

0
0.6

1.0

0.7

1O

0.8
0.6
0.4

0O

0.2
0

(144)

(147)

For a small variation

B =
b

1
c(N02 3M02 )N0 sin 3t
32
1

c(3N02 M02 )M0 cos 3t

32

(137)

Thus for the nonresonant case we have a unique periodic

state in the form of Eq. (135).
Resonant Case Where 1. As 1, we put
1 2 =
a,

547

0.2

0.4
b

0.6

0.8

1.0

Figure 22. Amplitude characteristic curves of Eq. (146).

548

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

where

2.0
0O

b=

1.5

a1 = { (1) (2 ) + (2) (2 )} = 2
{1(1) (2 ) + 1(2) (2 )}

2 {2(1) (2 ) + 2(2) (2 )}

1.0
0.5

a2 = (1) (2 ) (2) (2 ) (2) (2 ) (1) (2 )

= 1 +
{1(1) (2 ) + 1(2) (2 )}

1O

+
2 {2(1) (2 ) + 2(2) (2 ) + 1(1) (2 )1(2) (2 )

1.0
r

1(2) (2 )1(1) (2 )} +

b = 1.0

Hence the conditions stated in Example 7(1) become

0.5

0.5

0.3

0O

0.2

(1) = 1 a1 + a2 = 4 +
{ } + > 0

0.1
0

(155)

(1) = 1 + a1 + a2

2.0

1.0

=
2 {1(1) (2 )1(2) (2 ) 1(2) (2 )1(1) (2 )} +
3 { } +

3.0

a2 = 1 +
{1(1) (2 ) + 1(2) (2 )} +

(156)

Figure 23. Frequency characteristic curves of Eq. (146).

where
the variational equation becomes

1(1) (2 )

+ =
{3c( (t))2 + }

(149)

Hence we calculate the fundamental solutions of Eq. (149),

that is, the solutions

(1) (t) = 0(1) (t) +

1(1) (t) +
2 2(1) (t) +

(2)

(t) =

0(2) (t)

1(2) (t)

2 2(2) (t)

k(1) (0)
k(2) (0)

= k(1) (0) = 0

(150)

with the initial conditions

0(1) (0)
0(2) (0)

0(1) (0)
0(2) (0)

= 1,
= 0,

= 0,
= 1,

= k(2) (0) = 0

(k = 1, 2, . . .)
(151)

Substituting Eq. (150) into Eq. (149) and equating the same
power of , we have

0(1)
0(2)
1(1)
1(2)

+
+
+
+

0(1)
0(2)
1(1)
1(2)

=0
=
{3c( (t))2 0(1) + 0(1) }

(152)

=
{3c( (t))2 0(2) + 0(2) }

0(1) = cos t,
0(2) = sin t
t


3c( ( ))2 cos + sin sin(t )d
1(1) (t) =
1(2) (t) =

0
2

=
0

1(2) (2 ) =
1(2) (2 ) =

0
2

[3c( ( ))2 cos + sin ] sin d =

[3c( ( ))2 cos + sin ] cos d =

2

Q
M0

[3c( ( ))2 sin cos ] sin d =

[3c( ( ))2 sin cos ] cos d =

P
M0

P
N0

Q
N0
(157)

From the first equation of Eq. (156) we see that an inversely

unstable periodic solution cannot exist in Eq. (139). Substituting Eq. (157) into Eq. (156) we obtain the relations

(1) =
2 det A +
3 { } +
a2 = 1 +
trace A +
3 { } +

(158)

where

P
M0
A=
Q

M0

P
N0

(159)

N0

Finally from Eqs. (143) and (146), we have

trace A = 2 < 0
det A = a2 + 2 3acr2 +

(153)

3c( ( ))2 sin cos sin(t )d

The characteristic equation is given by


 (1) (2 )

() = 
 (1) (2 )

=0

Hence the solutions of Eq. (152) can be found as

1(1) (2 )


(2) (2 ) 
 = 2 + a 1 + a 2 = 0
(2) (2 )
(154)

27 2 4
db2
c r =
16
dr2

(160)

Note that from the first equation of Eq. (160), we see that no
completely unstable type of periodic solution exists in Eq.
(139). Hence the stability of the periodic solution is determined as follows:
(a) If det A 0, that is, db2 /dr2 0, then the periodic
solution is a completely stable type: 0D.
(b) If det A 0, that is, db2 /dr2 0, then the periodic
solution is a directly unstable type: 1D.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Now we return to the characteristic curves shown in Fig.

22. Considering the above conditions we find the completely
stable portion and the directly unstable portion on each curve
const. The vertical tangency of the curves results at the
stability limit, which is indicated by the thick curve. Starting
from the small b of Fig. 22, the amplitude r increases slowly
with increase of b. When the curve comes to the point with
vertical tangency, a slight increase b will cause a discontinuous jump of r to the upper portion of the curve. With decreasing b, the amplitude r jumps down from the upper portion to
the lower portion at another point with vertical tangency.
Thus the process exhibits a hysteresis phenomenon (see Fig.
24). We refer to the periodic solution with larger amplitude
as the resonant state and to the other with smaller amplitude
as the nonresonant state. Similar hysteresis phenomenon is
observed for the frequency characteristic curves illustrated in
Fig. 23.
Averaging Method. Averaging method is another conventional method for studying periodic solution of quasilinear
systems. Consider again Eq. (139) in normal form as
x = y
y = x +
(b cos t + ax y cx3 ) = x +
G(x, y,
, t)

(161)

We assume an approximate periodic solution of Eq. (161) as

x(t) = u(t) cos t + v(t) sin t

(162)

y(t) = u(t) sin t + v(t) cos t

where u(t) and v(t) will be found slowly varying functions.

Substituting Eq. (162) into Eq. (161), we have
u(t)

=
G(u cos t + v sin t, u sin t + v cos t,
, t) sin t
v(t)
=
G(u cos t + v sin t, u sin t + v cos t,
, t) cos t

(163)

Averaging the right-hand side of Eq. (163), we obtain

2 0
G(u cos + v sin , u sin + v cos ,
, ) sin d
(164)
2

v(t)
=
2 0
G(u cos + v sin , u sin + v cos ,
, ) cos d

u(t)

0O

1O

1
S
2

R
N

2
Figure 25. Phase portrait of Eq. (165) with a c 1, 0.1, and
b 0.3.

That is, we have an autonomous equation

 !
3

u + a cr2 v = P(u, v)
u =
2
4
2


!
3

a cr2 u v + b = Q(u, v)
v =
2
4
2

(165)

where P(u, v) and Q(u, v) are given in Eq. (143). An equilibrium point of Eq. (165) gives a periodic solution Eq. (162).
Hence we have the correspondence between the equilibria of
Eq. (165) and the periodic solutions of Eq. (161). Moreover,
the phase portrait of Eq. (165) gives information about global
behavior of the solutions of Eq. (161). Figure 25 shows a
phase portrait of the case where three equilibria exist in Eq.
(165). We see two sinks R and N corresponding to the resonant and nonresonant solutions, respectively. We also illustrate a saddle S whose stable manifold forms the basin
boundary of two attractors.
References in This Section
The Poincare map stated in this section is discussed in any
books on nonlinear dynamics; for example, see Refs. 4, 9, and
12. Hyperbolicity of fixed point of the Poincare map is introduced in Refs. 7 and 12. The classification of the hyperbolic
fixed point is found in Refs. 1721. Various numerical methods are well treated in Refs. 22 and 23. Various nonlinear
resonancesthat is, subharmonic resonance and higher harmonic resonance as well as harmonic resonanceare treated
in the standard books on nonlinear oscillations (see Refs. 3
6). For the perturbation method stated in the last paragraph,
see Ref. 24. Practical applications of the averaging method
are found in Ref. 3.
BIFURCATIONS OF EQUILIBRIA AND PERIODIC STATES

0O

0 b = b1

549

b = b2

Figure 24. Jump and hysteresis phenomenon on an amplitude characteristic curve.

When the system parameter varies, the qualitative properties of the state space may change at 0. We may observe
the generation or extinction of a couple of equilibria or fixed
points, the branching of new equilibria or fixed or periodic
points, and the change of a topological type of equilibrium

550

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

point or fixed point. We call these phenomena the bifurcation

of equilibrium point or fixed point and call 0 a bifurcation
value. These bifurcations occur when the hyperbolicity is violated at 0, which corresponds to the critical distribution
of the eigenvalues or multipliers of the characteristic equation. Typical bifurcation is observed under the single bifurcational condition and is called generic or codimension one bifurcation. Mathematically, we have to discuss the normal
form theory of vector fields, the center manifold theorem, and
the unfolding theory. For our circuit application, however, the
bifurcation condition is the most important to study bifurcations of concrete circuit examples. Thus we will introduce only
some basic results of bifurcation problems of equilibrium
point or fixed point. We will discuss the bifurcation of periodic
state as the bifurcation of fixed points of the Poincare map.

where the symbol indicates the relation before and after

the bifurcation and 0
denotes the extinction of equilibria. The
plus sign appearing in the left-hand side of the relation
means that before the bifurcation we have a couple of equilibria of the type kO and k1O. At the bifurcation value 0
these two equilibria coalesce into one nonhyperbolic equilibrium point, and after the bifurcation they disappear completely. The bifurcation condition is then given by

Bifurcation of Equilibrium Point

The Hopf Bifurcation. This bifurcation is observed if a couple of characteristic roots becomes purely imaginary numbers
at 0. The stability of the equilibrium point changes and
a limit cycle appear or disappear after the bifurcation. Symbolically we have the following relation:

Consider an autonomous system

x = f(x, ),

x Rn , Rm

(166)

where x Rn is a state vector and Rm is a system parameter. Suppose that x0 Rn is an equilibrium point of Eq.
(166):
f(x0 , ) = 0

(167)

The Jacobian matrix of Eq. (167) is given by

Df(x0 , ) = A()

(168)

The characteristic equation is written as

() = det(In A())
= n + a1 n1 + + an1 + an = 0

(169)

Hyperbolicity is violated at a bifurcation value 0 when

the Jacobian A Df(x0, ) becomes singular or a couple of
characteristic roots become purely imaginary numbers. In the
former case we observe the number of equilibria may change,
whereas in the latter case the type of equilibrium point may
change; that is, the stability may change and new periodic
orbit will be generated. We assume that along the variation
of , the above location of characteristic root actually changes,
that is,


d Re() 
= 0
d =

(170)

(0) = det(0 A()) = an = 0

(172)

Geometrically in the parameter space Rm, Eq. (172) gives a

hypersurface with the dimension m 1. Hence this bifurcation is called a codimension one bifurcation. The tangent bifurcation is also called a saddle-node bifurcation, a fold bifurcation, or a turning point in various contexts.

kO

kO

+ LC(k+1 D)

k+2 O

+ LC(k D)
k+2 O

(k = 0, 1, . . . , n 2)
(k = 0, 1, . . . , n 2)

(173)

where LC(kD) denotes a limit cycle whose type of the corresponding fixed point of the Poincare map is kD. The first relation shows that before the bifurcation a k-dimensionally unstable hyperbolic equilibrium point exists, and after the
bifurcation the equilibrium point becomes a (k 2)-dimensionally unstable and k-dimensionally unstable limit cycle of
the type kD appears. If k 0, then a sink becomes two-dimensionally unstable and an orbitally stable limit cycle appears.
This type of Hopf bifurcation is called a supercritical type,
whereas the second relation shows a subcritical type (see Fig.
26). The bifurcation condition is then given by
( j) = det( jIn A()) = 0

(174)

where j 1. This condition gives two relations derived

from the real and imaginary parts. By eliminating the unknown , which gives the angular frequency of the bifurcated
limit cycle, we obtain a single condition. Hence this is also a
codimension one bifurcation.
Example 8. 1. The Hopf bifurcation for low-dimensional systems. For low-dimensional systems, the condition Eq. (174) is
easily obtained as follows.

(a) Two-dimensional system. The condition is given by

Then the generic bifurcation of equilibrium point is the two
cases described below.
Tangent Bifurcation of Equilibrium Point. If one of the characteristic roots becomes zero at the bifurcation parameter
0, then the generation or extinction of a couple of equilibria occurs. Symbolically we have the following bifurcation relation:
kO

k+1 O

(k = 0, 1, . . . , n 1)

(171)

( j) = ( j)2 + ja1 + a2 = 0

(175)

Hence we have
a1 = 0,

a2 = 2 > 0;

a2

(176)

(b) Three-dimensional system. The condition is given by

( j) = ( j)3 + a1 ( j)2 + ja2 + a3 = 0

(177)

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

kD

551

k+ 1D

Equilibrium point

Equilibrium point

kO

k+ 2O

kO

Limit cycle

k+ 2O

Limit cycle

= 0

= 0

(a)

Figure 26. Schematic diagram of Hopf bifurcation.

(a) Supercritical case, (b) subcritical case.

(b)

Hence we have
a1 a2 + a3 = 0,

a2 > 0;

= a2

(178)

(c) Four-dimensional system. The condition is given by

( j) = ( j)4 + a1 ( j)3 + a2 ( j)2 + ja3 + a4 = 0

tangent bifurcation curve (see also Fig. 28). The diagram

shows the region in which three or one equilibrium points
exist, and on the boundary curves t1, t2 we have the tangent
bifurcation. Note that at the cusp point C in Fig. 28 we have
a degenerate equilibrium point, that is, a codimension two
bifurcation point.

(179)
Bifurcation of a Fixed Point

Hence we have


a4
> 0;
a2

a24 + a21 (a4 a2 ) = 0,

a4
a2

(180)

2. Bifurcation diagram of equilibria of Eq. (165). Consider

the equilibria of Eq. (165). The equilibrium point satisfies Eq.
(146). Figure 27 shows the surface defined by Eq. (146) in the
(, b, r) space, where we set a c 1. Projecting this surface
into the (b, r) plane, we have the amplitude characteristic
curve as illustrated in Fig. 22. On the other hand, by projecting the surface into the parameter (b, ) plane, we obtain
a diagram, called a bifurcation diagram, which indicates the

Characteristic surface of Eq. (146)

Consider the Poincare map T defined by Eq. (109). T depends

on the parameter Rm so that a bifurcation of a fixed point
may occur under the change of . Suppose that x0 Rn is a
fixed point of T:
x0 T (x0 ) = 0

(181)

The characteristic equation is written as

() = det(In DT (x0 ))

(182)

= n + a1 n1 + + an1 + an = 0

Hyperbolicity is violated at a bifurcation value 0 when

the characteristic multiplier has the critical distribution:
1, 1, or ej. Hence we have actually three different
types of codimension one bifurcations for fixed point of T.

0.7

1O

0O

0.5

0.5
1

b
00
Amplitude characteristics

1
0.4

0
0

0.5

0.3

t1

0.2

t2

0.1

3
0

0.6

0.5

0
1

Bifurcation diagram
Figure 27. Characteristic surface of Eq. (146) with amplitude characteristic curves and bifurcation diagram.

0.1

0.2

0.3
b

0.4

0.5

0.6

0.7

Figure 28. Bifurcation diagram of equilibria. Tangent bifurcation occurs on the curves t1 and t2, and the cusp point C is a degenerate
tangent bifurcation point.

552

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Tangent Bifurcation of Fixed Point. Under the change of parameter , at 0 the generation or extinction of a couple
of fixed points occurs. The types of bifurcation are

?
?

k1 D + k D
k1 I

(183)

+ kI

where denotes the extinction of fixed points and the symbol

indicates the relation before and after the bifurcation. This
type of bifurcation is observed if one of the multipliers of Eq.
(182) satisfies the condition 1 or, equivalently,

= 1 + a1 + + an1 + an = 0

Period-Doubling Bifurcation. If a real characteristic multiplier passes through the point (1, 0) in the complex plane,
then the original fixed point changes its type and 2-periodic
points are branching. This bifurcation is called a period-doubling bifurcation. The types of bifurcation are

kD

kI
kI

k+1 I

+ 2 k D2

k1 I

+ 2 kD

k+1 D + 2 k D

k1 D +

(1) = det(In DT (x0 ))

= (1)n + a1 (1)n1 + an1 + an = 0

kD

k2 D +

kI

k+2 D

kI

k2 D +

+ ICC

(186)

(191)

sin 2 + a1 sin = 0
Hence we have
a2 = 1,

2 < a1 < 2

(192)

(e j ) = e j3 + a1 e j2 + a2 e j + a3 = 0

(193)

2 < a3 a1 < 2

(194)

Second consider autonomous systems. In this case the characteristic equation has at least one unity multiplier. Thus we
factor the characteristic equation as
() = n + a1 n1 + + an1 + an = ( 1)A () = 0
(195)
where

A () = n1 + b1 n2 + + bn1 ,

bk = 1 +

k

ai (196)

i=1

The bifurcation condition is then given by using a new characteristic equation:

A () = n1 + b1 n2 + + bn1 = 0

A (e j ) = e j2 + b1 e j + b2

(187)

(197)

= e j2 + (a1 + 1)e j + (a2 + a1 + 1) = 0

(198)

or, equivalently,

where ICC indicates an invariant closed curve of the Poincare

map T. The condition for this type of bifurcation is given by

= e jn + a1 e j(n1) + + an1 e j + an = 0

cos 2 + a1 cos + a2 = 0,

For the three-dimensional system the condition is given by

ICC

(e j ) = det(e j In DT (x0 ))

That is,

a1 (a3 a1 ) + a2 = 1,

+ ICC
ICC

(190)

or equivalently

The NeimarkSacker Bifurcation. Similar to the Hopf bifurcation for equilibrium point, a fixed point becomes unstable
and there may appear an invariant closed curve of the Poincare map. Here the invariant closed curve C is a closed curve
in Rn such that T(C) C, which corresponds to doubly periodic oscillation in the original periodic nonautonomous system. This bifurcation indeed occurs if a pair of the characteristic multipliers and pass transversally through the unit
circle except for the points (1, 0) and (1, 0). The types of the
bifurcation are
k+2 D

(e j ) = e j2 + a1 e j + a2 = 0

(185)

where 2 kD2 indicates two numbers of 2-periodic point of the

type D. This type of bifurcation is observed if 1 or,
equivalently,

Example 9. The NeimarkSacker bifurcation for two- or

three-dimensional systems. First consider nonautonomous
systems.

2. Three-dimensional system. The condition is given by

2 k D2

kD

(189)

Note that in this case we need an additional inequality satisfying the condition: cos 1.

(184)

and the remainder of the characteristic multipliers lies off the

unit circle in the complex plane.

NS (x0 , ) = 0

1. Two-dimensional system. The condition is given by

() = det(In DT (x0 ))

kD

Hence by eliminating in Eq. (188) we have the single condition

a2 + a1 = 0,

3 < a1 < 1

(199)

Numerical Method of Computation

(188)

The numerical determination of the codimension one bifurcation value 0 and the location of the nonhyperbolic fixed

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

point is accomplished by solving the fixed point equation and

the bifurcation condition, simultaneously. The unknown variables are the location of the fixed point and one of the components of . The computation is achieved by Newtons method,
and the Jacobian matrix is evaluated by the solutions of the
variational equations with respect to the initial conditions
as well as the system parameters (see Theorem 2 and Remark 3).
Harmonic Synchronization of Forced Rayleigh Equation
Let us consider the harmonic synchronization or entrainment
of Rayleighs equation with a sinusoidal external force:
x = y
y = x +
(1 y2 )y +
B cos t

(200)

Assume that the periodic solution of Eq. (200) as

x(t) = u(t) cos t + v(t) sin t
y(t) = u(t) sin t + v(t) cos t

(201)

By using the averaging method we have an autonomous equation:



3 2

1 r u v = f (u, v)
u =
2
4

u + 1 r2 v + B = g(u, v)
v =
2
4

(202)

where

a1 = 3 r2 2
a2 = 2 + 1 3 r2 +

2( 1)

(203)

9
27 2 4
3
r = 2 + 1 r2
1 r2
16
4
4
(208)

Hence we can determine the type of equilibrium point by the

sign of the coefficients in Eq. (208) as in Example 5(1). Figure
29 shows the characteristic surface of Eq. (205) in the (, B,
r) space. Topological type of the equilibrium point is indicated
on the surface. Projecting the surface into the (, B) plane we
have the bifurcation diagram for the equilibria. The projected
plane is also shown in Fig. 30(a), where the type of equilibrium point is indicated in each region. Roughly speaking, harmonic synchronization occurs in the region in which a stable
0O equilibrium point exists. The curves t1, t2,, and t3 indicate
the tangent bifurcation curves joined at cusp points c1 and
c2. The curves h1 and h2 illustrate the Hopf bifurcation, which
join the tangent bifurcation curves at points P and Q [see Fig.
30(b)]. If we decrease B transversally across the curves h1
and h2, we see a supercritical Hopf bifurcation. Hence below
the curves h1 and h2 we have a stable limit cycle. This state
corresponds to an asynchronous statethat is, a beat oscillation or quasiperiodic oscillation.
Parametric Excitation. 1. Mathieus equation. Consider the
second-order linear system, called Mathieus equation,

where
r2 = u 2 + v 2 ,

553

x + (a + b cos 2t)x = 0

(209)

x = A(t)x

(210)

or, equivalently,

Hence the equilibrium point is given by


3 2
r u v = 0
4


3
u + 1 r2 v = B
4
1

(204)

0O

That is, the amplitude satisfies the relation


2
3 2
2
1 r
+ r2 = B2
4

1O

(205)

a1 = 0

a2 = 0
P

2O

At the equilibrium point the Jacobian matrix becomes

f
u

g
u

3
f
2
2
1 4 (3u + v )

v
=
g 2
3
uv +
v
2

3
uv
2

3
1 (u2 + 3v2 )
4
(206)

Thus the characteristic equation is given by



 f
f 



v  = 2 + a + a = 0
() =  u
1
2

g
g



u
v

0.5

1.5

P
1

B 0.5

(207)

0.5

0
0
1

0
1

0.5

0.5

Figure 29. Characteristic surface of Eq. (205) and projected bifurcation diagram.

554

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

0.6

C1

C2

h2

0O

0.5

h1

t2

0.4
2O

0.3

h1

2O

0O+ 1O+ 2O

0O

t2

0.1

0O+ 1O+ 2O

0
0.8 0.6 0.4 0.2

Figure 30. (a) Bifurcation diagram of equilibria of

Eq. (202) and (b) its partially enlarged diagram.


A(t) =

(a + b cos 2t)


(211)

The origin is a stationary solution. Hence we will discuss its

stability. Let the principal fundamental matrix solution be


(t) =

1 (t)

2 (t)

1 (t)

2 (t)

(212)

As the period of the coefficient is , the Poincare map T is

defined by
T = ( ) :

R2 R2 ;

x0
x1 = ( )x0

(213)

The characteristic equation is then given by

() = det[I2 ( )] = 2 m + 1 = 0

(214)

where we put
m = 1 ( ) + 2 ( ) = 1 + 2

(215)

and use the relation

"

(0) = 1 2 = det( ) = det(0)e

0 trace A ( ) d

=1

(216)

0.2 0.4 0.6 0.8

(b)

2) log 22, and (t) and (t) are periodic functions with
period 2.
(c) If m 2, then the origin is a nonhyperbolic fixed
pointthat is, a center-type fixed point. The general
solution is then a doubly periodic function. In the last
case the characteristic multipliers lie on the unit circle
in the complex plane:

1 = 2 = exp( j ),

j = 1,

= tan



4 m2
m
(218)

Note that Eq. (210) is a lossless system so that the

Poincare map of Eq. (213) is the area-preserving map
on R2. The stability chart is a diagram of the (a, b)
parameter plane, which shows contour curves of m and
where we find the origin being a directly hyperbolic, an
inversely hyperbolic, or a nonhyperbolic type. By numerical integration we can easily obtain the value of
Eq. (215). Figure 31 shows the contour curves for different values of m. The shaded regions indicate the regions where the origin becomes the 1D or 1I type of instability. These regions approach the a axis near the
point a k2, k 1, 2, . . ..
2. Damped Mathieus equation with a cubic nonlinear restoring force. Consider the damped nonlinear system
x + kx + (a + b cos 2t)x + x3 = 0

Hence we have the following results:

(a) If m 2, then 0 1 1 2 and the origin is a
directly unstable: 0D. From the Floquet theorem we
have the general solution of the form
x(t) = c1 e 1 t (t) + c2 e 2 t (t)

t1

(a)

where


x
x=
,
y

2O

t1

t3

0.2

0O+2x 1O

(217)

where c1 and c2 are arbitrary constants, 1 (1/) log

1, 2 (1/) log 2, and (t) and (t) are periodic functions with period .
(b) If m 2, then 1 1 2 0 and the origin is an
inversely unstable: 1I. The general solution has the
same form as Eq. (217), but 1 (1/2) log 12, 2 (1/

(219)

or, equivalently,
x = y
y = kx (a + b cos 2t)x x3

(220)

The variational equation for the origin becomes

+ k + (a + b cos 2t) = 0

(221)

The characteristic equations has the form

() = det[I2 ( )] = 2 m + a2 = 0

(222)

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

555

20
1I
1D

m = 10

15
m = 50

1I

20

10

10

m = 15

0
1

10

1
0

10

2
5
2
2

0
5

10
100

400

1D

0
1

Figure 31. Stability chart or contour m chart of

Eq. (209). The origin becomes unstable of the type
1D or 1I in the shaded region.

15

where
a2 = (0) = det( ) = det(0)ek < 1

(223)

Hence the origin is a completely stable, a directly unstable,

or an inversely unstable fixed point of the time Poincare
map. Parametric excitation occurs in the parameter regions
in which the origin becomes an inversely unstable or a directly unstable fixed point. Figure 32 shows the bifurcation
diagram near the first unstable region just above a 1. The
white region and the shaded region indicate that the origin
becomes a completely stable and an inversely unstable fixed
point, respectively. On the curves P1 and P2 we have a perioddoubling bifurcation of the origin. That is, two 2-periodic
points branch off from the origin. Changing parameters from
the area A to B, we see that two completely stable 2-periodic
points branch off; see the phase portrait of the Poincare map

of Fig. 33(a). This is the typical parametric excitation phenomenon, also called the parametric resonance. Stable 2-periodic points 0D12 and 0D22 T(0D12) have the period 2 which is
the double period of the injected pumping signal. Traversing
the curve P2 from the region B to C, we observe that two directly unstable 2-periodic points branch off from the origin
and the origin itself becomes a completely stable fixed point.
Hence in the region C we have the phase portrait shown in
Fig. 33(b). On the tangent bifurcation curve T, 2-periodic
points 0D12 and 1D12, (and also 0D22 and 1D22) coalesce and disappear in the region A below the curve T.
References in This Section
Many books are available on bifurcation theory. We refer to
only a few of them: Refs. 79, 25, and 26. For the higherorder bifurcationsthat is, codimension two bifurcations
see Refs. 9, 26, and 27. Various numerical methods are stated
in Refs. 21 and 2628. Harmonic synchronization is analyzed
in Refs. 3, 6, and 9. Mathieus equation and more generally
the linear periodic differential equations are well surveyed in

1I

y
2
0D1

2
0D1

P1

P2
0D

1I
2
D
0 2

0D

T
c
0

2
1D1

2
1D2

0D

2
0D2

a
Figure 32. Bifurcation diagram of Eq. (219) with k 0.1. Curves
P1 and P2 indicate the period-doubling bifurcation of the origin, and
T denotes the tangent bifurcation of 2-periodic points.

(a)

(b)

Figure 33. Phase portrait of the time Poincare map of Eq. (219).
(a) k 0.1, a b 1.0; (b) k 0.1, a b 0.54.

556

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Ref. 29. Parametric excitation is found in Refs. 5, 8, 30, and

31.
HOMOCLINIC STRUCTURE OF
NONLINEAR CIRCUIT DYNAMICS
Thus far in the previous sections we have discussed local
properties of circuit dynamics. Global properties, such as the
geometrical behavior of invariant manifolds of a saddle-type
equilibrium point or a fixed point, the abrupt disappearance
of attractors, and the appearance of chaotic states, really reflect nonlinearity of dynamical systems. These properties relate a wide range movement of state in state-space and longterm behavior of a trajectory. In this section we extract two
topics on the global structure of phase portraits. First we illustrate the separatrix loop in two-dimensional autonomous
systems. Second we discuss the homoclinic points and related
chaotic states in Duffings equation. These simple examples
illustrate the complexity of the global behavior of nonlinear
systems.
Separatrix Loop
Two-dimensional autonomous systems in the plane have been
studied for many years and exhibit many interesting properties. To see the global structure of a phase portrait, it is important to know the behavior of stable and unstable orbits
of saddle points. In fact in planar systems, the candidates of
invariant steady states are known as equilibria, periodic orbits, or a set of saddles and trajectories connecting them if
they exist. The latter are called saddle connections or heteroclinic orbits if they connect distinct saddles, and they are
called separatrix loop or homoclinic orbit if they connect a
saddle to itself (see Fig. 34). It is known that these connections are violated under small variation of parameters . That
is, they are structually unstable and if such a connection exists at 0, then a global bifurcation may occur by changing
parameter . An example of such a bifurcation is the disappearance of a limit cycle associated with a separatrix loop,
which is shown in Fig. 35. A limit cycle approaches the stable
and unstable orbit of a saddle in Fig. 35(a), and at 0 the
cycle coalesces into and forms the separatrix loop in Fig.
35(b). Afterward the bifurcation the cycle disappears completely as in Fig. 35(c). Thus in the process of this bifurcation
the phase portrait changes globally and the oscillatory state
corresponding to the stable limit cycle abruptly disappears at
0.

(a)

(b)

(c)

Figure 35. Bifurcation of a separatrix loop. A stable limit cycle

shown in (a) disappears after this bifurcation shown in (c).

Example 10. DuffingRayleigh equation. Consider a forced

oscillator described by
x = y

(224)

y = x +
{(1 y2 )y cx3 + B cos t}

Comparing with Eq. (200), Eq. (224) has a cubic nonlinear

restoring term and is called the DuffingRayleigh equation.
Assuming the harmonic oscillation as Eq. (201) and using the
averaging method we have the autonomous system:

 
3
3

1 r2 u cr2 v
2
4
4



3 2

3 2
cr u + 1 r v + B
v =
2
4
4

u =

(225)

where we put the amplitude and the detuning as

r2 = u 2 + v 2 ,

2( 1)

(226)

Then the equilibrium point satisfies the relation

3
1 r2
4

2 

3 2
r2 = B2
+ cr
4

(227)

Figure 36 shows the bifurcation diagram of the equilibria

given by Eq. (227). The diagram is similar to that of Fig. 30.
But tangent bifurcation curves are right side up so that we

3
t2
h1 t
1
2

1O
1O2

t1

h2
Q

0
1
(a)

h1

R
t2

SL

1O1

(b)

Figure 34. Schematic diagram of a saddle to saddle orbit. (a) A saddle connection orbit, or heteroclinic orbit; (b) a separatrix loop, or
homoclinic orbit.

t3
0

Figure 36. Bifurcation diagram of equilibria of Eq. (227). The curves

t, h, and SL denote the tangent bifurcation, the Hopf bifurcation, and
the bifurcation of separatrix loop, respectively.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

can more clearly discuss the region near the intersection

point P of the tangent bifurcation curve t2 and the Hopf bifurcation curve h1. Actually from the point P to the point R on
the curve t1 there exists a bifurcation curve SL on which we
have a separatrix loop. Figure 37 is a schematic diagram of
the phase portraits in each region. The point P is a degenerate bifurcation point (i.e., t2 and h1 meet at this point) and is
called the BogdanovTakens bifurcation point. The appearance of separatrix loop on SL suggests that in the original
system, Eq. (224), there exist homoclinic points of the time
2/ Poincare map. This phenomenon will be discussed in the
next section.

557

(a)

(b)

Figure 38. Invariant curves of saddle-type fixed points and doubly

asymptotic points. (a) Transversal homoclinic point, (b) transversal
heteroclinic point.

D, we have two invariant curves:

#
$
(P) = W u (P) = u R2 | lim T k (u) = P
k
#
$
(P) = W s (P) = u R2 | lim T k (u) = P

Homoclinic Point
Now we consider the phase portrait of the Poincare map. We
focus our attention to the behavior of invariant manifolds
stated in Remark 5(1) [see Eq. (124)] and its related property.
For simplicity consider a two-dimensional periodic nonautonomous system defined by Eq. (107):
x = f(t, x, ),

x R2 , Rm

(228)

where x (x, y) R2 is a state vector and Rm is a system

parameter. We assume that f is periodic in t with period 2:
f(t, x, ) f(t 2, x, ) for all t R. Let x(t) be a solution
x(t) (t, x0, ) with x(0) (0, x0, ) x0. Recall that we
define the time 2 mapping as the Poincare map:
T:

R2 R2 ;

x0 = (x0 , y0 )
x1 = (x1 , y1 )
= T (x0 ) = (2, x0 , )

(230)

We simply call (P) and (P) and branches, respectively.

We are interested in the behavior of these curves in the phase
plane of T. Let P and Q be directly unstable fixed points of T.
A point x R2 is called a doubly asymptotic point if it has
the asymptotic property such that
(x) = P,

(x) = Q

(231)

Clearly if x R2 is a doubly asymptotic point, then every

point in the orbit
Orb(x) = {xk R2 | xk = T k (x), k = , 1, 0, 1, } (232)

(229)

If a solution x(t) (t, x0, ) is periodic with period 2, then

the initial state x0 is a fixed point of the map T. Recall also
that a saddle-type fixed pointthat is, a directly unstable or
an inversely unstable fixed pointhas a stable manifold and
an unstable manifold defined by Eq. (124). In two-dimensional case, these manifolds are curves in the phase portrait
of T. For example, if the point P is a directly unstable type

becomes a doubly asymptotic point. If P Q, then the doubly

asymptotic point is called a homoclinic point [see Fig. 38(a)].
Otherwise (i.e., P Q), the doubly asymptotic point is called
a heteroclinic point [see Fig. 38(b)]. Hence a homoclinic point
approaches the saddle point P by the forward and backward
iterations of T. A remarkable property found by Poincare and
developed by Birkhoff and Smale is that near a homoclinic
point there exist infinitely many periodic points and a nonperiodic invariant set of T. Actually S. Smale defined the horseshoe map which exists in the neighborhood of a transversal
homoclinic point as illustrated in Fig. 39. Note that a trans-

h1

t2
P

t1

SL

1D

Figure 37. Schematic diagram of the phase portraits in each region

or on the curve of the diagram of Fig. 36.

c
a
d

Figure 39. Schematic diagram of a horseshoe map on the small rectangle abcd near homoclinic points. The region comes back to the
curved rectangle abcd after some finite iteration of the Poincare
map T.

558

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

versal homoclinic point is an intersection point of (1D) and

(1D) transversallythat is, not tangentially. As shown in
Fig. 39, if we choose a small rectangular region abcd along
the (1D), the image of Tk, k 1, 2, . . ., first approaches the
saddle point and then leaves along the (1D) and for some k
it returns to near the original rectangular region as a curved
rectangle abcd by stretching one direction and contracting
the other direction. We see that the horseshoe like returned
rectangle abcd intersects the original rectangle abcd at two
parts. The map on the rectangle abcd is called a horseshoe
map and will be discussed in next paragraph.

C
H0

H1

H2

Example 11. Consider Duffings equation

1D

x = y
y = 0.02y x3 + 0.3 cos t 0.08

By numerical analysis we find the phase portrait shown in

Fig. 40, where the point 1D is a directly unstable fixed point
with the location (x, y) (1.0278, 0.08358) and the multipliers (1, 2) (0.1862, 4.7362). The and branches intersect
each other as shown in Fig. 40 and create homoclinic points.
A curved rectangular region ABCD is mapped into the shaded
region ABCD by the map T. Hence T defined by Eq. (233)
on ABCD is a horseshoe map. Note that the result is only
numerically verified. Theoretically, it is very difficult to determine the behavior of these invariant curves.

H2

H1

(233)

Figure 41. Schematic diagram of a horseshoe map on the rectangle

ABCD. Invariant curves represent and branches of a fixed point
1D, and a homoclinic point H0 and its images are indicated.

indicated as

H2 = T 2 (H0 ),

H1 = T 1 (H0 ),

H0 , H1 = T (H0 ),

H2 = T (H0 )
2

Figure 42(a)(c) shows the images T(R), T 2(R), and T 3(R), respectively. We see that the number of intersections,

Horseshoe Map
A horseshoe map on a rectangular region contains a complex
invariant set. This is a typical chaotic state. Hence we summarize briefly some of the properties of the map. Let a map
T have a directly unstable fixed point 1D and let its and
branches intersect each other, forming homoclinic points as
schematically illustrated in Fig. 41. Then the map from the
rectangular region R ABCD into the plane becomes a horseshoe map. In the figure, images of the homoclinic point H0 are

#{R T k (R)} = 2k

(k = 1, 2, . . .)

(234)

increases as 2k while forming the vertically very narrow rectangles. And the positively invariant set becomes
R = R

T k (R) CantorSet I

(235)

k=1

Topologically, the set R has a one-to-one correspondence to

the Cantor set in the horizontal direction and has an interval
I in vertical direction. The same is true for the inverse iteration:

y
A

R = R
C

T k (R) I CantorSet

(236)

k=1

D
B

1D

A
A

B C
(a)

Figure 40. Phase portrait of the Poincare map defined by Eq. (233).

D
(b)

(c)

Figure 42. Schematic diagram of the images of the rectangle

ABCD in Fig. 41 under the iteration of the Poincare map T.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

Hence the invariant set in the rectangle R has the structure

R
= R

T k (R)

k=1

T k (R) CantorSet CantorSet

2S

k=1

(237)

559

1S
1S

By making the correspondence between the symbolic dynam

ics and T on R
, we know the following properties:

2S

1. R
has countably many periodic points of T with an
arbitrarily high period, and these periodic points are all
of the saddle type.

2. R
has uncountably many nonperiodic point of T.

3. R

has dense orbits.

has sensitive dependence on iniMoreover, each point in R

tial conditions. That is, for any point x in R

, no matter how
we choose a small neighborhood of x, there is at least one
point in the neighborhood such that after a finite number of
iterations of T, x and the point have separated by some fixed

distance. We say that T is chaotic on R

or that the invariant

set R
is chaotic. Note that this chaotic invariant set R
is
unstable because of the above properties 1 and 3. To observe

R
as an attractor, there exists another mechanism to encapsulate this invariant set in some bounded region of the phase
plane. Mathematically, this problem is not yet solved completely. In circuit dynamics, however, this mechanism may be
achieved by the dissipative property of the circuit.

Example 12. Consider the phase portrait of Duffings equation:

x = y
y = ky x3 + 0.3 cos t

(238)

Cascade of Period Doubling Bifurcations

One of the most popular bifurcation processes from a single
fixed point attractor to chaotic state is a cascade of perioddoubling bifurcations. Recall that the period-doubling bifurcation has the following bifurcational relation:
2k

1I

2k

+ 2 0 D2

k+1

k = 0, 1, 2, . . .

(b)

S
2S

(c)

S
2

(239)

In many systems with weak dissipation, this bifurcation occurs successively until k tends to infinity under the finite
change of parameters. The universality of this cascade of bifurcations is studied by Feigenbaum. We illustrate this cascade by the following example.

(d)

Figure 43. Phase portrait of the Poincare map defined by Eq. (238).
Homoclinic points appear when k becomes small. (a) k 0.1, (b) k
0.05, (c) k 0.005, (d) k 0.

Example 13. Consider again Duffings equation

x = y

Varying the damping coefficient k, we observe numerically

the and branches as shown in Fig. 43. At k 0.1, we
have only three fixed points: a nonresonant stable fixed point
1
S, a resonant stable fixed point 2S, and a directly unstable
fixed point D [see Fig. 43(a)]. There is no homoclinic point at
this parameter. At k 0.05, there appear homoclinic points,
see Fig. 43(b). By decreasing k, the intersection property becomes complex as illustrated in Figs. 43(c) and 43(d).

0D

(a)

y = 0.1y x3 + B cos t + B0

(240)

Figure 44 shows the bifurcation diagram of a fixed point corresponding to a nonresonant oscillation. P and T denote the
period doubling and tangent bifurcation curves, respectively,
on which these bifurcations appear. The superscript k indicates the k-periodic point, and the subscript shows the numk
ber for distinct curves. On the curve labeled P12 the bifurcation process of Eq. (239) occurs. These curves accumulate on
just the inner region of the curve P18 so that in the shaded
region we see a chaotic state. Phase portraits of the perioddoubling cascade are shown in Fig. 45. Stable 2-periodic
points exist in Fig. 45(a), which bifurcate into 4-periodic
points in Fig. 45(b). Chaotic states separated into four groups
appear in Fig. 45(c). They gather as two parts in Fig. 45(d)
and finally coalesce into one big attractor in Fig. 45(e). The
attractor grows until it touches the branch of the directly
unstable fixed point D. After intersecting, the chaotic state
loses its attractivity and the attractor disappears, although
an unstable chaotic state exists.
Lyapunov Exponent to Measure a Chaotic State
To determine whether an attractor is chaotic or not, we have
a conventional method of evaluating the mean value of the

560

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

0.15

P1

P12
0.1

P18

I
I22 S 4
2
S44

B0

S22
T12
0.05

S14

I12
S34

S12

P14

(b)

(a)

T22

P22
0.0

T32
0

0.2

0.1

0.3

0.4

B
D
Figure 44. Bifurcation diagram of Eq. (240). Period-doubling cascade
appears on a fixed point corresponding to a nonresonant periodic solution.

Ch41
I12

Ch42

Ch44
2

Ch43

expansive rate of the orbit of the Poincare map T. The mean

value is known as the Lyapunov exponent. Consider an orbit
starting from an initial point x0 R2:
Orb(x0 ) = {xk R2 | xk = T k (x0 ), k = 0, 1, 2 . . .}

k 2k

log
DT k (x0 )v

I2

(d)

(c)

(241)
y

For any vector v R2 with v 1, the Lyapunov exponent

of x0 with respect to v is defined by
v(v, x0 ) = lim

Ch21
I
Ch22

(242)

It is known that for almost all v R2 with v 1, (a) v(v,

x0) 0 if x0 R2 is a stable fixed point or a stable periodic
point, (b) v(v, x0) 0 if x0 R2 belongs to a stable invariant
closed curve corresponding to a stable quasi-periodic solution,
and (c) v(v, x0) 0 if x0 R2 belongs to a chaotic attractor.
Moreover, v(v, x0) does not depend on x0 and v in the above
cases. Hence we denote simply v and call it the maximum
Lyapunov exponent. Note that Eq. (242) can be easily calculated by using the chain rule of the derivative DTk(x0) and the
solutions of the variational equation with respect to the initial condition.

D
Ch

Ch
x

(f)

(e)

Figure 45. Phase portraits of the Poincare map defined by Eq. (240)
with B0 0.075: (a) B 0.15, (b) B 0.185, (c) B 0.195, (d) B
0.197, (e) B 0.199, (f) B 0.217.

Example 14. As a numerical example, consider Duffings

equation in Example 13. Figure 46 shows the Lyapunov exponent. By changing parameter B we see that v reaches zero at
every period-doubling bifurcation curve and becomes a positive value at chaotic states. The discontinuous jump from the
positive value to the negative value at the point marked E
means the disappearance of the chaotic attractor stated in
Example 13.

0.08

Chaotic attractor

0.06
0.04
P4

0.02
0

References in This Section

0.02

For the plane dynamical systems, many studies are reported

in Refs. 3235. The homoclinic point of the Poincare map was
studied in Refs. 3639. Examples of Duffings equation is
found in Refs. 3 and 40. The numerical method of the computation of the Lyapunov exponent can be found in Refs. 22
and 41.

0.04
0.06
0.10

P2

P
4
0D
0D

0.12

0D

P8

P
E
0D

0.14 0.16
B

0.18

0.2

0.22

Figure 46. Lyapunov exponent of the attractors in Eq. (240) with

B0 0.075.

NONLINEAR DYNAMIC PHENOMENA IN CIRCUITS

FURTHER REFERENCES ON NONLINEAR

PHENOMENA IN CIRCUIT DYNAMICS
Thus far we have stated basic facts on nonlinear phenomena
in circuit dynamics. During the last two decades, interest on
nonlinear dynamics has been directed to chaotic states and
related topics. Our interest is also directed to nonlinear phenomena in higher-dimensional systems. Here we briefly summarize the available books which will serve as further study
on these topics.
Self-Excited Oscillations and Chaos
Simple self-excited oscillation occurs as a consequence of the
Hopf bifurcation. The van der Pol oscillator stated in Examples 1(1) and 6(1) is probably the simplest sinusoidal oscillator. In higher-dimensional circuits, the same is true for this
type of oscillation (see Refs. 42 and 43). As stated in the last
section, we know that in two-dimensional autonomous systems, chaotic oscillation never occurs. Hence a problem arises
as to how to find or design a simple chaotic oscillator. Already
many circuits are proposed (see Refs. 4447). On the other
hand, how to control chaotic states is another interesting
problem. Several methods are proposed for stabilizing of an
unstable periodic orbit in chaotic states or, conversely, for destabilizing stable periodic state to chaotic states (see Refs. 48
and 49).
Synchronization and Chaos
Mutually coupled identical oscillators have symmetrical properties which restrict the behavior of attractors or invariant
sets in state space. A group-theoretical approach has been developed for equilibria and periodic solutions (see Refs. 50 and
51). On of the interesting results is that the symmetrical
property produces chaotic synchronization (see Ref. 49).
Global Bifurcations
Bifurcations in higher-dimensional systems are well summarized in Ref. 26. A zoo of bifurcation phenomena is illustrated
in Refs. 7 and 52. The appearance of homoclinic and heteroclinic points produces very complicated boundary of basin of
attractions, called fractal basin boundary. For more information on this topic, see Refs. 46, 47, 53, and 54.
BIBLIOGRAPHY
1. A. A. Andronov, A. A. Vitt, and S. E. Khaikin, Theory of Oscillators, Elmsford, NY: Pergamon, 1966.
2. N. N. Bogolieubov and Y. A. Mitropolskii, Asymptotic Methods
in the Theory of Nonlinear Oscillations, New York: Gordon and
Breach, 1961.
3. C. Hayashi, Nonlinear Oscillations in Physical Systems, New
York: McGraw-Hill, 1964.
4. N. Minorsky, Nonlinear Oscillations, New York: Van Nostrand,
1962.
5. T. E. Stern, Theory of Nonlinear Networks and Systems, Reading,
MA: Addison-Wesley, 1965.
6. J. J. Stoker, Nonlinear Vibrations in Mechanical and Electrical
Systems, New York: Interscience, 1950.
7. R. Abraham and J. E. Marsden, Foundations of Mechanics, New
York: Benjamin/Cummings, 1987.

561

8. V. I. Arnold, Mathematical Methods of Classical Mechanics, New

York: Springer-Verlag, 1978.
9. J. Guckenheimer and P. Holmes, Nonlinear Oscillations, Dynamical Systems, and Bifurcations of Vector Fields, New York:
Springer-Verlag, 1983.
10. V. I. Arnold, Ordinary Differential Equations, Cambridge, MA:
MIT Press, 1973.
11. J. K. Hale, Ordinary Differential Equations, New York: Interscience, 1969.
12. M. W. Hirsch and S. Smale, Differential Equations, Dynamical
Systems, and Linear Algebra, New York: Academic Press, 1974.
13. R. A. Rohrer, Circuit Theory: An Introduction to the State Variable
Approach, New York: McGraw-Hill, 1971.
14. R. FitzHugh, Mathematical models of excitation and propagation
in nerve, in H. P. Schwan (ed.), Biological Engineering, New
York: McGraw-Hill, 1969.
15. M. Hasler and J. Neirynck, Nonlinear Circuits, Norwood, MA:
Artech House, 1986.
16. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear
Circuits, New York: McGraw-Hill, 1987.
17. N. Levinson, Transformation theory of nonlinear differential
equations of the second order, Ann. Math., 45: 723737, 1944.
18. M. L. Cartwright, Forced oscillations in nonlinear systems, Ann.
Math. Stud., 20: 149241, 1950.
19. N. V. Butenin, U. I. Neimark, and N. A. Fufaev, Introduction to
the Theory of Nonlinear Oscillations (in Russian), Moscow:
Nauka, 1976.
20. K. Siraiwa, A generalization of the Levinson-Masseras equalities, Nagoya Math. J., 67: 121138, 1977.
21. H. Kawakami, Bifurcation of periodic responses in forced dynamic nonlinear circuits: Computation of bifurcation values of
the system parameters, IEEE Trans. Circuits Syst., CAS-31: 248
260, 1984.
22. T. S. Parker and L. O. Chua, Practical Numerical Algorithms for
Chaotic Systems, New York: Springer-Verlag, 1989.
23. E. Hairer, S. P. Norsett, and G. Wanner, Solving Ordinary Differential Equations I and II, New York: Springer-Verlag, 1987 and
1991.
24. I. G. Malkin, Some Problems in the Theory of Nonlinear Oscillations, Oak Ridge, TN: U.S. At. Energy Comm., 1959.
25. V. I. Arnold, Geometrical Methods in the Theory of Ordinary Differential Equations, New York: Springer-Verlag, 1983.
26. Y. A. Kuznetsov, Elements of Applied Bifurcation Theory, New
York: Springer-Verlag, 1995.
27. H. Kawakami and T. Yoshinaga, Codimension two bifurcation
and its computational algorithm, in J. Awrejcewicz (ed.), Bifurcation and Chaos, New York: Springer-Verlag, 1995.
28. M. Kubicek and M. Marek, Computational Methods in Bifurcation
Theory and Dissipative Structures, New York: Springer-Verlag,
1983.
29. V. A. Yakubovich and V. M. Starzhinski, Linear Differential
Equations with Periodic Coefficients 1 and 2, New York: Wiley,
1975.
30. N. W. McLachalan, Theory and Application of Mathieu Functions,
New York: Dover, 1964.
31. Y. Ueda, Some Problems in the Theory of Nonlinear Oscillations,
Osaka, Japan: Nippon Printing and Publishing Company, 1968.
32. A. A. Andronov et al., Qualitative Theory of Second-Order Dynamic Systems, New York: Halsted Press, 1973.
33. A. A. Andronov et al., Theory of Bifurcations of Dynamic Systems
on a Plane, New York: Halsted Press, 1973.
34. S. Lefschetz, Differential Equations: Geometric Theory, New York:
Interscience, 1963.

562

NONLINEAR EQUATIONS

35. N. N. Bautin and E. A. Leontovich, Methods and Examples of the

Qualitative Analysis of Dynamical Systems in a Plane (in Russian),
Moscow: Nauka, 1990.
36. G. D. Birkhoff, Nouvelles recherches sur les syste`mes dynamiques, Mem. Accad. Nuovi Lincei, Ser. 3, 1: 85216, 1935; also in
Collected Mathematical Papers, New York: Dover, 1968, Vol. 2.
37. S. Smale, Diffeomorphisms with many periodic points, in Differential and Combinatorial Topology, Princeton, NJ: Princeton
Univ. Press, 1965, pp. 6380.
38. S. Wiggins, Global Bifurcations and Chaos, New York: SpringerVerlag, 1988.
39. S. Wiggins, Introduction to Applied Nonlinear Dynamical Systems
and Chaos, New York: Springer-Verlag, 1990.
40. C. Hayashi, Y. Ueda, and H. Kawakami, Transformation theory
as applied to the solutions of non-linear differential equations of
the second order, Int. J. Non-linear Mech., 4 (3): 235255, 1969.
41. I. Shimada and T. Nagashima, A numerical approach to ergodic
problem of dissipative dynamical systems, Prog. Theor. Phys., 61
(6): 16051616, 1979.
42. J. E. Marsden and M. McCracken, The Hopf Bifurcation and Its
Applications, New York: Springer-Verlag, 1976.
43. J. L. Moiola and G. Chen, Hopf Bifurcation Analysis, Singapore:
World Scientific, 1996.
44. T. Matsumoto et al., Bifurcations Sights, Sounds, and Mathematics, New York: Springer-Verlag, 1993.
45. T. Kapitaniak, Chaotic Oscillators, Theory and Applications: Singapore: World Scientific, 1992.
46. F. C. Moon, Chaotic and Fractal Dynamics, New York: Wiley,
1992.
47. J. M. T. Thompson and S. R. Bishop, Nonlinearity and Chaos in
Engineering Dynamics, New York: Wiley, 1994.
48. T. Carroll and L. Pecora, Nonlinear Dynamics in Circuits, Singapore: World Scientific, 1995.
49. M. Lakshmanan and K. Murali, Chaos in Nonlinear Oscillators,
Singapore: World Scientific, 1996.
50. M. Golubitsky and D. G. Schaeffer, Singularities and Groups in
Bifurcation Theory, New York: Springer-Verlag, 1985, Vol. 1.
51. M. Golubitsky, I. Stewart, and D. G. Schaeffer, Singularities and
Groups in Bifurcation Theory, New York: Springer-Verlag, 1988,
Vol. 2.
52. E. A. Jackson, Perspectives on Nonlinear Dynamics, New York:
Cambridge Univ. Press, 1990, 1991, Vols. 1 and 2.
53. C. Mira, Chaotic Dynamics, Singapore: World Scientific, 1987.
54. C. Mira et al., Chaotic Dynamics in Two-Dimensional Noninvertible Maps, Singapore: World Scientific, 1996.

HIROSHI KAWAKAMI
The University of Tokushima

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Explicit solutions of the voltages and currents in a nonlinear dynamic circuit are generally not available. In
many cases, however, a qualitative description of the circuit behavior is possible and useful. Instead of solving
the circuit equations exactly, we ask questions such as: Is the circuit stable? Does the circuit oscillate? Do the
solutions remain bounded? Although circuit simulators, such as SPICE, give accurate solutions to the circuit
equations, generally they cannot answer these questions because they give us only the solution for a specific
set of initial conditions. To know whether the circuit is stable for all initial conditions, a new run needs to
be performed for each set of initial conditions, which is impractical. Furthermore, a qualitative analysis of a
circuit also tells us about its behavior when the circuit parameters are changed, which is difficult to do with a
circuit simulator.
Many techniques of the mathematics of dynamic systems theory are useful for qualitatively analyzing
dynamic (and resistive) circuits. A very useful technique for analyzing complicated dynamical systems is to
study a quantity derived from the system, such as energy, and use it to draw conclusions regarding the system.
Most of the methods of analysis in this article are of this nature. We assume that the reader is familiar with
basic circuit theory (1). We assume that the voltages or currents in external sources in a dynamic circuit are
bounded functions of time.
Abstractly speaking, a dynamic circuit is a network whose behavior changes over time. The following
definition, however, is sufficient to classify a large enough class of useful circuits, especially under the lumped
circuit approximation, where we do not consider wave propagative phenomena. A dynamic circuit is a network
composed of n-terminal (possibly nonlinear) resistors, capacitors, and inductors. A resistor is a resistive element
whereas a capacitor or an inductor are called dynamic elements. For one-port or two-terminal elements, their
notation along with reference directions are shown in Fig. 1. For simplicity in this article, we assume that all
elements are two-terminal elements. A nonlinear resistor is described by a relationship between the voltage
across it and the current through it. Similarly, a nonlinear capacitor is described by a relationship between
the charge on the capacitor q and the voltage across the capacitor v, and a nonlinear inductor is described by a
relationship between the flux and the current i. More formally, nonlinear resistors, capacitors and inductors
are defined by the relationships

respectively. These equations are the constituency relationships of the elements. If an element is time-varying,
then we need to write the relationships as R(v, i, t) = 0, C(q, v, t) = 0, and L(, i, t) = 0. A resistor is voltagecontrolled if the current i is a function of the voltage across the resistor, that is, the constituency relationship
R(i, v) = 0 is expressed as i = (v). A resistor is current-controlled if the constituency relationship is written
v = v (i). A capacitor is voltage-controlled if the charge is a function of the voltage across the capacitor, that
is, C(q, v) = 0 is rewritten q = q (v). Similarly, a capacitor is charge-controlled if we write the constituency
relationship v = v (q). An inductor is flux-controlled if it is described by a function i = () and current-controlled

if it is described by = (i).
1

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 1. Two-terminal nonlinear elements along with their reference directions.

Passivity
Because many of the results in this article rely on energy-like quantities, the concept of passivity is important.
Passivity implies that the nonlinear element dissipates energy (or at least does not supply energy), which is
the case for elements without a power source.
Definition 1. A nonlinear resistor with a constituency relationship i = g(v) is passive if vg(v) 0 for all v. It is
strictly passive if vg(v) > 0 for all v = 0. It is eventually passive if there exists a k > 0 such that vg(v) 0 for |v|
> k. It is eventually strictly passive if vg(v) > 0 for |v| > k.
If the constituency relationship is given by v = r(i), the previous definition still holds when v is replaced
by i. Passive resistors are such that the power vi fed into the resistor is always nonnegative, that is, the
constituency relationship lies in the first or third quadrant of the v-i plane.
Definition 2. A nonlinear element (resistor, inductor, or capacitor) with a constituency relationship y = f (x) is
strongly locally passive if there exists a, b > 0 such that the following holds for all x, x :

It is eventually strongly locally passive if Eq. (2) holds for all |x| > k, |x | > k for some k > 0.
A strictly locally passive nonlinear element has a constituency relationship that is strictly increasing and
is not necessarily passive.

Stationary or Equilibrium Points

The state of a capacitor and an inductor is the charge and the flux, respectively. The state of a dynamic circuit
consists of the charges and fluxes of the capacitors and inductors, respectively. A dynamic circuit is autonomous
(or time-independent) if it does not contain any time-varying circuit elements or sources. A stationary or
equilibrium point of a dynamic circuit is defined as the state of the circuit such that the state does not change
with time. This is also called the dc-operating point. Because the change of charge and flux with respect to time
is the current through the capacitor and the voltage across the inductor, respectively, an equilibrium point is
the state where all the branch currents of the capacitors and branch voltages of the inductors are zero. Thus,
at the equilibrium point, we can replace a capacitor by an open circuit, and an inductor by a short circuit, and
reduce the dynamic circuit to a resistive circuit. Thus finding equilibrium points of a dynamic circuit consists
of two steps. First the operating points of the corresponding resistive circuit are found. These operating points,

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

which are expressed as branch currents and branch voltages, are used to find the equilibrium points of the
dynamic circuit as follows: for each capacitor Ci , the branch voltage vi at the operating point is used to find all
the qi s which satisfy Ci (qi , vi ) = 0. Similarly this is done for inductors to find the i s. Each operating point of
the resistive circuit can correspond to many equilibrium points of the dynamic circuit.

State Equations and Uniqueness and Existence of Solutions

The equations governing a dynamic circuit consists of Kirchhoffs current law (Ai = 0), Kirchhoffs voltage law
(Bv = 0), the constituency relationships of the elements, and the equations i = dq/dt, v = d/dt. This forms a
set of constrained differential equations. Suppose that we can eliminate the variables v and i, so that we are
left with the equations:

where qc is the vector corresponding to the charges on the capacitors and l is the vector of fluxes of the
inductors. These are the state equations of the dynamic circuit.
If all the capacitors are charge-controlled and have differentiable and invertible constituency relationships v = v (q) and all the inductors are flux-controlled and have differentiable and invertible constituency
relationships i = (), then we can express the state equations in terms of capacitor voltages vc and inductor
currents il . Let us write vc = gc (qc ) and il = gl (l ). The hypothesis implies that gc , g 1 c , gl , and g 1 l exist.

This form is more desirable in practice because voltages and currents are more easily measured than charge
or flux.
Even if the state equations of the system exist, there is still no guarantee that solutions to the equations
exist, let alone that they are unique for each initial conditions. A mild requirement guaranteeing the existence
and uniqueness of solutions for all time t of ordinary differential equations of the form x = f (x, t) is that f is
continuous and uniformly Lipschitz continuous with respect to x (2).
In this article, unless otherwise stated, we assume that we can always write the state equations [Eq. (3)]
of a dynamic circuit and that solutions to x = f (x, t) exist and are unique for all time and that f is continuous.

Simple First- and Second-Order Nonlinear Dynamic Circuits

For a dynamic circuit with only two-terminal dynamic elements is called the order of the system, because, in
general, the resulting state equations (when they can be written) consist of this many first-order equations

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 2. First-order autonomous dynamic circuit consisting of a resistor in parallel with a capacitor.

(except for cases such as where there are loops of capacitors, in which case there are less equations than the
number of dynamic elements). The simplest types of dynamic circuits are the first-order and second-order
circuits. In this section we study some simple first-order and second-order dynamic circuits in some detail and
illustrate how the qualitative behavior of these systems is derived.
One Nonlinear Resistor and One Nonlinear Capacitor. Consider the first-order circuit consisting
of a nonlinear capacitor coupled with a nonlinear resistor (Fig. 2). If the resistor is voltage-controlled with
driving-point characteristic i = g(v) and the capacitor is charge controlled with driving-point characteristic
v = c(q), then the state equation of the circuit is written

What is the possible behavior of this system? The following theorem shows that nothing very interesting can
happen in this case:
Theorem 1. Suppose that c and g are continuous functions. Any solution q(t) of Eq. (4) is monotonic with no
inflection points (isolated points with slope 0). Thus, q(t) converges to an equilibrium point, or q(t) becomes
unbounded.
This can be proved as follows. Existence and uniqueness of solutions imply that, if dq/dt = 0 at some
time t0 , dq/dt = 0 for all time t. Because g and c are continuous and q(t) is continuous, q = dq/dt = g[c(q)] is
a continuous function of time. Suppose that q > 0 at some time t0 and that q < 0 at some time t1 . Then, by
the mean value theorem (18), q = 0 at some time t2 , which contradicts the above. So q always has the same
sign, and q is either constant or a strictly monotonic function. If q(t) is bounded, then it converges to some
number q. Because q(t) is monotonic, there exists a sequence tn such that g{c[q(t)]} = q 0, as n
. Therefore g[c(q)] = 0 which implies that q is an equilibrium point.
One Resistor, One Capacitor, and One Periodic Input. Now assume that a periodic voltage source
u(t) is connected in series with a nonlinear capacitor and resistor as shown in Fig. 3. We assume that u(t) is a
continuous function of t. Again assuming that the capacitor is charge-controlled and that the resistor is voltage

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 3. First-order nonautonomous dynamic circuit obtained from Fig. 2 by adding a periodic voltage source in series with
the capacitor.

controlled, we get the state equation:

For the initial condition q(t0 ) = q0 , we denote the corresponding solution as q(t, t0 , q0 ). Let T be the period of
u(t). Then, by uniqueness of solutions, q(t + nT, t0 , q0 ) for n an integer depends only on q(t, t0 , q0 ). This implies
that a map Pt0 exists, which maps q0 to q(t0 + T, t0 , q0 ). Note that Pt0 depends on t0 . The map Pt0 is called
a Poincare map. By continuity of solutions of ordinary differential equations, Pt0 is continuous because u(t) is
continuous. Pt0 is also invertible by uniqueness of solutions. This implies that Pt0 is a strictly monotonic map.
Note that uniqueness of solutions also implies that q(t0 + 2T, t0 , q0 ) = Pt0 [Pt0 (q0 )] etc., so that q(t0 + nT, t0 , q0 )
is just the nth iterate of the map Pt0 evaluated at q0 . Because Pt0 is monotonic, its iterates either diverge or
converge toward an equilibrium point. This implies that q(t, t0 , q0 ) as a function of t either diverges to infinity
or converges toward a periodic waveform with period T.
One Resistor, One Capacitor, and One Inductor. Consider a second-order circuit consisting of
a capacitor, an inductor, and a resistor connected in parallel (Fig. 4). Assuming that the resistor is voltagecontrolled, the inductor is flux-controlled, and the capacitor is charge-controlled with constituency relationships
i = f (v), i = g(), v = h(q), respectively, then the state equations are given by

The PoincareBendixson theorem (2) states that second order autonomous circuits cannot exhibit behavior
more complicated than periodic solutions.
Theorem 2. If the trajectory of an autonomous second-order system is bounded and does not approach an
equilibrium point, then it must approach a periodic solution.

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 4. Second-order autonomous dynamic circuit consisting of a resistor, a capacitor, and an inductor in parallel.

In particular, in second-order autonomous systems with one unstable equilibrium point, almost all
bounded trajectories must approach a periodic solution.
If the characteristics of the nonlinear elements are of a certain form, the LevinsonSmith theorem (2)
allows us to conclude that there exists a periodic solution which is stable in the sense that nearby solutions
converge toward it.
Theorem 3. If the following conditions are satisfied:
(1) the inductor is linear and strictly passive;
(2) the capacitor is strictly passive such that h is odd and differentiable;
(3) the function F(x) = f (h(x)) is odd and differentiable and there exists a > 0 such that F(x) < 0 on 0 < x < a,
F(x) > 0 on x > a, and F  (x) > 0 on x > a:


(4) x 0 h(s)ds , as |x| ; and
(5) F(x) , as x ;
then Eq. (5) has a nonconstant periodic solution which is stable.
This nonconstant periodic solution is unique if, in addition, the following conditions are satisfied (3):
(1) F(x) is zero only at x = 0, x = a and x = a; and
(2) F(x) monotonically, as x for x > a.
By using index theory (19), it can be proved that any periodic solution encircles at least one stationary
point.
When the circuit is autonomous but higher than second-order (e.g., Chuas circuit) or the circuit is secondorder but nonautonomous, that is, driven by an external input, the behavior can be very complex. In fact,
circuits of this type can be chaotic and can exhibit complicated bifurcation phenomena (4,5,6). See the article
(Circuits exhibiting chaotic behavior) for an introduction to bifurcation and chaos in nonlinear circuits and
systems.

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 5. The function x(t) = a/(b t) goes to infinity in finite time.

No Finite Escape-Time Criteria

General ordinary differential equations can have solutions which diverge to infinity in finite time, such as
x(t) = a/(b t) (Fig. 5). In this case the solutions do not exist for all time and this is a nonphysical situation.
The following criterion guarantees that dynamic circuits do not have such solutions (7).
Theorem 4. A dynamic circuit does not have solutions which escape to infinity in finite time if the following
conditions are satisfied:
(1) There are no loops nor cut sets consisting only of capacitors and/or inductors.
(2) All capacitors and inductors are eventually strongly locally passive.
(3) All resistors are eventually passive.

Eventually Uniformly Boundedness of Trajectories

Even if the solutions exist for all time, we do not want the voltages and currents in practical circuits to diverge
to infinity. Therefore, we want the trajectories of the system to be bounded.
Definition 3. A dynamic circuit is eventually uniformly bounded if there exists a bounded set K such that, for
each initial condition x(t0 ), there exists a time T for which the state x(t) remains in K for all t T.
The following result states that dynamic circuits which consist of independent sources and passive elements eventually have uniformly bounded solutions (7).
Theorem 5. Suppose that the constituency relationships of the elements are differentiable functions. A dynamic circuit is eventually uniformly bounded if the following conditions are satisfied:
(1)
(2)
(3)
(4)

There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltages sources.
There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
All resistors (not including sources) are eventually strongly locally passive.
All capacitors and inductors are eventually strongly locally passive.

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Stability of Equilibrium Points

Consider an autonomous dynamic circuit. Let us rewrite the state equations [Eq. (3)] in a general form as:

In terms of Eq. (6), an equilibrium point is a state x such that x = 0, that is, f (x) = 0.
The property of uniqueness and existence of solutions allows us to show that, if the state of the circuit is
at an equilibrium point, then it remains there for all time. Because of physical noise, we are also interested
in behavior near the equilibrium point. Compare this with a ball balanced on the tip of a needle. This is an
equilibrium state, and theoretically the ball remains balanced for ever. But, because of small noise, the ball
invariably leaves the equilibrium state. We call such equilibrium states unstable. On the other hand, a ball
lying at the bottom of a bowl is at a stable equilibrium state because a ball lying near the bottom will move
toward the bottom of the bowl. More precisely, an equilibrium point is (Lyapunov) asymptotically stable if all
initial conditions nearby do not leave a neighborhood of the equilibrium and converge toward the equilibrium
point as time goes on. If initial conditions nearby do not stay within a neighborhood of the equilibrium point,
the equilibrium point is called unstable.
A consequence of the HartmanGrobman linearization theorem (8) is that it allows us to deduce the
stability of an equilibrium point by looking at the eigenvalues of the linearization.
Theorem 6. Consider Eq. (6). Let xe be an equilibrium point, that is, f (xe ) = 0. Suppose that Df (xe ), the Jacobian
matrix of f at xe , does not have purely imaginary eigenvalues. If all the eigenvalues have negative real parts,
then xe is asymptotically stable, and otherwise it is unstable.

Lyapunov Functions and Lyapunovs Direct Method

As alluded to before, many of the techniques for studying the qualitative behavior of dynamic circuits are based
on studying a simple quantity related to the circuit. One class of such techniques is called Lyapunovs methods.
In these methods, a Lyapunov function is constructed that maps the state of the system x into a simple (usually
scalar) quantity V(x). We then observe how V(x) evolves with time and draw conclusions about the system. For
general nonlinear systems, there are no systematic ways for constructing Lyapunov functions. In some cases,
an energy-like quantity is used for the Lyapunov function.
Definition 4. Let a and b be strictly increasing continuous functions such that a(0) = b(0) = 0. A function V :
Rn R is a Lyapunov function if b(|x|) V(x) a(|x|) for all x.
The basic Lyapunov asymptotic stability theorem is as follows (20):
Theorem 7. Consider the system x = f (x). If V is a differentiable Lyapunov function such that V f (x)
c(|x|) for some strictly increasing function c with c(0) = 0, then the origin is globally asymptotically stable,
that is, all trajectories converge toward the origin.
The construction of V to show stability in this way is called Lyapunovs direct method. A local version of
this theorem is also true when for all x in Definition 4 is replaced by in a neighborhood of 0.
An extension of this theorem, called LaSalles invariant principle (9), is stated (for autonomous systems)
as follows:

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Theorem 8. Consider the system x = f (x). Let V : Rn R be a differentiable function such that V(x) C for
all x and some constant C and

for all t > 0 and some continuous W. Define

Then each solution x(t) of x = f (x) approaches E {}. Although V does not necessarily satisfy the conditions
in Definition 4, we still call V a Lyapunov function when used in the context of Theorem 8.

Content, Co-Content, Energy, and Co-Energy of Two-Terminal Elements

Consider a dynamic circuit consisting of two-terminal elements. We can define energy-like quantities for each
element. For resistive elements, we define content and co-content whereas for dynamic elements, we define
energy and co-energy.
Content and Co-content. A resistive two-terminal elements driving-point characteristic is a relationship between v and i. For a current-controlled resistor, the content is defined as

where v (i) is the voltage-vs-current characteristic of the nonlinear resistor. Similarly, the co-content of a voltagecontrolled resistor is defined as

This is illustrated in Fig. 6. The co-content is the area below the curve, and the content is the area above the
curve within the rectangle. For resistors, which are both voltage- and current-controlled, it is easy to see from

Fig. 6 that, for V = v (I), G(I) + G(V)

= VI is the power dissipated by the resistor.
Energy and Co-energy. We assume that the charge on the capacitors and the flux in the inductors
are zero at time t = 0. For a two-terminal, charge-controlled capacitor with the device characteristic v = v(q),
the capacitive energy (10) is defined as:

The capacitive energy is derived as the work done by the capacitor:

10

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 6. The co-content of a resistor is the area under the curve bounded by the coordinate axes and the dashed vertical
line. The content of a resistor is the area above the curve bounded by the coordinate axes and the dashed horizontal line.

For a two-terminal, voltage-controlled capacitor with the device characteristic q = q(v), the capacitor co-energy
is defined as

A graphical interpretation of the energy and the co-energy is shown in Fig. 7 for the case when the capacitor
is both voltage-controlled and charge-controlled. The co-energy is the area below the curve, and the energy is

the area above the curve bounded by the rectangle. It is clear that, for V = v (Q), U(Q) + U(V)
= QV.
Dually, the energy and co-energy of an inductor are defined as

and

= I.
respectively, and, for I = (), T() + T(I)

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

11

Fig. 7. The co-energy of a capacitor is the area under the curve bounded by the coordinate axes and the dashed vertical
line. The energy of a capacitor is the area above the curve bounded by the coordinate axes and the dashed horizontal line.

Using Content and Energy to Derive the Qualitative Behavior of Dynamic Circuits
Conservation of Energy. Consider a dynamic circuit where all the capacitors are charge-controlled
and all inductors are flux-controlled. Let Dj = vj ij be the power dissipated by the nonlinear resistor Rj . Let U k
and T l be the energies of capacitor Ck and inductor T l , respectively. Then the law of conservation of energy
(expressed as a particular form of Tellegens theorem:  vn in = 0) implies that

at each instant.

Completely Stable Behavior. Definition 5. A dynamic circuit is convergent (or completely stable) if
all of its trajectories converge toward an equilibrium point.
Theorem 9. Consider a dynamic circuit with only charge-controlled capacitors and resistors. Assume that
the characteristics v = v (q) of the capacitors are differentiable and have positive slope everywhere. Assume
also that the resistors are either independent voltage sources or voltage-controlled, eventually strictly passive
resistors with differentiable constituency relationships. If the circuit has a finite number of equilibrium points,
then the system is convergent.
The proof is based on LaSalles invariant principle. The resistors are combined into a resistive n-port
whose constituency relationship is the gradient of a potential function which we choose as the Lyapunov
function. The passivity is used to guarantee eventually bounded solutions. The local passivity of the capacitor
guarantees the negativity of the derivative of the Lyapunov function with respect to the trajectories. Here we
the simple proof from (11). The Lyapunov function equals the sum of the co-contents of the resistors: V = 

give
vk
0 k (v)dv where the summation is over all resistors. Because of the eventual strict passivity of the resistors, a
C can be chosen such that V C. By Theorem 5, the solution of the circuit is eventually bounded. The derivative

12

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

of V with respect to t is given by

where the second equality is from Tellegens theorem. By applying LaSalles theorem (Theorem 8), the conclusion follows.
The following theorems provide criteria for a circuit to have a unique equilibrium point and be convergent
(7):
Theorem 10. An autonomous dynamic circuit is convergent and has a unique equilibrium point if the following
conditions are satisfied:
(1)
(2)
(3)
(4)

There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltages sources.
There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
All resistors (not including sources) are strongly locally passive.
All capacitors and inductors are strongly locally passive.

Theorem 11. An autonomous dynamic circuit is convergent and has a unique equilibrium point if the following
conditions are satisfied:
(1)
(2)
(3)
(4)
(5)
(6)

There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltages sources.
There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
Every loop containing a voltage source also contains a capacitor.
Every cut set containing a current source also contains an inductor.
All resistors (not including sources) are strictly passive.
All capacitors and inductors are eventually strongly locally passive.

Equivalent Resistors, Capacitors, and Inductors. Even though the elements are nonlinear, the
content, co-content, energy, and co-energy enjoy the following linear superposable property. Consider a one-port
N consisting only of arbitrarily connected, nonlinear, charge-controlled capacitors and its equivalent capacitor,
an example of which is shown in Fig. 8. The energy of the equivalent capacitor is the sum of the energies of the
capacitors in N. Similarly, this result is also true for the co-energy of a one-port of voltage-controlled capacitors.
By duality, this result is also true for a one-port consisting only of inductors.
We give the proof here for the energy of a one-port N composed only of capacitors. The sum of the energies
of the capacitors is given by

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

13

Fig. 8. A one-port N consisting of arbitrarily connected capacitors and its representation as an equivalent capacitor.

where the summation is over all branches b in the one-port N. By Tellegens theorem,  vb ()ib ()= v0 ()i0 (),
and thus

which is the energy of the equivalent capacitor.

For a one-port consisting only of resistors, this theorem is true for the content and co-content, provided
that all of the resistors are passive (12).
We give the proof here for the content. Consider a nonlinear one-port as in Fig. 8, except that all the
capacitors are replaced by passive resistors. We wish to show that the sum of the contents of the resistors in
the one-port is equal to the content of the equivalent resistor. The derivative of the sum of the contents of the
resistors with respect to i0 is given by

14

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

where the summation is over all capacitors in the one-port. By Tellegens theorem,

Therefore b Gb /i0 = v0 and

Suppose that i0 = 0. Passivity of the resistors implies that ib = 0 for all
b and consequently Gb = 0 for all b.
i
Putting this into the above equation, we get c = 0 and therefore b Gb = 00 v0 di0 which is the content of the
equivalent resistor.
Stationary Principles. The total content G of a circuit consisting only of current-controlled resistors is
of a circuit consisting only of voltage-controlled
the sum of the contents of each resistor. The total co-content G
resistors is the sum of the co-contents of each resistor. Because the branch currents are uniquely determined
by a link (or co-tree) branch vector, the total content G is expressed as a function of the link branch vector il .
is a function of the tree branch voltage vector vt . Millars theorem on stationary
Similarly, the total co-content G
content (12) states that a set of link branch currents is a solution of the circuit if and only if it is a stationary
point of the total content G, that is, G/il = 0 if and only if il is the link branch current vector corresponding
to a solution of the circuit equations. Similarly, a tree branch voltage vector is a stationary point of the total
co-content if and only if it is a solution of the circuit.
Here we give the proof presented in (13). Let i be the branch current vector. By Kirchhoffs Current Law,
i = BT il , where il is the link branch current vector. Let v be the corresponding voltage vector across the resistors,
v and i satisfy the constituency relationships of the resistors:

which is zero if and only if v satisfies Kirchhoff voltage law, that is, i and v are solutions of the circuit.
These results are also valid for inductor-only and capacitor-only circuits. The total energy of a dynamic
circuit consisting only of charge-controlled capacitors is defined as the sum of the energies of the capacitors.
Similar definitions exist for the total co-energy. Then, in a circuit of charge-controlled capacitors, the link
branch current vector corresponding to a solution of the circuit is a stationary point of the total energy at every
instant. Similar for a circuit of voltage-controlled capacitors, a tree branch voltage vector is at a stationary point
of the total co-energy. In a circuit of flux-controlled inductors, the tree branch voltage vector is at a stationary
point of the total energy, whereas, in a circuit of current-controlled inductors, the link branch current vector is
at a stationary point of the total co-energy.

Unique Asymptotic Behavior

In many applications, we want the circuit to behave roughly the same way, no matter what the initial charges
and fluxes are on the capacitors and inductors, respectively. This is difficult to achieve because the initial
conditions vary widely, so we are content if the circuit behaves roughly the same way after a long enough time
regardless of the initial conditions, that is, the transient behavior dies down.

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

15

In linear systems, we can separate the system response into two parts: the transient or zero-input response
due to the initial states and the zero-state response due to the input. The transient response goes to zero if the
system is stable, leaving us with only the zero-state response, which we call the steady-state solution, and this
gives us the desired property.
In nonlinear circuits and systems, this separation does not exist any longer, but the convergence toward
a steady-state solution regardless of initial condition can still be defined as follows (14):
Definition 6. Assume that the state equations of the system exist and are written as

If all solutions are bounded and any two solutions of Eq. (7) converge toward each other asymptotically, that is
if x(t) and y(t) are solutions of Eq. (7), we get

then we say the system has a unique steady-state solution.

The following theorem gives criteria for a dynamic circuit to have a unique steady-state solution (7,15):
Theorem 12. A dynamic circuit has a unique steady-state solution if the following conditions are satisfied:
(1)
(2)
(3)
(4)

There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltage sources.
There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
All capacitors and inductors are weakly nonlinear and passive.
All resistors (not including sources) are strongly locally passive.

There is a tradeoff between the local passivity of the resistors and the nonlinearity of the capacitors and
inductors. The more locally passive the resistors are, the more nonlinear the capacitors and inductors can be,
and the theorem still remains valid.

Qualitative Behavior of Dynamic Circuits Driven by Periodic Inputs

We have mentioned earlier that even simple, second-order, nonautonomous circuits driven by periodic input
can exhibit complicated chaotic behavior. In these cases the state trajectory can contain frequency components
which are not integral combinations of the driving frequencies. In this section we present some conditions
(7) guaranteeing that solutions of circuits driven by periodic inputs generate only frequency components at
integral combinations of the driving frequencies (harmonics).
Theorem 13. Consider a dynamic circuit driven by periodic inputs. The circuit has a unique steady-state
waveform with frequency components only at integral combinations of the driving frequencies if the following
conditions are satisfied:
(1)
(2)
(3)
(4)

There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltages sources.
There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
All capacitors and inductors are linear and passive.
All resistors (not including sources) are strongly locally passive.

16

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

(5) The external driving sources are defined by differentiable periodic functions.
Theorem 14. Consider a dynamic circuit driven by periodic inputs. The conclusion of the previous theorem
holds if the following conditions are satisfied:
(1)
(2)
(3)
(4)
(5)

There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltages sources.
There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
The circuit either has no capacitors or no inductors.
All resistors (not including sources) are linear and passive.
The external driving sources are defined by differentiable periodic functions.

Theorem 15. Consider a dynamic circuit driven by periodic inputs. The conclusion of the previous theorem
holds if the following conditions are satisfied:
(1) There is no loop in the circuit formed exclusively by capacitors, inductors, and/or voltages sources.
(2) There is no cut set in the circuit formed exclusively by capacitors, inductors, and/or current sources.
(3) All capacitors and inductors are strongly locally passive and have twice-differentiable (C2 ) constituency
relationships.
(4) All resistors (not including sources) are strongly locally passive.
(5) The external driving sources are combinations of dc sources and sufficiently small periodic sources.

ManleyRowe Equations
A characteristic feature of nonlinear circuits is the ability to generate beat frequencies m,n = m1 n2 given
two sinusoidal input signals of radial frequencies 1 and 2 . For resistive networks this can be seen as follows.
Given an input signal sin 1 t + sin 2 t, the output is written as y(t) = f (sin 1 t + sin 2 t). Expressing f as a
Taylor expansion around zero, we obtain

which gives terms of the form m,n sin[(m1 + n2 )t].

The ManleyRowe equations describe the relative power in the various beat frequency components. In
particular, consider the following nonlinear circuit driven by two sinusoidal voltage sources v1 (t) = E1 sin(1 t)
and v2 (t) = E2 sin(2 t) with incommensurable frequencies 1 and 2 as shown in Fig. 9. Two frequencies 1 and
2 are incommensurable if their ratio 1 /2 is an irrational number, that is, there do not exist integers n and
m such that n1 + m2 = 0. The 1 filter indicates an ideal filter, which is a short circuit for sinusoids with
frequency 1 and an open circuit for all other frequencies. We assume that the capacitor is charge-controlled.
Let Pm,n denote the average power corresponding to the frequency m,n which is flowing into the nonlinear

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

17

Fig. 9. A circuit driven by two periodic voltage sources illustrating the ManleyRowe equations.

capacitor. The ManleyRowe equations are expressed as (16):

The same result is valid when the capacitor in Fig. 9 is replaced by a flux-controlled inductor.

Duality
Many of the results in this chapter have dual counterparts. A theorem about RC circuits is also valid for
RL circuits, etc., because of the dual properties of current and voltage. If we look at the circuit equations
(Ai = 0, Bv = 0, constituency relationships, i = dq/dt, v = d/dt) and interchange v with i and interchange q
with , then we obtain another set of constrained differential equations. When do these correspond to the
circuit equations of another circuit (the dual circuit)? The equations i = dq/dt, v = d/dt are interchanged after
the variable interchange. For each constituency relationship, we get the constituency relationship of a dual
element. For a resistor with constituency relationship f (v, i) = 0, the dual element is a resistor with constituency
relationship f (i, v) = 0. For a capacitor with constituency relationship g(q, v) = 0, the dual element is an inductor
with constituency relationship g(, i) = 0. For an inductor with constituency relationship h(, i) = 0, the dual
element is a capacitor with constituency relationship h(q, v) = 0. Finally Kirchhoffs Laws becomes Av = 0,
Bi = 0. Are these the Kirchhoff Laws of another circuit? The answer is affirmative if and only if the underlying
graph of the circuit is planar, that is, it can be drawn on the two-dimensional plane so that branches intersect
only at the nodes.
For a circuit with a connected planar underlying graph, the dual circuit is found by the following algorithm
(17):
(1) Draw the underlying graph in planar form with n nodes and b branches. It partitions the plane into (b n
+ 2) connected regions by Eulers formula. The dual graph has (b n + 2) nodes and b branches. Draw
exactly one node of the dual graph lying in each region.

18

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

Fig. 10. (a) A nonlinear circuit and its associated graph. The dual graph is shown with dashed branches. (b) The dual
circuit of (a) and its associated graph.

(2) Each branch of the graph lies exactly between two regions. Draw a branch of the dual graph connecting the
nodes of the dual graph in these two regions.
(3) The direction of the branch in the dual graph is found as follows. For a branch in the graph, find the region
adjacent to the branch which is bounded. If the branch encircles this region clockwise, the corresponding
branch of the dual graph points toward the region. Otherwise, it points away from this region.
(4) A branch of the dual graph corresponds to each branch of the original graph. The dual circuit has the
topology of the dual graph, and the element of each branch is the dual element of the original circuit at the
corresponding branch.
For example, in Fig. 10(a), we show a circuit and its corresponding graph. The dual graph is shown with
dashed lines. In Fig. 10(b), we show the dual circuit along with its corresponding graph. From the previous
discussion, a circuit and its dual circuit have the same qualitative dynamics, because they share the same state
equations except for a renaming of the variables.
Note that the dual of the dual circuit is the original circuit, but with all the nonlinear elements turned
upside down.

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

19

Thus for a circuit with a planar underlying graph, the operation of turning all the elements upside down
results in a circuit with the same qualitative dynamics as the original circuit. In fact the underlying graph
needs not be planar.
Theorem 16. By turning all the elements of a circuit upside down, we obtain a circuit with the same state
equations.
This can be shown as follows. Turning all the elements upside down reverses the directions of all the
branch currents and branch voltages but does not change the constituency relationships nor the equations
i = dq/dt and v = d/dt. If Kirchhoffs laws are Ai = 0, Bv = 0 for the original circuit, they are now Ai = 0 and
Bv = 0 for the new circuit. So the same Kirchhoff laws for the original circuit also hold for the new circuit.
Note that the underlying graph does not need to be planar for this theorem to be true.
Many of the results in this article can be extended to general circuits with multi-terminal devices. In
some of the results, e.g., the results on completely stable behavior, an additional technical requirement of
reciprocity is imposed on the circuit elements. Unfortunately, many of todays circuits contain nonreciprocal
circuit elements such as transistors (17,18,19).

BIBLIOGRAPHY
1. L. O. Chua C. A. Desoer E. S. Kuh Linear and Nonlinear Circuits, New York: McGrawHill, 1987.
2. R. K. Miller A. N. Michel Ordinary Differential Equations, New York: Academic Press, 1982.
3. D. W. Jordan P. Smith Nonlinear Ordinary Differential Equations, Oxford Applied Mathematics And Computing Science
Series, Oxford, 1977, Chap. 11, 333338.
4. K. Murali M. Lakshmanan L. O. Chua The simplest dissipative nonautonomous chaotic circuit, IEEE Trans. Circuits
Syst. I, Fundam. Theory Appl., 41: 462463, 1994.
5. C. W. Wu G. Q. Zhong L. O. Chua Synchronizing nonautonomous chaotic systems without phase-locking, J. Circuits,
Syst., Comput., 6 (3): 227241, 1996.
6. L. O. Chua et al. A universal circuit for studying and generating chaos, parts III, IEEE Trans. Circuits Syst. I, Fundam.
Theory Appl., 40: 732761, 1993. Special Issue on Chaos in Electronic Circuits, Part A.
7. L. O. Chua Dynamic nonlinear networks: State-of-the-art, IEEE Trans. Circuits Syst., 27: 10591087, 1980.
8. P. Hartman Ordinary Differential Equations. New York: Wiley, 1964.
9. J. P. LaSalle An invariance principle in the theory of stability, in Differential Equations and Dynamical Systems (J. K.
Hale and J. P. LaSalle, eds.), New York: Academic Press, 1967, pp. 277286.
10. C. Cherry Some general theorems for non-linear systems possessing reactance, Philos. Mag., 42 (333): 11611177, 1951.
11. M. Hasler Qualitative analysis, in The Circuits and Filters Handbook (W.-K. Chen, ed.), Boca Raton: CRC Press, 1995,
Chap. 31, pp. 914934.
12. W. Millar Some general theorems for non-linear systems possessing resistance, Philos. Mag., 42 (333): 11501160, 1951.
13. L. O. Chua Stationary principles and potential functions for nonlinear networks, J. Franklin Inst., 296 (2): 91114,
1973.
14. L. O. Chua D. N. Green A qualitative analysis of the behavior of dynamic nonlinear networks: Steady-state solutions
of nonautonomous networks, IEEE Trans. Circuits Syst., 23: 530550, 1976.
15. M. J. Hasler P. Verburgh On the uniqueness of the steady state for nonlinear circuits with time-dependent sources,
IEEE Trans. Circuits Syst., 31: 702713, 1984.
16. J. M. Manley H. E. Rowe Some general properties of nonlinear elementspart I. general energy relations, Proc. IRE,
44: 904913, July 1956.
17. L. O. Chua Introduction to Nonlinear Network Theory, New York: McGrawHill, 1964.
18. W. Rudin Principles of Mathematical Analysis, 3rd Ed., New York: McGrawHill, 1990.
19. J. Guckenheimer P. Holmes Nonlinear Oscillations, Dynamical Systems, and Bifurcations of Vector Fields, New York:
Springer-Verlag, 1983.
20. M. Vidyasagar Nonlinear Systems Analysis, Englewood Cliffs, NJ: Prentice-Hall, 1978.

20

QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS

READING LIST
Reference 17 is an excellent classic text on nonlinear circuit theory.
M. P. Kennedy L. O. Chua Circuit Theoretic Solutions for Neural Networksan Old Approach to A New Problem, Proc.
IEEE ICNN, San Diego, CA, June 1987, II-169II-176. This paper uses the co-content function of a nonlinear network
to study the stability of the Hopfield neural network
Reference 7 is a good source of more advanced results in the qualitative analysis of nonlinear circuits.
L. O. Chua Nonlinear Circuits, IEEE Trans. Circuits Syst., 31 (1): 6987, 1984. Contains extensive bibliography.

CHAI WAH WU
IBM T. J. Watson Research Center

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

OSCILLATOR DESIGN
The development of electronic oscillators was strongly related to the invention of the vacuum tube at the
beginning of the twentieth century. The first oscillator circuits were presented by Meissner, Hartley, and
Colpitts, among others, and basic ideas for a theory of such circuits were presented by Vallauri in 1917 (1).
In 1914 Zenneck considered an oscillatory arrangement with an arc as the active device, and he discussed
nonlinear aspects of electronic oscillators by means of an energy balance equation. Unfortunately, he did not
derive the corresponding differential equations for the currents and voltages. A differential equation for a
triode oscillator was presented for the first time by van der Pol in 1920. His studies became the starting point
for a long series of research in mathematics, physics, and electrical engineering on oscillatory networks and
systems. As a result, a first monumental monograph about this subject was published by Andronov et al. in
1937 (2) that included the essential aspects of the theory of oscillatory circuits and systems and was illustrated
by many examples. At the same time Krylov and Bogoliubov (3) published essential results about the analysis of
oscillatory circuits. Both groups started from the work of van der Pol and used ideas and results from the work
of the French mathematician and physicist Henri Poincare. Short presentations of the history of these methods
can be found in Sanders and Verhulst (4) and Mathis (5). Although the results of these authors were discussed
several times in the literature, most of them were unknown to many researchers until the late sixties. Maybe
this is one of the reasons that, in contrast to the linear analysis of oscillatory circuits and systems, details of the
nonlinear theory due to the above-mentioned Russian research groups were not included in a design theory of
oscillators. We will show in this article that the design of oscillators can be clarified if their ideas are included.

Foundations
Properties of Electrical Oscillators. In order to understand the difficulties related to electronic
oscillators it is useful to discuss the main properties of the behavior of such electronic circuits and consider
some aspects of their modelling. It is well known that the basic behavior of an electronic oscillator should be
characterized as follows (e.g. Parzen (6)]:

Some voltages and/or currents should behave in a periodic manner. The most important shapes of the
output are sinusoidal, saw tooth, and square waves.
The oscillator frequency should be well determined.
After a transient, the oscillator amplitude should be well determined and independent of the initial conditions.
Perturbations of the oscillatory behavior in the steady state should die out after some transient behavior.
The oscillatory behavior should not be destroyed by parasitic circuit elements (structural stability).

From these qualitative properties the main features of electronic oscillators can be extracted and serve
as main specifications:
1

OSCILLATOR DESIGN
Oscillator frequency
Oscillator amplitude
Rate of the startup and decay

Obviously we have to add further properties if electronic oscillators are to be designed. The signal-tonoise ratio, the stability of the oscillator frequency and amplitude and the distortions with respect to a desired
waveform are a few of these properties. The basic behavior of electronic oscillators cannot be realized or
modelled by using linear (time-invariant) circuits, because such circuits have to be nondissipative (no ohmic
resistors can be included) if periodic behavior is desired. Therefore, the energy is conserved and their oscillatory
amplitude depends on the initial conditions. Furthermore, such linear (nondissipative) oscillator models are not
structurally stable (see the above characterization), because the periodic behavior is destroyed by arbitrarily
small dissipative elements (e.g. ohmic resistors). Thus mathematical models of electronic oscillators have to
be nonlinear. In 1963 it was emphasized by Hale (7) that our knowledge of nonlinear systems is still far from
complete, and only a few mathematical techniques are available to analyze such models. Although intensive
research has been carried out in this area for more than thirty years, many problems still have to be solved to
obtain a satisfactory theory. Good illustrations of this statement can be found in Guckenheimers discussion of
the van der Pol equation (8).
Oscillator Models. Although a linear LC-circuit without dissipation is not suitable as a complete model
for electronic oscillators, it is useful to start with such a circuit and to introduce the following changes:

Compensation of the dissipation with negative resistors or positive feedback

Comparison of the oscillator amplitude with a prescribed value in an implicit or explicit manner, and control
the negative resistor or the feedback

It should be emphasized that compensation is a linear technique, whereas amplitude control by using
parameter variation is an inherently nonlinear technique.
These two steps can be described mathematically if we start from the differential equation for an LC
circuit with a rather small resistor (dissipation).

where is proportional to the (positive) resistance. Using a compensation technique, can be cancelled. For
example, this can be done by adding a negative resistor in series (or parallel) with the positive resistor, with
the same magnitude. If Eq. (1) is converted to the state-space form x = Ax by the notation x1 : = x, x2 : = x , it is
easy to see that applying a compensation technique results in a pair of eigenvalues of A on the imaginary axis.
In more general cases the state space has dimension n > 2, since there are more than two reactances. Usually
the matrix A has at least one pair of eigenvalues other than those with negative real parts. In the subsection
The Linear Design Theory of Sinusoidal Oscillators below, several approaches are discussed that can be used
to find a set of parameters where a pair of eigenvalues with zero real part occur. Furthermore, it should be
emphasized that it is not necessary that we start with an LC circuit, since it is for example, possible, to realize
inductors in an active manner by means of resistors, capacitors, and (operational) amplifiers. In contrast to LC
oscillators, these kind of oscillators are called RC oscillators [see e.g. Millman and Grabel (9)]. The first RC
oscillator was presented by Heegner (10) in 1927; see also Sidorowicz (11) further references.
If the resistor, or in other words , is controlled by the state variables (x, x ), we get the following nonlinear
differential equation:

OSCILLATOR DESIGN

Special choices of the function = (x, x ) lead to particular nonlinear oscillator models. In the next subsection
this problem is discussed by means of the theorem of Poincare, Andronov and Hopf.
It is mentioned above that the van der Pol (vdP) equation was the first model of an oscillator circuit. The
normalized version of this equation has the following form (with normalized 2 0 = 1):

Note that this differential equation is of the above-mentioned form. Another differential equation of a similar
type is the (R) Rayleigh equation (with normalized 2 0 = 1)

Unfortunately, the equilibrium solution O : = {x(t) = 0 |t IR} is the only solution that is known in exact terms.
All other solutions, and in particular the periodic solution, have to be calculated with perturbation methods.
Therefore we consider a modified differential equation (with normalized 2 0 = 1),

with the periodic solution xp :={x(t) = cos t t IR}, which can be calculated in a simple manner. Obviously, this
solution is unique up to an additive phase , and the periodic solution does not depend on the parameter .
An advantage of this equation is that it can be interpreted very easily. For this reason xp is represented in the
state space (x1 := x , x2 : = x) as a circle. The state-space representation of Eq. (5) is

Within the circle the (nonlinear) coefficient of the second term in Eq. (5) is negative, and outside the circle the
coefficient is positive. If this coefficient is constant, both differential equations correspond to the descriptive
equation of an LC circuit with linear damping through an ohmic resistor. If we assume the (nonlinear) coefficient
in Eq. (5) to be constant for a moment, the first case corresponds to an LC circuit with a negative resistor, and
the second case to a circuit with a positive resistor. From this heuristic point of view it is easy to interpret the
global behavior of Eq. (5). Although its solutions cannot be calculated analytically if the initial conditions are
prescribed within or outside the circle xp , the qualitative behavior of the differential equation follows from the
analogy with an LC circuit with damping. We find that the amplitude of every solution that starts within the
circle increases and approaches xp as t . On the other hand, the amplitude of every solution that starts
outside the circle decreases and approaches xp as t . From a physical point of view the two-dimensional
state space of the differential equation (5) is decomposed by the circle xp into two areas that have different
meanings:

The negative-damping area (inside the circle), where energy is supplied to the system
The positive-damping areas (outside the circle) where energy is dissipated by the system.

The periodic solution xp can be interpreted as a dynamical equilibrium between the negative and the
positive damping area. Stable periodic solutions of this kind are called limit cycles [see e.g. Jordan and Smith

OSCILLATOR DESIGN

Fig. 1. Negative-damping area of the Rayleighvan der Pol equation.

Fig. 2. Damping areas: vdP van der Pol equation; R Rayleigh Equation.

(12)]. In contrast to limit cycles, a stable equilibrium O is embedded in a positive-damping area. Both types of
solutions are called steady-state solutions. In Fig. 1 the state space and the steady-state solutions of Eq. (5)
are shown together with the damping area.
The physical situation of this rather special differential equation is the typical case in two-dimensional
state-space systems. In Fig. 2 we show the damping areas of the van der Pol equation and of the Rayleigh
equation, which extend infinitely in the x2 and x1 directions, respectively. It is clear why sinusoidal solutions
are impossible, since the damping areas are not symmetric with respect to the unstable zero solution point.
The parameter  can be interpreted as a measure of deviation from the sinusoidal case. If << 1, we
have a sinusoidal oscillator that is discussed in the next sections. For large  >> 1 we obtain a relaxation
oscillator that is considered in this subsection. The latter case is much more complicated from a mathematical
point of view, because circuits of this kind have to be described by differentialalgebraic equations or analyzed

OSCILLATOR DESIGN

by singular perturbation methods [see e.g. Mathis (5)]. However, the design of square-wave oscillators can be
simplified if the transistors are modelled as switches. Such models are piecewise linear. In the case of sinusoidal
oscillators an overall model is available.
The MandelstamPapalexiAndronov Oscillator Model. Although the simple oscillator equations
in the last section are very suitable for illustrating the physical reason for periodic steady-state solutions, a
more extended model should be considered that includes additional parameters. From a systematic point of
view a family of differential equations is considered that is parametrized by means of the mentioned parameter,
and the following questions are studied:

Is there a subset of equations that permit a periodic steady-state solution?

If so, what is the critical value of the parameter where a qualitative change within the family arises?

These questions are crucial for the design of electronic oscillator circuits. Therefore these problems
were studied around 1930 by Mandelstam, Papalexi, and Andronov using ideas from Poincares theory of
celestrial mechanics. As a result they proved a theorem including a criterion for the occurrence of a limit
cycle in differential equations depending on a certain parameter. In the mathematical literature this theorem
is known as the Hopf bifurcation theorem because Hopf, rediscovered it in 1944 while studying problems in
hydromechanics [see Arnold (13)], p. 271) for further information about the reception of this theorem]. The
MandelstamPapalexiAndronov oscillator model contains a parameter that is suitable for generating a limit
cycle if a critical value is passed. In oscillator design this parameter corresponds to a circuit parameter. (e.g.
the load resistor). Before formulating the PoincareAndronovHopf theorem, we will demonstrate the birth of
a limit cycle. For this purpose a modification of Eq. (5) is used, since it can be solved exactly. This equation is
formulated in the state-space representation [see e.g. Nicolis and Prigogine (14)]

where the parameter is included in another way. To solve this differential equation we transform it into the
magnitudephaseangle representation

Obviously the system of two differential equations is decoupled, and in this case solutions of both equations
are known. We have

In Fig. 3 the steady-state behavior of Eqs. (8), (9) is illustrated for < 0 and > 0, and we find that in the
latter case we have the desired limit cycle. The above-mentioned critical parameter value is zero.

OSCILLATOR DESIGN

Fig. 3. Bifurcation of a limit Cycle: (a) < 0, (b) > 0.

It can be shown that this case already describes a very general situation. If we consider n-dimensional
systems of differential equations that describe more complicated electronic oscillators, the so-called center
manifold theorem can be used to reduce the dimension of the system to two. [For details of this theorem we
refer to the monograph of Arrowsmith and Place. (15)]. Then the former case is obtained, but in this introductory
article we cannot discuss further details, and therefore the reader is referred, (for example) to Hassard et al.
(16).
In the following, the PoincareAndronovHopf theorem is formulated.
Theorem (PoincareAndronovHopf). Let

be a system of differential equations where f (0, ) = 0 for all in a neighborhood of 0. The Jacobian Dx f (0,0) of
f in (0, 0) has the eigenvalues 1,2 = j with = 0 and n 2 other eigenvalues k with  k < 0. Furthermore
d d  {1 ()}| = 0 > 0, and the equilibrium point 0 is a stable spiral in = 0. Under these assumptions
sufficiently small positive numbers 1 and 2 exist such that for all  ( 1 , 0) the equilibrium point 0 is a
stable spiral and for all  (0, 2 ) the equilibrium point 0 is an unstable spiral. In the last case the unstable
spiral is surrounded by a stable limit cycle whose amplitude increases with .
Instead of a proof [see e.g. Hassard et al. (16) or Mathis (5)], this theorem is illustrated by the van der Pol
equation.
Example. The van der Pol equation (3) can be formulated by a standard
y := x into a

transformation
system of differential equations of first order. Using the normalization u : = x and v : = y, the following
differential equations result:

The eigenvalues of the Jacobian matrix are

OSCILLATOR DESIGN

and therefore 1,2 = j (for = 0) and d d  1 () | = 0 = 12 > 0. It can be shown that if = 0, the equilibrium
point (u, v) = (0, 0) is a stable spiral. It results from the PoincareAndronovHopf theorem that a stable limit
cycle is generated for > 0 that encloses an unstable spiral.
This oscillator model and the theorem were formulated for the first time by Andronov and his coworkers
in 1934, studying electronic oscillator circuits, but it was 1979 before Mees and Chua published theoretical
considerations about oscillator design using this theorem [see Mees (17)]. On the other hand, a necessary
condition of this theoremBarkhausens oscillatory conditionwas a known long time ago and became the
basis of a linear design theory for oscillators.

Design Aspects
The Linear Design Theory of Sinusoidal Oscillators. It is known from the PoincareAndronov
Hopf theorem that one pair of eigenvalues has to cross the imaginary axis, whereas the other eigenvalues have
to remain within the left half complex plane. Obviously, it is a necessary condition that oscillator circuits have
a pair of eigenvalues on the imaginary axis for a certain value of some circuit parameter. It is mentioned in
the subsection Oscillator Models above that this condition can be interpreted as the compensation step of
oscillator design, which can be performed in a linear manner using a linear negative resistor. This necessary
assumption of the PoincareAndronovHopf theorem has been known since the first oscillator paper of Vallauri
(1) in 1917, and during the following few years several variants of his results were published. One of the most
popular criteria was the Barkhausen oscillatory condition [see e.g. Millman and Grabel (9)]. All these variants
can be classified by using the following topological structures of oscillator circuits:

the negative-impedanceadmittance model

the positive-feedback model

and applying corresponding methods of network analysis. It has been known for a long time that these
two models are equivalent from a network-theoretical point of view.
Many oscillator circuits contain tubes or transistors. In the case of tuned-circuit oscillators it is more
efficient to describe such a circuit as an active 3-pole with a passive impedance embedding (see Fig. 4). This
was done for the first time in 1920 by Hazeltine (18). He showed that in Fig 4 the impedances Z1 , Z2 , and Z3
have to be capacitive, capacitive and inductive, respectively. The reader will find systematic conderations about
this subject in the books of Spence (19) and Cassignol (20). Since this rather restricted model for oscillator
circuits can be reformulated in the form of the negative-impedanceadmittance model or the positive-feedback
model, we discuss the use of the latter models in more detail. For this purpose we consider a rather simple
oscillator circuit in order to avoid tedious calculations; further examples can be found in textbooks of electronics
[e.g. Millman and Grabel (9)].
As the first step the network elements of an actual oscillator circuit have to be associated with the defining
blocks of the above-mentioned models. In general this step includes some arbitrariness. The second step uses
the conditions that a pair of eigenvalues with vanishing real parts have to occur, formulated for the special
topology of the models. As a result we obtain (necessary) conditions for the occurrence of oscillations with
respect to the oscillator frequency and the gain of the active elements parametrized by means of the network
parameters of an actual oscillator circuit. These conditions represent the linear part of the design of oscillator
circuits.
Now we compile the corresponding conditions for the above-mentioned oscillator models (see Parzen (6),
Chap. 1):

OSCILLATOR DESIGN

Fig. 4. Active 3-pole structure of transistor oscillators.

Fig. 5. Negative-impedance and admittance oscillator model.

Negative-impedance model The real and imaginary parts R and X, respectively, of the model in Fig. 5 have
to satisfy the conditions

Negative-admittance model The real and the imaginary parts G and B, respectively, of the model in Fig. 5
have to satisfy the conditions

Positive-Feedback model The open-loop gain consisting of the transfer functions A(s) and (s), respectively,
of the active block and the passive block (see Fig. 6) has to satisfy the condition

In the literature these conditions are called the Barkhausen criterion [see e.g. Millman and Grabel (9)].
Instead of the decomposition of the complex equation into the real and the imaginary part, a representation
with magnitude and phase angle is preferred.

OSCILLATOR DESIGN

Fig. 6. Feedback oscillator model.

Of course, a network analysis in a straightforward manner leads to equivalent conditions for the occurrence of oscillations. For this purpose we consider the ac network model of an oscillator circuit that contains
no independent sources and derive its network equations in the frequency domain. As a result we obtain a
homogeneous system of linear equations

with the oscillation frequency j as the parameter. Note that an oscillator circuit contains only constant
independent sources. Therefore these sources are omitted in the small-signal model. The matrix coefficients
contain the network parameters. It is known from linear algebra that nontrivial solutions are obtained if the
condition

is satisfied. The equivalence of this expression to the other criteria can be shown.
There is another method that is equivalent to a circuit analysis under certain conditions. In this case a
transfer function is defined with respect to a (sinusoidal) input source and two terminal as the output port.
This approach can be applied in a successful manner only if

The input current or voltage source does not change the oscillator circuit substantially, that is, we recover
the initial circuit if the input source vanishes
The circuit is controllable and observable with respect to the chosen input and output ports

The first condition is satisfied if we use pliers entry and an independent voltage source or soldering-iron
entry and an independent current source [see e.g. Desoer and Kuh (21)]. For the second condition a careful
analysis of the circuit is needed before the two-ports are chosen.
Example: Tunnel Diode Oscillator [Mees (17)]. The nonlinear network equations of the circuit in Fig. 7
can be formulated as (if R 0)

10

OSCILLATOR DESIGN

where u C := U 0 uC . Since the constant solution can be calculated in a simple manner as

the ac network model (linearized network equations) can be derived without distinction between large and small
signal currents and voltages. Let g be the derivative of g with respect to its argument; then the transformation
of this equation into the frequency domain leads to the following condition:

The roots of this quadratic equation are

and therefore a purely imaginary pair of eigenvalues is obtained if the condition

is satisfied. In this case the oscillator frequency is given by 2 0 = 1/(LC). We find from the tunnel-diode characteristic that this is possible if the operating point of the diode is located at its maximum or minimum,
where the derivative g (U 0 ) vanishes. If the ac network model of this tunnel-diode circuit is interpreted as the
negative-conductance model, we find the oscillatory conditions

Obviously these conditions are equivalent to the previous one. A negative-resistance model is not suitable
in this example. If the negative-conductance model is assumed, a transfer function is determined if an extra
(index E) independent sinusoidal voltage source U E is located as an input quantity in series with the linearized
tunnel diode resistor and the capacitor voltage U C is used as output quantity; both U E and U C are represented
in the frequency domain. The corresponding transfer function can be derived:

The zeros of the denomiator are the eigenvalues of this circuit. Under the same condition [g (U 0 ) = 0] on the
voltage U 0 , we obtain a pair of imaginary eigenvalues and the oscillatory frequency) given by 2 = 1/LC. Finally
we consider the approach where the positive-feedback model is applied. For this purpose we reformulate the
negative-conductance model so that the conductances Y g = g (U 0 and Y L (j) = 1/ZL (j) become identical,
that is the sum of the admittances Y g and Y L has to be zero. By means of ZL (j) an interpretation as a product

OSCILLATOR DESIGN

11

Fig. 7. Tunnel-diode oscillator model.

is possible if the sum is reformulated as

This is Barkhausens condition if Y g and ZL (j) are interpreted as transfer functions of a feedback model. Since
this reformulation is derived by means of equivalent calculation steps, the same conditions for the occurrence
of oscillations are obtained. Probably it is rather a problem of taste and/or experience which approach is used
to derive the oscillatory conditions. For example, Parzen (6) discusses the design of tuned-circuit oscillators
with transistors, and therefore he uses the above mentioned active three-pole representation with passive
embedding. Based on this model, the author applies the negative-resistanceconductance model to calculate
the oscillatory conditions. Mauro (27), prefers the positive-feedback model and derives similar conditions for
tuned-circuit oscillators as well as RC oscillators. In general both approaches can be used successfully, and
therefore the choice makes no difference from a theoretical point of view.
The Nonlinear Design Aspects of Sinusoidal Oscillators. Although many aspects of the nonlinear
theory of oscillator circuits are known, it is not trivial to make use of them to construct a systematic design
concept for these circuits. The theoretical results are at least suitable for a classification of oscillator circuits
and for the construction of simulation tools. We will discuss these subjects in this and the following sections.
Just as in other cases of circuit design, an oscillator circuit is determined if its network topology as well as its
network parameters is known. A design process starts with some specifications of the desired oscillator circuit,
and then we try to find an oscillator topology together with a certain set of network parameters in order to
fit these specifications. For this purpose the following approach can be used. Further details can be found for
example, in the monograph of Parzen (6).
(1) Basic Specifications The form of the oscillator behavior (sinusoidal, rectangle, triangle, etc.), frequency of
the oscillator, the amplitude, and so on, are taken into consideration.
(2) Choice of the Circuit Devices The application of the oscillator circuit, the working temperature, and so on,
are taken into consideration.
(3) Choice of the Type of Resonator The frequency stability, the amplitude stability, the variability of the
frequency, and the economic expense are taken into consideration.
(4) Choice of the Kind of Limiting that Maintains the Oscillator Amplitude A self-limiter, external limiting, or
automatic-level-control limiting can be chosen.
(5) First Draft of the Oscillator Circuit The above aspects are taken into consideration.
(6) Determination of Circuit Parameters The actual circuit devices and its circuit parameters have to be chosen.
(7) Optimization Circuit simulations and/or an experimental realization are necessary. If the circuit does not
meet the specifications, then some steps have to be repeated.

12

OSCILLATOR DESIGN

This design summary shows that each design process of an oscillator circuit presents peculiar problems.
However, we will make some general remarks based on the theoretical considerations above. Although the
frequency of an sinusoidal oscillator can be determined by a linear analysis (see the Barkhausen condition
in the previous subsections, in view of the PoincareAndronovHopf theorem nonlinearities are essential for
the functionality of oscillators (see the subsection Oscillator Models above). We already mentioned in that
subsection that a nonlinearity is necessary for limiting the amplitude. This can be provided in one of three
ways:
(1) Self-Limiting The inherent linearity of an active device (tube, transistor, operational amplifier, etc.) is used
to build up a nonlinear differential equation with a stable limit cycle. In this case the amplitude is fixed
implicitly by the type of nonlinear characteristic. The only requirement is to calculate the amplitude with
a suitable model of the nonlinear device.
(2) External Limiting This is a variant of the first case, since the resonant circuit works in a linear mode and
the limiting is introduced by an additional device (Zener diode, symmetrical clippers, thermistors, etc.).
(3) Automatic-Level-Control Limiting The natural approach to limiting is amplitude controlthat is, measuring the amplitude, comparing it with a desired amplitude value, and adjusting (if necessary) a circuit
parameter that controls the damping of the circuit through a suitable control strategy. Even if the resonant
circuit is approximately linear, the entire circuit, including the control part, is nonlinear because there
is a coupling between at least one state variable and a circuit parameter. A suitable discussion for the
construction of such control devices can be found in the monograph of Parzen (6) and the dissertation of
Meyer-Ebrecht (23).
The first way of limiting of the oscillator amplitude leads to a rather simple construction of the oscillator
circuit, but in this way the damping element is influenced by the large signal gain factor. Unfortunately, this
gain factor varies with the instantaneous amplitude of the oscillator and results in spectral distortions. This
is an essential disadvantage in the case of sinusoidal oscillators. If such

an oscillator with low distortion is
desired, the nonlinear damping should depend on an indefinite integral x(t) dt of the amplitude x(t) instead of
the instantaneous amplitude. In mathematical terms this statement can be formulated as follows if we restrict
our discussion to an oscillator circuit of van der Pol type. Then the descriptive equation is of the form

instead of

Although the structure of an oscillator circuit and its amplitude stabilization are essential, analysis
methods are necessary in order to calculate at least the amplitude and the frequency as a function of certain
circuit parameters for a suitable design of a sinusoidal oscillator. Since analytical solutions of the corresponding
network equations of an oscillator are not available, perturbation methods have to be applied for this purpose.
Several approaches are available:

Perturbation methods
Averaging or harmonic balance, methods

OSCILLATOR DESIGN

13

Describing-function method
Volterra series method

Most of the different variants of perturbation methods start with some Fourier polynomial and, based on
this first step derive a set of associated differential equations. Therefore these methods can be interpreted as
time-domain methods, which are considered and illustrated in the monograph of Nayfeh (24). The first-order
perturbation results are of special interest in practical oscillator design. Also the averaging (harmonic balance)
methods can be interpreted as time-domain methods. A very efficient variant of an averaging method that
can be implemented in a computer algebra program uses Lie series [see Kirchgraber and Stiefel (25)]. It was
applied for studying electronic oscillators by Keidies and Mathis (26).
Another time-domain method can be interpreted as an extension of the convolution description of linear
time-invariant inputoutput systems, which is implemented in Volterra series methods. In this case a series
of integrals is used as a first step and the coefficients are convolution kernels of higher order. Illustrations of
this method are included in the paper of Chua and Tang (27).
An efficient iterative procedure for calculating the steady-state output waveform of almost sinusoidal
nonlinear oscillators using the feedback formulation is presented by Buonomo and Di Bello (28). In their paper
this method is compared with the alternative methods of Mathis and Keidies as well as Chua and Tang. Just
like the other methods, the interative approach can be implemented by means of a computer algebra system.
Since frequency-domain methods are very successful in the case of linear time-invariant circuits and
systems, many electrical engineers are greatly interested in extensions of these approaches to nonlinear
circuits and systems. The describing-function method is very popular because it can be interpreted as an
extension of the transfer-function method, which is a standard method in the analysis of linear time-invariant
networks. We have to assume that only the first-harmonic part of the response of a nonlinear block to a
sinusoidal input function is of interest, because the other parts will be filtered out. If the functionality of
the sinusoidal oscillator is interpreted in terms of the feedback structure in Fig. 6, this filter is realized
within the feedback loop. Although the nonlinear block produces an entire spectrum of output frequencies as
a response to a sinusoidal input function, only the first-harmonic part is essential for the functionality of a
sinusoidal oscillator. Therefore the describing-function method is illustrated by means of the feedback model
of a sinusoidal oscillator, although extensions of the negative-impedance and admittance models, respectively,
are possible [see e.g. Cassignol (20)].
We restrict our discussion to the case where only the A block in Fig. 6 contains nonlinear elements and
the input signal is x(t) =  cos t. Then a first-harmonic part can be extracted from the output signal

where we assume that no constant part is included in the output signal. Clearly the amplitudes y1 , y2 , and the
phases 1 , 2 , . . . depend on  and . The describing function is defined by

As a result we obtain a generalization of the Barkhausen oscillatory condition:

In many cases N( ) is independent of . Then () can be plotted as a single polar curve in the complex
plane, graduated in , and likewise the locus of 1/N() can be plotted, graduated in . The intersection

14

OSCILLATOR DESIGN

Fig. 8. Two-port oscillator.

of these curves corresponds to a limit cycle, whose stability properties can be studied. More details of this
approach are included in the monograph of Mees (17), where its problems are also discussed.
Design of Two-Port Oscillators. In the following we consider the two-port oscillator formed by a
frequency-dependent linear feedback two-port and a nonlinear active two-port as depicted in Fig. 8. The output
signal of the linear two-port is amplified in the nonlinear active two-port and then fed back to the input of the
linear two-port. A necessary condition for the occurrence of a stationary harmonic oscillation is that the phase
and the amplitude of the signal, after passing both two-ports, are unchanged. Due to the frequency-dependent
linear feedback two-port, the phase condition is only fulfilled for one frequency. Due to the nonlinearity of the
active two-port, the amplitude condition is only fulfilled for one value of the amplitude of the signal.
In our example we consider the simple model of an active two-port formed by a voltage-controlled current
source. The voltagecurrent characteristic of the voltage-controlled current source is assumed to be nonlinear.
If the active two-port contains additional linear elements, these elements may be moved to the linear two-port.
In our example the linear frequency-dependent two-port consists of a transformer with primary inductance
L1 , secondary inductance L2 , and mutual inductance M; a capacitor C; and a conductor G. The primary and
secondary coils of the transformer are in antiphase, and therefore M < 0. The secondary inductance L2 and
the capacitor C together form a parallel resonant circuit. This inductor-coupled resonant circuit is the most
compact model we can establish for the linear feedback circuit.
In more complex cases we can replace the reactive part of the feedback two-port by the canonical Foster
representation (29). In the neighborhood of the resonant frequency the essential part of the canonical Foster
realization is given by a transformer-coupled resonant circuit, as assumed in our model. In the case of small
losses it is also possible to include the losses in this model (30). The conductor G accounts for the losses in the
passive and the active two-ports. At the resonant frequency of the parallel resonant circuit,

the phase change in the linear two-port is 180 . This compensates for the 180 phase change occurring in the
active circuit, and the phase condition for oscillation is fulfilled.
The nonlinear dependence of the output current i2a (t) of the linear two-port on its input voltage i1a (t) is
given by

The active two-port is considered to be frequency-independent. It is assumed that all reactive elements of the
active element have been moved to the linear two-port. This can be done easily if the reactive elements are
linear, and if it is possible to concentrate all reactive elements in a  equivalent circuit. The relation between

OSCILLATOR DESIGN

15

the spectra of the input current I1l () and the output voltage U 2l () of the linear feedback network is given by

where A21 is the matrix element of the chain two-port representation. According to Fig. 8 we obtain u1a = u2l
and i1l = i2a . Furthermore, we consider i1l (t) I1l () and u2l (t) U 2l (), where ()(t) ()() denotes in a symbolic
manner a pair of Fourier-transformed functions in time and frequency domain.
We assume that in the oscillator circuit, Fig. 8, oscillations are excited by an initial perturbation. After
some period of growth of amplitude due to the nonlinearity of the active element, the oscillator will saturate in
a stationary state oscillating at a frequency 0 . In the case of a weak nonlinearity the oscillation exhibits only
low harmonics. The linear feedback network acts as a bandpass filter and attenuates the harmonics. In the
case of a sufficiently high Q factor of the resonant circuit and a weakly nonlinear active element, the transient
of the oscillator from excitation to the stationary state exceeds the period of oscillation by orders of magnitude.
We also can assume that the time constants governing the decay of the perturbation of the stationary state of
the oscillator exceed the period of oscillation by orders of magnitude. Under these assumptions we can make
for u2l the first step

where V(t) and (t) denote the amplitude and the phase of the oscillator signal. Due to the nonlinearity of the
active two-port, the output amplitude I at the fundamental frequency 0 depends nonlinearly on the input
amplitude V. With 0 t = we obtain from Eq. (36) the fundamental frequency component of the output current,

This relation holds also for slowly time-varying amplitudes, and we obtain

With a21 (t) A21 () we obtain from Eq. (37) the relation between the input current i1l (t and the output voltage
u2l (t of the linear feedback circuit in the time domain:

Representing Eq. (40) by

and expanding into a first-order power series yields

16

OSCILLATOR DESIGN

Inserting this expression into Eq. (41) gives

With the substitution t t1 = t2 we obtain

Using a21 (t) A21 () and ta21 (t) j A 21 () with A 21 () = dA21 ()/d, we obtain

With Eq. (40) and i1l = i2a it follows that

Introducing the conductance G0 and the susceptance B0 by

yields

where the prime () denotes the derivative with respect to evaluated at = 0 . For the stationary state it
follows that

OSCILLATOR DESIGN

17

We now investigate the influence of small perturbations V 1 of the stationary amplitude V 0 . With the first
step

we linearize I(V) VG0 in a neighborhood of the stationary amplitude V 0 . With

we obtain for small-amplitude deviations V 1 from the stationary state the linear differential equation

The stationary state of oscillation is stable if any perturbation V 1 is decaying. This holds for

The relation between I and V may be expressed by a nonlinear transconductance S given by

In this case the stability condition (58) can be written in the following form:

For the Meissner oscillator with transformer feedback circuit according to Fig. 8 the parameters G0 and B0 are
given by

The condition (54) yields the frequency of oscillation 0 in the stationary state according to Eq. (35). Due to
Eq. (53), the stationary amplitude V 0 can be determined from

18

OSCILLATOR DESIGN

From

and Eq. (60) it follows that the stationary state of the two-port oscillator considered is stable for

that is, for a transconductance S that decreases with increasing amplitude V.

Design of Relaxation Oscillators. In the subsection Oscillator Models it was mentioned that the
van der Pol equation is suitable also as a model for relaxation oscillators if << 1 is considered. Unfortunately,
analytical solutions are not available in this case, and for the derivation of approximative solutions advanced
mathematical methods are necessary [see e.g. Andronov et al. (2) or Mathis (5)]. Therefore almost all design
methods for relaxation oscillators are based on more simplified models for the active devices (e.g. transistors or
operational amplifiers). If the transistors are replaced by switches [see e.g. Horenstein (31)] we obtain piecewise
linear oscillator models; note that such models are nonlinear, as was always the case. Some disadvantages of
this approach are known:

The transient to the steady state (or limit cycle) cannot be obtained in a simple manner.
A limit cycle has to be assumed.
The results are independent of certain parameters of the active devices.

However, under these assumptions simple design formulas can be derived, since only linear (timeinvariant) networks have to be analyzed. We illustrate this approach in the case of a symmetrical multivibrator
that is working in saturated mode. More complicated situations (e.g. if transistors are not working in saturated
mode) will be found for example in Gray and Meyer (32).
Example: Symmetrical Multivibrator. We consider the multivibrator that is shown in Fig. 9. Let us assume
that at the initial instant t = 0, the left transistor T 1 conducts and the right transistor T 2 is cut off. If the voltage
across the left capacitor is near to zero while that across the right capacitor reaches the voltage U 0 , a switching
event occurs. During the commutation where T 1 switches to the cut-off state while T 2 changes to the conducting
state, the left Capacitor charges and the right capacitor discharges. The situation for t > 0 can be analyzed by
means of a simple analysis of the network in Fig. 10. The following differential equation results:

where uC (0) = U 0 . The solution is derived by well-known calculations:

A switching event takes place if uC (t) that corresponds to the baseemitter voltage of T 2 exeeds the cutoff
voltage (which is simplified to zero in our case). From the above solution we have

OSCILLATOR DESIGN

19

Fig. 9. Symmetrical multivibrator.

Fig. 10. Dynamic operation.

and therefore the period of the square wave is T 1.38 Rb C. It is an easy matter to include cutoff and saturation
quantities for the transistors [e.g. Cassignol (20)]. In the same way, results for other relaxation oscillators can
be derived that include operational amplifiers or digital gates [see e.g. Horenstein (31) or Kurz and Mathis
(33)]. Furthermore, saw tooth-wave oscillators can be analyzed if piecewise linear models of the active devices
are used. The reader is referred to the literature for further details [e.g. Davidse (34)].

Advanced Microwave Oscillator Design Tools

Problems in Microwave Oscillator Design. Although this article is concerned with design methods
for all kinds of oscillators, the design of microwave oscillators has been of special interest during the last 15
years. Many results are published in the literature. Therefore an overview is presented in this section. But it
should be mentioned that almost all methods can be used to design other kinds of oscillators.
The design of monolithic integrated microwave and millimeter-wave oscillators requires accurate and
efficient tools for numerical modelling and optimization. Today the design of microwave oscillators in many
cases is based on a linear analysis of the oscillation conditions. To predict and to optimize the oscillator output
power or the oscillator spectral behavior, however, a nonlinear design approach is indispensable.
The task of oscillator modeling can be separated into two parts:

Nonlinear modeling of the unperturbed oscillator

Modeling of the noise properties of the oscillator

20

OSCILLATOR DESIGN

The nonlinear modeling of the unperturbed oscillator may be done in the time domain by numerical
integration (35,36,37) in the frequency domain using harmonic balance or Volterra series methods (38,39,
40,41,42) or by using combined timefrequency-domain methods (43,44,45,46). Microwave oscillators may be
subdivided into a linear embedding circuit and one or more nonlinear subcircuits. By this subdivision, the
computational effort may be reduced considerably. The easiest approach is to subdivide the active element
of the oscillator into a linear embedding network and a single nonlinear controlled source. In this way, the
modeling may be improved over the linear approach, as shown for example in Refs. 47,48. This method is
restricted to a single dominant nonlinearity in the oscillator circuit.
More accurate circuit modeling requires the inclusion of numerous nonlinear circuit elements in the
simulation. Approximating the distributed elements within a broad but finite frequency interval by a lumpedelement equivalent circuit facilitates the description of the unperturbed network by a set of nonlinear and
autonomous first-order differential equations in the normal form

The components of the vector x are the state variables of the system. Time-domain integration of the network
equations describing the equivalent lumped-element circuits usually requires an enormous computational
effort, since the system of differential equations is usually high-dimensional and also exhibits high stiffness.
One method for reducing the computational effort is to combine time-domain and frequency-domain calculations
(43). The periodic steady-state solution can be found in the time domain by solving the periodic boundary-value
problem (35). The solution obtained in the time domain is exact and in this respect superior to that from
harmonic balance. Using the multiple shooting algorithm of Bulirsch, the convergence of the time-domain
boundary-value problem may be improved (49,50).
Schwab et al. have applied the time-domain boundary-value method to the self-consistent determination
of the steady-state solution of oscillators (37). The time-domain method has the advantage that it is not
necessarily restricted to a certain number of harmonics of the signals.
The most common method for frequency-domain analysis of oscillators is the harmonic balance method.
Using that method, a nonlinear system of equations

has to be solved. In this equation X is the system state vector summarizing the amplitudes of n signals at
the fundamental frequency 0 and at K harmonics (38,39,40,41,42). The advantage of the harmonic balance
method is that distributed circuits can also be considered in the analysis.
In the combined timefrequency-domain method the oscillator circuit is subdivided into a linear circuit
and a nonlinear circuit (43,44). The linear part of the circuit is described in the frequency domain, whereas
a state-variable description in time domain is applied to the nonlinear part. This allows one to combine the
advantages of frequency-domain and time-domain methods. In the linear part of the circuit, distributed circuit
elements can also be considered.
Time-Domain Method. The computation of the steady-state solution of the oscillator by solving the
initial-value problem (86) for t has the disadvantage of large numerical effort. For most practical cases
interest is restricted to the periodic steady-state solution x(t) = x(t + T 0 ) for the nonlinear oscillator waveform.
The period of oscillation T 0 is not known. In order to determine it we include T 0 as an additional variable with
the state variables x and introduce the normalized time variable = t/T 0 . We have now to solve the two-point

OSCILLATOR DESIGN

21

boundary-value problem for [0,1]:

The n + 1 boundary conditions are

where the last condition fixes the phase of the limit cycle. Let us denote the solution of the initial-value problem
(71) at +1 with the initial conditions s at by e(s , , +1 ). The solution of the boundary-value problem is
equivalent to the determination of the zeros of the vector-valued function

This algorithm is called the single-shooting method, and in general it has only a small domain of convergence.
A better way to solve the boundary-value problem is to use the multiple-shooting algorithm (43,49,50).
This algorithm is more stable and has a wider domain of convergence than the single-shooting one. By this
method the region between the boundaries is divided into several subregions,

and for every subregion a starting point is chosen:

These starting points are varied until a continuous solution fulfilling the boundary condition is found, which
can easily be seen to be the zero of the vector-valued function

where the last two rows represent the boundary conditions and the others the continuity conditions.

22

OSCILLATOR DESIGN

Because of the special structure of Eq. (77), the zeros can be computed in a very efficient way (49). To
achieve starting values for T 0 and x, the set of nonlinear differential equations (86) is linearized at the unstable
stationary point x0 , with the Jacobian

with x0 given by F(x0 ) = 0. Then T 0 and x(t) can be estimated by

where 1 ,. . .,n the n eigenvalues and e1 ,. . .,en the corresponding eigenvectors of the Jacobian J. Here v is
the eigenvalue with  v > 0. The stiff-stable Gear algorithm (36) has proven to be an effective method for
numerical integration.
Frequency-Domain Method. Using the harmonic balance technique, the steady state of the unperturbed oscillator may be computed in the frequency domain. The n state variables of the oscillator are summarized in the state vector X:

Since all state variables are periodic in the limit cycle, the time-domain state variables xi can be expanded into
Fourier series with the Fourier coefficients X i,l . The frequency range considered is limited to K harmonics:

The Fourier coefficients of the state variables X 0 are determined by the solution of a nonlinear system of
equations

This system, with dimension n(2k + 1) and n(2k + 1) unknowns, exhibits an infinite one-dimensionl manifold
of solutions, since the phase of a free-running oscillator is arbitrary. The solution can be made unique by
specifying the phase of one Fourier coefficient. The frequency of oscillation is an unknown variable and is also
determined by solution of the system equations.
TimeFrequency-Domain Method. Time-domain methods are efficient for the analysis of circuits
exhibiting strong nonlinearities. However, it is not possible to include linear distributed circuits in the timedomain analysis. Especially in microwave oscillator design, the linear embedding circuits usually contain
distributed circuits. The method described in the following is based on the subdivision of the oscillator network
into the following two subsets:

The linear embedding network

The nonlinear subnetworks with neighboring low-pass structure

OSCILLATOR DESIGN

23

Fig. 11. Linear and nonlinear parts of oscillator Network.

Fig. 12. Separation of the linear and nonlinear network parts.

Therefore the network can be represented by a circuit model as shown in Fig. 11.
The linear embedding network may be described effectively in the frequency domain. The linear and
nonlinear parts of the oscillator network are connected via a number M of ports. The port voltages and currents
are described by the vector l(t) = [vT (t), iT (t)]T . Nonlinear resistors and nonlinear conductances are replaced by
voltage and current sources and described, in common with all other sources within the nonlinear subnetwork,
by the vector l(t) = [v0 (t), i0 (t)]T . In a subsequent step the linear and the nonlinear subnetworks are separated
from each other, and the port voltages and currents represented by the vector l(t) are also replaced by voltage
and current sources, as shown in Fig. 12.
Based on the time-domain description (36), the nonlinear subnetwork is characterized by

where x are the independent state variables, and w is a function of the state variables and their time derivatives,
w = w(w, x ). The matrices A, B, C, and D, representing also nonlinear capacitors and inductors, depend on
x and x . Due to the dependence of the matrices A, B, C, D and the vector w on x , the system of differential
equations (83) is implicit. This system can be made explicit and put into the normal form by imposing the
condition that the matrices A, B, D and vector w depend only on x and not on x . This condition is fulfilled if:

24

OSCILLATOR DESIGN
In the nonlinear subnetwork no current source is connected to a node that is connected only to current
sources and to inductors.
In the nonlinear subnetwork no voltage source is within a mesh containing only voltage sources and
capacitors.

Under these conditions the matrix C vanishes. If we also require that w depend only on the system state
variables x and not on their time derivatives, we obtain from Eq. (83)

The vector cT (t) = [ir (t), ur (t)], dual to l(t), is given by

By appropriate separation into a nonlinear and a linear subnetwork, large time constants (originating for
example from feedback loops or bias networks) may be eliminated. As a result, the differences between the
time constants are smaller, and the stiffness of the system is reduced considerably. If we treat the whole
network totally in the time domain, the linear subnetwork does not exist, and therefore the term D(x)l(t) in
Eq. (84) vanishes and we obtain

The nonlinear oscillator subnetwork is described by Eqs. (84) and (85). In addition to the periodic boundary
condition x(t) = x(t + T 0 ), the voltages and currents of c(t) and c (t) must coincide. c (t) may be expressed by

where V(t) is the impulse response of the linear subnetwork. As in the previous section we normalize the time
variable with respect to T 0 and obtain

Since the oscillator signals are assumed to be periodic, it is possible to represent the port variables l(t) by
periodic Fourier series,

From Eq. (87) we obtain

OSCILLATOR DESIGN

25

where V is the hybrid matrix of the linear multiport, at the th harmonic, which can be computed with
standard linear network analysis methods. The Fourier series expansion representing the port variables is
truncated after the kth element. In this case, due to the sampling theorem, it is necessary and sufficient that
the condition c(t) = c (t) be fulfilled for 2K + 1 discrete time values within the interval T 0 ). We obtain

The solution of Eq. (91) and the periodic boundary condition may be expressed, as in the subsection TimeDomain Method as the solution of a boundary-value problem. The state equations of the nonlinear subnetwork
are therefore supplemented by (2K + 1)M additional state equations

The required n + (2K + 1)m boundary conditions are

Notice that the boundary conditions are no longer only given at = 0 and = 1, but at 2K + 2 points = (1)/(2K
+ 2), = 1, . . ., 2K + 2. Because of the special structure of the boundary-value problem the multiple-shooting
algorithm can be adapted in a numerically efficient way (43).

Noise in Oscillators
Problems in Microwave Oscillator Noise Analysis. Noise analysis of microwave oscillators is usually based on the assumption that the unperturbed state of the oscillator is almost sinusoidal. This allows the
application of a describing-function method for the characterization of the nonlinear devices in the oscillator
(52),
(51). Based upon this method, the noise behavior of microwave oscillators has been analyzed by Spalti
Edson (53) and Kurokawa (54,55). These methods have been applied and extended to special cases (56,57,58).
The above methods provide a good qualitative and to some extent also a quantitative description of the
oscillator noise behavior. However, their applicability is restricted to simplified oscillator models, since their
accuracy depends on the validity of the approximation of the dynamic behavior of the nonlinear elements by a
describing function (55). Another severe limitation is that the upconversion of low-frequency noise such as 1/f
noise cannot be treated by these methods.

26

OSCILLATOR DESIGN

Kartner
has developed a time-domain method for noise analysis of oscillators, based on the solution of
the Langevin equations (59, 60). Adding the noise terms to the normal-form equations (69) yields

The vector describes white noise sources, and y1 ,. . ., yM represent f noise sources. Colored noise sources may
be derived from white noise sources by inserting linear systems transforming the white noise sources to colored
noise. For considering f noise sources infinite-dimensional systems are required. However, as shown in Ref.
60, these infinite-dimensional systems may be treated with analytical formulas, so that f noise sources may
be treated with low computational effort. Using the perturbation method, the correlation spectra of the phase
and amplitude noise due to white noise sources as well as due to f noise sources can be calculated. The
method has been applied to bipolar transistor oscillators (59,60), to planar integrated microwave oscillators
(61,62), and to varactor tunable oscillators (63).
Frequency-domain noise analysis can be performed on the basis of the harmonic balance method (64,65,
66). Starting from the harmonic balance equations (70), we obtain a nonlinear system of equations

In this equation X T is the system state vector summarizing the signal spectra of n signals at a frequency
close to the fundamental frequency 0 and at k harmonics. The subscript T denotes that the signals are timewindowed (67,68). The vector N T summarizes the r noise-source spectra at a frequency and at harmonics.
The numerical solution of this equation is based on correlation-matrix techniques.
Combining time- and frequency-domain techniques is also possible in noise analysis (69). The phase noise
is computed in the time domain. The linear subcircuits are described by noise multiports. This method again
exhibits the advantages of the timefrequency-domain method.
In Ref. 66 the results of measurements on designed and fabricated integrated oscillators are compared
with numerical simulations based on the methods discussed above. Furthermore that paper considers a method
to minimize oscillator phase noise by numerical optimization. Based on the computation of the oscillator steadystate and spectral behavior in the time domain, single-sideband phase noise is minimized using a method for
optimal-control problems, a direct collocation algorithm (69,70)
Another essential requirement is the simulation of the startup behavior of oscillators. If the resonator
is weakly damped, it is well known that many oscillations occur on the way to the steady state. Although
some analytical results are available [see e.g. Rusznyak (71). where a simplified model of a crystal oscillator is
used, the corresponding simulation problem is very complicated [see Schmidt-Kreusel (72)]. Recently SchmidtKreusel published an efficient solution for this problem, which is based on the idea that the transient trajectory
of a weakly damped oscillator consists of nearly closed trajectories in the state space. If only a few parts of
this transient are approximated by periodic solutions, the envelope of the transient behavior can be calculated
in a fast manner. This approach is described in detail by Mathis (73). Recently, an alternative approach was
published by Brachtendorf and Laur (74) that uses a certain kind of partial differential equations for calculating
the envelope.
Description of Noisy Circuits. In linear noisy circuits we usually have to deal with stationary Gaussian noise signals. Such signals may be characterized completely by their correlation spectra (75). For a signal

OSCILLATOR DESIGN

27

s(t) unlimited in time, the average power within the time interval of length 2T centered around t is given by

If for large time intervals 2T the average power approaches a limit, which is independent of t, the signal s(t) is
called stationary. The average power P of a stationary signal can be exactly defined by

We investigate the more general function

Which is called a correlation function. For i = j, the function Cii () is the autocorrelation function of the signal
si (t) and for i = j we have the cross-correlation function Cij () of the signals si (t) and sj (t). With the time-windowed
function sT (t) of the signal s(t) defined by

we can write Eq. (98) in the form

The average power P of the signal Si (t) is given by

We denote the Fourier transform of the time-windowed function siT (t) by SiT (f ):

As mentioned before, the symbol represents the correspondence between a pair of Fourier transforms. From
Eq. (102), we obtain

28

OSCILLATOR DESIGN

The symbol denotes the convolution operation

The correlation spectrum Cij (f ), given by

is the Fourier transform of the correlation function:

Cii (f ) with i = j is the autocorrelation spectrum of the signal si (t) and Cii (f ) with i = j is the cross-correlation
spectrum of the signals si (t) and sj (t). With the exception of a dimensional factor, Cii (f ) is a spectral power density
or a power spectrum. Since the autocorrelation function is a real and even function of , the autocorrelation
spectrum is a real and even function of frequency.
The cross-correlation function is complex. Changing the sign of the frequency or interchanging the indices
i and j yields its complex conjugate.

The factor 2 results from considering both the positive- and negative-frequency parts. In general for random
signals no amplitude spectra exist, whereas power spectra may be calculated even for random signals.
For a stationary noise signal sni (t) the Fourier integral does not exist. However, a correlation function

can be defined, in which the brackets indicate the statistical mean over signals measured on an ensemble of
identical circuits. If the signals sni (t) and snj (t) have zero mean, in general, the mean of the product sni (t)snj (t )
approaches 0 with arbitrary order for , so that the integral (108) and also its Fourier transform exist.
Since the Fourier integral of a time-windowed function exists in general, the correlation spectrum may also be
defined by

In this case, T has to be carried out after the ensemble averaging. The autocorrelation and cross-correlation
spectra Cij (f ) of the noise sources of a linear network are given by

OSCILLATOR DESIGN

29

where SiT (t), SjT (t) are the spectra of the time-windowed signals of the noise sources. The correlation spectra
Cij (f ) can be combined in the correlation matrix

The correlation matrix C(f ) can be represented as the product of the column vector

and its Hermitian conjugate row vector

in matrix notation by

We now formally use the complex amplitudes SiT (f ) in the same way as the amplitudes of deterministic signals.
SiT (f ) is the spectrum of a time-windowed noise signal. We can measure the noise signal within some finite
interval of time, and we may calculate the spectrum of this sample. This specific sample of a noise signal
has to be considered as a deterministic signal, since we have exact knowledge of its time dependence. The
transition from deterministic signals to random signals is carried out in our description by performing the
ensemble average. After doing so, in the case of random signals, the decomposition of the correlation matrix
into a product of a column vector and a row vector will be impossible. For example in the case of a signal vector
describing independent random noise sources, the nondiagonal elements will be averaged out to zero and the
correlation matrix will be diagonal.
In general, the network equations have the following form in matrix notation:

The coefficient matrix M(f ) combines the complex amplitude vectors ST (f ) and S T (f ). Multiplying Eq. (115) on
the right by its Hermitiean conjugate, we obtain

30

OSCILLATOR DESIGN

Fig. 13. Noisy two-port oscillator.

Evaluating the ensemble average on both sides and subsequently carrying out the transition T we obtain

This establishes a general rule for deriving equations for the correlation matrices from linear equations
for the signal amplitudes. A linear noisy two-port may be characterized by two equivalent noise sources. These
sources may be located at the input or at the output. If both sources are located at the same port, one must be
a voltage source in series with the port and the other must be a current source in parallel with the port. If one
equivalent noise source is assigned to every port, in general we may choose an equivalent current source or an
equivalent voltage source at each port.
Noise in Two-Port Oscillators. We analyze the noise behavior of the simple two-port oscillator shown
in Fig. 13. The left two-port is the linear frequency-determining feedback two-port. In our example the feedback
network of the Meissner oscillator was chosen. The right two-port is the nonlinear amplifying two-port. In our
example, all internal noise sources of the linear two-port as well as the nonlinear two-port are summarized in
the noise current source IT r (f ). This equivalent noise source is obtained in the following way: In the first step,
describe the noise properties of the linear feedback two-port by an equivalent output noise located at its output,
and the noise properties of the active two-port by equivalent noise sources located at its input. To extract the
noise parameters of the active two-port, we consider it to be linear. After connecting the output of the feedback
two-port to the input of the active two-port, we can contract the four equivalent noise sources into one noise
source IT r (f ).
For the oscillator circuit depicted in Fig. 13 the following equations are valid:

OSCILLATOR DESIGN

31

The variables I1lT (f ), V 2lT (f ), V 1aT (f ) and I2aT (f ) are the noise current and voltage amplitudes at the ports
of the two-ports. To investigate of the oscillator noise behavior we have to consider the nonlinear saturation
properties of the active two-port. A21 (f ) and A22 (f ) are circuit parameters of the feedback two-port in chain
representation. In our simple model we describe the active element by a nonlinear voltage-controlled current
source. With the real amplitude V of the oscillator signal at the input of the nonlinear two-port we describe
the relation between input and output noise signals by the amplitude-dependent transconductance S(V). From
Eqs. (118) to (121) we obtain

The autocorrelation spectra CI (f ) and CV (f ) of the noise current source Ir T (f ) and the voltage current
source V r T (f ) are given by

With Eq. (122) we obtain

For the Meissner oscillator the circuit parameters of the linear feedback two-port are given by

32

OSCILLATOR DESIGN

where M is the mutual inductance of the transformer and L2 is the inductance of the secondary coil. Substituting
into Eq. (125), we obtain

The power spectral density at the load conductance G is

and the total power flowing into G is given by

With

we obtain

The frequency deviation f from the carrier is given by f = f f 0 . For f << f 0 we can approximate

To characterize the oscillator noise we introduce the noise measure M r . The noise measure is the factor by
which the power spectral density of a noise source exceeds the thermal noise. The autocorrelation spectrum of
the equivalent noise source of a conductance G exhibiting thermal noise at a temperature T is given by 2kTG.
From this definition it follows that

From Eqs. (130), (131), (135), and (136) we obtain the power spectral density of the oscillator,

OSCILLATOR DESIGN

33

From Eqs. (132) and (136) we obtain the average total power

We define the spectral width of the oscillator as the ratio of the average power P 0 to the power spectral density
W (f 0 ) at the center frequency f 0 ,

and obtain

In the oscillator without noise, S equals G0 , whereas in the noisy case we have G0 S > 0. The oscillator
amplitude is determined by the nonlinear gain characteristics of the active element. It is only slightly influenced
by the noise source. The ratio G0 /(G0 S) is determined by the ratio of the saturation power P 0 to the injected
noise power. Using Eq. (138), we can express G0 S the ratio of the power spectral density of the equivalent
noise source to the saturation power of the oscillator and obtain

The spectral width of the oscillator is directly proportional to the noise measure M r , and inversely
proportional to the reciprosal saturation power and to the square of the quality factor Q of the resonant circuit.
Low-noise design of oscillators requires a low-noise active element, a high quality factor of the active circuit,
and a high saturation power of the oscillator. Since the amplitude of the oscillator is stabilized by the nonlinear
saturation behavior of the oscillator, an oscillator exhibits primarily amplitude noise.
Noise Analysis in the Frequency Domain. In the following a frequency-domain perturbation method
for simulating the noise behavior of free-running microwave oscillators is presented (66). The method is based
on a piecewise harmonic balance technique. The single-sideband phase noise of the oscillator is derived from
the system equations. The method is limited neither to certain circuit topologies nor to certain types of noise
sources.
Fluctuations of the State Variables. In the frequency-domain method, noise sources may be considered by extending the nonlinear system of equations (82). Introducing the noise source vector NT (), which
summarizes the time-windowed spectra of the noise sources, the system equations now exhibit the following
form:

The index T denotes the time-windowed signal spectra as defined in Eq. (102). The vector NT  Cr(2k+1) summarizes the amplitudes at the fundamental frequency 0 and at the harmonics up to K0 of a number r of noise
sources of arbitrary spectrum. In Eq. (142) all harmonics up to kth order and their fluctuations are considered.

34

OSCILLATOR DESIGN

This allows us to compute the complete correlation spectrum at the frequency deviation m = 0 . All noise
processes, including the upconversion of low-frequency noise, are considered. Since the noise contribution is
small compared with the deterministic part of the oscillator signal, the noise contribution may be considered
as a first-order perturbation. From Eq. (142) we obtain

with G(X 0 T , )  Cn(2k+1)r(2k+1) and

The matrix G(X 0 T , ) describes the coupling of the noise sources NT with the system. It is assumed that noise
sources effect only a small perturbation of the limit cycle of the oscillator:

Therefore the system of nonlinear equations (143) may be linearized in the neighborhood of the limit cycle, and
we obtain

with the Jacobian matrix J(X 0 T , )  Cn(2k+1)n(2k+1) of the unperturbed system equations given by

This equation describes the perturbation of the oscillator by the noise sources. It includes the mixing of the
injected noise signals NT with the unperturbed state variables XT 0 . From the solution of the linearized system
of equations (146) the correlation spectra of the state variables may be computed.
A problem arises from the fact that the Jacobian matrix J(X 0 T , 0 ) is singular for the limit cycle of the
unperturbed system (35,76) The linearized perturbed system equations cannot be solved by inversion or by
LR decomposition. The smallest eigenvalue of the Jacobian is 1 = 0. A perturbation XT corresponding to
the eigenvalue 0 of the Jacobian induces a perturbed solution X 0 T + XT, which is again a solution of the
system equations (142). The eigenvector corresponding to the eigenvalue 1 = 0 is tangent to the limit cycle.
The fluctuations in direction of this eigenvector are the phase fluctuations. The subspace spanned by the other
eigenvectors of the Jacobian is the space of the amplitude fluctuations. This subdivision of the eigenvector
space of the Jacobian allows a clear and well-defined distinction between phase and amplitude fluctuations.
Solution of the System Equations Including Noise. The Jacobian is singular at the steady state, and
for a small frequency deviation f m of the carrier frequency the deviations of the matrix elements are small and
the condition number of the Jacobian remains high (76). The condition number cond, defined by

OSCILLATOR DESIGN

35

provides a measure for the numerical error in the solution of a linear system of equations (77, 50). Here J is
the matrix norm of the Jacobian J. The condition number of a matrix may be approximated by the ratio of its
largest to its smallest eigenvalue (77). The largest eigenvalue is much larger than the frequency of oscillation
f 0 , because it is related to the fastest process of the system. The smallest eigenvalue is of the order of the
frequency deviation f m , as we will show later in Eq. (166). Therefore the condition number cond of the Jacobian
is much larger than the ratio of the carrier frequency to the frequency deviation of interest (78):

This means that the steady state of an oscillator has to be determined to a much higher precision than the
reciprol of the condition number to achieve a relative error smaller than 1 (50). Considering a 10 GHz oscillator
and a frequency deviation of say, f m = 10 kHz, the condition number is much larger than 106 . To overcome the
numerical problems the Jacobian is linearized at the carrier frequency with respect to the frequency:

with the abbreviation

An eigenvalue decomposition (77) of the Jacobian with left- and right-side eigenvectors is used. Thus the
complete correlation spectra can be calculated in a numerically stable way. First we want to analyze the
unperturbed Jacobian J (X 0 T , 0 ). The left- and right-side eigenvectors of the Jacobian are denoted by V j and
Wi , and the eigenvalues by V j and W j respectively. We have

The eigenvalues of the Jacobian are equal for a set of left- and right-side eigenvectors:

The left- and right-side eigenvectors satisfy the orthogonality relations (76)

36

OSCILLATOR DESIGN

According to these equations, the eigenvector V1 is orthogonal to all right-side eigenvectors Wi with the
exception of W1 . The eigenvectors corresponding to the eigenvalue 1 = 0 are denoted by V1 and W1 . These
eigenvectors will be investigated in the following in detail.
The eigenvector W1 is determined by the steady-state solution (64,79):

where K  IRn(2k+1)n(2k+1) is a matrix that has only nonvanishing diagonal elements consisting of the numbers
of the harmonics:

Figure 14 illustrates the meaning of the eigenvectors i (t) and i (t) in the time domain. The vector 1 (t) V1 (f )
is the tangent vector to the steady-state limit cycle x0 (t), and 1 W1 (f ) is the normal vector defining a plane
N that is mapped onto itself by the unperturbed flux of the linearized set of differential equations (Poincare
map); see Ref. 60. The left-side eigenvector V1 is determined via

which is a linear homogeneous system of equations and can be solved with a standard LU decomposition. The
length of the vector V1 has to be normalized to satisfy, Eq. (155):

The eigenvectors Wi are a complete basis for the state space, and due to Eq. (155) a multiplication of V 1 with a
vector within the state space is a projection onto the complementary space of the plane N. This means that the
projection operator W1 V 1 applied to any vector z = n i = 1 ai Wi results in a vector with a tangential component
a1 with respect to the limit cycle. So if this projection operator W1 V 1 is applied to the noise sources in the state
space G(X 0 T,)NT the contributions of the noise sources that cause a phase shift of the unperturbed steady
state are separated. This will be shown in the following. For a small frequency deviation f m the deviations of
the elements of the Jacobian are small. Therefore the deviations of the eigenvalues and eigenvectors of the
Jacobian are small too (77):

OSCILLATOR DESIGN

37

The eigenvalues and eigenvectors of the perturbed Jacobian J (X 0 T , 0 ) are denoted by a prime. It is sufficient
to consider the deviations of the eigenvalues and eigenvectors up to the first order in m :

The eigenvalue  1 is of special interest, since it is identical with the deviation 1 from the lowest eigenvalue
1 = 0 of the unperturbed system. Using Eq. (156), we obtain

The smallest eigenvalue of the perturbed Jacobian  1 = 1 is therefore of the same order of magnitude as
the small frequency deviation m . The inverse J 1 (X 0 T , 0 ) of the Jacobian is represented by an eigenvalue
decomposition with the eigenvalues and left- and right-side eigenvectors of the Jacobian J (X 0 T , 0 ):

This inversion will not be performed, due to the ill-conditioning of the Jacobian. We have derived this equation
only to calculate the correlation spectrum of the state-variable fluctuations. Later on we take into account the
special eigenvalue  1 that causes the ill-conditioning of the matrix and the problems associated with numerical
inversion.
The state-variable fluctuations are given by

Correlation Spectrum of the Oscillator Noise. The correlation spectra of the state variables CX (f ) and
the noise sources CN (f ) are given by

38

OSCILLATOR DESIGN

Fig. 14. Limit cycle in a two-dimensional phase space.

where the brackets denote the ensemble average. The correlation spectra of the state variables are derived
using Eqs. (169), (171) and the equation (168) of the state-variable fluctuations:

with the abbreviation

The approximations Eqs. of (163), (164), and (165) for the eigenvalues and eigenvectors of the perturbed
Jacobian are used to derive the correlation spectra of the state-variable fluctuations. The term with the major
contribution to the correlation spectrum is the term with i = j = 1, due to the small eigenvalue  1 =  1 given
in Eqs. (27). This term represents, as already described, the phase noise of oscillators. As the perturbations
of the eigenvectors W1 and V1 are of the order of m and therefore small compared with the unperturbed
eigenvectors, they are negligible, and we have

Due to the special situation of the eigenvalue  1 and the eigenvectors W1 and V1 , the terms with i = 1
and j = 1 or i = 1 and j = 1 in Eq. (171) represent the amplitude-phase correlation spectra. Finally, the terms

OSCILLATOR DESIGN

39

with i = 1 and j = 1 in Eq. (171) represent amplitude noise. These noise contributions are small compared with
the phase noise, due to their larger eigenvalues, and are not taken into account in the following.
Single-Sideband Phase Noise. The single-sideband phase noise L(f m ) is the ratio of the noise power in
a sideband of bandwidth 1 Hz at a frequency deviation f m = f f 0 from the carrier frequency to the total signal
power PS . The value of L(f m ) is the same for all state variables, and therefore we can choose any state variable
xi to calculate the single-sideband phase noise:

In order to obtain the single-sideband phase noise at the fundamental frequency, the matrix element corresponding to the ith state variable is chosen, which represents the noise power at the fundamental frequency.
We have to select the element |X 0 i,1 |2 of the matrix KX 0 X 0 X and obtain for the noise power PNi (f m ) in a 1 Hz
bandwidth

Here Rn is a normalization resistance. The signal power of the fundamental frequency is represented by

With the definition of the single-sideband phase noise in Eq. (174) we derive an equation for L(f m ) using the
approximations of the noise power (175) and the signal power (176):

where V 1 is the solution of the homogeneous linear system of equations

which can be obtained very easily with a standard LU decomposition of the Jacobian. The derivative of
the Jacobian with respect to the frequency, J (U 0 , 2F 0 ), can be calculated numerically, as we will show
in our example. The denominator of the second factor is constant for different frequency deviations and
needs to be calculated only once. The numerator consists of the correlation spectrum of the noise sources
multiplied by the vector V 1 on the left side and by V1 on the right side. As we already described, this
multiplication is a projection of all noise sources of the state space onto the tangent vector to the steady state.
That means the vector V1 selects the contributions of the noise sources that are tangential to the steady state
and therefore induce phase noise. The noise sources (1/f noise and white noise and their modulation are taken
into account in the correlation matrix CGN . The correlation spectrum of a 1/f -noise source decreases at 10 dB
per frequency decade, and therefore L(F m ) decreases at 20 + 10 dB per decade. The single-sideband phase noise
decreases at 20 dB per decade due to white noise sources, because the correlation spectra of white noise sources
are independent of frequency. This method results in a numerically stable calculation of the phase noise of

40

OSCILLATOR DESIGN

free-running oscillators, where all effects of the noise sources converted with harmonic signals are taken into
account.

Synchronization of Oscillators
In the previous sections electronic oscillators without excitation are considered but even in the early days
of oscillators an undesired entrainment phenomena in forced oscillators was described by Moller (80) and
others [see van der Pol (81) around 1920. Although van der Pol mentioned forced oscillations in his 1920
paper he only considered circuits with positive (differential) resistances. In 1922 Appleton (82) discussed
automatic synchronization of forced triode oscillators (only another expression for entrainment), and in the
following years this subject was studied in more detail [see van der Pols review paper (83)], but a sound
mathematical basis for entrainment phenomena was not presented until the paper of Andronov and Vitt (84)]
in 1930, where again mathematical ideas of Poincare were used. A modern presentation can be found for
example in the monograph of Jordan and Smith (12). In 1945 Tucker emphasized (85), The synchronization
(or entrainment) of oscillators was originally investigated because of difficulties experienced with early radio
transmitters of pull-in to adjacent-station frequencies. Since then, however, the properties of oscillators under
the influence of injected tones have been utilized in several ways, and he mentioned ideas from his Ph.D. thesis
about applications to carrier telephone systems, and Kirschsteins (86) miscellaneous applications in radio and
other applications in communication engineering. Today many of these early applications of entrainment and
synchronization of forced oscillators are discussed in the context of so-called phase-locked loops [see e.g. Stensby
(87) for further details and references]. Although it seems that PLL circuits and forced electronic oscillators
differ in their circuit structure, a mathematical analysis shows similar phenomena in both circuits.
In this section some aspects of entrainment will be illustrated using the forced van der Pol equation (with
normalized 2 0 = 1)

where  > 0. Following Jordan and Smith (12), where van der Pols idea is used, we look for responses approximately of the form

we obtain after some calculations a system of differ b,

where a, b are slowly varying functions. Neglecting a,
ential equations for the amplitude functions a and b:

where r2 = a2 + b2 . The periodic solutions with the frequency of the input function  cos t [r.h.s. of
Eq. (179)] correspond to the equilibrium points (a = 0, b = 0) of these equations. Using the abbreviations
= (2 1)/ (detuning) and = /, we obtain from the equilibrium equations the following condition for

OSCILLATOR DESIGN

41

Fig. 15. Response Diagram of the van der Pol equation.

response solutions

Analysis of this polynomial equation shows that there are one or three real roots (since r > 2), depending
on the parameter values and . A graphical representation of r2 in dependence on || called the response
diagram can be found for example, in Jordan and Smith (12). Based on these equilibrium points, a stability
analysis has to be performed. As a conclusion it can be found that for certain values of the parameters and ,
around the frequency 2 0 = 1 ( = 0) of the free oscillator (i.e. zero input function) there is a finite region (lock-in
band) of detunings where a stable harmonic solution (with frequency ) exists. This region of frequencies
corresponds to the region of entrainment or synchronization. Outside this region of frequencies there are no
stable harmonic solutions with the input frequency , and in the ab plane limit cycles appear. In Fig. 15
a variant of the response diagram is shown using the coordinates r and . A first curve subdivides the r
plane into stable and unstable areas, whereas the upper semicircle corresponds to the stable solutions of the
polynomial equation (183). The dashed lines bound the entrainment or synchronization region. These results
were first published by Andronov and Vitt (84).
Note, that the forced vdp equation is nonlinear, and in contrast to linear differential equations with
constant coefficients, where general solutions are consist of a superposition of free and forced oscillations, this
distinction makes no sense, although it seems obvious if the frequencies 0 and are widely separated.
By means of the above mathematical concept some basic aspects of entrainment synchronization phenomena can be discussed, but there are other effects (e.g. higher harmonics, subharmonics) where more involved
techniques have to be applied. The reader is referred to the monograph of Jordan and Smith (12) for further
details. For the analysis of PLL circuits with feedback structure the monograph of Stensby (87) is very helpful.
Finally we should mention that there is a close relationship between synchronization and chaotic behavior.
This subject is treated in an interesting paper of Tsang et al. (88) As a conclusion of their discussion it can be
emphasized that each circuit with synchronization properties is a candidate for a chaotic system.

42

OSCILLATOR DESIGN

Miscellaneous Problems of Oscillator Design

Besides the design problems discussed above, there are further problems that are essential in the design of
oscillators. Some of these are mentioned here but the reader is referred to the literature; the monographs
of Parzen (6), Frerking (89), and Kurz and Mathis (33) discuss many interesting design aspects. Several
monographs are available that consider the design of microwave oscillators [e.g. Vendelin (90)]. We will discuss
only some more general aspects of oscillator design. Most spurious oscillations are caused by the parastic
inductances and capacitances in the active devices (e.g. transistors) or the physical layout of the components
of the oscillator circuit. A main approach to avoid these oscillations is to introduce additional damping (e.g.
additional resistors). Parasitics that are related to the layout and to poor design can be reduced only by an
experienced designer, since general rules to avoid it are not available.
In crystal oscillators there is a tendency to spurious signals due to the crystal itself. For studying these
effects a more complete model of the crystal with additional resonances (so-called modes) has to be taken into
consideration [see Parzen (6)].
Another effect is self-produced amplitude modulation of the high-frequency oscillation; this effect is often
called squegging. The physical reason for squegging is related to an interaction between the time constant of
the bias and coupling circuits and the time constants of the high-frequency tuned circuits of the oscillation part.
Squegging occurs more frequently in self-limiting oscillators with low Qs than in crystal oscillators, where a
high Q is usual. Furthermore, a suitable thermal design is necessary, especially if a crystal resonator is chosen.
Some hints about this subject can be found in the literature [see e.g. Kurz, and Mathis (33)].

BIBLIOGRAPHY

1. G. Vallauri Uber
die Wirkungsweise der in der drahtlosen Telegraphie benutzten Vakuumrohren mit drei Elektroden
(Audion), Jahrb. Drahtlosen Telegr., 12 349, 1917.
2. A. A. Andronov A. A. Vitts S. E. Khaikin Theory of Oscillators (reprint), New York: Dover, 1996.
3. N. M. Krylov N. N. Bogoliubov Einfuhrung

in die Nichtlineare Mechanik, Verlag Akad. Wiss. Ukr. SSR, 1937.

4. J. A. Sanders F. Verhulst Averaging Methods in Nonlinear Dynamical Systems New York: Springer, 1985.
5. W. Mathis Theorie Nichtlinearer Netzwerke, Berlin: Springer, 1987.
6. B. Parzen Design of Crystal and Other Harmonic Oscillators, New York: Wiley, 1983.
7. J. K. Hale Oscillations in Nonlinear Systems, New York: McGraw-Hill, 1963.
8. J. Guckenheimer Dynamics of the van der Pol equation, IEEE Trans. Circuits Syst. CAS-27: 983989, 1980.
9. J. Millman A. Grabel Microelectronics, New York: McGraw-Hill, 1987.

10. K. Heegner Uber

Schwingungserzeugung mittels Elektronenrohren, welche Selbstinduktion nicht enthalten, Jahrb.
Drahtlosen Telegr., 29: 1927, 151.
11. R. S. Sidorowicz An abundance of sinusoidal oscillators. Proc. IEE, 119: 283293, 1972.
12. D. W. Jordan P. Smith Nonlinear Ordinary Differential Equations, 3 ed. Oxford: Oxford University Press, 1999.
13. V. I. Arnold Geometrical Methods in the Theory of Ordinary Differential Equations, New York: Springer, 1983.
14. G. Nicolis I. Prigogine. Self-Organization in Non-equilibrium Systems, Wiley, Chichester: 1997.
15. D. K. Arrowsmith C. M. Place An Introduction to Dynamical System, Cambridge, UK: Cambridge University Press,
1990.
16. B. D. Hassard N. D. Kazarinoff Y.-H. Wan Theory and Applications of Hopf Bifurcation, Cambridge, Cambridge University Press, 1981.
17. A. I. Mees Dynamics of Feedback Systems, Chichester: Wiley, 1981.
18. L. A. Hazeltine Oscillating audio circuits, Proc. Inst. Radio Engrs. 6: 63, 1918.
19. R. Spence Linear Active Networks, New York: Wiley, 1970.
20. E. J. Cassignol Semiconductors, Vol. III. Non-linear Electronics, Philips Techn. Library, Eindhoven, The Netherlands:
N.V. Gloeilampenfabrieken, 1968.
21. C. A. Desoer E. S. Kuh Basic Circuit Theory, New York: McGraw-Hill, 1969.
22. R. Mauro Engineering Electronicsa Practical Approach, Englewood Cliffs, NJ: Prentice-Hall, 1989.

OSCILLATOR DESIGN

43

23. D. Meyer-Ebrecht Schnelle Ampitudenregelung harmonischer Oszillatoren, Dissertation, TU Braunschweig, 1974.

24. A. H. Nayfeh Introduction to Perturbation Techniques, New York: Wiley, 1981.
25. U. Kirchgraber E. Stiefel Methoden der Analytischen Storungsrechnung und Ihre Anwendung, Stuttgart: Teubner
Verlag, 1978.
26. C. Keidies W. Mathis Application of symbolic methods to oscillator design, Proc. 2nd SMACD92 Florenz, (Italy), 1992,
pp. 6772.

27. R. Knochel K. Schunemann

Noise in multiple-device oscillators, Arch. Elekktron ubertragungstech.
36 (10): 3139,
1982.
28. A. Buonomo C. Di Bello Asymptotic formulas in nearly sinusoidal nonlinear oscillators. IEEE Trans. Circuits Syst. I,
Fundam. Theory Appl., 43: 953963, 1996.
29. V. Belevitch Classical Network Theory, San Francisco CA: Holden-Day, 1968.
30. T. Mangold P. Russer Fullwave modeling and automatic equivalent-circuit generation of millimeter-wave planar and
multilayer structures, IEEE Trans. Microw. Theory Tech., MTT-47: 851858, 1999.
31. M. N. Horenstein Microelectronic Circuits and Devices, Englewood Cliffs, N: Prentice-Hall, 1996.
32. P. R. Gray R. G. Meyer Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1993.

33. G. Kurz W. Mathis Oszillatoren, Heidelberg: Huthig

Buch Verlag, 1994.
34. J. Davidse Analog Circuit Design, New York: Prentice-Hall 1991.
35. T. J. Aprille T. N. Trick A computer algorithm to determine the steady state response of nonlinear oscillators, IEEE
Trans. Circuit Theory, 19: 131139, 1972.
36. L. O. Chua P. Lin Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques, Englewood Cliffs, NJ: Prentice-Hall, 1975.
37. M. Schwab, et al. Steady state of a SAW stabilized bipolar oscillator obtained by solution of a boundary value problem,
Proc. 20th European Microwave Conf., Budapest, 1990, pp. 12401245.
38. S. A. Maas Nonlinear Microwave Circuits, Norwood MA: Artech House, 1988.
39. V. Rizzoli A. Neri State of the art and present trends in nonlinear microwave CAD techniques, IEEE Trans. Microw.
Theory Tech., MTT-36: 343364, 1988.
40. B. Roth H. Sledzik A. Beyer An improved method for the design and simulation of microwave oscillators, Proc. West
Germany IEEE MTT/AP Joint Chapter Workshop Progress in Microwave CAD and in CAD Applications, Ratingen,
1989, pp. 208224.
41. Y. Hu J. J. Obregon J.-C. Mollier Nonlinear oscillation via Volterra series, IEEE Trans. Circuits Syst., CAS-29:1 50168,
1982.
42. C.-R. Chang M. B. Steer Frequency-domain nonlinear microwave simulation using the arithmetic operator method,
IEEE Trans. Microw. Theory Tech., MTT-38: 11391143, 1990.
43. M. Schwab Determination of the steady state of an oscillator by a combined timefrequency domain method, IEEE
Trans. Microw. Theory Tech., MTT-39: 13911402, 1991.
44. S. K. Kundert A. Sangiovanni-Vincentelli Steady State Methods for Simulating Analog and Microwave Circuits, Boston:
Kluwer Academic, 1990.
45. M. Fillebock M. Schwab P. Russer Automatic generation of starting values for the simulation of microwave oscillators
by frequency domain techniques, IEEE Trans. Microw. Theory Tech., 41: 809813, 1993.
46. T. Goeller M. Schwab P. Russer Efficient simulation of millimeter-wave IMPATT oscillators by FATE, a combined timeand frequency-domain method, IEEE Microw. Guided wave Lett., 1: 343345, 1991.
47. A. Dupuis J. Hausner P. Russer Hybrid integrated Ku-band VCO, Proc. 19th European Microwave Conf., London 1989,
pp. 10091014.
48. R. Gratzl J. Hausner P. Russer Nonlinear design approach of a broadband hybrid integrated Ku-band common source
GaAs FET VCO, Proc. International Microwave Symp., Dallas, 1990, pp. 739742.
49. R. Bulirsch Die Mehrzielmethode zur Numerischen Losung von nichtlinearen Randwert-problemen und Aufgaben der
Mathematisches
Optimalen Steuerung, Heidelberg: Carl-Cranz-Gesellschaft, 1971; Munich: Technische Universitat,
Institut, 1985.
50. R. Bulirsch J. Stoer Introduction to Numerical Analysis, New York: Springer, 1980. Differential Equations, Englewood
Cliffs N: Prentice-Hall, 1971.
51. L. Gustafson G. H. B. Hanson K. I. Lundstroem On use of the describing functions in the study of nonlinear active
microwave circuits. IEEE Trans. Micro Theory Tech., MTT-20: 402409, 1972.

44

OSCILLATOR DESIGN

52. A. Spalti
Der Einflu des thermischen Widerstandsrauschens und des Schroteffektes auf die Stormodulation von
Oszillatoren, Bull. Schweiz. Elektr. Vereins, 39: 419427, 1948.
53. W. A. Edson Noise in oscillators, Proc. IRE, 48: 14541466, 1960.
54. K. Kurokawa Noise in synchronized oscillators, IEEE Trans. Microw. Theory Tech., MTT-16: 234240, 1968.
55. K. Kurokawa Injection locking of microwave solid-state oscillators, Proc. IEEE, 61: 13861408, 1973.

56. K. F. Schunemann
K. Behm Nonlinear noise theory for synchronized oscillators, IEEE Trans. Microw. Theory Tech.,
MTT-27: 452458, 1979.
57. L. O. Chua Y.-S. Tang Nonlinear oscillation via Volterra series, IEEE Trans. Circuits Syst., CAS-29: 150168, 1982.

Phasen- und Amplitudenschwankungen in Oszillatoren, Arch Elektron. Ubertragungstech.

58. K. Marz
24 (11): 477490,
1970.

59. F. X. Kartner
Determination of the correlation spectrum of oscillators with low noise, IEEE Trans. Microw. Theory
Tech., MTT-37: 90101, 1989.

60. F. X. Kartner
Analysis of white and f noise in oscillators, Int. J. Circuit Theory Appl. 18: 485519, 1990.

61. V. Gungerich
et al. Phase noise reduction of microwave oscillators by optimization of the dynamic behaviour, MTT-S
International Microwave Symp. 1994, San Diego, 1994, pp. 953956.
62. G. R. Olbrich et al. Calculation of HEMT oscillator phase noise using large signal analysis in time domain, IEEE-MTT
Symp. Digest, San Diego, Vol. 2, pp. 965968. 1994.

63. V. Gungerich
et al. Reduced phase noise of a varactor tunable oscillator: Numerical calculations and experimental
results. IEEE MTT-S International Microwave Symp. 1993 Atlanta, 1993, pp. 561564.

64. W. Anzill F. X. Kartner

P. Russer Simulation of the single sideband phase noise of oscillators, Second International Workshop of the German IEEE MTT/AP Joint Chapter on Integrated Nonlinear Microwave and Millimeterwave Circuits,
Duisburg, Germany 1992, pp. 97110.
65. W. Anzill P. Russer A general method based on harmonic balance techniques to simulate noise in free running oscillators,
IEEE MTT-S International microwave Symp. 1993, Atlanta, GA), 1993, pp. 655658.
66. W. Anzill P. Russer A general method to simulate noise in oscillators based on frequency domain techniques, IEEE
Trans. Microw. Theory Tech., 41, 22562263, 1993.
67. H. Hillbrand P. Russer An efficient method for computer aided noise analysis of linear amplifier networks, IEEE Trans.
Circuits and Syst. CAS-23: 235238, 1976.
68. P. Russer H. Hillbrand Rauschanalyse von linearen Netzwerken, Wiss. Beri. AEG-Telefunken, 49: 127138, 1976.

69. W. Anzill Berechnung und Optimierung des Phasenrauschens von Oszillatoren, Dis sertation, Technische Universitat

Munchen,
1995.
70. W. Anzill et al. Phase noise minimization of microwave oscillators by optimal control, IEEE MTT-S International
Microwave Symp., 1995, (Orlando, FL, pp. 15651568.
71. A. Rusznyak Start-up time of CMOS oscillators, IEEE Trans. Circuits Syst. CAS-34: 259268, 1987.

72. C. Schmidt-Kreusel Rechnergestutzte

Analyse von Quarzoszillatoren, Dissertation, University of Wuppertal, 1997.
73. W. Mathis An efficient method for the transient analysis of weakly damped crystal oscillators, Proc. MTNS98, Padova,
Italy, 1998.
74. H. G. Brachtendorf Laur. R. Multi-rate PDE methods for high Q oscillators Proc. 4th Circuits, Systems, Communications
& Computers (CSCC) 2000, Athens, 2000.
75. W. B. Davenport W. L. Root An Introduction to the Theory of Random Signals and Noise, New York: McGraw-Hill, 1958.
76. J. H. Wilkinson The Algebraic Eigenvalue Problem, Oxford: Clarendon, 1988.
77. G. H. Golub C. T. Van Loan Matrix Computations, Baltimore: Johns Hopkins University Press, 1989.

78. F. X. Kartner
Noise in oscillating systems, Proc. IEEE MTT/AP Workshop on Integrated Nonlinear Microwave and
Millimeter Wave Circuits (INMIC92), Duisburg, Germany, 1992, pp. 6175.

79. W. Anzill F. X. Kartner

P. Russer Simulation of the phase noise of oscillators in the frequency domain, Arch. Elek.
Ubertragung., AE 48(1): 4550, 1994.

80. H. G. Moller Uber

storungsfreien Gleichstromempfang mit dem Schwingaudion, Jahrb. Drahtl. Telegr., 17: 256, 1921.
81. B. L. Van der Pol Forced oscillations in a circuit with nonlinear resistance (reception with reactive triode), Phil. Mag.,
3: 6580, 1927. (First published in the Dutch journal Tijdschr. Nederlandsch Radiogenootschap in 1924.
82. E. V. Appleton The automatic synchronization of triode oscillators, Proc. Cambridge Phil. Soc., 21: 231, 1922.
83. B. L. Van der Pol The nonlinear theory of electrical oscillations, Proc. Inst. Radio Eng. (IRE), 22: 10511086, 1934.
84. A. A. Andronov A. A. Vitt Theorie des Mitnehmens von van der Pol. Arch. Elektrotechn. 24: 99110, 1930.

OSCILLATOR DESIGN

45

85. D. G. Tucker Forced oscillations in oscillator circuits, and the synchronization of oscillators. J. IEE, 92: 226234, 1945.
86. F. Kirschstein Die Mitnahme selbsterregter Schwingungen und ihre technische Verwertung, Elektr. Nachr. 20: 2938,
1943.
87. J. L. Stensby Phase-Locked Loops-Theory and Applications, Boca Raton, FL: CRC Press, 1997.
88. Y. S. Tsang A. I. Mees L. O. Chua Synchronization and chaos, IEEE Trans. Circuits Syst., CAS-30: 620626, 1983.
89. M. E. Frerking Crystal Oscillator Design and Temperature Compensation, Van Nostrand Reinhold, New York: 1978.
90. G. D. Vendelin Microwave Circuit Design Using Linear and Nonlinear Techniques, New York: Wiley, 1990.

WOLFGANG MATHIS
PETER RUSSER
Otto von Guericke University of Magdeburg

158

PHASE-LOCKED LOOPS

PHASE-LOCKED LOOPS
Although the first description of the phase-locked loop (PLL)
was published by Appleton (1) in 1923, the PLL did not attract widespread attention till much later. Today PLLs of various types are used extensively in electrical engineering, from
telecommunication systems to measurement equipment.
Depending on the loop components, especially on the operation of the phase detector, analog, digital, sampling, and hybrid PLLs are distinguished. The behavior of these circuits is
described by differential, difference, and mixed integro-difference equations.
Even though applications of PLLs require a variety of circuit configurations, and the mathematical models mentioned
above require different kinds of mathematical treatment,
their behavior can be approximated and studied by means of
a simple feedback structure. Unfortunately, the behavior of
this structure is complicated to analyze, because it is nonlinear, may contain edge-triggered digital circuits, and is driven
by random noise. In many cases, analytical results are not
available in closed form; they are often buried in complicated
mathematics that cannot be assimilated easily by the circuit
designer. On the other hand, the design of PLLs for many
applications can be performed successfully, based on a simple
linearized model and by means of a few rules of thumb. In
this article one shall differentiate clearly between the essential elements and secondary effects of loop behavior, the key
assumptions and approximations involved in the analysis will
be highlighted, and the conditions under which the approximations are valid will be collected. The main goals are to provide a survey of PLL theory and applications and to summarize the most important design rules and equations.
This article is organized as follows. The next section is devoted to the theory of the analog phase-locked loop (APLL).
First the baseband model for the APLL is developed, then the
linear theory of the APLL (tracking, modulation, and noise)
is discussed. Finally, the most important nonlinear effects
(acquisition, cycle slips, hang-up) are considered. The subsequent section discusses the most common applications of
PLLs.
The key element of the loop that determines the practical
performance of a PLL is the phase detector. To obtain the
best circuit performance, different phase detectors have been
developed for various applications. The operation of the most
widely used phase detectors is then discussed.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

PHASE-LOCKED LOOPS

The Digital Phase-Locked Loop (DPLL) has become popular

in many applications recently. A section is devoted to DPLL
circuits.
In other applications, analog, discrete-time, and edge-triggered digital circuits have to be used, or their mixed application assures the best loop performance. These loops are called
hybrid phase-locked loops (HPLL). The most commonly used
HPLLs are the sampling phase-locked loop (SPLL) and the
charge-pump phase-locked loop. The operation of SPLLs and
charge-pump PLLs will be discussed.
ANALOG PHASE-LOCKED LOOP
In an APLL, all loop components are analog circuits, that is,
their operation can be modeled by ordinary differential equations. For the sake of simplicity, an analog multiplier shall be
used as a phase detector in this section. This circuit is referred to as a sinusoidal APLL.
The APLL was the first, and is the most widely studied
version of the PLL. Many excellent books (211), two IEEE
special issues (12,13) and a tutorial (14) have been devoted to
the theory and applications of the APLL.
In many applications, the block diagram of the APLL has
to be completed with extra loop components such as a frequency divider, mixer, and so on. That is why the results developed for the APLL cannot be used directly in many cases.
However,
the theory of the APLL is very well developed and is easy
to understand;
equations describing the loop behavior in different applications can be developed in closed form;
having understood the operation of the APLL, it is easy
to study more complex PLL configurations; and
the APLL equations give a simple but useful approximation for many circuit design problems.
This article presents a concise treatment of the sinusoidal
APLL. First, the baseband model for the APLL is developed.
Then the so-called linear APLL theory is discussed. In the
majority of applications, the APLL operates in its linear region. The linear theory can be applied only if the phase-locked
condition has been achieved and is maintained. Under phaselocked condition the average input and voltage-controlled oscillator (VCO) frequencies are exactly equal and the VCO
phase tracks the input phase. The phase-locked condition is
achieved as a result of a highly nonlinear, so-called acquisition, process. In the last part of this section, the most important aspects of nonlinear APLL theory are discussed.

159

Demodulated Demodulated
PM output
FM output
Input
signal

Phase
detector

Loop
filter

+ Acquisition
voltage or
FM input

VCO

Recovered
carrier
signal
Figure 1. APLL block diagram showing inputs and outputs for various telecommunication applications.

frequency. By proper design of the PD, VCO, and loop filter,

the same APLL configuration can be used for tracking and
carrier recovery, modulation and demodulation, and so forth.
A nonzero output voltage must be provided by the PD, in
order to control the VCO frequency if the input frequency differs from the VCO center frequency. Consequently, the PLL
tracks the phase of input signal with some phase error. However, this phase error can be kept very small in a well-designed PLL.
Acquisition and Tracking
In every application, the PLL tracks the phase of the incoming signal. However, before a PLL can track, it must first
reach the phase-locked condition.
In general, the VCO center frequency 0 differs from the
frequency i of the incoming signal. Therefore, first the VCO
frequency has to be tuned to the incoming frequency by the
loop. This process is called frequency pull-in. Then the VCO
phase has to be adjusted according to the input phase. This
process is known as phase lock-in.
In the following, three important loop characteristics are
defined.
Pull-in Range. P i 0 is the maximum initial frequency difference between the input and VCO center frequency both in positive and negative directions, for which the
PLL eventually achieves the phase-locked condition. The pullin range is related to the dynamics of the APLL.

Basic Loop Configuration

Lock-in Range. L i 0 is the frequency range over

which the PLL achieves the phase-locked condition without
cycle slips. Cycle slips will be defined later.

A PLL is a feedback system that continuously tries to track

the phase of an input signal. It contains a phase detector (PD),
a time-invariant linear loop filter, and a voltage-controlled oscillator (VCO); the oscillator to be synchronized. As shown in
Fig. 1, the phase detector compares the phase of the input
signal against the phase of the VCO output and produces an
error signal. This error signal is then filtered, in order to remove noise and other unwanted components of the input spectrum, and the filter output controls the instantaneous VCO

Hold-in Range. Suppose the phase-locked condition has

been achieved in the PLL. Now vary the input frequency i
slowly and the VCO frequency will follow it. The hold-in
range H i 0 is determined by the lower and upper
values of i, for which the phase-locked condition is lost. The
hold-in range represents the maximum static tracking range
and is determined by the saturation characteristics of the
nonlinear loop elements in the PLL.

160

PHASE-LOCKED LOOPS

Loop Equation and Nonlinear Baseband Model

The block diagram of the APLL to be studied is shown in Fig.
2, where F(p) denotes the transfer function of the loop filter.
In the equations developed below, the time variable t is suppressed for conciseness where it does not cause misunderstanding. In order to write the differential equations in compact form, the operation of differentiation d/dt in the timedomain is denoted by multiplication by the Heaviside operator
p. Recall that if the transfer function F(s) of a linear network
is given in the complex frequency domain s then F(p)
F(s)sp. For more details on the Heaviside operator see page
73 in (6).
It shall be assumed during the PLL analysis that the loop
components are linear; the only source of nonlinearity is the
phase detector. The instantaneous VCO frequency can be varied about its center value 0 by the VCO control voltage.
Almost all signals and processes used in electrical engineering can be considered narrowband (15). Let the incoming
signal
s(t, ) =

2A sin 

(1)

be a narrowband signal, where A(t) describes the amplitude

modulation produced at the transmitter on purpose and/or
caused by the time-varying channel through which the signal
is transmitted. Let the phase of the incoming signal be expressed with respect to the VCO center frequency as
 = 0 t + i

(2)

where i(t) is the input phase modulation produced at the

transmitter and/or caused by the channel.
As shown in Fig. 2, the incoming signal s(t, ) is corrupted
by additive input noise ni(t). In almost all applications, the
additive input noise is a narrowband process centered about
0. By means of the analytic signal approach (15), narrowband processes or signals can be expressed as a product
of a slowly varying complex envelope and a sinusoidal carrier.
For example, an arbitrary narrowband signal g(t) centered
about 0 can be expressed in terms of a complex envelope
g(t) as
exp( j0t)}
g(t) = Re{g(t)

(3)

Since the carrier frequency component has been removed, the

complex envelope is a slowly varying function
= gI (t) + jgQ (t)
g(t)

(4)

ni(t)
s(t, ) +

x(t)
PD

vd(t)

F( p)

vf (t)
+ v (t)
e
+

r(t, )

VCO

vc(t)

Figure 2. APLL block diagram indicating the additive input noise

that corrupts the input signal.

where gI(t) and gQ(t) are the low-frequency in-phase and quadrature components of the narrowband signal g(t).
Let ni(t) be modeled by a narrowband Gaussian random
process of zero mean and symmetrical power spectral density.
Then the sample function of the narrowband noise can be expressed from Eqs. (3) and (4) in canonical form (6,15) as

ni = 2[nI cos(0t) nQ sin(0t)]

(5)
The in-phase and quadrature components are
1
nI = [ni cos(0t) + n i sin(0t)]
2

(6)

1
nQ = [n i cos(0t) ni sin(0t)]
2

(7)

and

where ni(t) is the Hilbert transform of ni(t) (15).

The VCO output is also a narrowband signal

= 2Vo cos 

r(t, )

(8)

(t) is the loop estimate of (t) that can be expressed,

where
with respect to the VCO center frequency as
= 0 t + o


(9)

In Eq. (8) and Eq. (9) Vo and o(t) denote the rms amplitude
and phase of the VCO output.
The PD multiplies the input signal x(t) s(t, ) ni(t) and
) and produces both difference- and sumVCO output r(t,
frequency terms. The PD always contains a low-pass filter
that eliminates the sum-frequency component. By means of
simple trigonometric identities is obtained for the PD output
vd = AVo sin e + Vo (nI cos o + nQ sin o )
= Kd [A sin e + N(t, o )]

(10)

where the phase error is defined by

e (t) = (t) (t)

= i (t) o (t)

(11)

and Kd Vo, a dimensionless quantity, is the gain of the PD.

The equivalent noise process is defined by
N(t, o ) = nI cos o + nQ sin o

(12)

The statistical properties of N(t, o) are given in the following section.

It follows from Eq. (10) and Eq. (12) that
even in the noise-free case, the PD output depends not
only on the phase error e(t) but also on the amplitude
A(t) of the incoming signal; and
the equivalent noise process N(t, o) is independent of
e(t); it appears as an additive term in the PD output.
The instantaneous VCO frequency o(t) do(t)/dt referenced to 0 is related to its input through
2 = Kv (v f + ve ) + 
2
o = Kv vc + 

(13)

PHASE-LOCKED LOOPS

where vc(t) vf (t) ve(t) denotes the VCO control voltage,

vf (t) F(p)vd(t) is the output voltage of the loop filter, ve(t)
denotes the external control voltage, Kv is the VCO gain in
rad/Vs, and 2(t) denotes the VCO jitter, that is, the phase
noise.
Taking into account the transfer function of the loop filter,
from Eq. (10) and Eq. (13),
o =

KF (p)
Kv
[A sin e + N(t, o )] +
v e + 2
p
p

(14)

where K KdKv defines the loop gain in rad/Vs . Substituting

Eq. (14) into Eq. (11), the following nonlinear stochastic
integro-differential equation is obtained
e = i

KF (p)
Kv
[A sin e + N(t, o )]
v e 2
p
p

(15)

which describes the operation of APLL. In general, the input

phase modulation i(t) consists of three terms
i = d + M + 1

(16)

where d(t) describes the Doppler effect appearing in the channel, M(t) is the digital or analog phase/frequency modulation,
and 1(t) denotes the jitter, that is, phase noise of the transmitter oscillator.
The loop equation given by Eq. (15) has two important advantages. Due to the introduction of a phase error, the highfrequency terms have been dropped and all signals involved
in the loop equations have become low-frequency signals, that
is, slowly varying functions. This means that, for example, in
a computer simulation a low sampling frequency can be used,
that is, a short simulation time is required. A further advantage of the phase error description is that it simplifies the
problem to be studied. In many cases, such as the acquisition
problem, Eq. (15) becomes an autonomous differential equation that is relatively easy to study.
Note that, in an implemented APLL, the phase error does
not exist as an explicit variable; it has been introduced only
to derive a simple mathematical model for the APLL. However, if e(t) is known, then all signals appearing in an implemented APLL can be expressed easily by the equations developed above.
The baseband model of the APLL can be developed from
Eq. (15) as shown in Fig. 3. The sinusoidal nonlinearity in Eq.
(15) is due to the particular type of PD and the sinusoidal
VCO and input waveforms. However, other kinds of PD and
signals can be also applied. Fortunately, the unified baseband
model shown in Fig. 3 remains valid for each loop configurang

i +

Ag( )

+
Kd

vd

F(p)

vf
+

+
+
+

Kv
p

vc

2
Figure 3. Unified baseband model of APLL.

ve

161

tion if the loop nonlinearity g( ) is selected according to the

actual PD characteristics and ng(t) describes the equivalent
noise process for the case to be studied. If an analog multiplier is used as the PD and the signals are sinusoidal, then
g( ) sin( ) and ng(t) N(t, o). Lindsey and Chie (11) have
collected g( ) and ng(t) for many other loop configurations.
Note that the input and output of the baseband model are
not measurable signals but are the input and output phase
modulations, respectively. If the real input and output signals
) can be exhave to be determined, then s(t, ) and r(t,
pressed using Eqs. (1) and (8).
Statistical Properties of Equivalent Noise
In order to use the baseband model in calculations, one needs
to know the statistical properties of the equivalent noise process N(t, o) that depends on both the additive input noise
ni(t) and the output phase o(t). This section summarizes the
properties of the in-phase and quadrature components of
ni(t) and gives the statistical properties of N(t, o).
Recall that the additive input noise is modeled by a narrowband Gaussian random process with zero mean. It can be
expressed either in canonical form or as a sinusoidal signal
ni =

2[nI cos(0t) nQ sin(0t)] = 2Nn (t) cos(0t + n )

(17)

where the envelope Nn(t) and phase n(t) processes are defined
by

Nn (t) =

n2I (t) + n2Q (t)

and

n (t) = tan1

nQ (t)
nI (t)


(18)

Note that the envelope Nn(t) differs from the complex envelope defined by Eq. (3). If the power spectral density of ni(t) is
symmetrical about 0, then a very simple relationship exists
between the autocorrelation functions of ni(t) and Nn(t)
Rn ( ) = 2r( ) cos(0 )

(19)

where Rn() and r() denote the autocorrelation functions of

ni(t) and Nn(t), respectively.
If ni(t) has a symmetrical power spectral density about 0
then the most important properties of the in-phase nI(t) and
quadrature nQ(t) components of ni(t) are as follows (10,15):
1. If ni(t) is a Gaussian process, then both nI(t) and nQ(t)
are also Gaussian.
2. If ni(t) has zero mean, then both nI(t) and nQ(t) have zero
mean values. Note that ni(t) is a bandpass signal, that
is, it always has zero mean.
3. The in-phase and quadrature components have the
same variance as the narrowband noise ni(t).
4. The correlation functions of nI(t) and nQ(t) can be expressed (6) as

nI (t)nI (t + ) = nQ (t)nQ (t + ) = r( )
nI (t)nQ (t + ) = nQ (t)nI (t + ) = 0

(20)

where overbar symbolizes the time-averaging operation.

The first equation shows that the autocorrelation func-

162

PHASE-LOCKED LOOPS

tions of Nn(t), nI(t) and nQ(t) are equal to each other,

while the second one means that nI(t) and nQ(t) are independent.
5. Both the in-phase and quadrature noise components
have the same power spectral density that is related to
the power spectral density SN( f) of ni(t) as

SI ( f ) = SQ ( f )

SN ( f f 0 ) + SN ( f + f 0 ), B f B
=
0,
elsewhere

(21)

where SN( f) occupies the frequency band f 0 B f

f 0 B and f 0 B.
To complete the APLL baseband model, the statistical
properties of N(t, o) have to be determined. The problem is
that the equivalent noise depends not only on ni(t), but also
on o(t). Due to the closed loop, the noise modulates the VCO
and o(t) also becomes a random process. Because the PD is
nonlinear, the fluctuations in o(t) intermodulate with the incoming signal and additive input noise ni(t).
The nonlinear operation of the PD makes exact analysis
impossible, so some kind of approximation must be used. Viterbi (3) introduced two assumptions, in order to get a simple
but useful result:
1. The additive bandpass noise ni(t) has a symmetrical
power spectral density; and
2. The bandwidth of ni(t) is much wider than the bandwidth of o(t).
The bandwidth of o(t) is determined by the noise bandwidth
of the loop, which will be defined later. In this case, the correlation time (6) of the additive input noise is much less than
that of the output phase. Consequently, o(t) can be thought
of as a slowly varying function compared to ni(t) and the two
processes are approximately independent (3).
Under these assumptions the equivalent noise process can
be approximated by white noise. The process N(t, o) shall be
treated as though it were white so that o(t) embedded in
N(t, o) does not enter into the APLL analysis, either linear
or nonlinear. Thus, if the additive input noise ni(t) is white
with spectral density N0 /2, then the power spectral density of
the equivalent noise ng(t) indicated in Fig. 3 is uniform with
value N0 /2.
Fortunately, the assumptions listed above are valid for almost all practical applications of the APLL and the design of
different circuit configurations operating in either the linear
or nonlinear region can be performed based on a simple baseband model.
Linear Operation of the APLL
Linear APLL theory is used extensively in designing APLLs
for different applications from telecommunication to measurement engineering. Furthermore, many system parameters
used in circuit development and characterization are introduced and defined in the linear theory.
The linear operation of APLL assumes that
the phase-locked condition has been achieved and is
maintained, and

the phase error remains in the neighborhood of its quiescent value, that is, one may write g(e) g(ss)
dg(e)/dess e, where ss is the quiescent value of e(t)
and e(t) denotes its perturbation.
In this section the linear baseband model for the APLL
will be developed, and then the transfer functions for different APLL applications will be determined. After evaluating
the stability properties, the tracking (transient and modulation) behavior and the noise performance of the APLL are
studied, based on the linear baseband model.
Linear Baseband Model. Recall that the behavior of the
APLL can be described by the following nonlinear stochastic
differential equation:
e = i

KF (p)
Kv
[Ag(e ) + ng ]
v e 2
p
p

(22)

where, for simplicity of notation, the dependence on t in all

variables has been omitted, the function g( ) describes the
nonlinearities of the loop, and ng(t) denotes the equivalent
noise process that depends on the additive input noise and
the characteristic of phase detector. In this section, it shall be
assumed that the APLL operates under phase-locked condition.
First the quiescent value of the phase error must be determined. Let ng(t) 2(t) 0 and let the input phase modulation be
i = (i 0 )t + i0 = i t + i0
where i is the initial frequency detuning and i0 denotes
the phase of the incoming signal. Taking into account that
under steady-state conditions all signals are constant and
that the Heaviside operator p means d/dt in the time-domain,
from Eq. (22) the quiescent value ss of e(t) can be obtained
as
ss = g1

i Kv ve0
KF (0)A


(23)

where ve0 denotes the external dc control voltage of F(0) is the

dc gain of the loop filter.
If the phase error remains in the neighborhood of ss then
g dg(e)/dess e, where e e ss. Furthermore, let
Kg dg(e)/dess be lumped with Kd. Then the linear loop
equation for the phase error takes the form
e = i



KF (p)
ng
Kv
Ae +
v e 2

p
Kg
p

(24)

where, in order to have a compact notation, e(t) is not distinguished from its perturbation e(t), and the new value of loop
gain is K KgKdKv. Note that Kg is measured in rad1 and the
new value of loop gain K is given in (vs)1. The output phase
can be expressed as
o =



KF (p)
ng
Kv
Ae +
v e + 2
+
p
Kg
p

(25)

PHASE-LOCKED LOOPS

APLLs are classified according to the type and order of the

loop. Let

ng

i +

+
Kd

vd

F(s)

vf

G(s) =
+

ve

+
+

Kv

vc

+
2

Figure 4. Linear baseband model of APLL.

The linear baseband model can be constructed from Eqs.

(24) and (25). The linear model shown in Fig. 4 will be needed
in the following section to develop the loop transfer functions
and to determine the most important properties of the APLL.
Although every real APLL is nonlinear, in many applications
after the acquisition process the APLL must operate in its
linear region in order to avoid distortion.
Transfer Functions. In order to describe the behavior of
APLL by means of transfer functions, Eq. (24) has to be rearranged as


Kv
n (s)
2 (s) H(s) g
ve (s) 
e (s) = [1 H(s)] i (s)
(26)
s
AKg
and substituting Eq. (11) into Eq. (25) the output phase has
to be expressed as




n g (s)
Kv
2 (s)
ve (s) 
o (s) = H(s) i (s) +
[1 H(s)]
AKg
s
(27)
where is introduced the Laplace transform variable s. Hereafter a tilde denotes the Laplace transform of the signal over
which it appears.
Note that only two transfer functions are required to characterize the APLL completely, namely, the closed-loop transfer function
H(s) =

AKF (s)
s + AKF (s)

(28)

and the error function

1 H(s) =

163

s
s + AKF (s)

(29)

have to be determined. The closed-loop transfer and error

functions have low-pass and high-pass characteristics, respectively. The parameters of H(s) and [1 H(s)] are determined
by the loop-filter F(s), the loop gain K, and the rms amplitude
A of the incoming signal. If A(t) varies due to either amplitude
modulation or a time-varying channel, then all parameters of
H(s) and [1 H(s)], for example, the cut-off frequency, also
vary with time. In the majority of applications, this time dependence is not allowed, that is, an AGC circuit preceding
the APLL must be used in order to fix the amplitude of the
input signal.

AKF (s)
s

(30)

denote the open-loop transfer function. The loop type is given

by the number of poles at the origin, that is, the number of
perfect integrators in G(s), while the loop order is equal to the
number of poles in G(s).
In the following are considered, as examples, a few important loop filter configurations, and the closed-loop APLL characteristics are determined. The closed-loop parameters for
other loop filter configuration are given in Table 1.
Case I: F(s) 1; First-Order, Type-One Loop. Substituting
F(s) 1 into Eqs. (28) and (29), the closed-loop transfer function

H(s) =

1
1+

s
AK

(31)

and error function

s
AK
1 H(s) =
s
1+
AK

(32)

can be expressed. The transfer function H(s) has a well-defined 3-dB bandwidth, which we call the closed-loop bandwidth and label 3dB. Note that the closed-loop bandwidth
is equal to AK; and
varies with the amplitude A of the input signal.
The disadvantage of a first-order APLL is that only one
free design parameter is available. The loop gain K determines all parameters of the APLL. For example, the quiescent
phase error ss given by Eq. (23) and the closed-loop bandwidth appearing in Eq. (31) cannot be selected independently
of each other; a small ss results in a large closed-loop bandwidth. It is not possible to implement simultaneously a small
tracking error and a small closed-loop bandwidth. This problem can be overcome by introducing more free parameters,
that is, a first-order loop filter.
Case II: Second-Order, Type-Two Loop. The circuit diagram
of the most frequently used active loop filter is shown in Fig.
5. Due to the finite DC gain, the transfer function of the loop
filter
F (s) =

1 + s2
s1

(33)

cannot be implemented, but is approximated closely by an operational amplifier. The time constants in Eq. (33) are: 1
R1C and 2 (R1 R2)C. A loop implemented with an active
loop filter is often referred to as an ideal second-order APLL.
After substituting Eq. (33) into Eq. (28) and (29) the
closed-loop transfer function
H(s) =

s2

2 n s + 2n
+ 2 n s + 2n

(34)

164

PHASE-LOCKED LOOPS

Table 1. Parameters of the Linearized APLL

Loop
Order

Type

Loop Filter F(s)

Key Parameters

H(s)

First

One

BL AK/4

4 BL
s 4 BL

Second

One

Passive lag filter

2n AK/ 1

1
1 s1

2 n 1/ 1

Passive lead-lag filter

2n AK/ 1

BL AK/4

1 s2
1 s1

2 n

AK
1

and

2 n
2

(35)

(36)

2 n s 2n
s2 2 n s 2n

APLL parameters that have to be selected in design of every

APLL. The main advantage of the ideal second-order APLL is
that these parameters can be selected independently of each
other:
The high dc gain of the operational amplifier ensures
that ss 0; furthermore ss does not depend on A.
Equation (37) shows that n can be calculated from the
required closed-loop bandwidth and damping factor.
Then AK/ 1 is given by Eq. (36).
The transient behavior of the loop is controlled by the
damping factor. From Eq. (36), 2 can be calculated.

The closed-loop bandwidth can be expressed as

1/2



3dB = n 2 2 + 1 + (2 2 + 1)2 + 1

1
4

where the natural frequency n and the damping factor of

loop are given by
n =

AK2
1
1
2BL n
4

(37)

The magnitudes of the APLL frequency response and error

response are plotted in Figs. 6 and 7, respectively, for several
values of damping factor. Note that H(s) and [1 H(s)] really
have low-pass and high-pass characteristics, respectively as
claimed.
The quiescent value of the phase error, the loops transient
behavior, and the closed-loop bandwidth are the three basic

5
(a)
Magnitude in dB

s2
+ 2 n s + 2n

2 n

is obtained and then the error function,

s2

n
2AK

2n
s 2n
AK
s2 2 n s 2n

2 n

2n AK/ 1

Active filter
1 s2
s1

1 H(s) =

1 AK2
1

2BL n 1
Two

2n
s 2 n s 2n
2

(d)
(c)

5
10

(b)

+
15

R1

R2

Figure 5. Circuit diagram of the most widely used active loop filter.

101

100
Normalized frequency, / n

101

Figure 6. Frequency response of APLL implemented with an active

loop filter for several values of damping factor: (a) 0.3; (b)
0.707; (c) 1; and (d) 2.

PHASE-LOCKED LOOPS

165

(a)
(b)
Magnitude in dB

0
(c)

10
(d)

20

30

10

100

101

Figure 9. Root locus for second-order APLL implemented with active

loop filter.

Normalized frequency, / n
Figure 7. Error response of an ideal second-order APLL for various
values of damping factor: (a) 0.3; (b) 0.707; (c) 1; and (d)
2.

A further advantage of second-order loops is that they are

unconditionally stable for all values of loop gain. However,
note that all closed-loop parameters depend on the rms amplitude of the incoming signal.
Case III: Second-Order, Type-One Loop. The passive leadlag filter offers a very simple APLL configuration. The circuit
diagram of the loop filter is shown in Fig. 8; its transfer function is
F (s) =

1 + s2
1 + s1

(38)

where 1 (R1 R2)C and 2 R2C.

The closed-loop transfer function can be expressed in the
form



2
s 2 n n + n2
AK
H(s) =
s2 + 2 n s + n2

(39)

with

n =

AK
1

and

n
=
2



1
2 +
AK

application of a passive lead-lag filter results in a nonzero ss

given by Eq. (23).
Other loop filters are also used in practical APLL circuits.
A short summary of loop parameters and closed-loop transfer
functions is given in Table 1 for different loop filter configurations.
Stability Considerations. So far, stability of the APLL has
been assumed. A necessary and sufficient condition for stability is that all of the poles of the closed-loop transfer function
lie in the left half-plane. As shown by Eqs. (31), (34) and (39),
the positions of the poles vary as the loop gain is changed.
The locus that the poles trace out in their migrations in the
complex s-plane as the loop gain varies from zero to infinity
is known as the root locus plot.
The root loci for the active and passive loop filters are
shown in Figs. 9 and 10, respectively. Root loci for other loop
filters are given in (3) and (10).
The root loci for the first- and second-order APLLs lie entirely in the left half-plane, that is, these circuits are unconditionally stable. However, the third-order APLL may become
unstable for low values of AK (10). Because A is the rms amplitude of the input signal, a third-order APLL may become
unstable for weak signals, even if it is stable under normal
operating conditions. The unconditional stability of the second-order APLL makes it popular in situations where the amplitude of the input signal is not constant.

(40)

Note that if AK is large enough, then these equations reduce

to Eqs. (34) and (36).
The design procedures for APLLs using passive lead-lag
or active filters are similar. The only difference is that the

j
Radius =

1
1

2 1

R1

2
R2
C
Figure 8. Circuit diagram of the passive leadlag loop filter.

Figure 10. Root locus for second-order APLL including a passive

lead-lag filter.

166

PHASE-LOCKED LOOPS

There is another technique that is very often used for the

design of APLLs. Bode plots offer a simple but useful graphic
tool for the analysis (10), since

vertical axis. In these cases both n and vary, but at least

the second-order APLL remain stable for any value of incoming amplitude.

all the important closed-loop parameters appear as distinctive points on the Bode plot; and
the loop stability can be also determined.

Linear Tracking. In many applications the phase of the incoming signal must be tracked with a small phase error. To
evaluate the tracking properties of APLL, one determines the
phase error response to different input phases i(t). Three
cases will be considered:

The Bode plot consists of a pair of graphs, where both the

magnitude and phase of the open-loop transfer function are
plotted. The open-loop transfer function of an APLL is given
by Eq. (30) that is repeated here for convenience
G(s) = AK

F (s)
s

(41)

The frequency B, where the open-loop gain becomes 0 dB is

a good approximation of the closed-loop bandwidth. The Bode
criterion for stability is that the absolute value of the phase
of G( j) at B must be less than 180.
Figure 11 shows the Bode plot for the most commonly used
second-order APLLs implemented with (a) active and (b) passive lead-lag loop filters. The pole and zero frequencies and
the most important closed-loop parameters are indicated on
the Bode plot. Note that the absolute value of the phase shift
never exceeds 180, that is, these loops are unconditionally
stable. The Bode plot shows that the damping factor is controlled by the zero frequency of the loop filter. Placing the
zero at the unity-gain point B yields a damping factor
0.5. The natural frequency n is assigned by the frequency at
which the extension of the 40 dB/decade line segment
crosses the unity-gain ordinate.
The open-loop transfer function is proportional to the amplitude of incoming signal, as shown by Eq. (41). If A varies,
then the Bode plot has to be shifted up or down along the

1. Transient response to phase step, frequency step and

frequency ramp,
2. Sinusoidal modulation; and
3. Modulation with an arbitrary stationary process.
In this section the linearized loop equation will be used to
determine the tracking properties of the loop. Recall that Eq.
(26) is valid for perturbations of the variables about their quiescent values.
From Eq. (26) is obtained the phase error response to the
input phase
e (s) = [1 H(s)]i (s) =

Magnitude in dB

(b)

lim e (t) = lim s[1 H(s)]i (s)

1
=
1



t2
u(t)
i (t) = i +  i t +  i
2

1
=
2

B = 2 n
log

Phase in degrees

= n
0

(43)

20 dB/decade

log
(b)

e =

135
(a)

Figure 11. Bode plot of second-order APLLs implemented with (a)

active and (b) passive leadlag loop filters.

(44)

where u(t) is the unit step function and the first, second, and
third terms denotes a phase step, frequency step and frequency ramp, respectively. The steady-state values of the
phase error for different loop filter configurations are given in
Table 2.
A heuristic derivation of the steady-state phase response
to a frequency step helps one better to understand the operation of the loop. In steady-state, the input and VCO frequencies are equal. The control voltage needed to retune the VCO
by i is i /Kv. The dc gain of the loop filter is F(0), that is,
the steady-state value of the PD output is i /KvF(0). The
phase error required to produce this output voltage is

90

180

s0

The most commonly encountered excitations can be expressed

as

40 dB/decade

(42)

This linear approximation is valid if e(t) remains small

enough both during the transient and under steady-state conditions. For the sinusoidal PD and if ss 0, the phase error
has to be less than 1 radian. In this case one may use the
approximation sin e e.
By means of the final value theorem of the Laplace transform, the steady-state value of the phase error can be expressed directly from the error function
t

(a)

s
(s)
s + AKF (s) i

i
i
=
AKd K v F (0)
AKF (0)

(45)

Table 2 shows the most important advantage of the ideal

second-order APLL. In real applications, the frequency of the
incoming signal always differs from the VCO center fre-

PHASE-LOCKED LOOPS

167

Table 2. Steady-State Values of the Phase Error Response to a Few Commonly Encountered Excitations
Loop
Order

Type

Steady-State Phase Error Response (in rad) to

Loop Filter
F(s)

Phase Step

Frequency Step

Frequency Ramp

First

One

AK

Second

One

1 s2
s1

2n

Two

1 s2
1 s1

AK

quency. Even if an ideal integrator cannot be implemented,

the high dc gain of the operational amplifier used in the active
loop filter keeps the steady-state phase error extremely small,
independent of the frequency error. Due to the constant and
zero phase error,
the PD gain Kd lumped with Kg dg(e)/dess becomes
constant, that is, the closed-loop parameters do not depend on the frequency error; and
the widest linear region of the analog multiplier can be
exploited, where sin e e.
The error responses of different APLLs to commonly used
inputs can be found in the literature. [For a good survey of
sources see (11), Table III p. 19.]
Next, we determine the loop response to angle-modulated
input signals. For sinusoidal phase modulation one may write
i (t) =  sin( m t)

(46)

where is the peak phase deviation and m denotes the

modulation frequency.
The steady-state phase error response can be calculated
from Eq. (42) as
e (t) = |1 H( m )| sin( mt +
)

should not forget that if the APLL is used to process anglemodulated signals, then a smaller phase error results in less
distortion.
Inspecting Figs. 7 and 12, it can be seen that the tracking
error becomes very large at n in the second-order loop for
small damping factors. Recall that the linear approximation
can be used only if the phase error remains small enough,
even at n.
It has been assumed above that the input angle-modulation is produced by a single sinusoidal signal. In general, the
modulating signal is a random process and all that may be
known are its mean and covariance function. In this case the
aim is to determine the power spectral density and variance
of the phase error process caused by the input PM and FM.
Let the input phase modulation process i,PM(t) be a widesense stationary process with zero mean and power spectral
density Si,PM(). As shown in (3), the power spectral density of
the phase error process in steady-state can be expressed as
Se,PM () = |1 H()|2 Si,PM ()

(51)

and its variance is

e2,PM =

(47)

1
2

Se,PM () d

(52)

where the gain 1 H(m) and phase shift are given by

 sin( m ) d =
0


cos( mt)
m

(49)

where denotes the peak frequency deviation. The phase

error is
e (t) = |1 H( m )|


cos( mt +
)
m

or

i (t) =

/ n

Let the input frequency modulation be expressed as

(48)

/(AK)

|1 H( m )|e j
[1 H(s)]|s= j m

(c)

(a)
0

5
(b)
10

15

(50)

where 1 H(m) and are given by Eq. (48). The error response is shown in Fig. 12 for the first-order and ideal secondorder loops. The high-frequency asymptote is the same for
both loops, but the responses are completely different below
the closed-loop bandwidth. The second-order APLL ensures a
much smaller tracking error than the first-order loop. One

101

100
m/AK or m/ n

101

Figure 12. Phase error generated by sinusoidal FM in (a) first-order

and ideal second-order APLL for (b) 1 and (c) 0.3. The modulation frequency m and the peak frequency deviation are normalized to AK in the first-order loop and to n in the second-order loop.
To make the figures comparable, AK n.

168

PHASE-LOCKED LOOPS

The variance of e(t) represents the mean square value of the

phase error process, which must be kept small for almost all
t in order to make the linear model valid. If the input of the
phase modulator generating i(t) is a stationary random process of zero mean and power spectrum Sm() then

The power spectral densities of the phase error Se,N() and the
output phase So,N() processes become

Si,PM () = K 2PM Sm ()

from which is obtained the variances of the phase error and

the output phase

(53)

where KPM is the modulator gain. Substituting Eq. (53) into

Eq. (51), the parameters of the phase error process can be expressed.
In the case of FM, the input phase modulation is

i (t) = KF M

m(t) d

(54)

where KFM denotes the modulator gain. Even if the modulating process m(t) is stationary its integral will not necessarily
be, so that the relationship between the power spectral densities of the input frequency modulation process and the phase
error process cannot be given. However, Viterbi has shown in
(3) that the power spectrum of the phase error process can be
expressed as
Se,FM () = K 2F M

|1 H()|2
Sm ()
2

(55)

where Sm() is the power spectrum of the input of FM modulator. The variance of the phase error process is
e2, FM =

1
2

Se, FM () d

(56)

Noise Performance for High SNR. As demonstrated earlier,

narrowband additive input noise ni(t) can be modeled by an
equivalent noise process ng(t) entering the baseband model
after the PD nonlinearity g( ), as shown in Fig. 3. If an analog multiplier is used as the PD, then ng(t) N(t, o). The
statistical properties of N(t, o) have been summarized earlier.
Recall here the most important characteristics of N(t, o). Let
ni(t) have a symmetrical power spectral density N0 /2 and let
the bandwidth of o(t) be much less than that of ni(t). In this
case the equivalent noise ng(t) is a Gaussian process with uniform spectral density N0 /2. Furthermore, if the variance of
the phase error caused by noise and input angle-modulation,
if any, is sufficiently small, then the linear baseband model
shown in Fig. 4 can be used to evaluate the noise performance
of the APLL. Provided that the linear model is valid, the superposition theorem holds and the effect of noise and input
angle-modulation can be determined independently of each
other.
The equivalent noise process having a power spectral density SN() N0 /2 is wide-sense stationary with zero mean.
Let the point where ng(t) is applied to the loop be considered
as input, and let e(t) and o(t) be considered as outputs. The
magnitude of the two frequency responses is obtained as


 | H()|

Kd K v F ()


 j + AK K F ()  =
A
d v

Se,N () = So,N () = | H()|2

2
2
e,N
= o,N
=

N0 1
2A2 2

N0
2A2

| H()|2 d

(58)

(59)

Let the noise bandwidth BL of the loop be defined as the bandwidth of an ideal low-pass filter, whose output variance is
2
e,N
when it is driven with Gaussian white noise of power
spectral density N0 /2A2
BL =

1
2

| H()|2 d

(60)

N0 BL
A2

(61)

Then Eq. (59) becomes

2
2
e,N
= o,N
=

The noise bandwidths for the most important loop filter configurations are given in Table 1.
Noise bandwidth for the ideal second-order loop is plotted
against damping in (10) (see Fig. 3.3 on p. 32). The minimum
BL is achieved for 0.5, but the noise bandwidth does not
exceed the minimum by more than 25% for any damping between 0.25 and 1.0.
Since the input additive noise and angle-modulaton are independent processes, the total variance of the phase error is
the sum of Eqs. (52) and (59). Taking into account Eqs. (51)
and (60) we get for PM
2
e2 = e2,PM + e,N
=

1
2

|1 H()|2 Si,PM () d +

N0 BL
A2
(62)

The linear approximation can be used only if the total variance of e(t) is small enough. For the ideal second-order loop,
e2 has to be less than 0.2 (10). If, in addition to the input
noise and angle-modulation, other random processes such as
VCO noise or frequency modulation of the VCO output signal
are present then the effects of these processes must also be
accommodated in e2 by applying the technique described
above.
Since there is no signal in the baseband model of the
APLL, an unambiguous definition of the signal-to-noise ratio
(SNR) in the loop cannot be given. The variance of the phase
error is used by Viterbi (3) and Lindsey (6) to define the SNR
in the APLL
SNRL =

A2
N0 BL

(63)

Nonlinear Operation of APLL

(57)

The linear theory of the APLL has been very well developed
and is very easy to understand. In the majority of circuit de-

PHASE-LOCKED LOOPS

sign and development, the linear APLL model is applied and

nonlinear effects are considered only as unwanted problems.
However, in many important situations the nonlinear
model of the APLL has to be considered, for example, if the
lock limits or acquisition properties have to be determined, if
the APLL operates at low SNR, and so forth.
In contrast to the linear APLL theory, a unified theory describing the nonlinear operation of APLL in closed form does
not exist. Many times individual methods and heuristic arguments are used to solve the problem. The details of the nonlinear mathematical analysis are beyond the scope of this exposition. In this section only the most important aspects of
nonlinear APLL theory will be discussed; the interested
reader should refer to the literature for further details, when
the need arises. The latest results on nonlinear theory can be
found in three IEEE publications (1113), while the nonlinear APLL theory is given in many excellent books (310).
Nonlinear Tracking in the Absence of Noise. In this section
we assume that the phase-locked condition has been achieved,
but the frequency or phase of input signal is changed. First
the hold-in range is determined, then the nonlinear transient
response to a phase or/and frequency step is determined by
means of the phase-plane portrait. In this chapter only the
noise-free case is considered.
Let i denote the frequency of the input signal. Then the
input frequency error can be expressed from Eq. (2) as i
i 0. The hold-in range is equal to the input frequency
error, which can be tracked by the APLL, that is, for which
the phase-locked condition is maintained. Mathematically the
hold-in range is equal to the maximum frequency error for
which Eq. (15) has a steady-state solution
sin e =

0
 i K v ve0
=
AKF (0)
AKF (0)

(64)

where ve0 is a dc voltage, 0 i Kvve0 denotes the initial

equivalent frequency detuning, and F(0) is the dc gain of loop
filter. Because the sine function cannot exceed unit magnitude, the hold in range is
|H K v ve0 | = AKF (0)

(65)

The physical meaning of the hold-in range is that the PD output voltage is bounded and so the maximum VCO frequency
detuning is also bounded.
Equation (65) states that the hold-in range can be made
arbitrarily large by using very high loop gain K. Of course,
this is not entirely correct because some other loop component
will then saturate before the phase detector. In the ideal
second-order loops, saturation of the loop amplifier generally
limits the hold-in range. Note that the hold-in range is a
static parameter, that is, its value does not depend on the order of APLL.
Consider next the nonlinear tracking properties, that is,
the dynamics of a first-order APLL in the absence of noise.
Assume that the APLL is operating in steady-state when the
input frequency is suddenly changed so that
i (t) =  i t + i0

(66)

169

where i0 is constant. Substituting F(p) 1, N(t, o) 2 0

and di /dt i into Eq. (15) one gets a nonlinear differential
equation
de
= i K v ve0 AK sin e = 0 AK sin e
dt

(67)

Observe that Eq. (67) is an autonomous differential equation.

To get the nonlinear transient response of APLL to the
input frequency step, Eq. (67) must be solved. The initial
value e0 of the phase error depends on the phase error measured under the previous steady-state conditions and i0.
A better insight into the APLL operation can be obtained
if we plot e de /dt, called the frequency error, as a function
of e , as shown in Fig. 13. A plot of a single solution in the
phase plane is called a trajectory. The trajectory starts from
the initial value e0 of the phase error and goes to its steadystate value for which de /dt 0. An ensemble of trajectories
emerging from different initial conditions is known as phaseplane portrait or flow. A trajectory shows the dynamic behavior of a loop in function of time as it settles (or fails to settle)
toward equilibrium.
As shown in Fig. 13, all trajectories of a first-order APLL
coincide with each other. Let the trajectory be started from
an initial phase error e0. If de /dt is positive for that value of
e , then the phase error will increase as a function of time.
In fact, the APLL follows the trajectory plotted in Fig. 13 and
moves toward the right until it reaches the steady-state for
which de /dt 0. Similarly, if de /dt is negative for e0, then
the phase error decreases until it reaches the steady-state
conditions. In either case, the point belonging to steady-state
is stable, since, after a small perturbation of e in either direction, the system will tend to return to the steady-state.
Since almost all phase detectors have a periodic characteristic, they cannot distinguish a phase step of i 2n, n
1, 2, 3, . . . from one of i. Therefore the APLL never loses
lock when it is driven by a pure phase step, irrespective of
the magnitude of the loop order.
In the first-order APLL, a frequency step breaks the lock
if, and only if, the frequency error exceeds the hold-in limit.
In this case, the phase-locked condition cannot be recovered
and the APLL remains unlocked.
In a second-order loop, the frequency step may also break
the lock if its magnitude is large enough. However, after a

0
sin e
AK

AK

0
AK

ss

ss

Figure 13. Phase-plane portrait for first order APLL.

PHASE-LOCKED LOOPS

e
AK

Saddle

0
Focus

Saddle

ss

ss

2
Focus

3
Saddle

Figure 14. Phase-plane trajectories of the ideal second-order APLL

for 0.707.

transient the APLL may achieve the phase-locked condition

again.
To obtain the phase-plane trajectories for the ideal secondorder APLL, first the time variable has to be eliminated in
Eq. (15). Substituting F(p) (1 p2)/p1 and Eq. (66) into
Eq. (15) one obtains


AK
2
de
d 2 e
+
+
AK
cos

sin e = 0
e
dt 2
1
dt
1

(68)

Letting t /(AK 2 / 1), so that de /dt AK 2 / 1 de /d, one

can eliminate one constant from Eq. (68). Taking into account
that AK 2 / 1, 0, Eq. (68) can be written as
1
d 2 e
de
+
+ cos e
sin e = 0
d 2
d
AK22

(69)

If one divides Eq. (69) by e de /d and recognizes that

d2e /d2 d e /d, then the first term of Eq. (69) becomes e / e
(d e /d)/(de /d) d e /de. Eliminating in Eq. (69), one
may treat the phase error e and the normalized frequency
error e as independent variables (3)
de
1 sin e
= cos e
de
AK22 e

if the loop is overdamped ( 1) or underdamped ( 1),

respectively. The steady-state phase-locked conditions which
are reached asymptotically are called equilibria.
The unstable singularity is called a saddle point. Even if
the loop state gets just into a saddle point, where it is in equilibrium, it cannot remain there, because any disturbance,
such as noise, will displace it slightly and then the saddle
point repels the loop state.
A trajectory that terminates on a saddle point is called separatrix. The separatrices are marked by heavy curves in Fig.
14.
Consider a stable singular point and the two separatrices
that terminate on the two adjacent saddle points. If the initial
conditions lie between these separatrices and the initial
phase error is in the 2 interval centered about the stable
equilibria to be achieved, then the trajectories emerging from
these initial conditions will terminate at that equilibrium
point without cycle slip. If the initial conditions lie outside
these separatrices, then the loop slips one or more complete
cycles before achieving the phase-locked condition.
We are now ready to evaluate the nonlinear transient
graphically for a second-order APLL. First, the initial conditions have to be determined from Eq. (66) and the previous
steady-state conditions. Then the initial conditions have to be
plotted on the phase-plane portrait, and the trajectory emerging from them gives the actual transient response of APLL.
The phase-plane portrait is a very useful tool for the determination of APLL dynamics. Phase-plane portraits for other
loop configurations can be found in (3) and (6).
Acquisition Behavior in the Absence of Noise. Before a PLL
can track, it must first acquire the phase-locked condition. In
general, the PLL quiescent frequency differs from the frequency of the incoming signal. Therefore, first the VCO frequency has to be tuned to the incoming frequency by the loop.
This process is called frequency pull-in. Then the VCO phase
has to be adjusted according to the input phase. This process
is known as phase lock-in.
The two parts of the acquisition process can be recognized
easily by plotting the phase error as a function of time. Figure
15 shows that the phase error e(t) generally goes through
multiple periods of 2 before finally settling in to the phaselocked condition. When the phase exceeds 2, a cycle slip occurs between the incoming and VCO phases. The position of

(70)

To get the phase-plane portrait, the solution of Eq. (70)

must be determined for different initial conditions. The
phase-plane trajectories for an ideal second-order APLL are
shown in Fig. 14.
The phase-plane portrait of an APLL with a periodic phase
detector characteristic is also periodic with the same period
in variable e, but is aperiodic in e. Trajectories proceed as a
function of time clockwise only as marked by arrows in Fig.
14. Intersection of trajectories may occur only at singular
points, that assign the possible steady-state solutions of loop
equation. Both stable and unstable singular points appear;
equilibrium occurs at stable singularities. In second-order
APLLs, an equilibrium is called a stable node or stable focus

e (t)
3

e in rad

170

Pull-in

Lock-in

Figure 15. Distinction between pull-in and lock-in.

Phase error in degrees

PHASE-LOCKED LOOPS

200
180
160
140
120
100
80
60
40
20
0

Table 3. Acquisition Parameters of First- and Second-Order

APLLs

(e)
(d)

Loop Order

(c)

Second

(a)

Loop Filter
F(s)

Acquisition Range
(rad/s)

Acquisition Time
(s)

4BL

2
BL

1 s 2
1 s 1

2AK n

20
2 3n

1 s2
s 1

20
2 3n

First

(b)

171

AKt
Figure 16. Acquisition behavior of first-order APLL. The initial values of phase error i0 are (a) 45; (b) 135; (c) 170; (d) 178.86 and
(e) 179.886.

cycle slips can be seen easily if one plots the modulo-2 process for e(t), shown in Fig. 15 by the lower curve. The jumps
of 2 in e(t) indicate the occurrence of a cycle slip. Note that
there are no cycle slips during the lock-in process.
Acquisition is inherently a highly nonlinear phenomenon.
It is started from given initial conditions and no external excitation is applied, apart from the initial phase and frequency
error. This means that acquisition can be described by an autonomous nonlinear differential equation and it can be studied by the phase-plane portrait introduced in the previous
section.
If the loop acquires lock by itself, the process is called selfacquisition. If it is assisted by extra circuits, it is called aided
acquisition. Since self-acquisition is relatively slow and unreliable, acquisition-aids are often used. For a good survey of
different aided acquisition techniques, see (10).
The acquisition behavior of a first-order APLL is described
by Eq. (15) and can be studied by means of the phase-plane
portrait shown in Fig. 13. Under steady-state conditions,
de /dt 0. It is clear from Eq. (15) and Fig. 13 that de /dt
becomes zero at any of the following values of phase error:


0
+ 2n,
n = 0, 1, 2, . . .
ss = sin1
AK


(71)
0
+ (2n 1),
n = 0, 1, 2, . . .
ss = sin1
AK
provided 0 AK. Referring to Fig. 13 one sees that the
equilibrium points denoted ss are stable, ss are unstable. If
the phase error is equal to ss then any perturbation in either
direction, caused by noise, for example, will cause e to move
until it reaches the next stable equilibrium. If 0 AK, no
stable equilibrium exists and the loop never reaches the
phase-locked condition, but e(t) moves along the sinusoidal
trajectory.
Figure 13 shows that an infinitely large number of equilibrium points exists. Since every cycle of the trajectory has a
stable equilibrium, e cannot change by more than one cycle
before phase-locking. Thus the pull-in and lock-in ranges are
equal, so cycle slipping never occurs during acquisition in the
first-order loop.
The phase transients of the first-order APLL during acquisition are shown in Fig. 16 for different values of the initial
phase error i0. Note that for small i0, the loop operation re-

mains near the equilibrium and the phase transient is almost

exponential, as expected from the linear theory of the APLL.
However, if i0 135, the waveforms diverge considerably
from exponential and the acquisition time becomes very long.
The acquisition parameters of the first-order loop are given in
Table 3.
As explained above, the first-order loop always achieves
the phase-locked condition without cycle slips. The same is
not valid for the second- and higher-order loops; for these, the
lock-in range is smaller than the pull-in range. The phaseplane portrait for an ideal second-order APLL is shown in
Fig. 14.
Gardner has proposed a simple method to estimate the
lock-in range (10). Let F() denote the high-frequency asymptotic response of the loop filter. For a second-order loop
F() 2 / 1. If the deviation of the input frequency from the
VCO center frequency is greater than 1/ 2, then the secondorder loop behaves like a first-order one, with open loop-gain
K KdKvF(). As a useful engineering approximation one
may say that higher-order loops have the same lock-in range
as first-order ones with equivalent gain. If ve0 0, one may
write
L AKF ()

(72)

The frequency pull-in, or simply pull-in, is much slower

than the lock-in process. The acquisition problem cannot be
solved in closed form; some approximation must be used.
Richman has developed a model (16) for the analysis of pullin process. Consider an ideal second-order APLL. The loop
filter can be divided into two parallel paths
F(s) =

1 + s2
1

=
+ 2
s1
s1
1

(73)

as shown in Fig. 17. Note that there is a high-frequency ac

path from the PD output to the VCO input with flat gain of
2 / 1 and a dc path which contains a perfect integrator.

(Beat-note)

Dc path
vp

1
( )dt
2

vI

VCO

vc

Ac path

Input
signal
PD

vd

0 = 0 + K vv I

+
+

Figure 17. Pull-in model for the ideal second-order APLL.

172

PHASE-LOCKED LOOPS

Input

signal

VCO

without FM

with FM

VCO

Figure 18. Pull-in spectra. The instantaneous center frequency of

the VCO is denoted by 0.

One can understand the pull-in process easily by plotting

the relevant spectra in the loop. Initially, the input and the
VCO frequencies are i and 0, respectively, as shown by the
upper two traces of Fig. 18. Let 0(t) denote the instantaneous
VCO center frequency, which is a slowly varying function,
and which is determined by the integrator output vI. The frequency difference 0 i is called the beat-note.
The analog multiplier used as a phase detector generates
the beat-note, which gets through the ac path and modulates
the VCO, generating FM sidebands as shown in the lower
trace of Fig. 18. Observe that the FM sideband ( 0 ) coincides with i and produces a negative dc voltage at the PD
output denoted by vp in Fig. 17. This dc voltage is integrated
by the dc path and the slowly varying output vI(t) of integrator pushes 0 toward i. The pull-in process is terminated
when 0 i.
Many approximate formulas for pull-in limits and pull-in
time have been developed by different authors for various
loop configuration. For a good survey, see Sec. 5.3 of (10). Formulas giving the acquisition parameters of first- and secondorder loops are given in Table 3.
Hangup Phenomenon. APLLs occasionally have extremely
long acquisition time that cannot be tolerated in many applications. In these cases, the loop seems to stick for a long time
at a certain value of phase error before moving toward the
phase-locked condition. This phenomena, studied by Gardner
in (17), is known as the hangup effect.
Almost all phase detectors have a phase error characteristic which is periodic. Due to this periodicity, the loop equation
has two steady-state solutions in every period. The locations
of steady-state solutions have been called the normal equilibrium null and reverse null by Gardner (10).
The slope of the PD characteristic is positive at the normal
equilibrium null providing negative feedback for the loop. At
the reverse null, the slope becomes negative causing positive
feedback in the APLL.
Consider an APLL implemented with an analog multiplier
and assume that 0 0, that is, that the steady-state phase
error is zero. The phase trajectories originating near 180 remain in that vicinity for a long time before decaying toward
equilibrium at 0. Examples for hangup are shown in Fig. 16,

where the phase transients are plotted for different initial

values of phase error. It must be emphasized that the hangup
effect appears in every APLL, independently of the loop order.
It is obvious from Fig. 17 that the rate of VCO control voltage is proportional to the dc output vp of the phase detector
that is, in reality, a slowly varying signal. Voltage vp can be
considered as a restoring force. If vp is very small, as occurs
near the reverse null, then restoring force is also small and
the loop converges extremely slowly toward the phase-locked
condition.
Techniques and design rules that help to avoid the hangup
effect are given in (17).
False Lock to Data Sidebands. The recovery of suppressed
carriers is also performed by PLLs. The most commonly used
circuit configurations will be discussed later. Since the carrier
is completely suppressed in these cases, the carrier recovery
circuit must regenerate a harmonic of the carrier (squaring
loop) or, equivalently, must generate a phantom carrier (Costas loop). In both solutions, the loop operation can be modeled
by a proper nonlinear operation followed by a CW tracking
loop.
In addition to the regenerated signal, discrete frequency
components spaced by integer multiples of half the symbol
rate also appear about the desired frequency due to the nonlinear operation (18,19). If the quiescent frequency of the
VCO is close enough to one of these sidebands, then the loop
will lock onto that spectral component instead of the desired
frequency. This phenomena is called false lock to data sidebands. The probability of false lock is especially high when
the SNRL is high.
Note that this kind of false lock is completely different
from that which appears in a superheterodyne PLL receiver.
In that case, false lock is caused by the narrowband IF filter,
which is included in the so-called long loop. For a comprehensive discussion of the false lock problem in long loops, and for
further references, see (10).
APLL Behavior in the Presence of Noise. When one tests the
behavior of a real APLL and reduces the SNRL below about 7
dB, the fluctuation in phase error, called phase jitter, becomes
more than predicted from Eq. (62). In this section, the behavior of the APLL for low SNRL when the linear approximation
is no longer applicable is briefly discussed.
We have seen that PLLs have an infinitely large number
of stable equilibrium points. At low SNRL, the phase error
migrates among the different stable equilibrium points, that
is, the probability density function (pdf) of e appears as a
multimodal function with each mode centered about a stable
equilibrium point.
To understand the problem, let the SNRL be very high at
the beginning and then let it be reduced later.
For high SNRL, a small fluctuation in phase error about
ss appears. This small fluctuation can be determined by
means of linear APLL theory.
If the SNRL is reduced then the linear approximation results in a large error [see Fig. 3.4 in (10)]; even more, cycle
slips occur. Migration caused by the cycle slipping problem
can be studied only in the context of nonlinear theory.
The detailed study of nonlinear APLL theory goes beyond
the scope of this chapter. This section will only summarize
the basic ideas and the most important results. Interested

readers may refer to the original sources of nonlinear APLL

theory (3,7).
The migration of phase error among the different stable
equilibrium points is illustrated in Fig. 19. The figures show
how the steady-state pdf of phase error is developing from its
initial position. Let the APLL initially be in phase lock so
that p(e, tss, t0) (e, ss). With time, the initial phase
begins to diffuse in the vicinity of ss, due to noise, but cycle
slip does not yet appear. However, after a sufficiently long
period, more and more cycle slips appear in both directions.
The average time for the occurence of cycle slips depends on
SNRL. After a long time, the probability density of phase error
will appear as a multimodal function, with each mode centered about a stable equilibrium point. If one considers the
equilibrium points as attractors, then one may say that the
phase error migrates among the basins of all of these attractors in the long run. As a result, the pdf of the phase error
possesses an unbounded variance.
Tikhonov (21,22) and Viterbi (23) have shown that the
phase error process reduced by modulo-2 is stationary and
possesses a bounded variance. If one treats the cycle slip effect as an independent problem and if one is interested in the
steady-state behavior of the APLL, then one may attend to
determining the pdf of the reduced modulo-2 phase error
process, which is denoted by (t).
The loop operation can be described in the presence of
noise by a nonlinear stochastic differential equation [see Eq.
(15)]. An exact nonlinear theory for APLLs can be developed
by means of FokkerPlanck theory (6). The solution of the

p( e, t ss, t0)

( e ss)
e

2(n 2)

2(n 1)

2n
ss

2(n + 1)

2(n + 2)

2(n + 1)

2(n + 2)

(a)
p( e, t ss, t0)

e
2(n 2)

2(n 1)

2n
(b)

p( e, t ss, t0)

Probability density function p( )

PHASE-LOCKED LOOPS

1.5
(c)
1
(b)
0.5

0
3

2(n 1)

2n

2(n + 1)

p( e, t ss, t0)

e
2(n 2)

2(n 1)

2n

2(n + 1)

2(n + 2)

(d)
Figure 19. Qualitative behavior of the phase error pdf with time.
Initially, the APLL is (a) in equilibrium position ss; then (b) the pdf
expands due to diffusion. Later a cycle slip appears and the phase
error migrates (c) to the adjacent stable equilibrium on the right side.
Then after a long period (d) the pdf appears as a multimodal function
about the stable equilibrium positions.

0
ss

Figure 20. Probability density functions of reduced phase error for

a first-order APLL with zero detuning. The curves are given for
SNRL values of (a) 0 dB (b) 5 dB and (c) 10 dB.

FokkerPlanck equation gives the pdf for the reduced phase

error process in closed form. Consider the first-order APLL
implemented with a sinusoidal phase detector. Viterbi (3) has
shown that, for zero detuning, the pdf of the reduced phase
error process is
p() =

exp( cos )
,
2I0 ()

<

(74)

where 4A/N0K SNRL is the loop signal-to-noise ratio

and I0() denotes the zeroth-order modified Bessel function.
Typical probability densities of (t) for a first-order loop and
zero detuning are shown in Fig. 20; probability density functions for other parameters are given in (3). The measured and
calculated probability density functions are compared in (7).
The Tikhonov probability density function can also be used
to describe the behavior of higher-order APLLs. Lindsey has
shown in (6) that, if the parameter is suitably modified,
then the steady-state pdf of higher-order loops can be approximated by Eq. (74).
Cycle slips in the carrier recovery circuit destroy the performance of digital telecommunication systems. Cycle slips
may occur either in isolated form or in bursts (24).
Consider again a first-order APLL with zero detuning. Using the FokkerPlank technique, Lindsey has shown in (6)
that the mean time between cycle slips is
=

2(n + 2)

(c)

(a)

Reduced phase error in rad

e
2(n 2)

173

2 I0 ()
2BL

(75)

These values agree perfectly with the measured data (24). Observe that is inversely proportional to the noise bandwidth
of the APLL, that is, for efficient carrier recovery a narrowband loop must be used.
Equation (75) can approximate the mean time between cycle slips in higher-order APLLs if the parameter is modified
appropriately (6). A better theory, giving more accurate results, has been published in (25); for measured data, see (24).
PLL APPLICATIONS
The baseband model of the analog phase-locked loop and the
linear and nonlinear APLL theories were discussed in the

174

PHASE-LOCKED LOOPS

previous sections. The operation principle and versatility of

PLLs cannot be understood without surveying the bases of
different PLL applications. The aim of this section is to provide this survey and not to discuss the latest circuit configurations developed for various PLL applications.
Although various circuit configurations have been developed for different applications, the baseband model discussed
above can be adopted, with minor modification, to these loop
configurations.
In all PLL applications, the phase-locked condition must
be achieved and maintained. In order to avoid distortion,
many applications require operation in the linear region, that
is, the total variance of the phase error process appearing due
to noise, modulation, and so on, must be kept small enough.
Recall that only the PD output, VCO control voltage, input
phase i(t), and output phase o(t) appear in the PLL baseband model. All these signals are low-frequency signals, i(t)
and o(t) are the phase modulations of the input and output
signals. Sometimes it is not easy to determine the spectrum
of the original bandpass input and output signals. If an analog multiplier is used as the phase detector, then, by knowing
the spectrum of the PD output and exploiting the frequency
shifting property of the analog multiplier, the output spectrum can be determined easily.
Different phase detectors are used in different applications, in order to achieve the best circuit performance. The
most commonly used PD circuit configurations will be discussed later; many of these are edge-triggered. The operation
of PLLs implemented by an edge-triggered PD cannot be described exactly by the simple APLL model. However, Gardner
has shown that, even in these cases, the APLL theory can be
used as a good approximation of the real operation if the
closed-loop bandwidth is less than one tenth of the input frequency (26).
The PLL is one of the most commonly used circuits in electrical engineering. A detailed discussion of different applications is beyond the scope of this article; for a comprehensive
survey of applications, see (11) and (14).
In addition to the conventional applications, new applications for the various PLLs have been published recently. It
has been shown that both the analog (27) and sampling PLLs
(28) may exhibit chaotic behavior. Bernstein and Lieberman
have proposed the application of an ideal sampling PLL for
random number generation (29). The quality of generated
random numbers has been evaluated by the run test in (30).
By means of a chaotic APLLs, very simple chaotic telecommunication systems can be implemented (31).

The filter characteristic is determined by the closed-loop

transfer function. A further advantage of PLL bandpass
tracking filters is that they reject the amplitude modulation,
that is, they can also be used as limiters.
The block diagram of a bandpass tracking filter is shown
in Fig. 21. If the loop parameters depend on the amplitude
of the input signal, an AGC circuit must precede the PD
in order to keep the filter parameters constant. Note that
the problems of and the difficulties associated with the design and implementation of a high-frequency bandpass filter
are reduced to the design and implementation of a baseband loop filter. The design of PLL bandpass filters is discussed in detail in (32).
CW Carrier Recovery
In every coherent receiver the carrier has to be recovered
from the noisy input signal (15). Here, it is assumed that the
carrier is present all the time in the received spectrum; the
recovery of a suppressed carrier will be considered later. The
aim of CW carrier recovery is to retrieve the unmodulated
carrier and to suppress as much noise, modulation, and interference as possible. Note that the CW carrier recovery circuit
is a narrowband bandpass tracking filter implemented by a
PLL, as shown in Fig. 21.
The noise-free recovery of a carrier in a noisy environment
requires a very narrowband PLL [see Eq. (61)]. As shown by
Table 3, the acquisition properties of narrowband PLLs are
very poor. We may overcome this problem by using two different loop bandwidths: a wide one during the acquisition process and a narrow one in steady-state, after the phase-locked
condition has been achieved (10).
The Doppler effect must also be considered in many carrier recovery circuits. The ideal second-order PLL can track
a frequency ramp, but the reduction of tracking error requires a wide loop bandwidth (see Table 2). On the other
hand, the noise-rejection performance of a PLL is inversely
proportional to the loop bandwidth. For low SNR, this contradiction can be solved by using third- or higher-order loop
configurations (33).
PLL Amplifier
The implementation of high-gain amplifiers in the extremely
high-frequency region is very expensive. As shown in Fig. 22,
the PLL can be also used for amplification of angle-modulated
signals. In the simplest circuit configuration, the multipliers
denoted by their multiplication factor N and the amplifier fol-

Tracking Bandpass Filter

Bandpass filters that must select very narrowband anglemodulated signals cannot be implemented by conventional
analog filters, due to their temperature dependence. In other
applications, the carrier frequency of an angle-modulated signal varies. These problems can be overcome if a PLL tracking
the carrier is used as a bandpass filter. The PLL separates
the spectrum of the angle-modulated signal from other interfering signals, or limits the transmitted spectrum to within
specified bounds. The output phase modulation is determined
by the closed-loop transfer function as given by Eq. (27)
o = H(s)i (s)

(76)

Noise
ni(t)
Input
signal
s(t, )

x(t)
AGC

PD

F(s)

VCO

Filtered
signal
s(t, )

Figure 21. PLL configuration for bandpass tracking filter and CW

carrier recovery. The AGC circuit is used to keep the input amplitude,
that is, loop parameters, constant.

PHASE-LOCKED LOOPS
Signal
to be
amplified
s(t, )

Amplified
signal
PD

F(s)

VCO

s(t, )

Figure 22. Amplification of angle-modulated high frequency signals

by PLL.

lowing the PLL are missing. The gain is determined by the

ratio of VCO output and input powers. Note that the amplification is performed in the baseband. In addition to amplification, the PLL also operates as a limiter and filter for the incoming angle-modulated signals.
Sometimes it is cheaper to implement the VCO and power
amplifier below the input frequency band, as shown in Fig.
22. Due to the frequency multiplier placed in the feedback
path of the APLL, the VCO output frequency is f i /N, where
f i is the input frequency. The input phase/frequency deviation
is also divided by N; however, the modulating frequency remains unchanged. Then the output frequency multiplier following the power amplifier restores the original carrier frequency and phase/frequency deviation.
Frequency Synthesis and Angle Modulation by PLL
Signals with high-frequency stability and high spectral purity
are often required in electrical engineering. In many applications, the frequency of generated signal must be varied by a
digital code.
The PLL is widely used in frequency synthesis to generate
spectrally pure signals and, if necessary, to operate as an analog or digital frequency or analog phase modulator. Frequency
multiplication and/or division, furthermore frequency addition and/or subtraction, may be performed, using a PLL in
conjunction with programmable frequency dividers and mixers as shown in Fig. 23. As a result, the output frequency f o
can be expressed as a combination of reference and offset frequencies, division ratios of frequency dividers. In frequency
synthesis, the PLL input is called reference signal and its frequency is denoted by f R. To optimize the system performance,
frequently a multiloop circuit configuration (36) is used.
In frequency synthesis applications, the dominant noise
sources are the VCO, frequency dividers, mixers, and phase
detectors. The main design goals are to minimize the output

Reference
signal
fR

+
1
M

PD

phase noise, to avoid the generation of spurious output signals, and to minimize the unwanted output FM caused by the
periodic output of the phase detector. These requirements can
be satisfied with special PD configurations, such as phasefrequency detector with a charge pump circuit or sample-andhold phase detector. The operation of these PDs will be discussed later. Many system aspects must be considered during
the development of frequency synthesizers. A detailed discussion of these questions can be found in (3639).
In addition to frequency synthesis, PLLs can be also used
as FM or PM modulators. The corresponding transfer functions for FM and PM are

so (s) = [1 H(s)]K vV F M (s)

o (s) = H(s)

N
V (s)
AK PM

K=

Kd K v
N

F(s)

VCO

Coherent Demodulation by APLL

The noise performance of coherent demodulators is much better than that of their noncoherent counterpart (15). A circuit
configuration, which is suitable for coherent PM, FM, and AM
demodulation, is shown in Fig. 24.
PM Demodulator. Assume first that the input signal s(t, )
is phase modulated and A(t) A constant. The demodulated PM signal can be measured at the output of the phase

fo = N fR + fS
M

1
N
Offset frequency
fS

(78)

The equations given above and the APLL theory discussed

earlier are valid only if an ordinary differential equation can
describe the operation of the PLL. The phase detectors used
in frequency synthesis are edge-triggered circuits. This is why
the exact modeling of these circuits can be performed only by
an integro-difference equation (26), (40). However, if the
closed-loop bandwidth is less than one-tenth of the reference
frequency f R, then the continuous-time approximation can be
used and the APLL theory is a good approximation of the circuit operation (26).

Modulated
output

+
+

(77)

where Kv and N/AK are the gains of the FM and PM modulators, respectively. The closed-loop error [1 H(s)] and transfer H(s) functions are given by Eqs. (29) and (28), respectively.
The only difference is that the frequency synthesizer has a
frequency divider in the feedback path. Therefore, the loop
gain becomes

vFM(t)
FM modulation
input

vPM(t)
PM modulation
input

175

Figure 23. Frequency synthesis by PLL.

176

PHASE-LOCKED LOOPS

Fig. 24). Since the PLL needs an input signal to be tracked

continuously, the spectrum of the AM signal must contain a
carrier component.
If the carrier is recovered by an ideal second-order PLL,
then the VCO output is

Demodulated
PM output
i(t)
Input
signal
A(t)s(t, )

Demodulated
FM output
PD

F(s)

=
r(t, )

d i
dt

(82)

and the difference-frequency output of multiplier

VCO

2Vo cos( i t + i0 )

A0Vo [1 + m(t)]
Demodulated
AM output

(83)

contains the demodulated signal m(t); A0Vo is the gain of the

AM demodulator.

m(t)
Figure 24. Coherent PM, FM and AM demodulation by APLL.

detector. In this case, the PD output signal is given by

V d (s) = [1 H(s)]AKd i (s)

(79)

where i(s) denotes the input PM and AKd is the gain of the
PM demodulator. The demodulated PM signal is multiplied
by the closed-loop error function which has a high-pass characteristic. Distortion can be avoided if the closed-loop bandwidth is less than the lowest modulation frequency. The other
source of distortion is the PD nonlinearity. This type of distortion does not appear if the total variance of the phase error
given by Eq. (62) remains small enough.
FM Demodulator. Assume that a frequency modulated input signal is applied to a PLL. If the phase-locked condition
is maintained, then the VCO frequency follows the incoming
frequency. Since the VCO frequency is proportional to the
VCO control voltage, the FM modulation may be recovered
from the VCO control voltage. By means of the transfer function concept, one may write
1
V c (s) = H(s)
s (s)
Kv i

(80)

where 1/Kv is the gain of FM demodulator. This equation

shows that the FM demodulator output, that is, the VCO control voltage, is proportional to the input FM if the closed-loop
bandwidth exceeds the highest modulation frequency.
The distortion caused by the PD nonlinearity is reduced by
feedback so the PD distortion is not critical. However, the
VCO transfer characteristic must be linear, in order to get an
FM demodulator with low distortion.
AM Demodulator. Let the input signal be amplitude modulated

x(t) = [1 + m(t)] 2A0 sin( i t + i0 )

(81)

where m(t) carries the information to be transmitted, and A0,

i and i0 are constants. The PLL demodulator contains a carrier recovery circuit (see the PLL in Fig. 24) and an AM demodulator (see the analog multiplier and low-pass filter in

Suppressed Carrier Recovery Circuits

In digital telecommunications, the optimum detection of
transmitted data requires that both the carrier and clock signals be available at the receiver (15). The carrier and clock
recovery circuits are used to retrieve these signals from the
noisy incoming waveform.
In order to maximize the power efficiency, modern digital
modulation techniques suppress the carrier completely, that
is, all transmitted energy resides in the data sidebands. Narrowband PLLs cannot be used for carrier recovery, because
the carrier frequency is missing from the input spectrum.
The missing carrier frequency component can be regenerated by nonlinear circuits called regenerators. The regenerator can be placed before the narrowband PLL as an entirely
separate circuit, or it may be included in the loop. Examples
for the first and second solutions are the squaring and Costas
loops, respectively.
Many factors have to be considered during the selection
and development of a suppressed carrier recovery circuit (20).
Here, only the basic operating principles of these circuits is
surveyed. Interested readers may find a discussion of the carrier recovery problem in the literature (7,10,20,4143).
For the sake of simplicity, only binary phase shift keying
(BPSK) modulation shall be considered here. In BPSK, the
binary information to be transmitted is mapped to the phase
of a sinusoidal carrier. If the data bit is a 1, the phase of
the carrier is zero; while if the data bit is a 0, the carrier
phase becomes 180. If the probabilities of 1s and 0s are
equal, then the carrier is completely suppressed. In the noisefree case, the received signal can be expressed in the form
vi (t) = m(t) sin(i t + i )

(84)

where i is the carrier frequency and the carrier phase i is

arbitrary but constant. The binary data stream is given by
m(t). From the carrier recovery problem of view, the intersymbol interference (ISI) problem (20) can be disregarded, that is,
we may assume m(t) 1. Three basic types of carrier recovery circuits will be discussed in the following: the squaring
loop, the Costas loop and the inverse modulator.
Squaring Loop. In this case, the nonlinear operation is performed by a square-law device, that is, a frequency doubler
circuit. As shown in Fig. 25, the nonlinear operation precedes

PHASE-LOCKED LOOPS

VCO output is

Frequency
doubler
m2(t) cos(2it + 2 i)

Input
signal

()2

2 cos(i t + o )

F(s)

m(t) sin( it + i)

2i

VCO

1 2
m (t) sin[2(i o )] sin(2e )
2

Recovered carrier
i
Figure 25. Suppressed carrier recovery by squaring loop.

the narrowband PLL. From Eq. (84) the output of frequency

doubler circuit is obtained:
1 2
m (t)[1 cos(2 i t + 2i )]
2

(86)

Equation (86) shows that, after the frequency doubler, a conventional narrowband PLL can be used to recover the second
harmonic of the carrier. Finally, the double-frequency output
of the PLL is frequency divided by two, in order to recover the
original carrier signal.
Costas Loop. In the squaring loop the nonlinear operation
is performed in the RF band. The Costas loop offers an alternative solution, where the BPSK modulation is removed in
the baseband.
The block diagram of Costas loop is shown in Fig. 26. The
circuit contains in-phase (I-arm) and quadrature (Q-arm)
channels and an analog multiplier, that is, a phase detector
that precedes the loop filter. The I- and Q-arms consist of an
analog multiplier and a low-pass filter.
To understand the operation of Costas loop, assume that
the phase-locked condition has been achieved and that the

(88)

By comparing Eqs. (10) and (88) we conclude that, in the

noise-free case, the output of the baseband multiplier in a
Costas loop is equal to the PD output of a conventional APLL.
The only difference is that the phase error is multiplied by a
constant of two that results in a higher PD gain.
In addition to carrier tracking, the Costas loop demodulates the incoming BPSK signal. If the phase error is small,
then the output of the low-pass filter in the I-arm becomes
m(t) cos(i o ) m(t)

(85)

Taking into account that m(t) 1, that is, m2(t) 1 one

may write
vx (t) cos(2it + 2i )

(87)

The output of the low-pass filters in the Q- and I-arms are

m(t) sin(i o), and m(t) cos(i o), respectively. Taking
into account that m2(t) 1, one may express the output of the
baseband multiplier as

1
2

vx (t) = v2i (t) =

177

(89)

Inverse Modulator. Two slightly different versions of an inverse modulator or remodulator can be found in the literature
(10). The terms inverse modulator and remodulator are
used interchangeably and indiscriminantly. As an example,
the operation of an inverse modulator is discussed here.
The block diagram of an inverse modulator contains demodulator and modulator circuits, as shown in Fig. 27. Assume that the PLL involved has achieved the phase-locked
condition and that the VCO output is
2 cos( i t + o )

(90)

Then the output of the demodulator can be expressed as

m(t td ) cos(i o )

(91)

where (i o) is the phase error of the PLL and td denotes

the time delay of the low-pass filter involved in the demodulator. This demodulated signal modulates the recovered carrier
in the modulator and produces an output
2m(t td ) cos(i o ) cos( i t + o )

(92)

m(t) sin( i o)

Q - arm

2 cos( it + o)
Input
signal
VCO

m(t) sin( it + i)

F(s)

m2(t)
sin 2( i o)
2

2
2 sin( it + o)
I - arm

m(t) cos( i o)
Demodulated
bit stream

Figure 26. Demodulation of BPSK signal

by Costas loop.

178

PHASE-LOCKED LOOPS
Demodulator

Input
signal

m(t td) cos( i o)

To bit
detector

m(t) sin( it + i)
2 sin( it + o)
2 cos( it + o)

Modulator

VCO

F(s)
1 2
m (t
2

Delay
td

td) sin 2( i + o)

m(t td) sin( it + i)

Phase
detector

Figure 27. Block diagram of the inverse

modulator.

which is multiplied in the phase detector by the delayed input

signal m(t td) sin(it i). The input signal has to be delayed, in order to cancel the effect of the delay in the demodulator.
Neglecting the sum frequency component the PD output is
obtained:
m2 (t td ) cos(i o ) sin(i o ) sin(2e )

(93)

As in Eq. (88), this signal can be considered as the PD output

of an equivalent PLL. Observe that if the phase error is small
enough, then the demodulator output is equal to m(t).
Clock Recovery Circuit
In addition to the carrier, the timing information, that is, the
clock signal, also has to be recovered in the digital telecommunication systems (7,20). There are two basic classes of
clock recovery circuits, but a PLL can be recognized behind
both solutions.
The clock frequency component is regenerated from the incoming signal via some nonlinear operation in the first class

2m(t td) cos( i + o) cos( it o)

of clock recovery circuits. These approaches offer the simplest

solution, but their performance is only suboptimal. Note that
these solutions are analogous to the squaring loop used in
suppressed carrier recovery. Examples for these circuits are
the cross-symbol synchronizer (44) and the squaring loop
symbol synchronizer (45).
The other class of clock recovery circuits is based on maximum a posteriori estimation (MAP) techniques (7,46). Many
variants of this technique are currently used; they differ
mainly in the phase, that is, clock error, detector characteristics. The operation of the early-late gate clock recovery circuit
(47), as an example, will be discussed here.
The block diagram of the early-late gate clock recovery circuit is shown in Fig. 28. The circuit contains a pair of gated
integrators called early and late gates, each performing its
integration over a time interval of T/2 s. The input bit stream
is

an p(t nT )
(94)
n

where T is the symbol duration and p(t) denotes a rectangular

pulse width duration T. Integration by the early and late

Early gate
1
T ( )dt
T

abs( )
CH

Bit stream

Timing

n an p(t T)
an = 1

F(s)

vd

T
1 +
2 ( )dt

Figure 28. Block diagram of the earlylate gate clock recovery circuit.

VCO

abs( )
CH
Late gate

Recovered
clock signal

PHASE-LOCKED LOOPS

=0

Perfect timing
vd = 0

No transition
vd = 0

Late
vd > 0

Early
vd < 0

Figure 29. Typical waveforms in the early-late gate clock recovery

circuit.

gates are performed during the T/2 s, just before and after,
respectively, the estimated location of data transition. Gate
intervals adjoin each other, but do not overlap.
Waveforms helping to understand the operation of clock
recovery circuit are shown in Fig. 29. If the timing error is
zero, then the data transition falls just on the boundary between the operation of the early and late gates. In this case,
the estimated and incoming data transitions coincide with
each other, and the output of the two integrators, stored in
the hold capacitors CH, are equal. As a result, the error voltage vd(t) becomes zero.
Because the error voltage is produced from the absolute
values of the integrator outputs, it is also zero if the data
transition is missing.
If a transition of input data does not coincide with the estimated time instant of a transition, then a timing error denoted by in Fig. 29 appears. In this case, the data transition
falls not on the boundary of operation of the early and late
gates, but occurs within the operation interval of one or other
gates as shown in Fig. 29. Since the input signal changes its
polarity during the gate operation, the associated integration
reaches a smaller magnitude than for the other gate, where a
transition does not occur. Comparing the magnitudes of the
two integrators gives the error voltage vd(t), which can be
used after low-pass filtering to control the VCO frequency.
PHASE DETECTORS
The loop component that has the greatest influence on the
performance of a PLL is the phase detector. There are many
types of phase detectors, each having its own special benefits.
Some can be used at very high frequencies; others may operate in a noisy environment. Different types of phase detectors
are used in various applications in order to obtain the best
performance. In this section, we consider the most important
characteristics of a PD and discuss commonly used PD configurations.
It has been shown that the gain of the phase detector Kd
[or AKd, in the sinusoidal APLL, see Eq. (10)] has a direct
influence on every PLL parameter from the quiescent value
of the phase error to the noise bandwidth. In the majority of
applications, these parameters have to be kept constant, even
if the amplitude of the incoming signal varies. However, the
product AKd appears in the loop equations for certain phase
detectors, in which case all of the loop parameters depend on
the input amplitude. In these cases, an AGC or limiting cir-

179

cuit may be needed before the phase detector, in order to keep

the input amplitude constant.
If one plots the PD output voltage against the phase error,
two important PD characteristics can be observed. The phase
range over which the feedback is negative in the loop is limited. Furthermore, the region over which the linear approximation is valid for the PD limits the maximum of allowable
excursion of the phase error in many applications. The sizes
of these regions are different for different phase detectors.
Many phase detectors implemented by digital circuitry are
edge-triggered circuits. In certain applications, the phase detector must operate in very noisy environment. However,
edge-triggered PDs are intolerant of missing or extra signal
transitions. This transition-sensitive property makes the use
of edge-triggered PDs impossible if the input SNR is low.
In addition to the desired dc voltage, a periodic signal appears at the output of the PD under phase-locked condition.
This periodic signal is attenuated, but cannot be completely
suppressed by the low-pass filter included in the phase detector and the loop filter. The periodic signal getting through to
the VCO input causes unwanted frequency modulation of the
output signal, that is, sidebands appear. These sidebands are
especially unwelcome in frequency synthesizer applications.
Earlier it was mentioned that the PLL acquisition consists
of frequency and phase pull-in processes. In higher-order
PLLs, the pull-in time can be extremely long; worse still, for
many loop configurations there is no guarantee that the
phase-locked condition will be reached. This problem can be
overcome by means of a phase-frequency detector, which operates as a phase detector under phase-locked condition, but
provides a frequency-sensitive signal to aid frequency pull-in
when the loop is out of lock.
Certain types of phase detectors, like a high-speed sampler, can be used in the extremely high-frequency region,
while others, such as the sample-and-hold phase detector,
may operate up to about 1 MHz. The operating frequency region is another important PD characteristic.
From an operation point of view, one must distinguish
between analog and edge-triggered phase detectors. In edgetriggered circuits, the information is transmitted only at discrete-time instants. Examples of edge-triggered phase detectors are the RS flip-flop, sample-and-hold phase detector, and
phase-frequency detector. Digital frequency dividers used in
the feedback path are also edge-triggered circuits. If a PLL
contains edge-triggered circuit(s) then an integro-difference
equation is required to model its operation correctly. However, if the closed loop bandwidth of the PLL is less than onetenth of the input frequency, then the continuous-time approximation can be used, that is, the APLL theory may be
applied (26).
In addition to phase detectors, many other loop components are used in various PLL applications, from frequency
dividers to VCO circuits. Discussion of these loop components
goes beyond the scope of this article; the interested readers
should consult the literature. The components of the APLL
are surveyed in (10); for the components of frequency synthesizers, see (3639); the building blocks of digital PLLs are
discussed in (48).
Gardner has distinguished in (10) two basic categories of
phase detectors: the multiplier-type and sequential circuits.
The multiplier-type phase detector determines the product
of the input and VCO waveforms. The PD output, which is

180

PHASE-LOCKED LOOPS

used as an error signal in the PLL, is the average value of

this product. These circuits have no memory and they can
operate in very noisy environments.
The output of a sequential phase detector is proportional
to the time interval between the zero crossings of the input
and VCO waveforms. The information is carried by the position of signal transitions; other details of waveforms have no
influence on the PD output. These detectors contain a memory of past crossing events. Since these phase detectors are
controlled by the signal transitions, missing or extra edges
disturb their operation. In general, they are more sensitive to
noise then multiplier-type phase detectors.

vd(t)

2
Figure 30. The average output voltage of the exclusive-OR (solid
line) and edge-triggered RS flip-flop (dashed line) if they are used as
phase detectors. The linear phase regions are marked.

Multiplier-Type Phase Detectors

Four-Quadrant Analog Multiplier. Four-quadrant analog
multipliers can be used as multiplier-type phase detectors
(10). Assume that the PD inputs are sine and cosine waveforms. Then the output of the four-quadrant analog multiplier
can be expressed as
vd = AKd [sin e + sin(20t + e )]

(95)

where 0 is the frequency of two inputs, Vo Kd, A and Vo

denote the RMS amplitude of the input signals.
Equation (95) shows the disadvantages of the circuit. In
addition to the phase error, the PD output also depends on
the amplitudes of the input signals. This means that the
steady-state phase error ss, the stability, and every closedloop parameter vary with A. Furthermore, an unwanted sinusoidal signal at the second harmonic of the input frequency
also appears at the output of the PD, with an amplitude equal
to the maximum available dc output. This sinusoidal signal
results in unwanted FM at the VCO output.
On the other hand, analog multipliers can be used at very
low values of input SNR. This is why they are almost exclusively used in coherent demodulators and suppressed carrier
recovery circuits.
Balanced Mixers. Balanced mixers offer another possible
implementation of multiplier-type phase detector, which can
operate at extremely high frequencies. Monolithic integrated
circuits and extremely wideband diode rings can be used even
in the microwave frequency region (10). These circuits are
also multipliers, where the VCO signal (also called the local
signal) drives the transistors or diodes into saturation, that
is, they operate in switching mode. For the other input, also
called the received signal, the balanced mixer is linear.
The advantages and disadvantages of balanced mixers and
analog multipliers are the same. The only difference is caused
by the high level of local signal. Balanced mixers have a socalled local leakage, that is, in addition to the sum-frequency
component, the input frequency component also appears at
the output of the PD.
Exclusive-OR Gate. The exclusive-OR gate can be considered as a digital implementation of a balanced mixer. The
balanced mixer operates as an exclusive-OR gate when it is
driven by rectangular waveforms of appropriate amplitude.
The output of an exclusive-OR gate is a square wave,
whose duty cycle depends on the phase error. The average
value of this square wave is taken to be the PD output.

If both inputs have a 50% duty cycle, then the phase detector has a triangular characteristic, as shown in Fig. 30, where
the average value of the gate output is plotted against the
phase error. The harmonic content of output and the PD characteristic for other duty cycles are given in (39).
The exclusive-OR gate must be driven by standard digital
signals, which are not usually available in communications
receivers. The high level of periodic output prohibits their use
in high-quality frequency synthesis. They are used in digital
environments and narrowband loops, particularly when the
unwanted output sidebands can be tolerated. They are often
used in frequency synthesis, not as the phase detector but as
a lock indicator.
High-Speed Sampler. The high-speed sampler is commonly
used in frequency synthesis to lock a VCO to an integer multiple of a reference frequency. The high-speed sampler is basically a single-balanced mixer, driven by a narrow pulse on
the local input (39). The sampling signal, that is, the stream
of narrow pulses, is generated by a step-recovery diode from
the reference frequency. For the sampling signal the mixer is
balanced. During a pulse, the two diodes of the sampling gate
conduct and charge the output capacitors.
The phase detection capability of the high-speed sampler
can be understood easily in the frequency domain. Harmonics
of the reference frequency are generated by the step-recovery
diode and the appropriate harmonic of the reference signal is
multiplied by the VCO signal. The difference-frequency component is used as the PD output. The only difference between
the high-speed sampler and a harmonic mixer is that there
are two hold capacitors in the sampler that enhance the level
of the low-frequency PD output.
The main disadvantage of every phase detector, based on
sampling, is that any periodic disturbances or noise about any
harmonics of the reference, that is, the sampling frequency,
are translated to the low-frequency region. All of these signals
appear at the PD output as unwanted signals. It must be emphasized that the sampling process also folds a broadband
noise floor over many times, aliasing the noise from the vicinity of many harmonics of the sampling frequency to the lowfrequency region. This is why sampling-type PDs can be used
for reference signals with very high spectral purity; otherwise, a bandpass filter must preceed the PD, in order to reject
the unwanted signals.
Sequential Phase Detectors
Edge-Triggered Flip-Flop. The edge-triggered RS flip-flop
can be used as a sequential phase detector (39). The input

PHASE-LOCKED LOOPS

and VCO signals are connected to the S and R inputs of a

flip-flop, respectively. The PD output signal appears at the Q
output, which is a square wave; its average value is proportional to the phase difference between the S and R inputs.
This phase detector has a sawtooth characteristic, as shown
in Fig. 30.
The benefits of the edge-triggered RS flip-flop are: it offers
a simple and digital-compatible phase detector; furthermore
it has a 2-wide and linear phase range. The first disadvantage results from its edge-triggered operation; it cannot be
used in a noisy environment. The second drawback is that the
reference frequency is present in the spectrum of PD output.
Sample-and-Hold Phase Detector. Sample-and-hold phase
detectors are often used for frequency synthesis and in zerocrossing digital phase-locked loops (ZC-DPLL).
Frequency synthesizers have to produce signals with extremely high spectral purity. The phase detectors discussed
so far have a periodic output in their steady-state, which
causes unwanted sidebands at the PLL output. The unique
feature of the sample-and-hold phase detector is that its output is a pure dc signal under phase-locked condition.
The sample-and-hold PD shown in Fig. 31 is an edge-triggered circuit, that is, a sequential phase detector. Let f R denote the frequency of the reference signal. The first block generates the sampled signal vR(t), which is synchronized with
the reference signal. The sampled signal may have any shape;
assume that it has a sawtooth waveform in our case. Since
the PD is edge-triggered, this sawtooth waveform converts
the time interval between transitions of the reference and
sampling signals into a voltage. The sampling switch is closed
at the sampling time instants denoted by tk, k 0, 1, 2, . . .
and the voltage of the hold capacitor CH becomes equal to the
instantaneous value of the sampled signal. Note that the voltage vd(t) of the hold capacitor, which is the PD output, is linearly proportional to the time between transitions of the reference and sampling signals, that is, to the phase error. The
capacitor CH holds this voltage until the next sampling time
instant.
The sampling switch can be implemented by an integrated
CMOS or discrete FET switch. In both cases, the switch has
a series resistance which is modeled by RS in Fig. 31. Due to
RS, a finite sampling time is required to charge or discharge
the hold capacitor. The sampling switch is closed at the sampling time instant tk and remains closed during the sampling
time tS.
The sampled signal vR(t) and PD output vd(t) are plotted by
solid and dashed lines, respectively, in Fig. 32. When the
sampling switch is closed, the PD output voltage vd(t) varies
exponentially from its previous value to the new one. The
time constant RSCH of the sampling switch has to be much

Reference
signal
fR

TR

vR(t)

181

TR

vd(t)
Xk + 1
Xk 1

vR(t)
vd(t)

Xk
t
tS
Tk + 1
tk

tk + 1

Figure 32. Waveforms in the sample-and-hold phase detector.

less than the sampling time tS. Note that the sampled signal
is kept constant during the finite sampling time tS. This must
be done in order to avoid the appearance of a periodic signal
at the PD output in steady-state.
Figure 33 shows the waveforms of sample-and-hold phase
detector in steady-state. Since the sampled signal (solid line)
is kept constant during the finite sampling time, the PD output (dashed line) becomes a pure dc voltage.
More details on the sample-and-hold phase detector and
its design are given in (38) and (39).
Phase-Frequency Detector with Charge Pump. Most of the
phase detectors discussed so far have two disadvantages:
1. Since they are not sensitive to the frequency error, their
pull-in time can be extremely long.
2. Apart from the sample-and-hold phase detector, they
have a periodic steady-state output.
The phase-frequency detector provides a signal that is sensitive to the frequency error during acquisition and operates
as a phase detector under phase-locked condition. As shown
in Fig. 34, it contains a logic circuit (the phase-frequency detector) and a charge pump circuit, implemented by controlled
current sources IU and ID. The output of the phase detector is
a current id(t).
The edge-triggered phase-frequency detector is driven by
the reference and frequency-divided VCO signals s(t) and
vo(t), respectively. The logic circuit has two outputs; if one of
these is active, then the other output is disabled. If the di-

vR(t)
vd(t)

TR

TR

TR

t
Generation of
sampled signal

RS

tS

+
vR(t)

tS
CH

+
vd(t)

tk
Figure 31. Simplified circuit diagram of sample-and-hold phase detector.

tk

tk + 1

tk + 2

Figure 33. Steady-state waveforms in the sample-and-hold phase

detector. Note if the sampled signal vR(t) (solid line) is kept constant
during tS, then the PD output vd(t) (dashed line) becomes a pure dc
voltage.

182

PHASE-LOCKED LOOPS

the reference and divided VCO signals coincide with each

other. This means that the steady-state phase error is zero in
the charge pump PLL.
The final advantage of the phase-frequency detector is that
its linear phase region is 4.

IU
s(t)
R

R2

U
id(t)

Logic
circuit
F

+
vf (t)

ID

vo(t)
Phase-frequency
detector

Charge-pump

Figure 34. Simplified circuit diagram of phase-frequency detector

with charge pump circuit.

vided VCO frequency is greater than the reference frequency,

then the U output is active and the D output is zero. In the
opposite case, the U output becomes zero and the output signal appears at the D output. The current sources IU and ID
are controlled by the U and D outputs. Depending on the sign
of the frequency error, the PD output contains only positive
or negative current pulses. This behavior of the logic circuit
provides frequency detection capability for the phase detector.
The output of the logic circuit is a rectangular pulse, the
duration of which depends on the phase error. The input signals of the phase-frequency detector and the output current
of the charge pump circuit are shown in Fig. 35. The PD output current id(t) has the following properties:
The sign of current pulses is determined by the sign of
frequency error; and
The duration of current pulses is proportional to the
phase error.
The VCO control voltage is equal to the output voltage
vf (t) of the charge pump circuit. In steady-state, the VCO output frequency, and hence vf (t), becomes constant. It can be
achieved only if id(t) 0, that is, if both the U and D outputs
of the logic circuit become zero. It follows from the operation
of the phase-frequency detector that in this case the edges of

s(t)

TR

vo(t)
t
id(t)

The operation, baseband model, and analysis of analog PLLs

have been discussed earlier. The APLL contains only analog
loop components and its operation can be described by a pure
differential equation.
Continued progress in the production of digital integrated
circuits and the widespread use of digital signal processing
have resulted in strong interest in the implementation of
PLLs directly in the digital domain. Various implementations
of DPLLs contain only digital loop components, that is, their
operation can be modeled by a pure difference equation.
In other applications, the circuit configuration requires the
use of edge-triggered or digital loop components (e.g., frequency synthesis), or they are used to achieve the best PLL
performance (e.g., sample-and-hold phase detector). These
PLLs are called hybrid phase-locked loops and their operation
can be described by an integro-difference equation.
PLLs are categorized into three basic classes in the literature (14):
1. analog;
2. digital; and
3. hybrid
phase-locked loops. The most important characteristics of
PLLs are summarized in Table 4. Sampling and charge pump
PLLs belong to the class of hybrid phase-locked loops.
In contrast with the APLL, a general theory does not exist
for these circuits. As typical examples, we will discuss the
operation of the ZC-DPLL, SPLL and charge pump PLL is
this section.
Digital Phase-Locked Loops
Various circuit configurations have been proposed by different
authors for the implementation of the DPLL concept. Lindsey
and Chie (48) have grouped the implementations into four
classes, according to the operation of their phase detectors:

TR
t

IU

OTHER PLL CONFIGURATIONS

ID
Figure 35. Input signals of the phase-frequency detector and output
current of the charge pump circuit.

1. Flip-Flop (FF)-DPLL, in which a positive zero-crossing

of the input signal sets a flip-flop circuit and the local
clock resets it. The phase error is derived from the
elapsed time between the set and reset time instants.
2. Nyquist Rate (NR)-DPLL, in which the input signal is
sampled at the Nyquist rate.
3. Lead/Lag (LL)-DPLL, in which the PD determines at
each cycle, whether the input leads or lags the local
clock signal.
4. Zero crossing (ZC)-DPLL, in which the loop tracks the
zero crossings of the incoming sinusoidal signal.
In this section, as an example, only the theory of ZC-DPLL
is surveyed. This DPLL configuration is the easiest to model

PHASE-LOCKED LOOPS

183

Table 4. Most Important Characteristics of Phase-Locked Loops

Type of PLL
APLL
ZC-DPLL
SPLL
Charge-pump PLL

PD

Loop Filter

VCO

Loop Equation

Analog multiplier
Ideal sampler
Sample-and-hold
Phase-frequency detector with charge pump

Analog
Digital
Analog
Analog

Analog
Digital
Analog
Analog

Pure differential
Pure difference
Integro-difference
Integro-difference

The hybrid PLL comprises the SPLL and charge pump PLL.

and analyze; however, its operation is indicative of the general behavior of any DPLL.
The block diagram of ZC-DPLL proposed by Natali (49) is
shown in Fig. 36. In the following equations, the time variable
t is again suppressed for conciseness, where it does not cause
misunderstanding.
Let the incoming signal be
s(t) =

2A sin(R t + i )

(96)

where R is the center frequency, that is, the carrier frequency of s(t), and i(t) denotes the input phase modulation.
The incoming signal is corrupted by bandpass filtered
Gaussian white noise ni(t). The signal s(t) ni(t) is sampled
by an ideal sampler (i.e., RS tS 0) at the sampling time
instants tk, k 0, 1, 2, . . ., the samples are held by CH and
converted to a digital signal xk by an analog-to-digital converter (ADC). The incoming signal, sampling time instants
and output of the ADC are plotted in Fig. 37 for the noisefree case.
In order to express the phase error, the sampling time instants determined by the digital clock have to be mapped to
the phase of an equivalent sinusoidal signal. Let tk be assigned by the positive zero-crossings of the equivalent sinusoidal signal characterized by its phase Rt o(t). Then the
positive zero-crossings
R tk + o (tk ) = R tk + ok = 2k

(97)

yk = D(z) xk = D(z)( 2A sin ek + nik )

(100)

The time elapsed between the (k 1)th and kth samples

is denoted by
Tk = tk tk1 ,

k = 1, 2, 3, . . .

(101)

and the output of the digital filter is used to control the next
period of a digital clock, according to the algorithm

Tk = T yk1 = T z1 D(z)( 2A sin ek + nik )

(102)

In Eq. (102), T is the nominal clock period that can be M/f R,

M 1, 2, 3, . . .. For M 1, the ZC-DPLL takes samples at
every positive zero crossing of the incoming signal, while
M 1 indicates subharmonic locking.
Let f o denote the PLL output frequency. Subharmonic locking, that is, f o f R /M, M 2, 3, 4, . . . may occur in every
PLL where a sampling phase detector is used. Subharmonic
locking means that the PD takes one sample at every Mth
period of s(t). For the sake of simplicity, it will be assumed
that M 1 in this section.
The difference between the kth and (k 1)th phase error
samples is
ek ek1 = ik ik1 (ok ok1 )

that is, the sampling time instants, can be expressed as

tk =

where ek ik ok is the phase error. The output of the

digital loop filter is

(103)

similarly, from Eq. (97) one may get

2k ok
R

(98)

ok ok1 = 2 R (tk tk1 ) = 2 R Tk

(104)

where o0 0 and k 0, 1, 2, . . .. Knowing the sampling

time instants, one may express the output of the ADC as
xk =

2A sin(R tk + ik ) + nik = 2A sin ek + nik

s(t)
TR

(99)

x0

x1

x2
t

ni(t)
+

TR

xk

+
ADC

s(t)

yk
D(z)

Digital
clock

CH

fR
tk

Figure 36. Block diagram of the ZC-DPLL.

f0 =

fR
M

e0 = i0

e1

T1
t0 = 0

e2
T2

t1

t2

Figure 37. Waveforms of a ZC-DPLL in absence of noise.

184

PHASE-LOCKED LOOPS
nik

ik

ek

2 Asin( )

+
D(z)

yk

1
R z
1 z1

to xk. In the time interval (tk tS, tk1) the sampling switch is
open, that is, vd(t) xk.
Here only the course and milestones of SPLL analysis are
discussed. The equations will be given only for the simplest
case, when F(s) A0. The details of SPLL theory and many
design equations can be found in (53).
The development of a baseband model for the SPLL can be
divided into three main steps:
1. First, the synchronization of vR(t) with the noisy reference signal has to be modeled.

Figure 38. Nonlinear baseband model of ZC-DPLL.

2. Then, the next sampling time instant tk1 has to be determined.

If M 1, then T 2/R. Using the unit delay operator
z1 and substituting Eq. (102) into Eq. (104) and the result
into Eq. (103), one gets the loop equation
ek = ik + R

z1
D(z)( 2A sin ek + nik )
1
1z

(105)

which is a nonlinear stochastic difference equation.

In Eq. (105), the unit delay operator appears. Sometimes
it is claimed that the z-transform can be used only in case of
uniform sampling. Here is used the definition of z1 given in
(50), which is valid for arbitrary time sequences. In the ZCDPLL and SPLL (see next section), the sampling time instants are varied; this is how the feedback is used to control
the operation of the loop.
From Eq. (105), a nonlinear baseband model of the ZCDPLL can be constructed. The model is shown in Fig. 38,
where Rz1 /(1 z1) denotes the transfer function of digital
clock. Note that the baseband models of the analog (see Fig.
3) and digital PLLs are structurally equivalent.
Linear and nonlinear theories of DPLLs are surveyed in
(48); the stability of the ZC-DPLL is analyzed in (51) and (52).
Interested readers are referred to these papers.
Sampling Phase-Locked Loop
A block diagram of the SPLL is shown in Fig. 39. The sinusoidal reference signal s(t) corrupted by noise ni(t) synchronizes
a sawtooth waveform in the phase detector. The sampled signal vR(t) is kept constant during the finite sampling time tS,
as shown in Fig. 32. The PD output vd(t) is an analog signal
that is processed by an analog loop filter F(s). The instantaneous VCO frequency is controlled by vc(t) and is divided by a
frequency divider; the division ratio is N. The sampling time
instants tk are determined by the frequency divider output.
The waveforms of the sample-and-hold phase detector are
shown in Fig. 32. Let xk denote the value of the sampled signal at tk and assume that RSCH tS. While the sampling
switch is closed, the PD output voltage vd(t) varies from xk1

3. Finally, all signals have to be generated in the continuous-time domain.

Let R, R0 and R(t) denote the frequency, phase, and
phase modulation of the reference signal
s(t) =

2VR sin[R t + R0 + R (t)]

(106)

The synchronization of vR(t) is edge-triggered, that is, a new

voltage ramp is started when the noisy reference signal becomes zero. Thus,
s(tn ) + ni (tn ) = 0

(107)

where tn, n 0, 1, 2, . . . denotes the starting time instants

of voltage ramps. In the general case, the synchronization and
sampling are independent of each other. Note that the value
of the sampled signal at tk depends on two variables n and k,
where n describes the synchronization, while k appears due
to sampling. A baseband model for the general case cannot
be developed.
Because of sampling, subharmonic locking is also possible.
Assume that one sample is taken in every Mth reference period, that is, the output frequency is
fo =

N
f
M R

(108)

It has been shown in (53) that if cycle slip does not occur,
then one may write
n = Mk

(109)

and the independent variable n can be canceled from the

equations. Then the sampled signal at tk can be expressed as
xk = vR (tk ) = g(ek )

(110)

ni(t)
s(t)
fR

Figure 39. Block diagram of SPLL. A frequency divider with a division ratio of N
has been placed in the feedback path.

Generation of
sampled signal

vR(t) Rs

tS

vd(t)

F(s)

CH
tk

1
N

vc(t)

VCO

fo =

N
f
M R

PHASE-LOCKED LOOPS

where the nonlinear periodic function g( ) describes the

shape of sampled signal and ek is the phase error
ek = Rk

N ok

The determination of tk1 requires the solution of the integrodifference equation given by Eq. (114).
Equation (114) cannot be solved in closed form, it must be
separated into a pure difference and a pure differential equation. Kolumban has shown that this separation can be performed in three cases (53):

(111)

In Eq. (111), ok is the output phase modulation and the

equivalent input phase modulation Rk involves the effects of
both noise and phase modulation of the reference signal

1. If the dominant time constant of the open loop transfer

function is much less than tS;
2. If the dominant time constant of the open loop transfer
function is much greater than Tk; and
3. If the SPLL remains in the neighborhood of equilibrium
during the operation.





1

Rk = R0 + R kMTR R0 +
ni kMTR R0
R
R
2VR
(112)
Let Tk1 tk1 tk denote the time between two adjacent
sampling time instants. Then following the method shown
earlier for the ZC-DPLL, one may express the phase error as
ek = Rk R

z1
(MTR Tk+1 )
1 z1

Fortunately, at least one of these conditions is almost always

valid in practice.
For example, consider the case when the loop filter is omitted, that is, F(s) A0. In this case, the dominant time constant is RSCH, which is much less than tS. The elapsed time
between two adjacent sampling time instants can be expressed as

(113)

The main difference between the ZC-DPLL and SPLL circuits

is in the signal processing technique by which the next sampling time instant tk1 is determined. In the SPLL, the PD
output is an analog voltage and is processed by the analog
loop filter and VCO circuits.
Note that the time interval Tk1 can be divided into two
distinct periods; from tk to tk tS the sampling switch is
closed, while from tk tS to tk1 the sampling switch is open.
This means that the topology of the SPLL is changed at tk
and tk tS. Since the VCO output is a sinusoidal signal and
the frequency divider is edge-triggered, the variation in the
VCO phase is 2N between tk and tk1. Let 0 denote the VCO
center frequency. Then the variation in the VCO phase can
be expressed as

t k+1

tk

[0 + Kv vc (t)] dt = 0 Tk+1 + K v

t k+1

t k +t s

Discrete-time domain

t k +t s

Tk+1 =

(114)

vc (t) dt 2N

RS

vd(t)

A0

(115)

0
Kv

Continuous-time domain

Zero-order
hold circuit

2N + A0 K v (xk xk1 )RSCH

0 + A 0 K v xk

The outputs of the SPLL are analog signals. Equations

(113) and (110) give the sampled signal at the sampling time
instants only; the analog signals have to be expressed in
terms of xk. It has been shown in (53) that the PD output
voltage vd(t) can be generated from xk by means of a zero-order
hold circuit and an RC low-pass filter as shown in Fig. 40. It
must be emphasized that the sampling is not uniform in the
SPLL, that is, the hold time of the zero-order hold circuit varies during its operation.
The nonlinear baseband model of the SPLL can be constructed from Eqs. (113) and (110). Then the discrete-time
signal xk is converted to the continuous-time domain by a
zero-order hold circuit as shown in Fig. 40. The time interval
Tk1 can be calculated from Eq. (115) if the loop filter is omitted. Expressions for Tk1 for other loop configurations can be
found in (53).

vc (t) dt

tk

185

vc(t)

Kv
s

o(t)

CH

MTR

rk +

ek

g( )

xk

Tk + 1()

N
M

Tk + 1

N R z1
M 1 z1

ok

Figure 40. Nonlinear baseband model of

SPLL. The dashed line separates the discrete- and continuous-time domains.

186

PHASE-LOCKED LOOPS

SPLLs are used primarily in frequency synthesis, because

they offer excellent spectral purity. Due to their discrete-time
operation, the frequency switching time can be minimized if
all poles of closed-loop transfer function are placed as close to
the origin in the z-plane as possible (54). The SPLL can be
also used as an FM or PM modulator (55). This section has
shown only the main steps of SPLL analysis; a complete analysis in the frequency domain is given in (40). The SPLL is
especially suited to applications where a very simple highperformance synthesizer is required (56).
Charge-Pump Phase-Locked Loop
Charge pump PLLs are widely used for frequency synthesis,
since
their phase-frequency detector is sensitive to both phase
and frequency errors; and
they are available as cheap integrated circuits.
The block diagram of a charge pump PLL is shown in Fig.
41. The operation of the phase-frequency detector has been
discussed earlier. The PD output id(t) charges or discharges
the capacitor C. The resistor R2 introduces a zero into the
open-loop transfer function, that is, it ensures the stability of
the loop. Charge pump PLLs are widely used in frequency
synthesis, normally with a frequency divider with division ratio N in the feedback path.
Depending on the phase and/or frequency error, id(t)
charges or discharges C. The VCO control voltage vc(t) is determined by the capacitor voltage. If the reference signal is
unmodulated, then, in steady-state, vc(t) is a dc voltage, that
is, the charge stored on C should be constant. This will happen only if id(t) 0, that is, current pulses do not appear at
the PD output in steady-state. Fortunately, if there are no
current pulses at the PD output in steady-state, then unwanted FM does not appear at the PLL output.
The charge pump PLL contains both edge-triggered and
analog circuits, just like the SPLL. By contrast, a baseband
model for the charge pump PLL has not yet been published.
Gardner has developed a system of nonlinear difference equations in (26), which can be solved numerically to determine
the transient response of the loop. The equations have been
linearized, in order to perform the stability analysis of the
loop. However, the signals can be calculated only in the dis-

IU
fR

U
Phasefrequency
detector
F
D

R2

id(t)

vc(t)

VCO

fo = NfR

ID
1
N
Figure 41. Block diagram of a charge pump phase-locked loop.

crete-time domain; their functions are not expressed in the

continuous-time domain.
Gardner has determined the transient response, using
both the continuous-time approximations, that is, the APLL
model, and the exact nonlinear difference equations. By comparing the results, he has shown that if the reference frequency f R exceeds ten times the closed loop bandwidth, then
the continuous-time approximation can be used in circuit design (26).
The primary disadvantage of the charge pump PLL, and
the reason why it is not suitable for high-quality frequency
synthesis, is the so-called crossover distortion (39). This
means that, compared with its nominal value, the PD gain
varies from 20 dB to 10 dB if the phase error is reduced
below a certain value. This effect appears, due to an internal
logic race condition in the digital part of the phase-frequency
detector. To avoid instability problems, the phase error has to
be pushed out of this region, generally a 1 M resistor is connected in parallel with the series R2 C circuit. However, this
means that the phase error is greater than zero in steadystate, and an unwanted FM appears at the output of every
built charge pump PLL.
To exploit the excellent frequency acquisition property of
the phase-frequency detector and the high spectral purity offered by the sample-and-hold PD, both phase detectors are
implemented on the same integrated circuit. The phasefrequency detector operates during the frequency pull-in and,
if the phase error goes below a certain threshold, then the
phase-frequency detector is switched off and the sample-andhold PD is used. In this way, the performance of a frequency
synthesizer can be optimized during both the pull-in transient
and in steady-state.

CLOSING REMARKS
The goal of this article was to survey the theory and most
important applications of phase-locked loops. The main emphasis was put on the APLL theory, because it is the simplest
to understand and it is the basis of every other PLL analysis.
While the APLL theory has been very well established, the
theory of the digital and hybrid PLLs is subject to continuous
development. For example, the effect of quantization that appears in DPLLs was neglected in this article. Gardner has
shown that the quantizing nonlinearity leads to a limit cycle
under the phase-locked condition (57).
A new model which can describe the transient behavior of
the charge pump PLL even if it is not locked has been developed in (58).
Clock generation and distribution is a very important problem in high performance microelectronics. This question is
discussed in (59,60).
The clock recovery circuit is one of the key elements of digital data communication equipment. It is hard to find the optimum trade-off between acquisition, tracking, and noise properties. A systematic design and optimization procedure has
been proposed in (61).
Last but not least it must be emphasized that another article in this encyclopedia has been devoted to the latest results
on applications of PLLs.

PHASE-LOCKED LOOPS

BIBLIOGRAPHY
1. E. V. Appleton, Automatic synchronization of triode oscillators,
part III. Proc. Cambridge Phil. Soc., 21: 231, 19221923.
2. A. V. Balakrishnan, Advances in Communication Systems, New
York: Academic Press, 1965.
3. A. J. Viterbi, Principles of Coherent Communication, New York:
McGraw-Hill, 1966.
4. J. J. Stiffler, Theory of Synchronous Communication, Englewood
Cliffs, NJ: Prentice-Hall, 1971.
5. J. Klapper and J. T. Frankle, Phase-Locked and Frequency-Feedback Systems, New York: Academic Press, 1972.
6. W. C. Lindsey, Synchronization Systems in Communications, Englewood Cliffs, NJ: Prentice-Hall, 1972.
7. W. C. Lindsey and M. K. Simon, Telecommunication Systems Engineering, Englewood Cliffs, NJ: Prentice-Hall, 1973.
8. A. Blanchard, Phase-Locked Loops, New York: Wiley, 1976.
9. W. C. Lindsey and M. K. Simon (eds.), Phase-Locked Loops and
Their Applications, New York: IEEE Press, 1978.
10. F. M. Gardner, Phaselock Techniques, New York: Wiley, 1979.
11. W. C. Lindsey and C. M. Chie (eds.), Phase-Locked Loops, New
York: IEEE Press, 1986.
12. F. M. Gardner and W. C. Lindsey, Special issue on synchronization, part I, IEEE Trans. Commun., COM-28: 11051388, 1980.
13. W. C. Lindsey and C. M. Chie, et al., Special issue on synchronization, IEEE Trans. Comm., COM-30: 22212411, 1982.
14. S. C. Gupta, Phase-locked loops, Proc. of the IEEE, 63: 291306,
1975.
15. S. Haykin, Communication Systems, 3rd ed., New York: Wiley,
1994.
16. D. Richman, Color carrier reference phase synchronization accuracy in NTSC color television, Proc. IRE, 42: 106133, 1954.
17. F. M. Gardner, Hangup in phase-locked loops, IEEE Trans.
Comm., COM-25: 12101214, 1977.
18. G. Hedin et al., Theory of false lock in Costas loops, IEEE Trans.
Comm., COM-26: 112, 1978.
19. S. T. Kleinberg and H. Chang, Sideband false-lock performance
of squaring, fourth-power, and quadriphase Costas loops for NRZ
signals, IEEE Trans. Comm., COM-28: 13351342, 1980.
20. I. Frigyes, Z. Szabo, and P. Vanyai, Digital Microwave Transmission, Amsterdam: Elsevier Science, 1989.
21. V. I. Tikhonov, The effect of noise on phase-locked oscillator operation, Automation Remote Control, 20: 11601168, 1959.
22. V. I. Tikhonov, Phase-lock automatic frequency control, Automation Remote Control, 21: 209214, 1960.
23. A. J. Viterbi, Phase-locked loop dynamics in the presence of noise
by FokkerPlanck techniques, Proc. IEEE, 51: 17371753, 1975.
24. G. Aschied and H. Meyr, Cycle slips in phase-locked loops: a tutorial survey, IEEE Trans. Comm., COM-30: 22282241, 1982.
25. D. Ryter and H. Meyr, Theory of phase tracking system of arbitrary order: Statistic of cycle slips and probability distribution of
the state vector, IEEE Trans. Inform. Theory, IT-24: 17, 1978.
26. F. M. Gardner, Charge-pump phase-lock loops, IEEE Trans.
Comm., COM-28: 18491858, 1980.
27. G. Kolumban and B. Vizvari, Nonlinear dynamics and chaotic
behavior of the analog phase-locked loop, Proc. NDES, 1995, pp.
99102.
28. G. Kolumban and B. Vizvari, Nonlinear dynamics and chaotic
behavior of the sampling phase-locked loop, IEEE Trans. Circuits
Syst., CAS-41: 333337, 1994.
29. G. M. Bernstien and M. A. Lieberman, Secure random number
generation using chaotic circuits, IEEE Trans. Circuits Syst.,
CAS-37: 11571164, 1990.

187

30. B. Vizvari and G. Kolumban, Quality evaluation of random numbers generated by chaotic sampling phase-locked loops, IEEE
Trans. Circuits Syst., CAS-45: 216224, 1998.
31. G. Kolumban, M. P. Kennedy, and L. O. Chua, The role of synchronization in digital communications using chaospart I: Fundamentals of digital communications, IEEE Trans. Circuits Syst.,
CAS-44: 927936, 1997.
32. H. J. Blinchikoof and G. R. Vaughan, All-pole phase-locked
tracking filters, IEEE Trans. Commun., COM-30: 23122318,
1982.
33. P. H. Lewis and W. E. Weingarten, A comparison of second-,
third-, and fourth-order phase-locked loops, IEEE Trans. Aerosp.
Electron. Syst., AES-3: 720727, 1967.
34. J. A. Develet, The influence of time delay on second-order phase
lock loop acquisition range, Proc. Int. Telem. Conf., London, 1963,
pp. 432437.
35. J. P. McGeehan and J. P. H. Sladen, Elimination of false-locking
in long loop phase-locked receivers, IEEE Trans. Commun.,
COM-30: 23912397, 1982.
36. U. L. Rohde, Digital PLL Frequency Synthesizers, Theory and Design, Englewood Cliffs, NJ: Prentice-Hall, 1983.
37. V. F. Kroupa, Frequency Synthesizers, Theory, Design and Applications, New York: Wiley, 1973.
38. V. Manassewitsch, Frequency Synthesizers, Theory and Design,
New York: Wiley, 1980.
39. W. F. Egan, Frequency Synthesis by Phase Lock, New York: Wiley, 1981.
40. G. Kolumban, Frequency domain analysis of sampling phaselocked loops, Proc. IEEE-ISCAS88, Helsinki-Espoo, June 1988,
pp. 611614.
41. M. Moeneclaey, Linear phase-locked loop theory for cyclostationary input disturbances, IEEE Trans. Commun., COM-30: 2253
2259, 1982.
42. C. L. Weber and W. K. Alem, Demod-remod coherent tracking
receiver for QPSK and SQPSK, IEEE Trans. Commun., COM-28:
19451954, 1980.
43. W. R. Braun and W. C. Lindsey, Carrier synchronization techniques for unbalanced QPSK signals, parts III, IEEE Trans.
Commun., COM-26: 13251341, 1978.
44. R. D. McCallister and M. K. Simon, Cross-spectrum symbol synchronization, Proc. ICC81, 1981, pp. 34.3.134.3.6.
45. J. K. Holmes, Tracking performance of the filter and square bit
synchronizer, IEEE Trans. Commun., COM-28: 11541158, 1980.
46. H. L. Van Trees, Detection, Estimation and Modulation Theory,
Part I, New York: Wiley, 1968.
47. M. K. Simon, Nonlinear analysis of an absolute value type of
early-late-gate bit synchronizer, IEEE Trans. Commun., COM18: 589596, 1970.
48. W. C. Lindsey and C. M. Chie, A survey of digital phase-locked
loops, Proc. IEEE, 69: 410431, 1981.
49. F. D. Natali, Accurate digital detection of angle modulated signals, Proc. EASCON Rec., 1968, pp. 407412.
50. A. V. Oppenheim and R. W. Shafer, Digital Signal Processing,
Englewood Cliffs, NJ: Prentice-Hall, 1975.
51. H. C. Osborne, Stability analysis of an Nth power digital phaselocked looppart I: First-order DPLL, IEEE Trans. Commun.,
COM-28: 13431354, 1980.
52. H. C. Osborne, Stability analysis of an Nth power digital phaselocked looppart II: Second- and third-order DPLLs, IEEE
Trans. Commun., COM-28: 13551364, 1980.
53. G. Kolumban, Design of sampling phase-locked loops: model and
analysis, C.Sc. Thesis, Budapest: Hungarian Academy Sci., 1989.
54. G. Kolumban, A fast frequency synthesizer for microwave radio.
In Proc. EuMC, pp. 180185, 1986.

188

PHASE METERS

55. G. Kolumban, Phase modulation by sampling phase-locked loop.

In Proc. URSI-ISSSE, pp. 9396, 1989.
56. G. Kolumban, A simple frequency synthesizer configuration for
low-capacity digital microwave radio links. In Proc. EuMC, pp.
14531458, 1991.
57. F. M. Gardner, Frequency granularity in digital phaselock loops,
IEEE Trans. Commun., COM-44: 749758, 1996.
58. M. V. Paemel, Analysis of a charge-pump PPL: A new model,
IEEE Trans. Commun., COM-42: 24902498, 1994.
59. D. K. Jeong et al., Design of PLL-based clock generation, IEEE
J. Solid-State Circuits, SC-16: 255261, 1987.
60. I. A. Young, J. K. Greason, and K. L. Wong, PLL clock generator
with 5 to 110 MHz of lock range for microprocessors, IEEE J.
Solid-State Circuits, SC-27: 15991607, 1992.
61. R. S. Co and J. H. Mulligan, Optimization of phase-locked loop
performance in data recovery systems, IEEE J. Solid-State Circuits, SC-29: 10221034, 1994.

GEZA KOLUMBAN
Technical University of Budapest

See also FREQUENCY SYNTHESIZERS.

166

OPERATIONAL AMPLIFIERS

OPERATIONAL AMPLIFIERS
The operational amplifier, or op amp, is a particularly useful
building block for electronic circuits. Although composed of
numerous other devices, an op amp is usually treated as a
single circuit element, commonly called the ideal op amp. By
considering the op amp as an ideal circuit element, it is possible to analyze and design many useful circuits quickly. Once
an op-amp circuit has been designed, the practical limitations
of real op amps should be considered. In most cases, the limitations of practical op amps can be compensated for. When
designing an op amp, the particular application and the type
of devices used to implement the op amp should be closely
considered.

THE IDEAL OP AMP

The ideal op amp has a differential input to an ideal voltage
amplifier that has infinite gain and a single-ended output.
While an infinite gain is somewhat impractical, op amps are
rarely used alone. Instead, op amps are used with external
circuitry connected between their output and input to set the
circuits overall characteristics. Since it is an ideal voltage
amplifier, the op amps input impedance is infinite. Hence,
the op amp does not draw any current from the circuitry connected to its input. Also, since it is an ideal voltage amplifier,
the ideal op amps output impedance is zero. Hence, the op
amps output voltage is unaffected by its output current. The
ideal op amps equivalent circuit and its symbol are shown in
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

OPERATIONAL AMPLIFIERS

v i

v+i

167

nal in Fig. 1. In addition, the op amps gain A fixes the relationship between vx and vo:
vo

vx =
(a)

vo
A

(2)

Combining Eqs. (1) and (2) yields the closed-loop gain

v i

R2 /R1
vo
=
vi
1 + (1 + R2 /R1 )/A

vo

v+i

+
+

(3)

where A is, by constrast, called the open-loop gain. For an

ideal op amp, A is infinite so Eq. (3) reduces to

Avd
A

R
vo
= 2
vi
R1

(b)
Figure 1. The ideal op amp: (a) symbol for an ideal op amp; (b)
equivalent circuit.

Fig. 1. The terminals marked and are commonly referred

to as the inverting terminal and the noninverting terminal,
respectively. While practical op amps do not exhibit truly
ideal behavior, their performance is such that the ideal opamp model can be used to determine the behavior of most opamp circuits with satisfactory results.
Common Op-Amp Configurations
Op-amp circuits combine an op amp with some external components. The characteristics of the resulting op-amp circuit
are largely determined by the configuration of the external
components. While numerous configurations exist, the most
common of them are the inverting amplifier configuration and
the noninverting amplifier configuration.
The Inverting Amplifier Configuration. The inverting configuration is shown in Fig. 2. The circuits input-to-output relationship can be determined using straightforward circuit
analysis. Since the op amps input impedance is infinite it will
have 0 input current. Therefore, the current through R1
equals the current through R2:
vi vx
vx vo
=
R1
R2

(4)

The negative sign implies the output signal is inverted while

the ratio R2 : R1 determines the amplification. Note that the
gain is set by the ratio of the external components and is independent of the op amps gain.
An important observation in the preceding analysis is that
the voltage between the op amps input terminals approaches
0 as the op amps gain approaches infinity. This is due to the
negative feedback provided by R2. Provided the op amp has
sufficiently high gain, when negative feedback is used, the
voltage between the op amps input terminals approaches 0
for finite output voltages. This leads to the concept of a virtual
short, a situation in which two terminals have the same potential but no current flows between them. When one of the
two terminals in a virtual short is connected to ground, the
other is said to be a virtual ground. A virtual ground is a node
that is at ground potential but does not have any current
flowing directly to ground from it. An example of a virtual
ground is the inverting terminal of the inverting amplifier
configuration. The concept of a virtual short and a virtual
ground is very useful for analyzing ideal op-amp circuits.
In Fig. 3, a virtual ground exists at the op amps inverting
terminal. Consequently, the currents through Ra, Rb, and Rc
only depend on va, vb, and vc, respectively. These currents are
all summed at the op amps inverting terminal but cannot

(1)

where vi is the circuits input voltage, vo is the circuits output

voltage, and vx is the voltage at the op amps inverting termi-

va

Ra
ia = va / Ra
R2

i=

vx vo

vb

R2

R2

ib = vb / Rb

R1
vi

vx
i=

vi vx
R1

vc

vo

Figure 2. The inverting configuration.

Rb
ia + i b + ic

Rc

ic = vc / Rc

vo

Figure 3. Generating a weighted sum.

168

OPERATIONAL AMPLIFIERS

Cf

R1
vi

vo

vi

vo

Figure 6. A voltage follower or unity-gain buffer.

Figure 4. An inverting integrator.

flow into it. Therefore, the sum of the currents flows through
R2 to the output yielding an output voltage of
vo = R2

1
1
1
va +
v +
vc
Ra
Rb b Rc

vi
R1

(6)

This current then flows from the virtual ground through Cf .

The voltage across the capacitor is the integral of the current
through it and can be expressed as
vo
1
=
vi
R1Cf s

(7)

where s is the Laplace variable. Such a circuit is known as an

integrator and is commonly used in active filters.
For the inverting configuration, the presence of the virtual
ground at the op amps inverting input allows signals from
different sources to be combined. The external circuit elements can be passive or active components. Provided the resulting circuits are stable and the op amp has sufficiently
high gain, the overall transfer function is independent of the
op amp.
The Noninverting Amplifier Configuration. The noninverting
configuration is illustrated in Fig. 5. In this circuit the signal
is applied directly to the op amps noninverting terminal.

R1

vi

R
vo
=1+ 2
vi
R1

(8)

Once again the circuits gain is set by the external components, independent of the ideal op amp.
Unlike the inverting configuration, the noninverting configuration does not draw current from the signal source. For
the inverting configuration, the current drawn from vi is determined by R1. In the noninverting configuration, the signal
is applied directly to the op amps input terminal, which ideally has an infinite input impedance. Consequently the noninverting configuration does not load the signal source.
In cases where the signal voltage is large enough but the
signal source has a high output impedance, the noninverting
configuration can be used as a unity-gain buffer. By making
R2 0 and R1 infinite as shown in Fig. 6, the output tracks the
input due to the virtual short across the op amps input terminals. The virtual short forces the output to track the input
(i.e., vo vi), but no current is drawn from the signal source.
Instead, the op amp provides the load current. Due to its high
input impedance, the op amp is particularly attractive for
buffering applications.
APPLICATION ISSUES
Real op amps differ from the ideal op-amp model. These differences, commonly referred to as op-amp nonidealities, limit
the range of signals for which an op-amp circuit can be used.
In most applications the op amps nonidealities do not cause
significant problems. In cases where the op amps nonidealities do cause problems, circuit design precautions often can
be used to reduce the problems to acceptable levels. Alternatively, higher-performance op amps, which are typically more
expensive, can be used. It is important to be aware of the
op amps dominant nonidealities, and their effect on op-amp
circuits and techniques to compensate for their effects.
Finite Dc Gain

R2

vx

Since R2 and R1 provide negative feedback, a virtual short

exists between vi and vx. Therefore, the current through R1 is
vi /R1. Due to the op amps high input impedance, this current
also flows through R2, resulting in an overall gain from vi to
vo of

(5)

The virtual ground prevents the input signals from interacting with each other. Consequently, the circuits output is a
weighted sum of the three inputs.
By replacing the resistors with other components, the inverting configuration can be used to perform other operations
on the input signal (1,2). For example, if R2 in Fig. 2 is replaced with a feedback capacitor Cf , as shown in Fig. 4, an
integrator can be made. The input current due to the virtual
ground at the op amps inverting terminal is
i=

vo

Figure 5. The noninverting configuration.

Unlike the infinite gain of an ideal op amp, the dc gain of a

practical op amp is finite. Nevertheless, an op amps dc gain,
denoted by AO, is typically quite high. AO ranges from 40 dB
for high-speed op amps to 120 dB for precision op amps. A
general-purpose op amp typically has a gain of 100 dB. The
actual gain of an op amp is not a well-controlled parameter.
Consequently, manufacturers typically specify both a minimum and a typical value for AO.

OPERATIONAL AMPLIFIERS

The effect of an infinite AO is to reduce the closed-loop gain

of an op-amp circuit (13). If an op amp has a finite gain and
the output voltage is vo, there must be a nonzero voltage
across the op amps input terminals equal to vo /AO. Using this
relationship, the op amps finite gain reduces the closed-loop
gain of the inverting configuration to
R2 /R1
vo
=
vi
1 + (1 + R2 /R1 )/AO

169

vo
V+
L+
Vos

vd

(9)

A0
1

while for the noninverting configuration, the closed-loop gain

is reduced to
V

(10)

When AO is very large, Eqs. (9) and (10) reduce to Eq. (4) for
the inverting configuration and to Eq. (8) for the noninverting
configuration, respectively. When AO becomes comparable to
1 R2 /R1 a noticeable reduction in the closed-loop gain occurs. To ensure a well-controlled closed-loop gain, the minimum open-loop gain specified by the manufacturer must be
significantly larger than the desired closed-loop gain. As a result, the op amps finite dc gain limits the maximum gain that
can be obtained accurately in an op-amp circuit.
Saturation
Although op amps can be used to provide large gains, in practical op amps the maximum output voltage is limited. When
called upon to deliver output signals close to and beyond the
op amps supply voltage, the op amps output signal is limited
to a value determined by the op amps supplies and becomes
independent of the input signal. When the op amps output
has reached its maximum level, the op amp is said to be saturated.
Like any electronic amplifier, an op amp requires a power
supply. Most stand-alone op amps require a positive, V, and
a negative, V, power supply but no connection to ground.
Typically, V and V are of the same magnitude but of opposite polarity and range from 5 V to 18 V for general-purpose op amps. To meet the needs of specialized applications,
special-purpose op amps such as single-supply op amps, for
use with a single supply, low-voltage op amps, for supplies
below 5 V, and high-voltage op amps, for use with supplies
beyond 18 V, are commonly available.
Irrespective of the supply voltage, the op amps maximum
output voltage L and minimum output voltage L cannot exceed the supply. For most op amps, the output saturates
within 1 V to 3 V of the supply as illustrated in Fig. 7. In the
case of low-voltage and single-supply op amps, the output
swing often extends to the supply levels, yielding a rail-to-rail
output swing. Output signals beyond this range are clipped,
leading to distortion. To ensure that the output is not clipped
at L or L, the op-amp circuits input signal must be kept
suitably small.

Figure 7. The op amps dc input/output relationship.

nique known as compensation, controls the op amps frequency response such that the gain rolls off at a constant 20
dB/decade from AO to below 0 dB. The op amps frequency
response can be expressed as
A() =

AO
1 + j/b

(11)

where b 2f b and f b is the frequency of the op amps dominant pole. Unfortunately, f b is dependent on AO. Hence, this
formulation of the op amps frequency response is rarely used.
Unity-Gain Bandwidth
A more predictable and useful point is the frequency at which
the op amps gain falls to unity. This point is called the op
amps unity-gain bandwidth and is denoted by f t, as shown in
Fig. 8. Typical values of f t range from 1 MHz, for high-gain
op amps, to over 100 MHz, for high-speed, low-gain op amps.
Due to the op amps one dominant pole, the op amps bandwidth f b can be expressed as
f b = f t /AO

(12)

Since AO can be fairly large, the op amps bandwidth is typically fairly low. Based on the relationship in Eq. (12), the op
amps frequency response is commonly expressed as
A() =

AO
1 + j(AO /t )

(13)

A0
Slope = 20 dB/decade

20 log vo /vd

1 + R2 /R1
vo
=
vi
1 + (1 + R2 /R1 )/AO

Frequency Characteristic
The frequency characteristic of a compensated op amp is
shown in Fig. 8 (13). Due to the op amps internal capacitances, the op amps gain decreases with frequency. For most
general-purpose op amps, the manufacturer, through a tech-

0 dB

fb

ft
Frequency (log scale)

Figure 8. Frequency response of a compensated op amp.

170

OPERATIONAL AMPLIFIERS

where t 2f t.
To determine the high-frequency response of an op-amp
circuit such as the inverting configuration or the noninverting
configuration, the op amps high-frequency gain, as given by
Eq. (13), can be approximated by
A() t / j

R2
R1

vo

(14)
Vos

If Eq. (14) is used in place of AO in Eqs. (9) and (10),

(a)

vo
() =
vi

R2 /R1
j
1+
t /(1 + R2 /R1 )

(15)

Cf

Rf

is obtained for the inverting configuration and

vo
() =
vi

1 + R2 /R1
j
1+
t /(1 + R2 /R1 )

(16)

Ri
vi

vo

+
is obtained for the noninverting configuration. For both circuits, the closed-loop bandwidth is given by
clb =

t
1 + R2 /R1

(b)

(17)

where 1 R2 /R1 is commonly referred to as the feedback factor and is denoted by B. Based on Eqs. (15) and (16) it can be
seen that the bandwidth of an op-amp circuit is the op amps
unity-gain bandwidth divided by the feedback factor. Greater
feedback factors imply lower gains. Hence, the lower the desired gain, the wider the circuits bandwidth.
Slew Rate
Due to internal circuitry limitations, the output voltage of an
op amp cannot change instantaneously. The maximum rate
at which the op amps output voltage can change is called the
slew rate, SR:

dvo 
SR =
(18)
dt max
Slew rate is expressed using the units V/s. The primary effect of a finite slew rate is that the output and input of an opamp circuit are not linearly related while the op amp is slewing. Consequently, slewing causes distortion.
The maximum frequency at which an op amp can be used
without slew-rate distortion depends on the size of the output
signal. For a sine wave output with a peak amplitude of Va,
the output voltage will be vo Va sin(2ft) and its maximum
rate of change is 2f Va. To avoid slew-rate distortion, 2f Va
must be less than SR. Slew-rate distortion can be avoided either by keeping the signal frequency small or by keeping the
signal amplitude small. For a full-power signal, that is, a signal with a peak-to-peak amplitude of L L, the maximum
frequency for which an undistorted output can be obtained is
given by
f max

SR
=
(L+ L )

Vos

(19)

This frequency is called the op amps full-power bandwidth.

Figure 9. (a) The effects of the offset voltage on the inverting and
noninverting configurations. (b) Reducing the effects of an offset voltage on the inverting integrator.

Offset Voltages. Ideally, a zero differential input voltage to

an op amp will produce a zero output voltage. For a practical
op amp, a 0 differential input voltage typically produces an
output of either L or L, as shown in Fig. 7. To restore the
op amps output voltage to 0, a voltage defined as the input
referred offset voltage Vos must be applied between the input
terminals.
Vos arises from mismatches in the devices used in the op
amps input stage and circuit asymmetries (4). Since Vos depends on physical devices, it is subject to drift due to temperature changes and as the circuit ages. Nevertheless, Vos is quite
small. For a general-purpose op amp Vos is in the range of 0.1
mV to 10 mV. When a low Vos is required, precision op amps
are available with Vos in the microvolt range.
To model the effects of Vos, a voltage source equal to Vos but
of unknown polarity is connected to one input terminal of the
ideal op amp. Then, provided the op-amp circuit is linear, superposition can be used to determine the resulting output
voltage due to Vos and the circuits input voltage. To analyze
the effect of Vos on either the inverting or noninverting configurations, the circuit shown in Fig. 9(a) can be used. Note
that the op amp has been replaced with an ideal op amp with
Vos in series with its noninverting terminal and the input vi
has been set to 0. Note also that due to superposition, the
effect of the op amps Vos on both the inverting and noninverting configurations will be the same. The output due to
Vos acting alone is called the output offset and is found to be
vo = Vos (1 + R2 /R1 )

(20)

Clearly, if R2 /R1 is large, a large output offset will result. If a

high gain is required but dc gain is not, a capacitor can be
added in series with R1 to reduce the output offset to Vos.

OPERATIONAL AMPLIFIERS

One class of circuits that is particularly affected by the op

amps offset voltage is the inverting integrator shown in Fig.
4. Due to the presence of Vos, a dc current flows through R1
and is integrated on Cf , which causes the output to saturate
at either L or L. To avoid the problem, a feedback resistor,
Rf can be added as shown in Fig. 9(b). Rf limits the dc gain to
a finite value and therefore limits the output offset voltage.
When very small offsets are required, a number of solutions exist: The simplest solution is to use a low-offset op
amp. Alternatively, many op amps have connections for an
offset nulling network. In either case, the offset will still be
subject to drift due to temperature and aging. To reduce the
offset problem further, techniques such as autozeroing, correlated double sampling, and chopper stabilization can be employed (5).
Input Bias Currents. To operate properly, all op amps require an input current. These input currents arise from the
needs of the op amps input devices. If bipolar junction transistors (BJTs) are used, the input bias currents are the required base currents of the input devices. If field-effect transistors (FETs) form the input stage, the FETs gate leakage
currents give rise to the input bias currents. Since there is a
bias current for each input, the average of the two currents,
IB, and the difference or offset between the two currents, Ios,
are usually specified (2). As the op amps bias currents flow
through the external components, they cause input errors
similar to Vos and hence can be combined with Vos using superposition.
Common-Mode Rejection. Practical op amps display both a
differential gain and a common-mode gain. Since the op amp
has two input terminals, two types of input signals can be
defined: a differential signal vd, which is the difference between the two signals, vd vi vi, and a common-mode
signal, vc, which is their average, vc (vi vi)/2. An ideal
op amp does not respond to vc. For practical op amps, changing vc changes vo, which implies a common-mode gain Ac,
Ac = vo /vc

R2
R1
v1

vo

R1

v2
R2

Figure 10. The differential configuration.

For the purpose of circuit analysis, an alternate interpretation of the CMRR is the ratio of the change in Vos due to a
change in vc.
Vos
1
=
CMRR
vc

vo =

CMRR = A/Ac

(22)

At dc the CMRR is usually very large but decreases with increasing frequency. The dc CMRR is usually expressed in
decibels and ranges from 60 dB to 120 dB for most op amps.

(23)

The two interpretations of CMRR are equivalent.

The common-mode gain is only a problem in op-amp circuits for which a sizable vc is applied directly to the op amp.
Consequently, with a virtual ground at the op amps output,
the inverting configuration is unaffected by the common-mode
gain. For circuits such as the noninverting configuration and
for the differential configuration, shown in Fig. 10, a sizable
vc is present at the op-amp inputs. Hence, these circuits are
affected by the op amps common-mode rejection properties.
In particular, if the signal at the op amps noninverting terminal exceeds the op amps input common-mode range, the circuit ceases to amplify the input signal linearly.
Even within the specified input common-mode range, the
differential configuration will not function properly if the op
amps CMRR is too low. Ideally, a differential amplifier amplifies the difference between two signals. For the differential
configuration, the input and output are related by

(21)

Like the differential gain, the common-mode gain is a function of frequency. Typically, Ac is relatively small over a specified range, known as the op amps input common-mode range.
For input signals beyond the common mode range, Ac rises
rapidly and the op amp no longer functions properly. In most
cases an op amps input common-mode range does not extend
to either the positive or negative supply voltage. For singlesupply op amps, the input common-mode range typically does
extend to and often slightly beyond one supply. For very-lowvoltage op amps, the input common-mode range may extend
to both supply levels, yielding what is referred to as a rail-torail input range.
Within the common-mode range, Ac is usually specified in
terms of the common-mode rejection ratio, CMRR:

171

R2
(v v1 )
R1 2

(24)

The differential configuration amplifies the difference between the two input signals and rejects their common-mode
component. The effect of the op amps common-mode gain can
be determined as follows: Since the CMRR and the presence
of a common-mode signal vc at the op amps input effectively
give rise to a signal dependent Vos [see Eq. (23)], the resulting
Vos can be expressed as
Vos = vc /CMRR

(25)

Then, by assuming the op amp is ideal except for the finite

Vos given by Eq. (25), the effects of a nonzero vc and finite
CMRR can be calculated. For the differential configuration, a
finite CMRR changes the output from that given by Eq. (24)
to
vo =

R2
R
(v v1 ) + 2
R1 2
R1

v
2
CMRR

(26)

172

OPERATIONAL AMPLIFIERS

It can be seen that the output now depends on both the difference in the applied signals and on the value of v2. Since v2
contains both a differential and common-mode component,
the differential configurations performance will be degraded
if the op amps CMRR is too low.
Summary. The applications of op amps are limited by their
nonideal behavior. The op amps offset voltage and CMRR
limit the accuracy of op-amp circuits. The op amps finite gain
and saturation levels limit the maximum useful gain of an opamp circuit. The op amps frequency response and finite slew
rate limit the maximum frequencies for which the op amp
can be used. In most cases, special-purpose op amps or circuit
techniques can be used to reduce the degradation caused by
the op amps nonidealities.
IMPLEMENTATION ISSUES
An op amp can be implemented in many ways. Typically, an
op amp is a multistage design composed of a differential input
stage, one or more high-gain middle stages, and, if required,
a low-impedance output stage. While many different technologies can be used to implement op amps, currently they are
most commonly implemented using either bipolar devices
(3,6) or complementary metal oxide semiconductor (CMOS)
devices (3,4,7). A simplified schematic of a typical bipolar implementation of a three-stage op amp is illustrated in Fig. 11.
The input stage is a differential pair formed by the
matched devices Q1a and Q1b. This configuration inherently rejects common-mode signals while producing an output current
proportional to the differential input voltage, i gm1 vi. The
ratio of Q1as and Q1bs output current to the input voltage is
called the transconductance gm1. At this point, the voltage
gain is usually relatively small.
In the high-gain stages, the relatively small voltage swing
at the input stages output is amplified to yield a very high
voltage gain. For example, the output current of the first
stage in Fig. 11 is effectively multiplied by the current gain

Input
stage
V+

High-gain Output
stage
stage
V+
V+
Ibias

v i

Q1a

Q1b

Ibias

v+i

Q2a

vo

Q3

Q2b

Ibias
V

Avi

Cp

vo
RL

CL

Figure 12. A Thevenin equivalent circuit for the output of an op

amps high-gain stage.

of Q3, 3, to yield a current of i 3gm1vi. Provided the output

stage adequately buffers the load, this current reacts with the
output resistance of Q3, ro3, to yield a gain of
vo /vi = 3 gm1 ro3

(27)

While this gain can be fairly high, the output impedance of

the node is also very high.
To buffer this high-impedance node, a voltage follower, illustrated in Fig. 11 as an emitter follower (i.e., Q4), is used.
This last stage does not provide any voltage gain. Instead, it
reduces the op amps output resistance so that the op amps
gain is unaffected by the load.
The actual configuration and number of stages in an op
amp depends on many factors: the type of load, resistive or
capacitive, that is to be driven, the type of devices, bipolar or
CMOS, that is to be used to implement the op amp, and the
need for compensation, to ensure stability, should all be considered.
Resistive or Capacitive Loads
The type of load seen by the op amp, be it resistive or capacitive, determines the need for a buffering stage between the
output of the op amps high-gain stage and the load. The output of the high-gain stage can be modeled as a voltage source,
AVi, with a large output resistance Ro and a parasitic shunt
capacitance Cp, as shown in Fig. 12. Ro is typically very high
to yield a large voltage gain [see Eq. (27)]. Often Ro is in the
megaohm range. When a resistive load RL is connected directly to the output of the high-gain stages, the overall gain
will be reduced by the voltage divider formed by Ro and RL.
For a purely capacitive load CL, this load appears in parallel
with Cp and does not affect the dc gain. Consequently, for resistive loads a buffering stage is required on the op amps
output while for capacitive loads, a buffering stage is typically
not required.
Bipolar and CMOS Implementations

Q4

Cc

Ro

Figure 11. A simplified three-stage op amp.

Currently the two most common devices for implementing op

amps are bipolar devices (i.e., BJTs) and CMOS devices [i.e.,
metal oxide semiconductor FETs (MOSFETs)]. Both devices
have advantages and disadvantages that determine how they
are best used in the different stages of an op amp.
Input Differential Stage. The input stage converts the differential input voltage to a current. A number of factors are important in this stage:
Random input offset voltages are largely determined by
the matching of the input devices.

OPERATIONAL AMPLIFIERS

The base or gate currents of the input devices determines

the input bias currents.

V+

The input devices transconductance determines the input stages voltage-to-current gain and SR (6).
The bias current of the differential pair typically limits
the op amps slew rate.

V+

Ibias
v+i

v i
M1a

M1b

173

V+

M4a

M4b

M3a

M3b
vo

Generally, BJTs display better device-to-device matching

then MOSFETs. Therefore, BJTs are preferred for op amps
with low input referred offsets. Unfortunately, due to their
base currents, BJT input devices will require much larger input bias currents than MOSFET input devices. For a large
input transconductance, BJTs are preferred over MOSFETs.
The BJTs high transconductance also provides a relatively
high bandwidth for the input stage but, due to the BJTs high
transconductance-to-bias-current ratio, the slew rate will be
poor. To improve the slew rate compared to the input transconductance, either emitter degeneration with BJTs or MOSFETs with their lower transconductance-to-bias-current ratio
can be used. Since any necessary gain can be achieved in the
following stages, the primary difference between BJT and
MOSFET inputs is the tradeoff between the input offset voltage and the input bias currents.
High-Gain Stages. In an op amp it is desirable to achieve a
very high gain without introducing a large number of parasitic poles that make compensating the circuit difficult. In
practical terms, the gain should be achieved with as few
stages as possible and with as few high-impedance nodes as
possible.
For the BJT, with its large transconductance, it is often
possible to achieve the desired gain with two gain stages as
illustrated in Fig. 11. This circuit can then be compensated
with a single compensation capacitor CC.
When trying to implement the same circuit using MOSFETs, two problems arise: First the gain for a common source
stage is typically much lower than that of a common emitter
stage. Consequently, two or more MOSFET gain stages may
be required to achieve the same gain as a single BJT gain
stage. Second, the compensation provided by CC is often inadequate due to a zero introduced by the feedforward path
through CC and the low stage gain. Polezero cancellation can
be used to compensate this circuit by placing a resistor in
series with CC (4,7). The resistor should have a value equal
to 1/gm of the common-source stage. While polezero cancellation will solve the latter problem, the former problem, that of
a relatively low stage gain, remains. If multiple commonsource stages are used to boost the gain, the ensuing compensation problem becomes very complex.
To achieve high-gain op amps using MOSFETs, without
stability problems, cascode designs are used (3,7). To maximize the signal swing at the output, the folded cascode configuration shown in Fig. 13 is commonly used. Unlike the bipolar design, which used a differential pair followed by a
common emitter stage to achieve a high gain, the folded cascode uses a differential pair followed by a common gate stage.
Now the circuit only has one high-impedance node and it occurs at the output. If the gain provided by one level of cascoding is insufficient, additional levels of cascoding can be added,
while still maintaining only one high-impedance node.

Vbias
M2a

M2b

Ibias

Ibias
V

Figure 13. A folded cascode op amp.

Output Buffers. The primary concern for the output buffer

is the buffers output impedance. When the output buffer is
implemented as an emitter or source follower, the output impedance is given by 1/gm of the output device. Due to the
BJTs relatively high transconductance-to-bias-current ratio,
BJTs make a better choice for low output impedance buffers.
When the op amp is only required to drive relatively small onchip capacitances, there is no need for an output buffer stage.
In summary, BJTs are well suited for op amps with high
gains, low output resistances, and low input referred offsets.
Consequently bipolar op amps are typically used for circuits
with resistive loads and for precision applications. MOSFETs
are well suited for applications requiring very low input bias
currents and for driving on-chip capacitive loads, this makes
them well suited for switched-capacitor circuits.
Compensation
Op amps are typically used in circuits employing feedback.
For a typical feedback circuit such as that shown in Fig. 14,
the feedback signal is subtracted from the input signal before
being applied to the amplifier. The subtraction operation reduces the signal seen by the amplifier. For a practical circuit,
the amplifier gain A is a function of frequency and the feedback factor B may also be a function of frequency. Hence, the
loop gain AB is also a function of frequency. Consequently,
due to phase shifts around the loop, at certain frequencies,
the feedback and input signals may be in phase. Then, the
input and feedback signals add together increasing the signal
seen by the amplifier. At this point the circuit becomes unstable. The amplifiers output grows and the circuit oscillates
at the frequency at which the input and feedback signals are

x0 +

x0

Figure 14. A generalized feedback system.

OPERATIONAL AMPLIFIERS

fp1

0 dB

Phase

fp3

Gain (dB)

A0

fp2

1/B

Frequency
(log scale)
Phase
margin

180

Figure 15. A Bode plot for analyzing the phase margin of an opamp circuit.

fp1

fp0

fp2 f'p2 fp3

A

Gain (dB)

in phase. This frequency corresponds to a phase shift around

the loop of 180. Consequently, in a feedback circuit, it is
desirable to ensure that the magnitude of the phase shift
around the loop is much less than 180 when the gain around
the loop is greater than or equal to 1.
Phase margin is defined as the difference between the
phase of the loop gain and 180 when the loop gain is equal
to unity. To avoid peaking in the circuits frequency response,
it is necessary to have a phase margin of 60 or more (2). In
applications where some peaking in the frequency response
can be tolerated, lower phase margins may be used.
The phase margin of an op-amp circuit can be estimated
from a Bode plot of the op amps transfer function. By adding
a line for 1/B to the plot, the difference between the A and B
lines is equal to AB (i.e., logAB logA log1/B). The point
at which the two lines intersect is the loops unity gain point.
This is illustrated in the asymptotic Bode plot shown in Fig.
15. The 1/B line is frequency independent in this case and
hence can be implemented with resistive feedback, such as
was used for the inverting and noninverting configurations of
Figs. 2 and 4. From this plot, the phase margin is almost 0
and hence would be inadequate for most applications.
To ensure an adequate phase margin, op amps must typically be compensated. Compensation involves either moving
the existing poles of an op amp or adding new ones to ensure
that the final circuit has the desired phase margin. Op amps
come in two main types: compensated and uncompensated. A
compensated op amp has been compensated by the manufacturer to be stable for all values of resistive feedback up to
B 1 (i.e., a unity-gain buffer). An uncompensated op amp
will not be stable for all values of resistive feedback but typically has provisions for the user to perform the necessary
compensation for the desired gain. While easier to use, compensated op amps will have an unnecessarily low bandwidth
for gains greater than 1. To achieve a better bandwidth for
higher-gain applications, uncompensated op amps can be
used.

Frequency
(log scale)

Phase

174

180

Original amplifier
First method
(adding a pole)
Second method
(shifting a pole)
Third method
(splitting a pole)
Figure 16. Compensating an op-amp circuit for a phase margin of
45 at unity gain.

Compensation can be performed in a number of ways (1

3,7,8). The simplest approach is to add a new pole at f p0 to
ensure that the loop gain falls to unity at the desired phase
margin, as illustrated in Fig. 16. For this example, the desired phase margin is 45. This technique will reduce the circuits closed-loop bandwidth to approximately the op amps
first, or dominant, pole f p1, which can be as low as a few hertz.
A better approach is to identify the op amps dominant pole.
Then increase the capacitance at that node until f p1 is reduced
far enough to reduce the closed-loop gain to unity at the desired phase margin (2). As illustrated in Fig. 16 this approach
yields a closed-loop bandwidth comparable to the op amps
second pole f p2, resulting in a significant increase in bandwidth.
In the common three-stage bipolar op amp of Fig. 11, the
dominant pole is typically at the base of Q3. While a large
capacitor can be connected between the base of Q3 and V, a
better approach is to connect the compensation capacitor
(CC) between the base and collector of Q3 as shown. This exploits the Miller multiplier effect, which results in increasing
the effective capacitance seen at Q3s base. In addition to lowering f p1, this technique, called Miller compensation, has the
effect of moving the pole at Q3s collector higher in frequency
due to pole splitting (6). Since the pole at Q3s collector is often f p2, Miller compensation has the effect of splitting f p1 and
f p2. Pole splitting in this circuit results in a larger compensated bandwidth than would be achieved by moving f p1 alone,
as illustrated in Fig. 16.
While there are many other techniques for compensating
op-amp circuits (1,8), one that is particularly useful is that
used for the folded cascode CMOS op amp in Fig. 13. This op

OPERATIONS RESEARCH DECISION MAKING

amp has been designed for driving capacitive loads. The circuits dominant pole is that formed by the cascodes output
resistance and the load capacitance. To compensate this circuit, the load capacitance should be increased and no additional circuitry is required. This last example illustrates one
of the advantages that can be achieved by using an op amp
specifically designed for the application at hand.
BIBLIOGRAPHY
1. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 2nd ed., New York: McGraw-Hill, 1998.
2. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 3rd ed., New
York: Oxford University Press, 1997.
3. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., New York: Wiley, 1993.
4. P. R. Gray and R. G. Meyer, MOS operational amplifier designA
tutorial overview. IEEE J. Solid State Circuits, SC-17: 969983,
1982.
5. C. C. Enz and G. C. Temes, Circuit techniques for reducing the
effects of op-amp imperfections: Autozeroing, correlated double
sampling, and chopper stabilization, Proc. IEEE, 84, 15841614,
1996.
6. J. E. Solomon, The monolithic op amp: A tutorial study, IEEE J.
Solid State Circuits, SC-9: 314332, 1974.
7. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for
Signal Processing, New York: Wiley, 1986.
8. J. K. Roberge, Operational Amplifiers: Theory and Practice, New
York: Wiley, 1975.

DAVID G. NAIRN
Analog Devices, Inc.

OPERATIONAL AMPLIFIERS. See CURRENT CONVEYORS.

OPERATION ONLINE. See ONLINE OPERATION.
OPERATIONS RESEARCH. See GEOMETRIC PROGRAMMING.

175

472

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

BASIC CONTINUOUS OPERATIONS

NONLINEAR CIRCUIT SYNTHESIS

USING INTEGRATED CIRCUITS
Integrated circuit (IC) components are intrinsically nonlinear,
as are all circuits built by interconnecting them. In some applications, such as amplification and filtering, nonlinearities
are sought as error sources, and the designer employs design
techniques to reduce their influence. In others, such as modulation, power measurement, sensor linearization, and signal
shaping, the objective is not to attenuate the components
nonlinearities but to use them to perform nonlinear processing tasks.
Nonlinear IC synthesis can be informally defined as a constructive procedure to interconnect IC primitive components
and to assign values to their parameters to realize specified
nonlinear relationships among electrical variables. This consists of several methodological steps:
1. Identify the intrinsic nonlinearities availables at the IC
primitives.
2. Construct nonlinear basic building blocks to realize elementary nonlinear operations such as logarithm, exponent, squaring, and sign.
3. Interconnect these blocks and the primitives themselves
to realize nonlinear functions such as multiplication, division, and absolute value.
4. Realize nonlinear tasks through the proper interconnection of all the circuit blocks.
This article presents principles and design techniques to
cover the first three steps above using bipolar junction transistors (BJTs) and metal oxide semiconductor transistors
(MOSTs)the basic primitives of most commonly used IC
technologies (13). Considerations related to the fourth step
are found elsewhere (410).
OUTLINE OF INTRINSIC PRIMITIVE NONLINEARITIES
The nonlinear behaviors exhibited by BJTs and MOSTs may
be classified for design purposes into two groups: continuous
(exponential functions, power functions, etc.) and piecewise
(abrupt transitions between conducting and blocked states).
These behaviors, and their associated characteristic equations, are outlined in Table 1. It is worth noting that these
equations are first-order models and, as such, give only rough
approximations to actual behaviors. As a consequence, nonlinear circuit designs based on these expressions will only approximate the intended functionality. Detailed analysis of second-order phenomena can be found in the references listed at
the end of this article.
According to the preceding classification for the intrinsic
primitive nonlinearities, the circuits used to realize the elementary nonlinear operations and the nonlinear functions are
also classified in two different groups: continuous and
piecewise. They are covered separately in the rest of the article.

Three basic continuous operations exploitable for nonlinear

synthesis can be identified, namely: (a) linearly controlled
transconductances, (b) exponentials and logarithms, and (c)
squaring and square-rooting.
Only those realizations based on the intrinsic primitives
nonlinearities outlined in Table 1 will be considered, although
they can be implemented by other means. For instance, logarithmic amplifiers can be realized using switched-capacitor
techniques (6) or approximated with parallel combinations of
MOST source-coupled pairs (1113). Similarly, squarers can
be easily implemented using multipliers with identical input
signals, or via piecewise linear (PWL) approximation. Exceptionally, the section entitled Squaring and Square Rooting
will show circuit solutions for the synthesis of the squaring
and square rooting operations based on the translinear principle (covered in the next section) (14,15) as an illustration of
this important technique for function generation.
Linearly Controlled Transconductances
Table 1 shows that the small-signal transconductance of BJTs
biased in the forward active region depends linearly on the
collector current Ic. A similar dependence is observed for
MOSTs biased in the weak inversion region. Correspondingly,
the transconductance of MOSTs biased in the saturation
strong-inversion region is a linear function of the gate-source
voltage overdrive Vp Vs. These linear dependences are at
the very heart of the translinear principle (14,15), which
allows the analysis and synthesis of current-mode circuits
able to generate algebraic transformations in an essentially
exact and temperature-insensitive manner. The translinear
principle can be formulated for BJTs and MOSTs as follows.
Consider a loop of n BJTs biased into forward active region
(correspondingly, MOSTs operated in forward saturation under strong inversion) such that their baseemitter junctions
(correspondingly, their gatesource voltages) are connected in
series. Assume that there are equal numbers of transistors
arranged clockwise and counterclockwise. Then, the product
(sum) of the collector current densities (square root of the
drain current densities) in the clockwise direction is equal to
the product (sum) of the collector current densities (square
root of the drain current densities) in the counterclockwise
direction. Mathematically, this can be expressed as

BJTs

MOSTs

I 

CW

Ak


CW

ck

I 

CCW

Ak

ck


Idk
=
(W/L)k
CCW

Idk
(W/L)k

(1)

where Ak represent emitter areas of BJTs; and (W/L)k aspect

ratios of MOSTs. Throughout this article, an extensive use of
the translinear principle will be made. For a more throughout
study of this essential principle for nonlinear synthesis, readers are referred to Refs. 14 and 15.
Exponentials and Logarithms
These operations can be easily implemented by taking advantage of the exponential large-signal characteristic of
BJTs (and MOSTs in weak inversion). Focusing on BJTs,

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

473

Table 1. Intrinsic Primitive Nonlinearities

BJT

MOST

Vce

_
E _

S _

D
Id

Ic

Vgs

Vbe +
B

Ib

Continuous
Square-law characteristic b of MOSTs in the forward saturation region
under strong inversion.c

Exponential IV characteristic of BJTs in the forward active region

(Vbe 0, Vbc 0), and the corresponding logarithmic transresistance VI characteristics.a
Ic IS exp

Vbe
Ut

Ib

Vce
VA

Id n(Vp Vs)2 1

Vd Vp
; Vs V p V d
VA

Product characteristic of a MOST operating in the conduction (ohmic)

region under strong inversion

1
Id 2n Vp (Vd Vs) (Vd Vs); Vs , Vd Vp
2

Ic

Exponential characteristic of a MOST operating in the forward saturation region under weak inversion.d
Id ID0 exp

Vp V s
Ut

V d Vp
; Vs , V d V p
VA

Small-signal transconductance of a MOST in saturation and strong inversion as a linear function of the gate voltage.
Small-signal transconductance of a BJT in the forward active region
as a linear function of the collector current.
gm

Ic
Vbe

Quiescent Point

Ic
Ut

gm 2

Id

n 2(V V )
p

Small-signal self-conductance of a MOST in ohmic region as a linear

function of the gate voltage.
gds 2n(Vp Vs)
Piecewise

Negligible output current for Vbe 4Ut .

Negligible output current for Vs Vp 4Ut and Vd Vp 4Ut .

Ut kT/q is the thermal voltage (26 mV at 300 K); IS is the collector saturation current (proportional to the emitterbase junction area); VA is the Early voltage
(typically from 50 V to 200 V); and is the forward basecollector current gain (typical values are between 50 to 200).
b
MOST voltages are referred to the bulk (local substrate) terminal, B.
c
(W/L)Cox/2 is the transconductance parameter (usually from 10 A/V2 to 50 A/V2 for W L); n is a slope factor usually smaller than 2, which tends to
1 for large values of Vg; Vp (Vg VT0)/n is the pinch-off voltage; VT0 is the threshold voltage; and VA is the equivalent Early voltage (proportional to the
transistor length).
d
ID0 is the specific current of the transistor (typically from 20 nA to 200 nA for W L), and it is proportional to the transconductance parameter .
a

if the baseemitter junction of the transistor is driven by

a voltage, Vbe, the resulting collector current, Ic, is roughly
proportional to an exponential function of Vbe. Reciprocally,
if the transistor is forced to accommodate a given collector
current, Ic, the resulting Vbe is approximately proportional
to the logarithm of Ic. Figure 1(a,b) shows simple logarithmic [Fig. 1(a)] and exponential [Fig. 1(b)] voltage amplifiers
based on these principles. These circuits exploit the virtual
ground of the opamp to obtain Ii Vi /R [Fig. 1(a)] and
Vo IiR [Fig. 1(b)].
The circuits of Fig. 1(a,b) are seldom used in practice because of some important nonidealities. For instance, Fig. 1(a)
has a notorious tendency to oscillate because of the nonlinear

feedback around the opamp. To ensure stability, a frequency

compensation circuit must be added to this feedback loop (5).
Another drawback is caused by their dependence on temperature, through both Is and Ut (see Table 1). The circuits in Fig.
1(c,d) compensate the former by using common-emitter differential pairs instead of single transistors. In this way, the dependence of the amplifiers output voltages with the saturation currents disappears to a first approximation, as shown in
the insets of Fig. 1(c,d). These expressions show that Vo in
both amplifiers still depend on temperature via Ut. This can
be compensated by implementing R2 with a temperature-dependent resistor having the same temperature characteristic
as Ut (5).

474

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

Ii
+
Vi

Ii
+
Vo

+
Vi

Vo UtIn

Vi

Vi

Vo RIsexp

RIs

(a)

Ut

(b)

Ii
+

+
Vo

IB

RB

Vi

+
VB

RE

Vo Ut

R2

R1

R1 + R2

In

R2

Vi
RIB

+
+

(c)
IB
+
VB

Io

RB

+
VB

+
R2

R1

RE

Vo RIB exp

Vi

R2

Ut

R1 + R2

+
+
Vi

(d)
Figure 1. Logarithmic (a) and exponential (b) amplifiers based on a single npn BJT. Logarithmic
(c) and exponential (d) amplifiers using matched pairs of npn BJTs to cancel out the dependence
with the collector saturation current.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

Squaring and Square Rooting

475

When a MOST is operated as a squaring device, its drain current contains other undesired terms together with the difference-squared component; and reciprocally, when a MOST is
configured as a square-rooting device, its gatesource voltage
includes an offset term.
Figure 2(ac) shows some squaring circuit blocks together
with their transfer characteristics assuming no body effect
(MOSTs source terminals are connected to their local substrates). Figure 2(a) uses a single MOST and a voltage buffer
to maintain the gatesource voltage independent of the current flowing through the device; this buffer is needed because
the source terminal is a low-impedance node. The buffer can
be implemented using voltage followers (16), shunt feedback

These operations can be synthesized by exploiting MOSTs

strong inversion saturation region. If two voltages (with identical common-mode values) are applied, respectively, to the
gate and source of a MOST in the saturation region, the drain
current contains a term proportional to the square of the difference of the two voltages. Reciprocally, if the transistor is
forced to accommodate a given drain current Id (this requires
application of feedback as occurs at the input stage of MOST
current mirrors), the resulting Vgs contains a term roughly
proportional to the square root of Id. However, these operations are adversely affected by the nonzero threshold voltage:

Io

Io
V1

Mn

V2

Mp

V1

eq =

VT,eq = VTn + VTp

( n p )/(nnnp)
[ n/nn +

p/np ]2

V2

Io = n (V1 V2 VTo)2

Io = eq (V1 V2 VTeq)2

(a)

(b)

Io

1 = 2

V1

M1

M2

V2

Io IQ +

n1 n2 n

(A1)

(V + Vd2 ) +
(Vd1 Vd2 )2
4ARs d1
8nA

A = 1 + 8 n Rs [VQ VT0]
Rs
Io =

n(1 A)
VQ VT0
+
Rs
4 R2s

V1 = VQ + Vd1/2
V2 = VQ + Vd2/2
(c)
Iin

Vo

M1

n2 2
n1 1 + n2 2

+
M2
VR

Vo

eq =

(d)

1 2
1 + 2

n2 2
eq

Iin

Figure 2. Squaring and square-rooting

circuits based on the large signal characteristic of MOSTs. (a) Squaring circuit using a single MOST with source buffering;
(b) squaring circuit based on a CMOS
composite pair; (c) squaring circuit using
a source degenerated differential pair; (d)
nested connection of two MOSTs for
squaring or square-rooting operations.

476

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

amplifiers (17), or opamp-based inverters (18). The squaring

block of Fig. 2(b) avoids the buffering stage by using a CMOS
composite pair (19). This circuit can be seen as an n- or pchannel MOST, operating in the saturation region, with the
parameters VT,eq and eq shown in the inset, but with high
impedance gate and source nodes. Finally, Fig. 2(c) uses a
source degenerated differential pair (20), whose large-signal
transconductance characteristic contains a term proportional
to the square of the difference of the two gate voltages. In
practice, the resistor can be implemented with another MOST
operating in the ohmic region.
Figure 2(d) shows a nested connection of two MOSTs
which, depending on the attachment, can perform either as a
square rooting of the input current [configuration in Fig. 2(d)]
or as a squaring of the input voltage (21). Interestingly
enough, both operations are free from other undesired terms
provided that the transistors have the same threshold voltage. However, the internal node of this nested connection cannot be directly loaded but must be sensed or driven through
a high-impedance node (21).
As previously stated, another possibility to implement the
squaring and square-rooting operations relies on the translinear principle. Circuit solutions exist for both the BJT (14,15)

IQ

IQ

and MOST (22) version of this principle, but we will restrict

to the latter. Figure 3(a,b) shows two possible realizations of
a MOST translinear current-mode squarer (22). Applying the
translinear principle [see Eq. (1)] on the loops formed by the
gate-source paths of transistors M1 M4 in the circuits of Fig.
3(a,b), obtains the expression,

I

d1

I

d3

I

d2

I

d4

(2)

where Idi and i represent the drain current and transconductance factor of transistor Mi, respectively. If the currents Id1
and Id3 are each forced to be equal to a bias current IQ; the
difference of Id4 and Id2 is defined by the input signal, Iin; and
the current Id2 Id4 is taken as the output of the circuit, Eq.
(2) becomes
Io = IQ +

I 2in
4IQ

(3)

where the aspect ratios of the transistors are such that 1

3 2 and 2 4 . Note that the offset term in Eq. (3)

IQ
IQ

IQ

Io
M1

M2

M3

M4

M3

Io

M2

Iin
M1

M4

Iin

Iin1

M5

(a)

Iin1

1 :

(b)

Iin2

Iin2

Iin1
Iin1

Io
M2

M1

M3

M4

Io

M2
M1

M5

Iin2

M3

M6

Iin2

1
(c)

M4

Iin2

Iin1

1 :

1
(d)

Figure 3. MOST translinear current-mode circuits: (a,b) squarers; (c,d) geometric mean operators.

M5

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

can be eliminated by inserting another replica of the bias current [dashed sources in Figs. 3(a,b)] at the output node. Valid
operation range is guaranteed when all transistors operate in
the saturation regime, which leads to Iin 2IQ.
Schematics similar to those in Fig. 3(a,b) enable to realize
the square-rooting operator (or more exactly, the geometric
mean operator). These are shown in Fig. 3(c,d). The synthesis
strategy is to take Id1 and Id3 as the input signals (Iin1 and
Iin2, respectively); Id4 and Id2 are made equal, and the current
Id2 Id4 is again considered as the output of the circuit. Assuming 1 3 and 2 4 2, the following characteristic is obtained:

Io = Iin1 + Iin2 + 2 Iin1 Iin2

(4)

which includes a term proportional to the geometric mean of

Iin1 and Iin2. Obviously, if one of the input currents is regarded
constant, such term becomes proportional to the square root
of the other input signal. Once again, the undesired terms in
the expression may be eliminated by applying a compensating
source at the output node, in this case Iin1 Iin2. Correct performance of the circuits is ensured whenever Iin1 and Iin2 are
positive.
BASIC PIECEWISE NONLINEAR OPERATIONS
Three basic discontinuous nonlinear operations can be identified, namely: (a) comparison, (b) rectification, and (c) controlled switching.
Comparison
A voltage comparator produces an output binary voltage y to
codify the polarity of an analog input voltage x with respect
to a reference value E,

VOH , x > E
y=
(5)
VOL , x < E
where VOL and VOH are voltage levels associated to the low and
high logical states, respectively.
The simplest way to realize Eq. (5) is employing a onestage voltage amplifier. Figure 4(a) shows three possible
CMOS implementations of this concept: two are unilateral
(reference voltage is set by the transistor threshold voltages);
the third is differential (reference voltage set by an external
source). Similar implementations can be made with BJTs.
The behavior of one-stage voltage comparators can be approximated to a first-order by the circuit model shown in the
inset of Fig. 4(a). This model captures three nonideal features: input offset voltage (Eos), finite dc gain (Av gmRo), and
time constant ( RoCo). It models also the amplifier output
voltage saturations. Assuming that a small positive voltage
step x E is applied at t 0, the output voltage evolution in the linear region is calculated as



y(t) = ( Eos )Av 1 et/
(6)
A similar equation is found for negative input steps. From Eq.
(6) two major drawbacks of this comparator structure can be
identified. On the one hand, the input sensitivity (i.e., the

477

minimum needed for the output to reach the logical levels)

is limited by the input offset voltage and the finite dc gain;
the larger Eos the larger the needed to obtain a positive
output, and the smaller Av the larger the needed to reach
y VOH. On the other hand, the output transient evolution is
dominated by a rather large time constant . [The maximum
speed capability of Fig. 4(a) is set by the time constant u
Co /gm. However, the time constant of the one-stge comparator
is reduced by the dc gain (i.e., u /Ao.] To raise the operation speed and increase the gain of the one-stage comparator,
two nonexclusive strategies can be adopted (23): using
multistage amplifiers [Fig. 4(b)], and using positive feedback
to obtain regenerative amplification [Fig. 4(c)]. This latter implies synchronous operation. On the other hand, to cancel the
comparator offset, autozeroing techniques, where the offset is
periodically sensed, stored, and added to the input in such a
way as to cancel itself, are commonly usedalso involving
synchronous operation [Fig. 4(d)].
Consider now that the input and the reference are currents. They can be compared by first injecting both into a
sensing block to convert their difference in an intermediate
voltage and then using this voltage to drive a voltage-mode
comparator. Figure 5(a) shows the concept (24). The resistive
part of the current sensing device is such that the equivalent
resistance is large for low currents (Rs) and small for large
currents (R*s ). This enables us to combine very low current
detection capability with reduced input voltage excursion.
Figure 5 shows two practical CMOS implementations of this
concept. The circuit of Fig. 5(b) uses the nonlinear resistor
formed by transistors Mn and Mp. In many practical applications, a simple CMOS inverter can be used in place of the
voltage-mode comparator (24), thus leading to very compact
realizations. An important drawback of Fig. 5(b) is that the
transient behavior is largely dominated by the overlapping
capacitance Cf , which connects input and output terminals of
the voltage amplifier. The circuit in Fig. 5(c) overcomes this
drawback by decoupling the input and output nodes of the
amplifier (24).
Rectification
The two most basic rectification operators are the so-called
positive and negative half-wave rectifiers, which are defined
as (represented at the top of Fig. 6)

y = u+ (x) =


x, x 0
0, otherwise


y = u (x) =

x, x 0
0, otherwise

(7)

where variables x and y can be in the form of currents or

voltages. The relevance of these operators comes from the fact
that they are basic building blocks for the realization of any
elementary piecewise linear function, as will be shown in the
section entitled Derived Piecewise Nonlinear Operations.
The basic rectification mechanism is the controlled transition between the blocked and conducting states of either diode
or diode-connected transistors, and leads to implementations
of Eq. (7) with input and output current [see Fig. 6(a)]. A
drawback of these circuits is the current-dependent nonzero
voltage drop in the conducting state. It can be reduced by
using feedback to create superdiodes, shown in Fig. 6(b) for
the grounded case and Fig. 6(c) for the floating case (exempli-

gm ( x E Eos )

y
Ro

Co

x
IB

I
Slope
m

Slope Ro1

Es

x
(0,0)

Es+

IB

(a)

gm ( x E )

Co

Ro

Co

Ro

+
v2

+
v3

Co

Ro

g mv n

g mv 2

(b)

x+

y+

Reset

Set

Set

Reset

Co

Co
Ro

Ro

(c)

Reset

Set
x

+
Reset

(d)
Figure 4. Voltage-mode comparators: (a) based on one-stage voltage amplifiers; (b) using
multistage amplifiers; (c) via regenerative amplification; (d) with offset cancellation.
478

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

479

Current sensing device

Is
x

Cs

+
+

Vm

Vm

Is

Slope G*s

Slope Gs
E
E+

(0, 0)

Vm

(a)

Mn
Mp
In

In
E

Ip

Ip

Figure 5. (a) Current-mode comparator

based on voltage amplification. (b) Current sensing device made of transistors
Mn and Mp; (c) Current steering configuration.

Mn

Mp

(b)

fied with a MOST). In both cases, the reduction of the forward

voltage drop is proportional to the dc gain of the amplifier.
Another building block widely used for current rectification
is the current mirror. Figure 7 shows the rectifying characteristics of very simple current mirrors using n-channel [Fig.
7(a)] and p-channel [Fig. 7(b)] MOSTs with bias-shifting. For
both cases, we assume that the aspect ratio W/L of the output
transistor is m times larger than that of the input. The transfer characteristic of the circuit in Fig. 7(a) can be easily derived taking into account that the input transistor enters the
cut-off region for values of Iin below IB1, for which the input
voltage becomes lower than the threshold voltage VTon. Similar analysis also applies for the circuit in Fig. 7(b). Dashed
lines in Fig. 7(a,b) show the transfer characteristics for zero
IB1 and IB2. In this situation, the breakpoints of the characteristics are at the origin, and the output current is given by
Io mu(Iin) for the circuit in Fig. 7(a), and Io mu(Iin)
for the circuit in Fig. 7(b). BJTs can also be used for rectification based on the current mirror concept.

(c)

The most important limiting factor of using current mirrors for rectification is the delay time required to discharge
the input capacitance in the transition from cut-off to conduction. To improve this, class AB configurations can be used
(25). The reason is that in class AB circuits there is always a
low-impedance path for the input current to flow and thus the
voltage at the input node remains limited. Figure 8(a) shows
an example of a class AB current rectifier. The output currents Io1 and Io2, assuming matched devices and saturated operation, can be described by
Io1 = m

(4IB + Iin )2
16IB

and Io2 = m

(4IB Iin )2
16IB

(8)

for Iin 4IB. When the input current magnitude exceeds

4IB, Eq. (8) no longer holds because one of the output mirrors
now takes virtually all the current, the other one being effectively switched off. This means that proper rectification occurs only for large enough input currents. Another class AB

480

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

y
x

u+()

u-()

Iin

Iin
Io = u
+

Vin

Io = u

(Iin)

(Iin)

Iin

Iin
Io = u - (Iin)
+

Vin

Io = u - (Iin)

(a)

Iin

Io = u

+ (I in )

Vin

+
Iin

Figure 6. (a) Diode and diode-connected

transistors for current rectification; (b,c) super-diodes.

Io = u

(Iin)

+ Vin
(b)

configuration which avoids this lack of accuracy at low currents is shown in Fig. 8(b), and it is based on the rectification
properties of the nonlinear feedback current comparator of
Fig. 5(b). Any positive input current increases the input voltage, turning the bottom device, Mp, ON. Because both devices
share the input voltage, the top device, Mn, becomes OFF.
Similarly, the input voltage decreases for negative input currents, so that Mn becomes ON and Mp, OFF. In sum, positive
input currents are drawn to the bottom device, whereas negative currents are drawn to the top device, thus achieving
nearly perfect rectification. Furthermore, the circuit is insensitive to transistor mismatch; hence, it can be realized
through minimum size devices. Proper routing and scaling of
the drain currents passing through transistors Mn and Mp obtain the concave and convex basic characteristics, as shown
at the bottom of Fig. 8 (2426).
Controlled Switching
Switches, often operated by comparators, are used locally in
nonlinear circuitry to establish new conditions when a threshold on a given variable has been crossed (27). For instance,
they may change a gain, reverse a polarity, or initiate a new
mode of operation, thus producing an overall nonlinear response. Signal processing multipliers, covered in the section
entitled Multiplication, represent an application example of
the controlled switching operation for nonlinear synthesis.
Figure 9 shows three common analog switches used in
practice (23). Figure 9(a) is the most simple realization and

(c)

consists of a single MOST with its gate voltage controlling the

resistance between its drain and source. As shown in Table 1,
when the MOST operates in the linear region, this resistance
can be expressed as
Ron =

1
2(VG VT0 nVs )

(9)

and when the device turns blocked, this resistance (Roff ) becomes virtually infinite. In order to extend the input swing of
the single MOST switch and further reduce the on resistance
in Eq. (9), the complementary structure of Fig. 9(b) is used
instead. It is formed by an NMOS and a PMOS device, whose
gates are controlled with complementary logical levels so that
the two devices turn on and off simultaneously. In pure bipolar technologies, where MOSTs are not available, controlled
switching is performed by diode bridges, illustrated in Fig.
9(c).
DERIVED CONTINUOUS NONLINEAR OPERATIONS
Here we include (a) sigmoid transfer characteristics, (b) belllike transfer characteristics, (c) multiplication, (d) division, (e)
vector magnitude calculation, (f) normalization, and (g) maximum and minimum.
Sigmoid Characteristic
IC implementation of arbitrary nonlinear functions is possible
using universal representation techniques as, for instance,

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

481

Io
IB1

IB2

IB2
Io

Vin

IB1

Vo

Iin

Io = IB2 mu+(Iin + IB1)

S

Slope m

mS

(a)
Io

mS

IB1

Iin

Vo

Vin

Iin

Io

Io1

Slope m
Io = IB2 mu(Iin IB1)

IB1

IB2

IB2

(b)
Figure 7. Rectifying characteristics of current mirrors using (a) n-channel and (b) p-channel
MOSTs with bias-shifting as basic transconductors.

multilayer perceptrons, for which elementary computational

units realize sigmoidal functions. Figure 10 depicts two sigmoidal shapes used in practice. Figure 10(a), the hard limiter,
has an inner piece of large (ideally infinite) slope, whereas for
Fig. 10(b), the soft limiter, this slope is smaller and can be
used as a fitting parameter. Hard-limiter characteristics can
be easily achieved using the comparison operators discussed
in the previous section entitled Comparison. On the other
hand, soft-sigmoid characteristics can be easily synthesized
by exploiting the global transfer characteristics of basic differential amplifiers (11,28) or using simple CMOS inverters (10).
Here, we will restrict ourselves to the first approach.
Figure 11 shows the expressions for the large-signal output current of a basic differential pair implemented with saturated MOSTs (top expression) and with bipolar transistors
(bottom expression). In the first case, the sigmoid characteristic exhibits a quadratic dependence with the input voltage
and saturates at IB and IB. In the second case, identical
saturation levels hold, but dependence with the input voltage
is now exponential. In both cases, transfer function presents
a continuous derivative Gm(IB), which is tunable through the
biasing current of the differential pair. Circuits in Fig. 11
have been widely used in neural network implementations
and function synthesis hardware. For instance, Fattaruso and
Meyer (11) use arrays of MOS differential pairs in the saturation region as analog function synthesizers and propose a biasing strategy that allows independence to temperature and
processing variations. On the other hand, MOS differential

pairs operated in weak inversion have become one of the basic

elements in the implementation of feedforward neural networks and other massively parallel computation paradigms
as a result of their low power consumption and high integration density (7).
A problem arising with basic differential pairs for function
synthesis is that the tuning of the biasing current implies not
only a variation on the slope of the sigmoid characteristic but
also a shift of the saturation levels. Several techniques have
been proposed to overcome this problem. A first approach consists on truncating the output current of the differential pair
so that the saturation levels remain always between IB and
IB for any value of the transconductance. This truncation
operation is implemented in the current domain by loading
the differential pair with adequate rectifying or maximum/
minimum operators. A second strategy to control the slope of
the sigmoidal characteristic without affecting the saturation
levels relies on input voltage scaling (13). In this way, if Vin is
linearly preamplified by a factor k at the input of the differential pair, the slope of the sigmoid becomes kGm(IB) and can be
tuned by controlling the voltage gain k. A third approach is
based on degenerating the source/emitter of the differential
pair through a voltage-controlled resistor so that the transconductance of the amplifier turns dependent on the equivalent degenerative resistance (29). A last approach to achieve
continuous and electrically tunable changes in the slope of the
sigmoid characteristic uses compound transistors (28). These
compound transistors have the same signal terminals as con-

482

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

IB
S

mS

Io2

Mn

Iin

mS

Iin

Mp
Io1

Io2

Mn

In

+
Vs

Io1

Mp

Ip

mS

mS

IB

(a)

(b)

Io1

Io2

Slope m
Slope m
Figure 8. Class AB current mirrors with
positive and negative rectifying outputs:
(a) using a second-generation current conveyor; (b) using a feedback current comparator.

Iin

Iin

Vc
Vin

Vo

I1
Vc

Vo

Vin

(a)

Vc

Vin

Vo
I2

Vc

C
Vc
Figure 9. Basic switches: (a) single MOST;
(b) complementary MOS; (c) diode bridge.

(b)

(c)

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

E+

E+

ter coupled pairs and is always comprised in [0, 2IB] regardless of the devices replacing the rectangular blocks. The width
and center of the bell are given, respectively, by
slope =

0,0

0,0

2 = V2 V1

(a)

(b)

Figure 10. Typical sigmoidal shapes: (a) hard limiter; (b) soft
limiter.

ventional transistors in Fig. 11, but their transconductance is

controllable through a parameter associated to either a digital
word or a control voltage.
Bell-Like Function
Several bell-shaped functions have been proposed as interpolation operators in the framework of radial basis networks
and neuro/fuzzy controllers (9). Among these operators, the
polynomial and Gaussian basis functions, represented in Fig.
12(a,b), respectively, are the most widely found in the literature. The electronic realization of these characteristics involves the interconnection of squarers, power computation
blocks, and exponential operators. However, these exact
shapes are not required in many applications and can be approximated using simpler circuits.
One possibility to approximate the polynomial bell-shaped
characteristic shown in Fig. 12(a) is to combine two differential pairs as indicated in Fig. 13, where rectangular blocks
can be replaced by MOSTs, BJTs, or other compounds devices
(13,28). In this circuit, V1 and V2 are used to adjust the width
of the bell-like function, and the voltage amplifier with gain
parameter k is used to change the slope of the transconductance characteristic. In Fig. 13, some of the current components generated by the circuit are also shown. The differential
output current of the block Io is obtained as the sum of the
individual differential output currents of the two source/emit-

S=k

ViA

r 2I

=

S=

kIB
2Ut

=

2nI

k2

(11)

4Ut
k

(12)

where it should be noted that is now independent of the

bias current IB.
With regard to the Gaussian radial basis function, Fig. 14
shows a circuit implementation based on MOS differential
pairs in the saturation region (10). Contrary to the circuit in
Fig. 13, the input signal is in differential form. The center of
the bell is defined by the voltage difference VA VB, and the
standard deviation of the Gaussian function can be varied by
changing the sizes of the transistors in the input differential
pairs using digitally programmed structures (30). On the
other hand, parameters a and b can be chosen to better approximate the ideal Gaussian curve.
Multiplication
Analog multipliers implementation has long been an important topic in electronic research. Besides their suitability for
function synthesis, analog multipliers also find a wide range

Vin

2 IB 2Vin2 V
in
n
n2

nIB

Vin

nIB

IBsgnVin
ViB

Io IB tanh
IB

(10)

assuming that the width of the bell is larger than (2)min

2(nIB /)1/2. If the rectangular blocks are replaced by bipolar
transistors, S and take the form

Io
IoB

V2 + V1
2

which are controlled by the designer. On the other hand, the

slope of the bell at the crossover points depends on the transconductance of the differential amplifiers and the gain k of
the input voltage amplifier. If the rectangular blocks are replaced by MOSTs in the saturation region, the slope at the
crossover points S and the width of the rise or fall edges
are given by

Io = IoA IoB
Vin = ViA ViB
IoA

483

Vin
2Ut

( )

Figure 11. Differential amplifiers and their associated large-signal characteristics.

484

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

(x)

Slope = /2

1.0
0.5

(x)
1.0
0.5

0.0

0.0

(x) =

( )

x
1+

( x )2
2 2

(x) = exp

2b

(a)

)
Figure 12. Basic interpolation functions:
(a) polynomial; (b) Gaussian.

(b)

of applications in signal processing systems, including communication and instrumentation systems, wave generation,
modulation, dynamic gain setting, power measurement, and
computational circuits, as well as in artificial neural networks. There are two basic strategies to realize multiplication circuitry,
using signal processing, and
exploiting some nonlinear mechanism of the primitive
components.
In the following sections, we intend to provide a brief overview of both approaches.

Io

Io+

I1

I1+

I2

I2+

V 1

Signal Processing Multipliers. The most popular signal processing multiplier is the so-called pulse-modulation multiplier. It relies on the principle that the area under a rectangular pulse equals to the product of its amplitude and duration.
Thus, if the amplitude of a pulsed signal is made proportional
to one multiplicand, and the duty cycle proportional to the
other multiplicand, the area under the pulse-train becomes
proportional to the multiplication operation. Figure 15(a)
shows a voltage domain implementation of this concept based
on averaging. This is performed by a low-pass filter whose
input is a pulse-train Vt with amplitude proportional to Vx
and duty cycle proportional to Vy. This latter proportionality
is achieved through nonlinear sampling, by comparing Vy
with a time reference triangular (or saw-tooth) signal with
period T and amplitude V. If the variation rate of Vy is much
less than the averaging frequency f 1/T, then the duty cycle
of the control signal Vc and, therefore, of the pulse train Vt,
results in /T Vy /V. As a consequence, if the low-pass filter
has unity gain, the average output voltage of the filter reads
as

Vz =

VxVy
V

(13)

k
IB

IB
Vin

IB
I1 = I1+ I1

V 1

aIB

IB

I2 = I2+ I2
I1

I2

IB
0,0

IB

0,0
V 2

Vin

V A

ViA

V B

ViB

Vin

IB

IB

IoA

Io

IoB

Io = I1 + I2
Io

2IB

2IB

bIB

Io+

bIB

IB
Io

0,0
V 1

V 2

Vin

V 1 0,0

V 2

Vin

Figure 13. Transconductance circuits for bell-shaped function.

V = V A V B

Vin = ViA ViB

Figure 14. Gaussian function circuit with differential input.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

485

Vc
Vy

Vc
T

Vx

3T

Vy

Vz

Vt

2T

2T

3T

(a)

Vy

Vc

+ V
t
Vx

Vy
T
=
1+
2
V

Vz
+

Figure 15. Pulse-modulation multipliers:

(a) two-quadrant and (b) four-quadrant
realizations.

(b)

Note that the Vx multiplicand can be either positive or negative, but voltage Vy is limited to positive values, since the duty
cycle /T cannot be negative. Thus, the circuit in Fig. 15(a)
realizes two-quadrant multiplication. To extend its operation
to four-quadrant multiplication, a bipolar triangular waveform oscillating between V and V must be used (this
makes a zero Vy input corresponds to a 50% duty cycle), and
signal Vx must be sampled in balanced form, as shown in Fig.
15(b). Further details on the performance of pulse-modulation
multipliers are discussed in classical texts on analog computation (5). Also in Ref. 6, several configurations using
switched capacitor (SC) techniques are reported. In particular, some designs that avoid the use of external waveform references by applying feedback around the voltage comparator
are presented.
Figure 16(a) shows an alternative signal processing multiplier based on the transient evolution of linear circuits. For
reasons that will become apparent soon, this technique is referred to as temporal shaping. Again, voltage-mode operation
is assumed. The circuit in Fig. 16(a) uses two linear blocks
with normalized unit step response given by h1(t) and h2(t).
The last is driven by level Vx to obtain
Vt (t) = Vx h2 (t), 0 t <

V 
y

Vx

While switch S is closed, the output voltage Vz follows the

signal Vt. At t , that switch opens, and Vz is held to Vt().

Sample and
hold

Vz

h1(t)

Sample and
hold

Vz2

(a)

Vx

Vx

Vx

h2(t)

S2

Vxn

hn(t)

Vt2

Vtn
Sn
Vxn =

(15)

Vt

h2(t)

h1(t)

(14)

where denotes the amplitude of the time interval during

which the switch S remains closed. The other is driven by a
reference level V to render given by
h1
1

Vy

Sample and
hold

Vzn

Vx; n odd
Vx ; n even
(b)

Figure 16. Signal processing multipliers by shaping in time domain.

486

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

Thus, assuming both linear blocks are identical and the time
function invertible, one obtains

case, the linear blocks are selected to fulfill the condition,

h j (t) = h1j1 (t); j = 2, . . ., n

VxVy
Vz =
V

(17)

(16)

in the steady state situation. The simplest implementation of Fig. 16(a) uses integrators [i.e., hj(t) t] as linear
blocks (31). Another possibility uses exponential ramp generators with a normalized unit step response given by hj(t)
exp(t/Tj).
Interestingly enough, the principle can be extended to the
generation of powers of an input signal by higher-order shaping in time domain. This is illustrated in Fig. 16(b). In this

where hj( ) denotes the normalized unit step response of the

jth linear block. On the other hand, signals Vtj(t) take the
form

Vt j (t) =

j odd

|Vx |h j (t);

(18)

j even

for 0 t , and the time internal during which switches Sj

I1


Vx h j (t);

I3

Q1

Q3

I2

Io

Q2

Q4

+
(a)

Ix

Iy

Ix

kR

(1-k)R

+
R

Q1

Q1

(k-1) R

Q2

Q3

Q3

for k > 1

Iy
Q2

Iy

Ix

+
R

for 0 < k < 1

(b)

-kR
Q1

Q2

Q3

for k < 0
(c)
Figure 17. (a) Core block of a logantilog multiplier; (b), (c) circuits to elevate to a power.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

( j 2, . . ., n) are closed is defined as

= h1
1

where

|V | 
y

(19)

Combining the last three equations, the steady state value of

the output signals Vzj results in
Vz j
V

V j
x

; j = 2, . . ., n

(20)

There are various alternatives for the design of the linear

blocks under the restriction Eq. (17). One of them obtains the
linear block with unit step response hj(t) as a cascade of
j 1 integrators (31). Another alternative relies on the use of
time exponentials with scaled time constants, Tj T1 /( j 1)
for j 2, . . ., n. Realizations suitable for integrated circuits
of these time-function generators can be found in Refs. 6
and 32.
Another type of signal processing multiplier that operates
in the voltage-charge domain has been proposed in Ref. 33.
Its operation principle shares some properties from the aforementioned pulse modulation and temporal shaping concepts.
Instead of controlling the amplitude and duty cycle of a pulsetrain, the multiplier modulates the amplitude and decay
time of a single-sided exponential current pulse. The integral charge delivered by such a pulse is proportional to the
product of the peak amplitude and the decay time constant;
in other words,


t
Qz =
exp
u(t) dt =
(21)

0
where Qz is the charge delivered. Thus, if the amplitude of
the exponential pulse is made proportional to one multiplicand, Vx, and the decaying time constant is modulated by the
other multiplicand, Vy, the integral charge is proportional to
Vx Vy. An important feature of the multiplier in Ref. 33 is its
low device complexity and large modularity, which renders
its usage very well suited for the implementation of neural
network paradigms.
Other signal processing multipliers are based on the operation of the generalized integrator, which is an electronic circuit capable of integration with respect to a dependent variable. In the most general case, its functionality is described
by the integral


z(t) = z0 +

x(t )
x0

y(t)
d[x(t)]
(t)

(22)

where x(t), y(t), (t) 0, and z(t) are time-dependent signals

and x0 and z0 denote initial values at t 0. Proper usage of
generalized integrators allows the synthesis of any nonlinear
multivariate function z f(v1, v2, . . ., vn), including multiplication (6). The method simply consists of expressing the function (assumed real and analytic) as a closed set of ordinary
differential equations. These equations can be easily obtained
by successively differentiating f( ) as follows:

dz =

N

i=1

zi dvi

dzi =

N

j=1

zi j dv j

dzi j =

487

N


zi =

f
vi

zi j =

2 f
vi v j

zi jk =

3 f
vi v j vk

...

(24)

Because the terms on the right-hand side of the equations in

Eq. (23) have the same functional form as the integrand in
Eq. (23), function f( ) can be implemented as a network of
layered generalized integrators. In Ref. 6, different approaches for the design of generalized integrators using SC
techniques are reported. Also, in this reference, experimental
results from a four-quadrant multiplier built upon generalized integrators are presented.
Multipliers Based on Primitive Components. The intrinsic
continuous nonlinearities listed in Table 1 of the primitive
components display several mechanisms that are exploitable
to realize analog multipliers. In the following sections, we will
briefly discuss four different techniques for analog multiplication, each one exploiting a particular device functionality
from those listed in Table 1.
LogAntilog Multipliers. The logantilog class of multiplying structures is based on the exponential large signal
transconductances of the BJT and MOST, this last either in
the subthreshold or bipolar region (8). The principle arises
from the following basic relationships:
ln(xy) = ln(x) + ln(y)

(25)

exp[ln(xy)] = xy

which can be realized as shown in Fig. 17(a) for the bipolar

case (5). This circuit operates on positive terminal currents
(one-quadrant multiplication) to obtain Io (I1I2)/I3, which
can be understood from translinear circuit principles, by noting that the four base-to-emitter voltages define a translinear
loop which verifies
ln

I 
1

Is

+ ln

I 
2

Is

= ln

I 
3

+ ln

Is

I 
o

Is

(26)

The same circuit can be made to operate in four-quadrant

mode, though restricted to currents larger than IB, by driving each terminal with a bias current source of value IB. Note
that the circuit of Fig. 17(a) operates in current-mode. Voltage-to-current transformation can be achieved using linear
resistors and exploiting the virtual ground property of operational amplifiers. Applying this transformation, the circuit of

x
+

+
y

1/4

zi jk dvk

...

k=1

(23)

x
Figure 18. Conceptual block diagram of the quarter-square multiplier.

488

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

Io2

Io1

V1A

V1B

V1A

V1B

V2A

V2B

V2B

V2A

V1A,B = VC + V x /2
V2A,B = VC + V y /2

Io1

Squarer

Io2

Io = Io1 Io2

2
2
n [ (Vx Vy) /2 + 2VT ]

4 V xV y
n

Fig.2(a)

2
2
n [ (Vx + Vy) /2 + 2VT ]

Fig.2(b)

eq [ (Vx + Vy) 2/2 + 2VT,eq2 ]

eq [ (Vx Vy) 2/2 + 2VT,eq2 ]

4 eqVxVy

Fig.2(c)

2IQ + 4nA (Vx + Vy)2

2IQ + 4nA (Vx Vy)2

V V
nA x y

Figure 19. Quarter-square multipliers.

Fig. 17(a) can be understood as the connection of three logarithmic amplifiers like that in Fig. 1(a) (those comprising
transistors Q1, Q2, and Q3), and one exponential amplifier like
that in Fig. 1(b) (comprising transistor Q4). Extension of this
circuit structure to generate arbitrary powers is discussed in
Ref. 15. Figure 17(b) uses similar techniques by introducing
scaling factors in the translinear loop (34). If the resistor values are low enough to neglect the voltage drop caused by the
base current of transistor Q2 in the three configurations, and
all the transistors are identical, the functionality of the circuits results in
Iy
=
I

I k
x

(27)

Square-Law Multipliers. A second class of multiplying structures is based on the quadratic large-signal law governing
MOSTs in strong inversion and saturation. Most of the multipliers exploiting this quadratic law use the quarter-square
technique, which is derived from the following relationship:
z=

1
[(x + y)2 (x y)2 ] = xy
4

garding the squarers in Figs. 2(ac), it must be noted that

their associated output currents contain other undesired
terms, together with the difference-squared component,
which must be cancelled out in order to apply the quartersquare technique. This can be done using cross-coupled topologies and fully balanced input voltages, as shown schematically in Fig. 19. In this figure, the black boxes are symbols for
the squarers of Figs. 2(ac), and the output currents Io1 and
Io2 of the corresponding multipliers are indicated in the
attached table. Note that these currents are also balanced.
They can be subsequently transformed into an output voltage
by applying a symmetric resistive load to the multiplier block
or into a single-ended output current Io (see the fourth column
of the table in Fig. 19) by using current mirrors. These transformations realize, indeed, the difference and scaling operations on the right-hand side of the block diagram in Fig. 18.
Technical literature contains several examples meeting the
general architecture of Fig. 19. Examples are in Refs. 1618
and 35. In all cases, the valid operation range of the multipliers is dictated by the need to keep all the transistors of the
squaring blocks properly biased in the saturation region. For

(28)

The block diagram associated with this algebraic identity is

conceptually shown in Fig. 18. As can be seen, multiplication
is performed in three steps. First, the sum and differences of
the two input signals are formed. Then, these variables are
squared. Finally, the difference of the squared values is obtained and scaled to get the desired result.
Any of the squaring blocks of Figs. 2(ac) and 3 can be
used to implement the concept of Fig. 18. Quarter-square
multipliers based on the current mode squarers of Fig. 3 can
be synthesized in a straightforward manner, by exploiting the
Kirchhoff s current law (KCL) to obtain the sums and differences of the signals. Examples can be found in Ref. 22. Re-

Io1

Io2

I1

I2

I1+

I2+
+

Gm1

V1B

T1

Tuning
circuitry

V1A

T2

V2A

V2B

Gm2

V1A

V1B

Figure 20. Concept of the variable transconductance multiplier.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

instance, if the squarer of Fig. 2(a) is used, it can be shown

that the multiplier input voltages must verify Vx Vy
2VT, and similarly, for the squarer of Fig. 2(b), the operation
range reads Vx Vy 2VT,eq. In applications where this operation range must be further extended, active attenuators or
level shifters can be used.
Transconductance Multipliers. A direct, straightforward
technique to realize the four-quadrant multiplication function
exploits the possibility of tuning the gain of differential-input
transconductors through an electrical variable (current or
voltage). Although this feature is exhibited also by singleended transconductors, most practical realizations use differential-input blocks to reduce offset problems and enhance linearity (2). Figure 20 shows the general concept of the variable
transconductance multipliers. It consists of two identical
cross-coupled transconductor cells, driven by the input signals V1A and V1B, such that
Im1 = I1+ I1 = Gm1 (V1A V1B )
Im2 = I2+ I2 = Gm2 (V1A V1B )

and, similarly, for the nonseparable tuning circuitry

Io = Io1 Io2 = Im1 Im2 = 2km kg (V1A V1B )(V2A V2B ) (34)
Observe that in both cases, Io is proportional to the product of
the differential input voltages V1 V1A V1B and V2 V2A
V2B, thus leading to four-quadrant multiplication. Also, it is
worth noting that, for separable tuning circuits, the block in
Fig. 20 can be seen as a cross-coupled connection of a pair of
two-quadrant multipliers because g( ) is positive definite,
and the sign of the output current is uniquely determined by
the differential voltage V1.
Figure 21(a) shows an example of MOST separable tuning
variable transconductance multiplier where variables T1 and
T2 are in the form of currents (a similar bipolar counterpart
can be found in Ref. 2). If the input signal V1 is small as compared to n1T1 /1 and n1T2 /1, then the differential output
currents Imj ( j 1, 2) of the cross-coupled differential pairs

(29)
Io1

and a tuning circuit, controlled by the voltages V2A and V2B,

which defines the transconductance gains Gmj ( j 1, 2) in Eq.
(29) through the associated variables Tj. Usually, the transconductance gains Gmj takes the form,
Gm j = km g(Tj )

T2 = g1 [kg (VB + V2B )]

Io2
I1+

I2+
V1A

M1B

M1C

M1D

(30)
T2

T1

V2A
M2A

V2B
M2B

(a)

(31)
Io1

Io2
I1+

T2 = g1 [kg (VB + V2B V2A )]

I2
V1B

M1A

or

T1 = g1 [kg (VB + V2A V2B )]

I1

V1A

where km is a scaling factor; and g( ) is a real positive-definite, positive-valued invertible function whose argument is
the tuning variable Tj. Thus, for multiplication purposes, the
tuning circuitry must provide either of the two following output signal pairs:

T1 = g1 [kg (VB + V2A )]

489

(32)

where g1( ) is the (positive definite) inverse function of g( );

kg is another scaling factor; and VB is a bias voltage that can
be implicitly contained in the common-mode value of V2A and
V2B. Taking into account the role of control signals V2A and
V2B in the argument of the function g1( ), the tuning circuitry
defined by Eq. (31) will be referred to as separable, whereas
that described by Eq. (32), as nonseparable. These mathematical definitions have a direct physical counterpart, since separable tuning circuits, contrary to the nonseparable ones, are
built in practice using separate blocks.
For the separable tuning circuit, substituting Eq. (31) into
Eq. (30), and considering the characteristics in Eq. (29), the
differential output current of the block in Fig. 20, takes the
form
Io = Io1 Io2 = Im1 Im2 = km kg (V1A V1B )(V2A V2B ) (33)

V1A

I1

Q1A

I2
V1B

Q1B

T1

Q1C

I2+

Q1D

V1A

T2

V2A

V2B
Q2A

Q2B

IB

(b)
Figure 21. (a) MOS separable tuning variable transconductance
multiplier; (b) bipolar nonseparable tuning variable transconductance multiplier.

490

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

Vd1
V1A
V1B

1V
= VC +
2 x
1 V
= VC
2 x

Vd2

V1A

V1B
M1A

Vd1 = Vs1 + Vy

M1B

Io1

Io2
Vs1

Vd2 = Vs2 + Vy

Vs2

Vy < min { V1A VTo, V1B VTo }

(a)

1
V1A = VC +
V
2 x
1 V
V1B = VC
2 x

Vd1

V1A

M1A

Im j = I j+ I j =

n1

(V1A V1B )

2
(V VSS VTo )2
n2 2A

T2 = 2 (V2B VSS VTo )2

n2

(35)

(36)

which when compared to Eq. (31), gives VB (VSS VTo)

and kg 2 /n2. Therefore, taking into account Eq. (33), the
differential output current of the multiplier is given by
2

Vs1

M1D

Vs2

Io2

(b)

T1 =

M1C

max { Vd1 Vs1, Vd2 Vs2 } < min { V1A VTo, V1B VTo }

Comparing Eqs. (30) and (35), it is clear that function g( ) is

the square root operator. As was previously shown, its inverse
function (i.e., the squaring operator) can be implemented by
simply exploiting the quadratic law of MOSTs in the saturation region. Consequently, the tuning circuit may consist of
two voltage driven MOSTs as shown in Fig. 21(a). This gives
the following values for the biasing currents T1 and T2,

Io = Im1 Im2 =

M1B

Io1

Figure 22. Four-quadrant multiplier

cores using MOS transistors in the ohmic
region. (a) Basic differential architecture;
(b) cross-coupled quad configuration.

2 T

V1A
V1B

1V
Vd1 = Vs1 +
2 y

Vd2 = Vs2 1 Vy
2

can be approximated as

Vd2

1 2
(V V1B )(V2A V2B )
n1 n2 1A

(37)

Figure 21(b) shows a bipolar transconductance multiplier using a nonseparable tuning circuit (indicated by the shaded
areas). This multiplier architecture is commonly known as
Gilbert cell or Gilbert multiplier core (15). Observe that the
tuning mechanism is provided by a third differential pair

with a constant bias current. Assuming that the differential

output currents of the emitter-coupled pairs in Fig. 21(b) are
defined as shown in Fig. 11, the output current of the multiplier core reads as (2)
Io = IB tanh

V

V1B
2Ut

1A


tanh

V

V2B
2Ut

2A


(38)

thus, an approximately linear response is obtained whenever

the input signals V1 and V2 are small as compared to 2Ut.
Bipolar-like Gilbert cells have been also implemented in complementary metal oxide semiconductor (CMOS) technologies
using MOST operated in the weak inversion region (7), and
using compatible lateral bipolar transistors (36). An inconvenience of the Gilbert cell, particularly stressing in the MOST
version, is the high supply voltage requirements to bias the
stacked differential pairs, which render the structure poorly
suited for low-voltage applications. This can be solved by using folded circuits (37).
A major drawback of the circuits in Fig. 21 is the rather
small multiplication range. This makes the circuits only suitable for low-resolution applications as in artificial neural networks (38). In order to improve the linearity performance,
several strategies have been proposed, usually employing Gilbert cells. One technique consists of using differential active
attenuators at the input of the multiplier core to increase signal swing capabilities (39). Most often, a predistortion nonlinearity in series with the input signals are used in order to
achieve an ideal four-quadrant multiplier. This is, for instance, the approach followed in the classical Gilbert multi-

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

+
E

plier (2), where a bipolar Gilbert cell is linearized by using

tanh1 type predistortion. Application of this approach to
MOST Gilbert cells can be found in Ref. 40. A third technique
to increase the multiplier linearity consists on using linearized transconductors instead of basic differential pairs. For
instance, in Ref. 37 the upper differential pairs of a MOST
Gilbert cell have been replaced with adaptively biased MOST
saturated transconductors. The proposals in Refs. 19 and 41
substitute all the three differential pairs of a MOST Gilbert
cell with source-coupled linearized stages. Finally, the separable MOST transconductance multiplier of Fig. 21(a) can be
improved by replacing the basic differential pairs with voltage-biased common-source differential pairs so that the difference between their respective tail voltages is proportional to
V2 (42).
Ohmic Region Multipliers. A fourth class of analog multipliers exploits the large-signal transfer characteristic of MOST
in the ohmic region, which contains a term proportional to
the product of the gate voltage and the drain-to-source voltage drop. As usual, remaining terms can be cancelled out by
using differential structures.
The most simple triode multiplier capable of four-quadrant
operation consists of two matched MOSTs with identical
drain-to-source potential and driven by fully balanced gate
voltages. The circuit is shown in Fig. 22(a). One of the multiplicands (that controlling the drain-to-source voltage drop) is
single-ended, while the other (controlling the gate voltages) is
differential. Taking into account Table 1 and assuming Vs1
Vs2, the differential output current of the cell results in

Y
Z = (X/Y)
(a)
R2

R1

Vx

Vy

I2
Vz

I1

Vz = (Vx/Vy) (R2/R1)
(b)

Io

Vx

I1

+
Gm

Vz

Vy

491

Io

Io = Io1 Io2 = 21VxVy

(39)

Vz = Gm(Vx/Vy)
(c)
Figure 23. Division operator using a feedback multiplier: (a) concept; (b) with voltage multiplier and opamp; (c) with transconductance multiplier and amplifier.

thus achieving linear multiplication. The valid operation

range is indicated in the inset of Fig. 22(a). Practical usage of
this circuit requires some extra circuitry to properly define
the voltages at the source and drain terminals, regardless of
the currents flowing through the transistors. The most simple
alternative is by using low output impedance unity-gain buffers at the drain terminals of transistors M1A and M1B, as well
as, at the source nodes. This is, for instance, the approach
followed in Ref. 43 where the voltage follower action of the
buffers is enhanced using local feedback. To keep the drain

(N + 1)
Io
Isq

Iq

I1

I2

IN

Figure 24. CMOS self-biased Euclidean

distance circuit.

492

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

x1(e)

x2(e)

+
+

xN(e)

(a)

Mt1
I1* I2

I1

I2*

IN

IN*

I1* I2

I1

Mt2
I2*

Mt1

IN*

IN

Mt2

Mt N
A

Mb1

Mb2

A
MbN

IB

IB

(b)

(c)

Figure 25. Current-mode normalization circuits: (a) feedback concept; (b) BJT; (c) CMOS.

terminals equipotential, corresponding buffers must be driven

by the same voltage. Another approach to obtain a virtual
short between the drain terminals exploits the virtual ground
between the input nodes of voltage-mode opamps (44).
A main disadvantage of the multiplier in Fig. 22(a) is that
the magnitude of the differential output current given by Eq.
(39) will generally be small as compared to the individual current values of Io1 and Io2. As a consequence, the processing
circuitry driven by the multiplier (either a subtraction stage
or a common-mode cancellation structure) will suffer from appreciable errors, the larger as the common-mode to differential mode output current ratio increases. An alternative triode
multiplier, for which the magnitude of the differential signal
components are comparable to their common-mode value, is
shown in Fig. 22(b) (4547). This multiplier can be seen as a
cross-coupled connection of two circuits like those in Fig.
22(a), but with fully balanced drain-to-source voltage drops.
Assuming Vs1 Vs2, the differential output current of the multiplier in Fig. 22(b) is given by
Io = Io1 Io2 = 21VxVy

(40)

with the valid operation range indicated in the figure. Again,

the accuracy of the fully differential multiplier in Fig. 22(b)

strongly depends on the availability of low-impedance loading

stages to sink the output currents of the triode transistors. A
common strategy consists on using cascade devices with very
large transconductance on top of the ohmic transistors. Some
circuit solutions following this approach can be found in Refs.
48 and 49. Another possibility is to exploit the virtual ground
property of operational amplifiers, as proposed in Refs. 45 and
50. Interestingly enough, the circuit in Ref. 50 is able to perform several algebraic operations (multiplication, division,
square rooting, and voltage amplification) without the use of
any external dedicated circuitry.
Division
Most of the divider solutions found in the literature are based
on the multiplication circuitry presented in the previous section. In some cases, application is straightforward since the
scale factor of the multiplication is inversely proportional to
a third variable, which acts as the dividend. This occurs, for
instance, in the signal processing multipliers of Figs. 15 and
16, which can be employed for division by making the reference level V variable, or in the logantilog multiplier of Fig.
17(a), by making the current I3 to represent the denominator
of the divider.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

In cases where there is no explicit electrical variable to be

used as dividend, analog division can still be realized by
applying feedback around a multipliera similar strategy to
that applied for the obtention of the logarithmic and square
rooting operators. The concept is illustrated in Fig. 23(a); the
multiplier obtains E (ZY)/, and, for A , the feedback
forces X E. Thus, if Y 0, the circuit obtains Z (X/Y).
This concept of division is applicable regardless of the physical nature of the variables involved. In the special case where
E and X are current and Z is a voltage, the division can be
accomplished using KCL to yield X E. Figure 23(b) shows
a circuit for the case where the multiplication is in voltage
domain, and Fig. 23(c) is for the case where multiplication is
performed in transconductance domain. The transconductance gain for input Z of this latter case must be negative to
guarantee stability (51).

493

x1

u -( )

u -( )

x2

xN

u -( )
(a)

Collective Computation Circuitry

Radial basis functions and fuzzy inference require multidimensional operators to calculate radial distances in the case
of radial basis functions and to normalize vectors and calculate T-norms in the case of fuzzy inference. These operators
can be expressed as the interconnection of the nonlinear
blocks discussed previously or realized in simpler manner
through dedicated collective computation circuitry. Most of
these circuits operate intrinsically in current domain and are
worth mentioning because their simplicity and relevance for
parallel information processing systems.

I2

I1
Mt1

Mb1

IN

Io

Mt2

MtN

Mb2

Mc

VG

Mo

MbN
IB

Vector Magnitude. Figure 24 (52) shows a CMOS circuit to

compute the magnitude of an N-dimensional vector with current components Ik, which is based on the translinear current
squarer of Fig. 3(b). The configuration of transistors M2, M4,
and M5 of Fig. 3(b) is repeated N times with the N input currents to produce the total current Isq
Isq

1  2
= NIq +
I
4Iq k=1.N k

(41)

This current is used to self-bias the structure of Fig. 24 by

imposing, through the weighted p-channel current mirrors:
Iq =

Isq
Io
=
2
N+1

(b)

Figure 26. Concept for (a) maximum operator and (b) current-mode
realization.

where F( ) is an increasing monotonic function of xk, for 1

k N; E is a reference level; and is a scale factor. An elegant strategy to achieve Eqs. (44) and (45) uses feedback to
maintain constant the sum of components of vector x* (53).
Figure 25(a) illustrates the concept. Every xk, 1 k N, is
controlled by the error signal, e, at the differential amplifier

(42)

which yields, by introducing Eq. (41),

Io =

r

Ik2

Normalization Operation. The normalization circuit operation can be summarized by the following two expressions:

(43)

If the current Ik at each terminal is shifted through a bias

current of value k, the circuit serves to compute the Euclidean distance between the vector of input currents and the vector .

k=1,N

k=1.N

xk = F (xx ), xk = xk

|xx | =
xk = E

u +( )

u ( )

k+

x ,if k+ = k = 1
y=
x ,if k+ = k = 1

(44)
(45)

Figure 27. Generic full-wave rectifier. Positive and negative absolute value functions can be implemented as shown in the inset.

494

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

y
v2

v1

(a)

u +( )

k
+

+
v1

u +( )

+
v1

(b)

u +( )

+
u ( )

x
v1 + v2

v1

v2

(c)
v2

u +( )

u ( )
+
v2 v1

+
x

u ( )

u +( )

+
v1
(d)
Figure 28. (a)(d) PWL soft-sigmoid function realizations.

output. If the open-loop gain is large enough and the loop stable, feedback forces the differential amplifier input to zero,
and consequently x*k (e*) 1, where e* is the steady-state
value of the differential amplifier output. Unfortunately, the
transient response of this normalization scheme is rather
poora negative consequence of feedback.

Figure 25(b,c) show circuit solutions, for the BJT (15) and
CMOS (28) case, respectively, which normalize an input current vector, I, without explicit feedback, and hence yield much
better transient response than the previous proposal. Their
operation is based on the translinear principle. Let us consider the BJT case. Assuming that all transistors are identi-

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

k = k2

k+ = k1

495

k1

x
+

k1

k2

k2

k = k2
k+ = k1
(a)

MIN

MAX

+
v1

v2

Figure 29. PWL soft-sigmoid function realizations based on (a) full-wave rectifiers;
(b) max-min operators.

(b)

cal, the voltage drop between the common emitter nodes A

and B verifies

VA VB = kT ln

Ik


kT ln

Is

Ik
Is


= kT ln


Ik
Ik


(46)

for 1 k N. Since this voltage drop is the same for all

transistor pairs, Eq. (44) is met. Simultaneously, KCL forces
the sum of all the output vector components to be equal to the
bias current IB (ignoring base currents), and thus we have
Ik = 

Ik
j=1,N

(47)

Ij

which is the intended operation. For the MOST circuit of Fig.

25(c), the translinear principle gives

VA VB =
which yields

Ik =

t
I
b k

1+

I
I

Ik

(VA VB )

(49)

Summing for all k, as in Eq. (45), and after some algebra, the
following expression is obtained for F( ):

Ik

= F (II ) = t Ik
b

(II )
1+
Ik

(II ) =

k=1,N

u

u

u
I
I
N
u

1
u1 +


t

Ik

k=1,N
2

(51)

k=1,N

Note that Eq. (45) is always fulfilled because I* IB; however, Eq. (44) is only verified if the quotient (I)/ Ik in Eq.
(50) is the same for all k. This occurs only if the input currents are already normalized; we have Ik (b /t)IB and
then (I) 0. Otherwise, depending on how Ik differs from
(b /t)IB, the proportionality constant becomes more and
more k-dependent and deviations from Eq. (44) increase. Nevertheless, proper design obtains quasilinear transformation
of Ik into I*k , which can be tolerated in most neurofuzzy systems, where nonlinearities are corrected through adaptation.

(48)

2
b

with,

Minimum and Maximum Operators. The calculation of the

minimum of an input vector x is functionally equivalent to
obtaining the complement of the maximum of the complements of its components. Thus, only maximum operators will
be considered hereafter. Figure 26(a) illustrates a classical
approach used in analog computation to calculate the maximum of an input vector x. It is based on the following steady
state equation (4):
y +

u [A(xk y)] = 0

(52)

k=1,N

2
(50)

where A is large and function u_( ) is defined in Eq. (5). This

concept can be realized in practice using operational trans-

496

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

conductance amplifiers (OTAs) or opamps, and diodes. Both

of these have voltage input and output. An alternative
maximum/propagate concept realizes the following equation:
y +

xk uo (xk y) = 0

(53)

k=1,N

where uo( ) is the threshold operator (Heaviside function),

which can be easily implemented in the current domain by
using current comparators (28). Unfortunately, both approaches exhibit a rather slow transient response as a consequence of the feedback mechanism used.
Another solution, which avoids this lack of operation
speed, is shown conceptually in Fig. 26(b). It is based on the
winner-take-all circuit of Lazzaro et al. (28,54) and exploits
the characteristics of MOSTs operating in ohmic region; in
particular, the possibility to reduce its current density by
driving it with small drain-to-source voltages. The operation
of the circuit is as follows. First, note that all transistors
Mbk, for k 1, . . ., N, have the same gate-to-source voltage
Vgs, which is also shared by the output transistor Mo. The
steady state value of this voltage is set by the largest input
current Ik,max as
Vgs = VTo +

nI

k,max

replication to drive the half-wave rectifiers, which require additional circuitry if x is in current form. This can be solved by
using the circuit of Fig. 28(c) which uses nested rectifications.
Observe that the circuit achieves the intended functionality
with a minimum number of block elements and, in this sense,
it can be regarded as canonical. The circuit in Fig. 28(d) is
also based on nested rectifications, but it is not canonical.
Anyway, because its symmetry, it leads to very modular implementations particularly using current-mode techniques.
Other signal limiter realizations employ building blocks
other than the basic rectifier circuits defined in Eq. (7). Some
examples are shown in Fig. 29. That in Fig. 29(a) obtains the
PWL soft-sigmoid function by adding the output signals of
two shifted odd-symmetric full-wave rectifiers. According to
Fig. 28(a) and the characteristic decomposition at the right of
Fig. 29(a), the slope of the central piece of the sigmoid is given
by k k1 k2. The circuit of Fig. 29(b) are based on the
maximum and minimum operators described in the previous
section.
Figure 30(b,c) shows two simple block diagrams, based on
the full-wave rectifiers devised in Fig. 27, for the Hermite linear basis functions represented in Fig. 30(a). In both cases,
the desired characteristic is obtained by shifting the full-wave
rectification map along the y axis by an amount equal to the

(54)
y

where b is the transconductance factor of transistors Mbk. All

bottom transistors are driven by this common voltage to draw
the maximum current Ik,max, while the externally applied current may be smaller than Ik,max. Thus, the gate of each top
transistor, Mtk, becomes an error-sensitive node that detects
differences between corresponding external current and the
maximum current. If Ik Ik,max, the error current Ik Ik,max is
integrated in the gate-to-source capacitor of transistor Mtk,
the corresponding voltage drop decreases and consequently,
the drain-to-source voltage of the associated bottom transistor Mbk decreases until the transistor enters in ohmic region
and the error current becomes null.

k2

k1

(a)

k = k1
k+ = k2

DERIVED PIECEWISE NONLINEAR OPERATIONS

As previously stated, the rectifier blocks devised in the section
entitled Rectification can serve as basic building blocks for
the realization of many elementary piecewise linear functions. Synthesis strategies for the implementation of the most
common PWL nonlinearities (absolute value, saturation, basis functions, etc.) are detailed in the following.
Regarding the absolute value function, Fig. 27 shows a
general realization that allows one to control the slopes of the
characteristic, as well as, the position along the x axis. If an
offset value along the y axis is also required, a constant contribution must be added to the rightmost summer. This kind
of circuit is commonly known as a full-wave rectifier. Figure
28 shows some implementations of the PWL soft-sigmoid
function represented in Fig. 28(a). These circuits are also
known as signal limiters. The circuit in Fig. 28(b) is built
upon the characteristic decomposition shown at the right of
the figure, based on the extension operator formulation. An
inconvenience of this architecture is the need for input signal

u ( )

v
(b)

k = k1
k+ = k2

(c)

Figure 30. Linear basis functions.

u +( )

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

497

y
k2

v
k1

b1

3 4

k1

u +( )

+
b2

+
+

b3

+
u ( )

3=

b3

k2

4=

b4

k2

k2

b2

k1

S = (b2 b1) = (b4 b3)

+
b4

2=

y
+

k2

b1

k1

u ( )

k1

1=

u +( )

(a)

u +( )

k2
+

+
v

u ( )

+
u ( )

k1

2
(b)
Figure 31. Trapezoidal membership functions.

height of the basis function and then rectifying in the proper

direction to obtain the triangular inputoutput representation.
Finally, Fig. 31 shows some implementations of trapezoidal membership functions based on half-wave rectifiers. The
circuit in Fig. 31(a) is a direct realization of the characteristic
decomposition in extension operators. A more simple circuit
can be obtained by nested rectifications. Figure 31(b) shows
an example based on the expression
y = u [k2 u+ (x 3 ) k1 u (x 2 ) v]

(55)

which allows saving functional blocks as compared to Fig.

31(a).

Alternative realizations of the trapezoidal membership

functions are shown in Fig. 32. That in Fig. 32(a) is similar
to the architectures used for linear basis functions but with
an additional nested rectification. Of course, a dual implementation starting from a negative full-wave rectifier is also
possible. The circuit in Fig. 32(b) obtains the trapezoidal function by adding the outputs of two PWL soft-sigmoid blocks
with central slopes of opposite signs. Finally, the implementation in Fig. 32(c) is a combination of two shifted Hermite linear basis functions with identical height, in order to obtain a
flat response between the breakpoints 2 and 3. Other realizations of trapezoidal functions consist of combinations of
sigmoid characteristics or linear basis functions with maximum and/or minimum operators.

498

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

v
k2
k1

k = k1
k+ = k2

x
h

u +( )

u -( )

v
(a)

y
v
+
x

v/2
y

v/2

(b)

y
v
+
x

+
x

(c)
Figure 32. Alternative trapezoidal membership function implementations.

As an example of application of the preceding synthesis

strategy for PWL functions, Fig. 33 shows an extensive catalog of circuit solutions (24) based on the current feedback
comparators, which are represented as square boxes. They
have three terminals corresponding to the input and drain
nodes of the comparator and, in some cases, a fourth terminal
for the binary signal Vs. On the other hand, triangular blocks
represent tunable current amplifiers with gain k 0, where

the flow of the output current can be made positive or negative according if the binary control signal s is in the high or
low state.
Figure 33(a) shows the construction of the positive concave
and convex extension operators and Fig. 33(b), the realization
of the positive full-wave rectification function. In both cases,
negative functions can be easily obtained by driving the current amplifiers with complemented binary signals.

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

499

s
k

Iin

Io

Iin

Io
k
I
I

Io

Io

Iin

Iin

(a)
s

k1

Io

Iin

k2

Io
s
k1
k2

Iin

I
s
(b)

s
s

k1

Io
s

Iin

Io

Iv

Iv

k2
k1

s
I

k2

Iin

s
(c)
Figure 33. Block diagrams for (a) concave and convex extension operators; (b) full-wave rectification; (c) Hermite linear basis function. Block diagrams for (d) dead-zone nonlinearity; (e) soft
limiter function; (f) discontinuous function; and (g) trapezoidal function. (Figure continues on
next page.)

Figure 33(c) shows the block diagram for a linear basis

function formed by three current comparators, two current
amplifiers, and four analog switches in the output stage. Note
that the central current comparator provides the binary signal that determines the sign of the current amplifiers and the
output branch through which Io flows.

Figure 33(d) shows a realization for the dead-zone nonlinearity. In this case, binary signals to the current amplifiers
are externally supplied, resulting in a complete control on the
slopes of the characteristic.
Figure 33(e) shows the implementation of a soft limiter
characteristic, which comprises three current comparators

500

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

c1
Iv1
k1

k2
Io

Iin

Io

I v1

I
k1

k2

Iin

+ I v2

Iv2
c2
(d)
Iv1
Io
kIv1
Iin

I Iv1

Io
k

Iin
c

I + Iv2

kIv2

I
Iv2
(e)
Iv1
s1
s2

s1

Iin

Io
kIv1

Io

w
k

Iin

s2
c

kIv2

I
Iv2
(f)

s
Iv1
k1

s
s

Iin
Iv

Io
Io

k2

Iv

s
s

k1
Iin

k2

I Iv1

Iv2
s
(g)
Figure 33. (Continued)

I + Iv2

NONLINEAR CIRCUIT SYNTHESIS USING INTEGRATED CIRCUITS

501

and one current amplifier. This realization is inspired by the

block diagram of Fig. 28(d), the only difference being that current amplification is performed at the backend of the circuit.
Relevant features of the circuit are its low area consumption
(bear in mind that current comparators may consists of just
six transistors if the voltage amplifier is implemented with a
CMOS inverter), high-speed operation (no nodal saturation
takes place), and high precision (errors in the rectification
knots are in the order of few picoamperes).
Figure 33(f) shows an example of construction of functions
with finite jump discontinuity, taking advantage of the binary
signal generated by the current comparators, together with
the logic gates.
Finally, Fig. 33(g) shows the realization of a trapezoidal
function. The architecture is similar to that in Fig. 31(b). Note
that instead of using two linear basis function like those in
Fig. 32(c), the function symmetry enables the number of circuit components to be reduced.

18. Z. Wang, A four-transistor four-quadrant analog multiplier using

MOS transistors operating in the saturation region, IEEE Trans.
Instrum. Meas., IM-42: 7577, 1993.

BIBLIOGRAPHY

25. A. Rodrguez-Vazquez and M. Delgado-Restituo, Generation of

chaotic signals using current-mode techniques, J. Intelligent
Fuzzy Syst., 2: 1537, 1994.

1. J. Singh, Semiconductor Devices: An Introduction, New York:

McGraw-Hill, 1994.
2. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., New York: Wiley, 1993.
3. A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design,
New York: Wiley, 1984.
4. A. Hausner, Analog and Analog/Hybrid Computer Programming,
Englewood Cliffs, NJ: Prentice-Hall, 1971.

19. E. Seevinck and R. F. Wassenar, A versatile CMOS linear

transconductor/square-law function circuit, IEEE J. Solid-State
Circ., SC-22: 366377, 1987.
20. J. S. Pena-Finol and J. A. Connelly, A MOS four-quadrant analog
multiplier using the quarter-square technique, IEEE J. SolidState Circ., SC-22: 10641073, 1987.
21. I. M. Filanovsky and H. P. Baltes, Simple CMOS analog squarerooting and squaring circuits, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., CAS-39: 312315, 1992.
22. R. Wiegerink, Analysis and Synthesis of MOS Translinear Circuits, Boston: Kluwer, 1993.
23. B. Razavi, Principles of Data Conversion System Design, Piscataway, NJ: IEEE Press, 1995.
24. A. Rodrguez-Vazquez et al., High-resolution CMOS current comparators: Design and applications to current-mode function generation, Analog Integrated Circuits and Signal Processing, 7: 149
166, 1995.

26. Z. Wang, Novel pseudo RMS current converter for sinusoidal signals using a CMOS precision current rectifier, IEEE Trans. Instrum. Meas., IM-39: 670671, 1990.
27. B. J. Hosticka et al., Design of nonlinear analog switched-capacitor circuits using building blocks, IEEE Trans. Circuits Syst.,
CAS-31: 354368, 1984.

5. D. H. Sheingold, Nonlinear Circuits Handbook, Norwood, MA:

Analog Devices, 1976.

28. F. Vidal and A. Rodrguez-Vazquez, Using building blocks to design analog neuro-fuzzy controllers, IEEE Micro, 15 (4): 4957,
1995.

6. R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and

Continuous-Time Integrated Circuits and Systems, Berlin:
Springer-Verlag, 1989.

29. T. Yamakawa, A fuzzy inference engine in nonlinear analog mode

and its application to fuzzy control, IEEE Trans. Neural Netw.,
4: 496522, 1993.

7. C. Mead, Analog VLSI and Neural Systems, Reading, MA: Addison-Wesley, 1989.

30. P. W. Hollis and J. J. Paulos, Artificial neural networks using

MOS analog multipliers, IEEE J. Solid-State Circ., SC-25: 849
855, 1990.

8. E. Vittoz, Analog VLSI signal processing: Why, where and how?,

Analog Integrated Circuits and Signal Processing, 6: 2744, 1994.
9. A. Rodrguez-Vazquez et al., Synthesis and design of nonlinear
circuits, in W. K. Chen (ed.), The Circuits and Filters Handbook,
Boca Raton, FL: CRC Press 1995.
10. B. J. Sheu and J. Choi, Neural Information Processing and VLSI,
Boston: Kluwer, 1995.
11. J. W. Fattaruso and R. G. Meyer, MOS analog function synthesis,
IEEE J. Solid-State Circ., SC-22: 10591063, 1987.
12. K. Kimura, A CMOS logarithmic IF amplifier with unbalanced
source-coupled pairs, IEEE J. Solid-State Circuits, SC-28: 78
83, 1993.
13. C. Turchetti and M. Conti, A general approach to nonlinear synthesis with MOS analog circuits, IEEE Trans. Circuits Syst. I,
Fundam. Theory Appl., CAS-40: 608612, 1993.
14. E. Seevinck, Analysis and Synthesis of Translinear Integrated Circuits, Amsterdam: Elsevier, 1988.
15. B. Gilbert, Current-mode circuits from a translinear viewpoint: A
tutorial, in C. Toumazou, F. J. Lidgey, and D. G. Haigh (eds.),
Analogue IC design: The current-mode approach, London: Peregrinus, 1990.
16. H.-J. Song and C.-K. Kim, An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers, IEEE J. Solid-State Circ., SC-25: 841848, 1990.
17. Y. H. Kim and S. B. Park, Four-quadrant CMOS analogue multiplier, Electron. Lett., 28: 649650, 1992.

31. D. Broadarac et al., Novel sampled-data MOS multiplier, Electron. Lett., 18: 229230, 1982.
32. C. Jansson, K. Chen, and C. Svensson, Linear, polynomial and
exponential ramp generators with automatic slope adjustment,
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., CAS-41:
181185, 1994.
33. L. W. Massengill, A dynamic CMOS multiplier for analog VLSI
based on exponential pulse-decay modulation, IEEE J. SolidState Circ., SC-26: 268276, 1991.
34. X. Arreguit, E. Vittoz, and M. Merz, Precision compressor gain
controller in CMOS technology, IEEE J. Solid-State Circ., SC-22:
442445, 1987.
35. K. Bult and H. Wallinga, A class of analog CMOS circuits based
on the square-law characteristics of an MOS transistor in saturation, IEEE J. Solid-State Circ., SC-22: 357365, 1987.
36. T. Pan and A. A. Abidi, A 50-dB variable gain amplifier using
parasitic bipolar transistors in CMOS, IEEE J. Solid-State Circ.,
SC-24: 951961, 1989.
37. J. N. Babanezhad and G. C. Temes, A 20-V four quadrant CMOS
analog multiplier, IEEE J. Solid-State Circ., SC-20: 11581168,
1985.
38. F. J. Kub et al., Programmable analog vector-matrix multipliers,
IEEE J. Solid-State Circ., SC-25: 207214, 1990.
39. S. Qin and R. L. Geiger, A 5-V CMOS analog multiplier, IEEE J.
Solid-State Circ., SC-22: 11431146, 1987.

502

NONLINEAR CONTROL SYSTEMS, ANALYTICAL METHODS

40. D. C. Soo and R. G. Meyer, A four-quadrant NMOS analog multiplier, IEEE J. Solid-State Circ., SC-17: 11741178, 1982.
41. S. L. Wong, N. Kalyanasundaram, and C. A. T. Salama, Wide
dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages, IEEE J. Solid-State Circ., SC21: 11201122, 1986.
42. K. Kimura, An MOS four-quadrant analog multiplier based on
the multitail technique using a quadritail cell as a multiplier
core, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., CAS42: 448454, 1995.
43. S.-I. Liu, Low voltage CMOS four-quadrant multiplier, Electron.
Lett., 30: 21252126, 1994.
44. M. Ismail et al., Configurable CMOS multiplier/divider circuits
for analog VLSI, Analog Integrated Circuits and Signal Processing, 5: 219234, 1994.
45. B. Song, CMOS RF circuits for data communication applications,
IEEE J. Solid-State Circ., SC-21: 310317, 1986.
46. Z. Czarnul, Novel MOS resistive circuit for synthesis of fully integrated continuous-time filters, IEEE Trans. Circuits Syst., CAS33: 718721, 1986.
47. M. Ismail, Four-transistor continuous-time MOS transconductor,
Electron. Lett., 23: 10991100, 1987.
48. A. L. Coban and P. E. Allen, Low-voltage, four-quadrant, analogue CMOS multiplier, Electronics Lett., 30: 10441045, 1994.
49. T. Botha, CMOS analogue current-steering multiplier, Electron.
Lett., 28: 525526, 1992.
50. N. I. Khachab and M. Ismail, A nonlinear CMOS analog cell for
VLSI signal and information processing, IEEE J. Solid-State
Circ., SC-26: 16891699, 1991.
51. E. Sanchez-Sinencio et al., Operational transconductance amplifier-based nonlinear function synthesis, IEEE J. Solid-State Circ.,
SC-24: 15761586, 1989.
52. O. Landolt, E. Vittoz, and P. Heim, CMOS Self-biased Euclidean
distance computing circuit with high dynamic range, Electron.
Lett., 28: 352354, 1992.
53. M. Sasaki, Current-mode analog fuzzy hardware with voltage input interface and normalization locked loop, IEICE Trans. Fundamentals, E75-A: 650654, 1992.
54. J. Lazzaro et al., Winner-take-all networks of O(n) complexity, in
D. S. Touretzky (ed.), Advances in Neural Information Processing
Systems, Vol. 1, Los Altos, CA: Morgan Kaufmann, 1989.

MANUEL DELGADO-RESTITUTO
Institute of Microelectronics of
Seville

FERNANDO VIDAL
University of Malaga

ANGEL RODRIGUEZ-VAZQUEZ
Institute of Microelectronics of
Seville

226

CHAOTIC CIRCUIT BEHAVIOR

CHAOTIC CIRCUIT BEHAVIOR

Many physical systems exhibit steady-state behavior that is
oscillatory but not periodic. Until recently, such behavior was
thought to be due to some inherent source of randomness in
the system and was classified as noise. Chaos refers to nonperiodic asymptotic behavior in systems that are completely
deterministic. This article describes a number of simple deterministic electronic circuits that exhibit chaos.
Since the pioneering days of electronics in the 1920s, dc
equilibrium, periodic, and quasi-periodic steady-state solutions of electronic circuits have been correctly identified and
classified. By contrast, the existence of chaos has been widely
acknowledged only in the past 30 years.
Even though the notion of chaotic behavior in dynamical
systems has existed in the mathematics literature since
Poincares work at the turn of the century, unusual behavior
in the physical sciences as recently as the 1970s was being
described as strange (1). Today we classify as chaos bounded
recurrent motion in a deterministic dynamical system that is
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CHAOTIC CIRCUIT BEHAVIOR

characterized by sensitive dependence on initial conditions

(2,3).
Although the future behavior of a chaotic system is in principle determined exactly by the initial conditions, sensitive
dependence on initial conditions means that the precision
with which these conditions must be specified grows exponentially with the length of the prediction. Thus a real chaotic
system appears to exhibit randomness in the time domain
because its initial conditions cannot be specified with sufficient precision to make accurate long-term predictions of its
behavior.
The earliest experimental observations of chaos in electronic circuits were in forced nonautonomous nonlinear oscillators, including the sinusoidally excited neon bulb relaxation
oscillator studied by van der Pol and van der Mark (4,5), the
forced negative-resistance oscillator of Ueda (6) and the
driven series-tuned RL-diode circuit (79). More recently
chaos has been observed and studied in a variety of unforced
autonomous electronic circuits such as Chuas oscillator (10
12), hysteresis oscillators (1315), classical circuits such as
the Colpitts oscillator (16,17) and the phase-locked loop (18),
and a number of important discrete-time systems, including
switched capacitor circuits (19), dcdc converters (20,21), digital filters (22), and sigma-delta modulators (23).
In the following sections we discuss a number of autonomous and nonautonomous chaotic circuits. While exhibiting a
rich variety of complex dynamical behaviors, these circuits
are simple enough to be constructed and modeled using standard electronic parts and simulators.
CHAOTIC CIRCUITS
Chaos may be defined as bounded steady-state behavior in a
deterministic dynamical system that is not an equilibrium
point, not periodic, and not quasi-periodic (24).
Solutions of a dissipative deterministic dynamical system
eventually settle into regions of the state space called at-

Er(P+)

(a)

tracting limit sets or attractors. Electronic circuits are typically dissipative due to resistive heating losses; consequently,
their long-term behavior is usually characterized by motion
on attractors. Here, we consider only dissipative circuits.
Attracting equilibrium point, periodic, and quasi-periodic
solutions of deterministic dynamical systems have the property that trajectories from nearby initial conditions that converge to the same limit set become correlated with time. By
contrast, two trajectories started close together on an attracting chaotic limit set diverge exponentially and soon become uncorrelated; this is called sensitive dependence on initial conditions and gives rise to long-term unpredictability.
Technically a chaotic circuit is one whose steady-state behavior is characterized by one or more positive Lyapunov exponents. Lyapunov exponents characterize the average exponential rate of separation of trajectories of a dynamical
system on the attractor. Negative Lyapunov exponents cause
trajectories to converge with time. If an attractor has a positive Lyapunov exponent, then nearby trajectories on the attractor are separated, on average, along some direction. In
practical terms, this means that trajectories of the circuit are
unstable yet bounded. Instability means that nearby trajectories diverge on average, and boundedness implies that they
remain in some finite volume of the state space.
How can nearby trajectories diverge exponentially and yet
remain within a bounded limit let? This may be achieved by
repeated stretching and folding of the flow, as shown in Fig. 1.
Consider the spiral attractor shown in Fig. 1. A trajectory
spirals away from the equilibrium point P along the plane
Ec(P) until it enters the D0 region, where it is folded back
into D1 and returns to the plane Ec(P) close to P. The recurrent stretching and folding continues ad infinitum, producing
a chaotic steady-state solution (12).
Note that two trajectories passing very close to X0 on
Ec(P) are separated quite dramatically when they cross the
plane U1 and enter D0. By the time they return to D1, they
are no longer close. This illustrates sensitive dependence on
initial conditions.

(b)

Ec(P+)

V1
P+
Er(0)

D1

V2

D0

D-1

U1
Ec(0)

I3

P-

227

U-1

X0
Ec(P-)

Er(P-)
Figure 1. Stretching and folding mechanism of chaos generation in Chuas oscillator. (a) Simulated spiral chaotic attractor showing affine regions (D1 and D1), separating planes (U1 and
U1), equilibrium points (P, 0, and P), and their associated eigenspaces (Er and Ec). (b) Experimentally observed attractor. Vertical axis: V1 (1 V/div); horizontal axis: V2 (200 mV/div). Positivegoing intersections of the trajectory through the plane defined by I3 1.37 mA are shown highlighted.

228

CHAOTIC CIRCUIT BEHAVIOR

(a)

(b)

(c)

(d)

Figure 2. Experimental manifestations of chaos in the double-scroll attractor from Chuas oscillator (R 1800 , C1 9.4 nF) (a) Two-dimensional projection of the attractor in state space;
vertical axis: V1 (1 V/div); horizontal axis: V2 (200 mV/div). (b) Time-domain waveforms. Upper
trace: V1(t) (2 V/div); lower trace: V2(t) (500 mV/div); horizontal axis: t (2 ms/div). (c) Power
spectrum of V2(t). Vertical axis: power (dB); horizontal axis: frequency (kHz). (d) Time-domain
waveforms showing sensitivity to initial conditions. Vertical axis: V1(t) (2 V/div); horizontal axis:
t (500 s/div).

Chaos is characterized by repeated stretching and folding

of a bundle of trajectories in state space. In the time domain
a chaotic trajectory is neither periodic nor quasi-periodic but
looks unpredictable in the long term. This long-term unpredictability manifests itself in the frequency domain as a broad
noiselike power spectrum (25).
Figure 2 shows experimental manifestations of chaos in
the well-known double-scroll chaotic attractor from Chuas oscillator (26).

In this section we consider three important classes of autonomous electronic circuits: Chuas oscillator, Saitos hysteresis oscillator, and the Colpitts oscillator.
Chuas Oscillator
Chuas oscillator (shown in Fig. 3) consists of a linear inductor, two linear resistors, two linear capacitors, and a single
voltage-controlled nonlinear resistor NR, called a Chua diode
(1012). NR is a voltage-controlled piecewise-linear resistor

CHAOS IN AUTONOMOUS ELECTRONIC CIRCUITS

R

In order to exhibit chaos, an autonomous circuit consisting of

resistors, capacitors, and inductors must contain (1) at least
one active resistor, (2) at least one nonlinear element, and
(3) at least three energy-storage elements. The active resistor
supplies energy to separate trajectories, the nonlinearity provides folding, and the three-dimensional state space permits
persistent stretching and folding in a bounded region without
violating the noncrossing property of trajectories.

IR

L
I3
R0

C2

V2
_

V1

C1

VR

Figure 3. Chuas oscillator.

NR

CHAOTIC CIRCUIT BEHAVIOR

IR

Gb

(Gb Ga)E
E

Ga
0

(Ga Gb)E

VR

E
Gb

229

transforms a limit cycle into one at half the frequency,

spreading the energy of the system over a wider range of frequencies. An infinite cascade of such doublings results in a
chaotic trajectory of infinite period and a broad frequency
spectrum that contains energy at all frequencies. Figure 5 is
a set of snapshots of the period-doubling route to chaos in
Chuas oscillator.
Bifurcation Diagrams

Figure 4. The VI characteristic of the nonlinear resistor NR in

Chuas oscillator has breakpoints at E and slopes Ga and Gb in the
inner and outer regions.

(27) whose continuous odd-symmetric three-segment VI

characteristic (shown in Fig. 4) is defined explicitly by the
relationship
IR = GbVR + 12 (Ga Gb )(|VR + E| |VR E|)

While state-space, time-, and frequency-domain measurements are useful for characterizing steady-state behaviors,
nonlinear dynamics offers several other tools for summarizing
qualitative information concerning bifurcations.
A bifurcation diagram is a plot of the attractors of a system
versus a control parameter. For each value of the control parameter, called the bifurcation parameter, one plots samples
of a state of the system. In the case of a fixed point, all samples are identical and the attractor appears on the bifurcation
diagram as a single point. If a periodic solution is sampled
synchronously, the attractor appears in the bifurcation diagram as a finite set of points. A periodic solution consisting of

Chuas oscillator is described by three ordinary differential

equations:

dV1
G
1
=
(V V1 )
f (V1 )
dt
C1 2
C1
dV2
G
1
=
(V V2 ) +
I
dt
C2 1
C2 3
1
R
dI3
= V2 0 I3
dt
L
L
where G 1/R and f(VR) GbVR 
(Ga Gb)(VR E
VR E).
Chuas circuit is a special case of Chuas oscillator where
R0 0 (11,12). In practice, an inductor typically has a nonzero
series parasitic resistance, implying that R0 0. Therefore
we consider only the general case of Chuas oscillator.
The primary motivation for studying Chuas oscillator is
that it can exhibit every dynamical behavior known to be possible in an autonomous three-dimensional continuous-time
dynamical system described by a continuous odd-symmetric
three-region piecewise-linear vector field. In particular, it can
exhibit equilibrium point, periodic, quasi-periodic, and chaotic
steady-state solutions. The oscillator is also useful in studying
bifurcations and routes to chaos. A user-friendly program for
studying chaos in Chuas circuit is available (28).
A bifurcation is a qualitative change in the behavior of a
system (2). One of the most familiar bifurcations in electronic
circuits is the Hopf bifurcation, where a circuit that had been
at an equilibrium point begins to oscillate when a parameter
is increased through some critical value called a bifurcation
point.
A well-defined sequence of bifurcations that takes a system
from dc or periodic behavior to chaos is called a route to chaos.
With appropriate choices of its component values, Chuas oscillator can follow the period-doubling, intermittency, or
quasi-periodic route to chaos.
Example: Period-Doubling Route to Chaos in Chuas Oscillator. The period-doubling route to chaos is characterized by a
cascade of period-doubling bifurcations. Each period-doubling

6
4
2
0
-2
-4
-6

V1

V2

I3

10

10

10

10

10

10

10

10

0
-20
-40
-60
-80
-100

(a)
6
4
2
0
-2
-4
-6

V1

V2

I3

0
-20
-40
-60
-80
-100

(b)
6
4
2
0
-2
-4
-6

V1

V2

I3

0
-20
-40
-60
-80
-100

(c)
6
4
2
0
-2
-4
-6

V1

V2

I3

0
-20
-40
-60
-80
-100

(d)

Figure 5. Period-doubling in Chuas oscillator with L 18 mH,

R0 12.5 , C2 100 nF, Ga 50/66 mS 757.576 S, Gb
9/22 mS 409.091 S, and E 1 V. Simulated state space trajectories (left), time waveforms V1(t) (top right), and power spectra of
V2(t) (bottom right). (a) G 530 S: periodic steady state; (b) G
537 S: period two; (c) G 539 S: period four; (d) G 541 S:
spiral chaotic attractor.

230

CHAOTIC CIRCUIT BEHAVIOR

Dynamics of D0

Chua's oscillator
4.6
4.5
4.4
V1(V)

4.3
4.2
4.1
4
3.9
3.8
0.000533

0.000538
G (S)

0.000543

A trajectory starting from some initial state in the D0 region

may be decomposed into its components along the plane Ec(0)
and the vector Er(0). When 0 0 and 0 0, the component
along Ec(0) spirals toward the origin along this plane, while
the component in the direction Er(0) grows exponentially.
Adding the two components, we see that a trajectory starting
slightly above the plane Ec(0) spirals toward the origin along
the Ec(0) direction, all the while being pushed away from
Ec(0) along the unstable direction Er(0). As the (stable) component along Ec(0) shrinks in magnitude, the (unstable) component grows exponentially.
Thus the trajectory follows a helix of exponentially decreasing radius whose axis lies in the direction of Er(0); this
is illustrated in Fig. 7.

Figure 6. Bifurcation diagram for V1 in Chuas oscillator.

Dynamics of D1 and D1
n points is called a period-n orbit. Since a chaotic solution is
nonperiodic, sampling produces an uncountable set of points.
When producing a bifurcation diagram, the sampling instants are determined by a clock that is derived from the dynamics of the system under consideration. In discrete systems, one simply plots successive values of a state variable.
For nonautonomous continuous-time systems with periodic
forcing, the driving signal provides a natural sampling clock.
Some type of discretization in time is needed for autonomous
continuous-time systems. In this case, the sampling instants
are defined by crossings of a trajectory of the system through
a reference plane in the state space that is called a Poincare
section.
Figure 6 shows a simulated bifurcation diagram for V1 in
Chuas oscillator as the bifurcation parameter G is swept
from 533 to 543 S. V1 is sampled when V2 0. Period-one,
period-two, and period-four orbits for G 530, 537, and 539
S yield one, two, and four points, respectively, on the bifurcation diagram.
Chaos Generation Mechanism in Chuas Oscillator

A trajectory starting from some initial state in the D1 region

may be decomposed into its components along the plane
Ec(P) and the vector Er(P). When 1 0 and 1 0, the
component on Ec(P) spirals away from P along this plane,
while the component in the direction of Er(0) tends asymptotically toward P. Adding the two components, we see that a
trajectory starting close to the real eigenvector Er(P) above
the plane moves toward Ec(P) along a helix of exponentially
increasing radius. Since the component along Er(P) shrinks
exponentially in magnitude and the component on Ec(P)
grows exponentially, the trajectory is quickly flattened onto
Ec(P), where it spirals away from P along the plane; this is
illustrated in Fig. 8.
By symmetry, the equilibrium point P in the D1 region
has three eigenvalues: 1 and 1 j1. The vector Er(P) is
associated with the real eigenvalue 1; the real and imaginary
parts of the eigenvectors associated with the complex conjugate pair 1 j1 define a plane Ec(P) along which trajectories spiral away from P.
Global Dynamics
With the given set of parameter values, the equilibrium point
at the origin has an unstable real eigenvalue and a stable pair

Because of the piecewise-linear nature of the nonlinearity

f( ), the vector field of Chuas oscillator may be decomposed
into three distinct affine regionsV1 E, V1 E, and
V1 Ewhich are called the D1, D0, and D1 regions, respectively (12). In each region, the dynamics are linear. The global
dynamics may be determined by considering separately the
behavior in each of the three regions (D1, D0, and D1) and
then gluing the pieces together along the boundary planes
U1 and U1.
Shilnikov Chaos in Chuas Oscillator
In the following discussion, consider a fixed set of component
values: L 18 mH, R0 12.5 , C2 100 nF, C1 10 nF,
Ga 50/66 mS 757.576 S, Gb 9/22 mS 409.091
S, and E 1 V. When G 550 S, the oscillator has three
equilibrium points at P, 0, and P. The equilibrium point at
the origin (0) has one real eigenvalue 0 and a complex conjugate pair 0 j0. The outer equilibria (P and P) each have
a real eigenvalue 1 and a complex conjugate pair 1 j1.

V1

Er(0)

D0

V2

I3
0

Ec(0)

Figure 7. Dynamics of the D0 region.

CHAOTIC CIRCUIT BEHAVIOR

Chua's oscillator

V1
Er(P

Er(P+)

231

4
+)

3
2

P+
D1
V1(V)

V2

I3

0
1
2

P_

Er(P_)

4
0.8 0.6 0.4 0.2

Er(P_)
Figure 8. Dynamics of the D1 region. By symmetry, the D1 region
has equivalent dynamics.

of complex conjugate eigenvalues; the outer equilibrium point

P has a stable real eigenvalue and an unstable complex pair.
In particular, P has a pair of unstable complex conjugate
eigenvalues 1 1 (1 0, 1 0) and a stable real eigenvalue 1, where 1 1. One can prove that the circuit is
chaotic in the sense of Shilnikov by showing, in addition, that
it possesses a homoclinic orbit for this set of parameter values. A homoclinic orbit is a closed trajectory that is asymptotic in forward and reverse time to the same equilibrium
point. Trajectories that lie close to a homoclinic orbit exhibit
complex dynamics.
A trajectory starting on the vector Er(0) close to 0 moves
away from the equilibrium point until it crosses the boundary U1 and enters D1. If this trajectory is folded back into D0
by the dynamics of the outer region, and reinjected toward 0
along the stable plane Ec(0), then the required homoclinic orbit is produced. That Chuas oscillator is chaotic in the sense
of Shilnikov was first proved by Chua et al. in 1985 (26).

0
0.2
V2(V)

0.4

0.6

0.8

Figure 9. A simulated double-scroll attractor in Chuas oscillator

with G 565 S.

1
+

2
+

IR
R3

R6

L
10

I3
C2

V2

V1

+
A
_ 1

C1 VR
4

R0

+
A
_ 2

6
R2
R1

R5
R4
NR

Figure 10. Practical implementation of Chuas oscillator using two

op amps and six resistors to realize the Chua diode.

Double-Scroll Attractor
The double-scroll attractor, a two-dimensional projection of
which is shown in Fig. 9, is a chaotic attractor in Chuas oscillator. This strange attractor is so called because of the intertwined scroll-like structure of a transverse section through
the attractor at the origin.

Table 1. Component List for the Practical Implementation

of Chuas Oscillator Shown in Fig. 10
Element
A1

Practical Implementation of Chuas Oscillator

Chuas oscillator can be realized in a variety of ways using
standard or custom-made electronic components. All of the
linear elements (capacitor, resistor, and inductor) are readily
available as two-terminal devices. A nonlinear resistor NR
with the prescribed VI characteristic (called a Chua diode)
can be implemented by connecting two negative-resistance
converters in parallel, as shown in Fig. 10 (29). A complete
list of components for this circuit is given in Table 1. Chua
diodes have also been implemented in integrated circuit
form (30).
The op amp subcircuit consisting of A1, A2 and R1 R6 functions as a negative-resistance converter NR with a VI charac-

A2
C1
C2
R
R1
R2
R3
R4
R5
R6
L, R0

Description
Op amp
(1/2 AD712 or equivalent)
Op amp
(1/2 AD712 or equivalent)
Capacitor
Capacitor
Potentiometer
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
Inductor
(TOKO type 10RB)

Value

10 nF
100 nF
2 k
3.3 k
22 k
22 k
2.2 k
220
220
18 mH, 12.5

232

CHAOTIC CIRCUIT BEHAVIOR

IR

CHUAS OSCILLATOR

Gb
Gc

Esat

Esat

Ga

-E
E

E
Gb

VR

Gc

Figure 11. Every physically realizable nonlinear resistor NR is eventually passivethe outermost segments must lie completely within
the first and third quadrants of the VR IR plane for sufficiently large
VR and IR.

teristic as shown in Fig. 11. Using two 9 V batteries to power

the op amps gives V 9 V and V 9 V. From measurements of the saturation levels of the AD712 outputs, Esat
8.3 V, giving E 1 V. With R2 R3 and R5 R6, the nonlinear characteristic is defined by Ga 1/R1 1/R4 50/66
mS, Gb 1/R3 1/R4 9/22 mS, and E R1Esat /(R1
R2) 1 V. Note that the real inductor is modeled as a series
connection of an ideal linear inductor L and a linear resistor R0.
Nonideality of an Op ampBased Chua Diode
The VI characteristic of the op ampbased Chua diode in
Fig. 10 differs from the desired piecewise-linear characteristic
shown in Fig. 4 in that it has five segments, the outer two of
which have positive slopes Gc 1/R5 1/220 S.
This nonideality is due to the fundamental laws of nature.
Any physical realization of a nonlinear resistor is eventually passive, meaning simply that for a large enough voltage across its terminals, the instantaneous power PR(t)
(VR(t)IR(t)) consumed by the device is positive.
Hence the VI characteristic of a real Chua dioide must
include at least two outer segments with positive slopes that
return the characteristic to the first and third quadrants.
From a practical point of view, as long as the voltages and
currents on the attractor are restricted to the negative-resistance region of the characteristic, these outer segments will
not affect the circuits behavior.
SPICE Simulation of Chuas Oscillator
Chaotic circuits may be readily simulated using commercial
circuit simulators such as SPICE (31). Figure 12 shows a netlist for the practical implementation of Chuas oscillator
shown in Fig. 10. The AD712 op amps in this realization of
the circuit are modeled using Analog Devices AD712 macromodel (32). The TOKO 10 RB inductor has a nonzero series
resistance, which we have included in the SPICE net-list:
R0 12.5 . Node numbers are as in Fig. 10: The power rails
are 111 and 222; 10 is the internal node of our physical
inductor where its series inductance is connected to its series resistance.
A double-scroll attractor results from our SPICE 3e2 simulation using the input deck shown in Fig. 12; this attractor is
plotted in Fig. 13.

L
1 10
0.018
R0
10 0
12.5
R
1 2
1770
C2
1 0
100.0N
C1
2 0
10.0N
* 2-VNIC CHUA DIODE
V+ 111 0
DC 9
V 0
222 DC 9
XA1 2 4 111 222 3 AD712
R1
4 0
3.3K
R2
3 4
22K
R3
2 3
22K
XA2 2 6 111 222 5 AD712
R4
6 0
2.2K
R5
5 6
220
R6
2 5
220
* AD712 SPICE Macro-model
1/91, Rev. A
* Copyright 1991 by Analog Devices, Inc.
* (reproduced with permission)
*
.SUBCKT AD712 13 15 12 16 14
*
VOS 15 8 DC 0
EC 9 0 14 0 1
C1 6 7 .5P
RP 16 12 12K
GB 11 0 3 0 1.67K
RD1 6 16 16K
RD2 7 16 16K
ISS 12 1 DC 100U
CCI 3 11 150P
GCM 0 3 0 1 1.76N
GA 3 0 7 6 2.3M
RE 1 0 2.5MEG
RGM 3 0 1.69K
VC 12 2 DC 2.8
VE 10 16 DC 2.8
RO1 11 14 25
CE 1 0 2P
RO2 0 11 30
RS1 1 4 5.77K
RS2 1 5 5.77K
J1 6 13 4 FET
J3 7 8 5 FET
DC 14 2 DIODE
DE 10 14 DIODE
DP 16 12 DIODE
D1 9 11 DIODE
D2 11 9 DIODE
IOS 15 13 5E-12
.MODEL DIODE D
.MODEL FET PJF(VTO=1 BETA=1M IS=25E-12)
.ENDS
.IC V(1)=0 V(2)=0.1
.TRAN 0.01MS 100MS 50MS
.OPTIONS RELTOL=1.0E-5 ABSTOL=1.0E-5
.PRINT TRAN V(1) V(2)
.END
Figure 12. SPICE deck to simulate the transient response of the
implementation of Chuas oscillator in Fig. 10. The op amps are modeled by the Analog Devices AD712 macromodel. R0 models the series
resistance of the real inductor L.

CHAOTIC CIRCUIT BEHAVIOR

233

IR

Chua's oscillator
4

Rb

V1(V)

ES

Ra

ES

VR

I
Rb

2
3
4
0.8 0.6 0.4 0.2

0
0.2
V2(V)

0.4

0.6

0.8

Figure 13. SPICE simulation of a double-scroll attractor in Chuas

oscillator.

Figure 15. The VI characteristic of the nonlinear resistor NR in

Saitos oscillator has breakpoints at I and slopes Ra and Rb in the
inner and outer regions.

In the limit as L0 0, the third equation imposes the constraint

V1 = g(I3 )

Hysteretic Chaotic Oscillator

A hysteretic chaotic oscillator is one in which the nonlinear
elements exhibits hysteretic behavior resulting from slowfast dynamics (33).
Hysteretic behavior in electronic circuits, such as that
which occurs in a Schmitt trigger or a nonmonotone nonlinear
resistor, is normally associated with fold bifurcations; it manifests itself as jumps in voltages or currents at impasse
points (13,27,34).
The fast dynamics associated with a nonmonotone currentcontrolled (voltage-controlled) negative resistor can be modeled by a small transit inductance (capacitance) in series (parallel) with the resistor (35).
Saitos oscillator, shown in Fig. 14, contains a nonmonotone current-controlled hysteresis resistor NR (14,15). L0 is
a small transit inductance that completes the model.
This circuit is described by a system of three autonomous
state equations:

Trajectories are thus constrained to lie along the drivingpoint characteristic of the nonlinear resistor NR. On the outer
segments of this characteristic,
I3 = V1 Es
where the intercepts Es are as shown in Fig. 15. In these
regions, the system is governed by two-dimensional dynamics

dV1
1
1
= I2
(V Es )
dt
C
RC 1
dI2
1
R
= V1 I2
dt
L
L
If the trajectory is on the upper segment of the VI characteristic and V1 decreases below E, I3 jumps to the lower segment. The trajectory then remains on the lower segment until V1 exceeds E, when it jumps back to the upper segment.
This behavior becomes apparent when I3 is plotted against
V1, as shown in Fig. 16.

dV1
1
1
= I2 I3
dt
C
C
dI2
1
R
= V1 I2
dt
L
L
dI3
1
1
=
V
g(I3 )
dt
L0 1 L0

Saitos oscillator
0.0008
0.0006
0.0004
0.0002
I3(A)

where g(IR) RbIR 
(Ra Rb)(IR I IR I).

0
0.0002

L
I2

L0
I3

V1

C1

0.0004
+

VR

Figure 14. Saitos oscillator.

IR
NR

0.0006
0.0008
5

V1(V)
Figure 16. Simulation of chaotic trajectory in Saitos oscillator showing how the fast dynamics associated with I3 cause the trajectory to
be confined to the outer portions of the VI characteristic NR and to
produce jumps between these segments.

234

CHAOTIC CIRCUIT BEHAVIOR

Table 2. Component List for the Practical Implementation
of Saitos Oscillator Shown in Fig. 18

Saitos oscillator

Element

0.0015

Description

A1

0.001

A2

I2(A)

0.0005
0
0.0005
0.001
0.0015
5

V1(V)

Value

Op amp
(1/2 AD712 or equivalent)
Op amp
(1/2 AD712 or equivalent)
Capacitor
Potentiometer
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
Zener diode
Zener diode
Inductor
(TOKO type 10RB)

C
R1
R2
R3
R4
R5
R6
R7
D1
D2
L

4.7 nF
5 k
1 k
1 k
3.3 k
10 k
10 k
100
2.7 V
2.7 V
100 mH

Figure 17. Simulation of Saitos oscillator.

Chaos Generation Mechanism in Saitos Oscillator

SPICE Simulation of Saitos Oscillator

In Saitos oscillator, stretching is accomplished by the negative resistor R which adds energy to the circuit to separate
trajectories. The hysteresis element switches the trajectory
between two two-dimensional regions to keep it bounded. Figure 17 shows a simulation of Saitos circuit with R 3 k,
L 100 mH, C 4.7 nF, L0 1 nH, Ra 3.3 k, Rb 10
k, and I 250 A.

Saitos circuit is characterized by slow-fast dynamics: slow

two-dimensional dynamics associated with the outer segments of the VI characteristic of the negative resistor, and
fast one-dimensional parasitic dynamics associated with the
jump through the inner region. Circuits of this type, which
are characterized by time scales that differ by several orders
of magnitude, are called stiff systems. Care must be taken
when solving the differential equations to account for the
abrupt change in dynamical behavior as the trajectory passes
through the inner region (35).
Figure 19 shows a simulation of Saitos circuit using the
SPICE deck in Fig. 20.

Practical Implementation of Saitos Oscillator

A practical implementation of Saitos oscillator is shown in
Fig. 18. The negative resistor R is implemented by means of
a negative-resistance converter (A1, R1, R2, R3). Provided that
R2 R3, then R R1. The nonmonotone current-controlled
nonlinear hysteresis resistor is constructed using a second
negative resistance converter. The breakpoint I is chosen by
means of zener diodes D1 and D2 such that op amp A1 remains
in its linear regime. The saturation voltages at node 5 are
given by Es 2.7 V 0.7 V 3.4 V. A complete list of components is given in Table 2.

1
V+
2

+
A_1

V1

V-

R6

4
+
A
_ 2

VR

V-

R7

V+

5
8

3
R2
R1

NR

_
0

R5
R4

1
V1(V)

I2

R3

Chuas oscillator and Saitos oscillator have been designed

with analysis in mind. Their piecewise-linear nature makes
analysis and implementation straightforward. In particular,
the fast dynamics in Saitos oscillator produces a relatively
simple discrete-time equivalent of this system.
Saitos oscillator

IR

Chaotic Colpitts Oscillator

D1

D2

2
3

Figure 18. Practical implementation of Saitos oscillator using an op

amp, resistors, and zener diodes to implement the current-controlled
nonlinear resistor.

4
5

V4(V)
Figure 19. SPICE simulation of Saitos oscillator.

CHAOTIC CIRCUIT BEHAVIOR

235

SAITOS OSCILLATOR

VCC
L
1 4
100M
C
4 0
4.7N
* NEGATIVE RESISTOR (VNIC)
V+ 111 0
DC 9
V 0
222 DC 9
XA1 3 1 111 222 2 AD712
R1
3 0
3.0K
R2
2 3
1.0K
R3
1 2
1.0K
* HYSTERESIS ELEMENT (INIC)
XA2 6 4 111 222 8 AD712
R4
6 0
3.3K
R5
5 6
10K
R6
4 5
10K
R7
8 5
100
D1
5 7
ZENER2E7
D2
0 7
ZENER2E7

RL
IL

L
3
Ic
4

.IC V(1)=1M V(4)=1M

.TRAN 0.1MS 15MS 5MS
.OPTIONS RELTOL=1.0E-5 ABSTOL=1.0E-5
.END
Figure 20. SPICE deck to simulate the transient response of Saitos
oscillator. Node numbers are as in Fig. 18. The op amps are modeled
by the Analog Devices AD712 macromodel.

IB

VCE

C1

VBE

* 2.7V ZENER DIODE

.MODEL ZENER2E7 D(BV=2.7)
* AD712 SPICE Macro-model
1/91, Rev. A
* Copyright 1991 by Analog Devices, Inc.
* (reproduced with permission)
*
.SUBCKT AD712 13 15 12 16 14
*
VOS 15 8 DC 0
EC 9 0 14 0 1
C1 6 7 .5P
RP 16 12 12K
GB 11 0 3 0 1.67K
RD1 6 16 16K
RD2 7 16 16K
ISS 12 1 DC 100U
CCI 3 11 150P
GCM 0 3 0 1 1.76N
GA 3 0 7 6 2.3M
RE 1 0 2.5MEG
RGM 3 0 1.69K
VC 12 2 DC 2.8
VE 10 16 DC 2.8
RO1 11 14 25
CE 1 0 2P
RO2 0 11 30
RS1 1 4 5.77K
RS2 1 5 5.77K
J1 6 13 4 FET
J2 7 8 5 FET
DC 14 2 DIODE
DE 10 14 DIODE
DP 16 12 DIODE
D1 9 11 DIODE
D2 11 9 DIODE
IOS 15 13 5E-12
.MODEL DIODE D
.MODEL FET PJF(VTO=1 BETA=1M IS=25E-12)
.ENDS

0
C2

REE
VEE

Figure 21. Chaotic Colpitts oscillator.

Most electronic oscillators are not piecewise-linear, and the

active elements are as likely to be transistors as negativeresistance converters. Provided that the circuits satisfy the
necessary conditions for chaos, it is possible that they will
exhibit complex steady-state behavior.
A drawback of both Chuas circuit and Saitos circuit is
that they are limited to relatively low frequency operation because of the requirements that the nonlinear element should
be resistive and piecewise-linear. Novel applications of chaos
are now driving the demand for high-frequency chaotic circuits derived from conventional oscillator topologies.
Recall that a harmonic oscillator is usually designed to
have a linearized loop gain of unity and a soft nonlinearity to
bound the amplitude of the oscillation. By increasing the loop
gain beyond unity and employing a hard nonlinearity, chaos
can be produced.
The Colpitts oscillator shown in Fig. 21 consists of a linear
inductor L with series resistance RL, a bipolar junction transistor Q, a linear resistor REE, and two linear capacitors C1
and C2.
Assuming that the transistor acts as a purely resistive element, this oscillator can be described by a system of three
autonomous state equations:

dVCE
= IL IC
dt
V + VBE
dV
C2 BE = EE
IL IB
dt
REE
dI
L L = VCC VCE + VBE IL RL
dt
C1

where, in common-emitter configuration, IC is written as a

function of VBE and VCE.

236

CHAOTIC CIRCUIT BEHAVIOR

Table 3. Component List for the Practical Implementation

of the Colpitts Oscillator Shown in Fig. 21
Element
RL
L
Q
C1
C2
REE

Description

Value

Potentiometer
Inductor
NPN bipolar transistor
Capacitor
Capacitor
1/4 W resistor

50
100 H
2N2222A
47 nF
47 nF
400 k

NONAUTONOMOUS CHAOTIC CIRCUITS

Thus far we have considered only autonomous systems where
no external forcing signal is applied. An important class of
circuits that may exhibit chaos includes those that are driven
by a periodic signal. Because the vector field is time-varying
in this case, these circuits are called nonautonomous. While
at least three energy-storage elements are necessary to produce chaos in an autonomous oscillator, chaos can occur in a
second-order circuit that is subject to periodic forcing.
Forced Neon Bulb Relaxation Oscillator

When the loop gain is slightly greater than unity and the
quality factor of the resonant circuit is high, the transistor in
the oscillator remains in its forward active region of operation, and the voltage waveform VCE is almost sinusoidal. By
making the loop gain greater than unity and reducing the
quality factor, this circuit can exhibit a variety of complex
behaviors, including chaos (16,17).
Chaos Generation Mechanism in the Chaotic Colpitts Oscillator
By selecting a sufficiently large small-signal loop gain, the
oscillation VCE grows rapidly, the transistor switches off, VBE
is driven negative, and then increases slowly until the transistor switches on again. Stretching results from the high
gain of the transistor in its forward active region; folding is
caused by the spiral decay in the cutoff region.
Practical Implementation of the Chaotic Colpitts Oscillator
A list of components for the chaotic Colpitts oscillator shown
in Fig. 21 is given in Table 3. This oscillator exhibits a series
of period-doubling bifurcations as R is varied from 0 to 50 .
Figure 22 shows a simulation of the chaotic Colpitts oscillator
using the SPICE deck in Fig. 23.

Colpitts oscillator
1
0.5

VBE (V)

0
0.5
1
1.5
2
2.5

3
VCE (V)

Figure 22. SPICE simulation of the Colpitts oscillator in Fig. 21

with VCC 5 V, VEE 5 V, RL 33 , L 100 H, C1 47 F,
C2 47 F, and REE 400 . Q is a type 2N2222A transistor. Vertical axis: VBE; horizontal axis: VCE.

One of the earliest recorded observations of chaos in an electronic circuit is the driven neon bulb relaxation oscillator
studied by van der Pol and van der Mark in 1927 (4,5). The
circuit, shown in Fig. 24, consists of a high voltage dc source
E attached via a large series resistance R to a neon bulb and
capacitor C1, which are connected in parallel; this forms the
basic relaxation oscillator. Initially the capacitor is discharged and the neon bulb is nonconducting. The dc source
charges C1 with a time constant RC until the voltage across
the neon bulb is sufficient to turn it on. Once lit, the bulb
presents a shunt low-resistance path to the capacitor. The
voltage across the capacitor falls exponentially until the neon
arc is quenched, the bulb is returned to its off state, and the
cycle repeats.
As the capacitance C1 is increased smoothly, the circuit exhibits jumps from one (periodic) mode-locked state to another.
For a critical value of the amplitude of the driving signal, the
pattern of mode-lockings has a self-similar fractal structure
consisting of an infinite number of steps. This is called a
Devils staircase (36).
When the amplitude of the forcing signal is greater than
the critical value, the steps of the staircase overlap. Van der
Pol noted that often an irregular noise is heard in the telephone receiver before the frequency jumps to the next lower
value; this is chaos.
The frequency-locking behavior of the driven neon bulb oscillator circuit is characteristic of forced oscillators that contain two competing frequencies: the natural frequency f 0 of
the undriven oscillator and the driving frequency f s. If the
amplitude of the forcing is small, either quasi-periodicity or
mode-locking occurs. For a sufficiently large amplitude of the
forcing, the system may exhibit chaos.
Figure 25 shows experimentally observed mode locking in
a driven neon bulb oscillator. Magnifications of the staircase
are shown in Fig. 26. For driving signals with amplitudes
greater than that shown, the monotonicity of the staircase is
lost and chaos occurs.
The presence of a single dynamic element (the capacitor)
in Fig. 24 might suggest that this is a first-order system, but
a first-order circuit with periodic forcing cannot exhibit chaos.
The hidden second state is associated with the fast transit
dynamics of the neon bulb. The neon bulb may be modeled as
a nonmonotone current-controlled nonlinear resistor with a
parasitic series inductor (5).
Driven RL-Diode Circuit
One of the simplest nonautonomous chaotic circuits is the series connection of a linear resistor, a linear inductor, and a

CHAOTIC CIRCUIT BEHAVIOR

237

COLPITTS OSCILLATOR
VCC
VEE
RL
L
Q
C1
C2
REE

1
5
1
2
3
3
4
0

4
4
2
3
4
0
0
5

PWL(0 0 1N 5 5M 5)
DC 5
33
100U
0 Q2N2222A
47N
47N
400

.MODEL Q2N2222A NPN(IS=14.34F XTI=3 EG=1.11 VAF=74.03 BF=255.9 NE=1.307

+
ISE=14.34F IKF=.2847 XTB=1.5 BR=6.092 NC=2 ISC=0 IKR=0 RC=1
+
CJC=7.306P MJC=.3416 VJC=.75 FC=.5 CJE=22.01P MJE=.377 VJE=.75
+
TR=46.91N TF=411.1P ITF=.6 VTF=1.7 XTF=3 RB=10)
.OPTIONS RELTOL=1E-5 ABSTOL=1E-5
.TRAN 10N 4M 3M
.END

Figure 23. SPICE deck to simulate the transient response of the Colpitts oscillator
shown in Fig. 21.

pn-junction, as shown in Fig. 27, which can exhibit chaotic

behavior when driven by a sinusoidal voltage source (7,8). In
this case chaos is due to parasitic nonlinear capacitive effects
in the diode. The behavior of the circuit can be confirmed by
using SPICE (9) (see Figs. 28 and 29).
Driven Negative-Resistance Circuit
Chaos in the driven RL-diode circuit is due to relatively complex nonlinear dynamical behavior in the pn-junction diode. A
simpler nonautonomous circuit containing only linear energystorage elements is the driven negative-resistance circuit
shown in Fig. 30. This consists of a series connection of a
periodic voltage source, a linear resistor, a linear inductor,
and a parallel connection of a nonmonotone voltage-controlled
nonlinear resistor and a linear capacitor.
This circuit is described by a pair of first-order nonautonomous ordinary differential equations:

The case of a cubic nonlinearitythe electrical analog of

the forced Duffing equationhas been studied extensively
(6). The undriven system has three equilibrium points, one of
which is a saddle. The two remaining equilibria are stable
fixed points. Chaos arises when the trajectory is driven close
to the saddle.
The same qualitative behavior, shown in Fig. 31, occurs
when a simpler piecewise-linear nonlinearity is used instead
of a cubic. Here A 2 V, f s 5000 Hz, R 660 , L 33
mH, and C 68 nF (37).

Forced neon bulb circuit

11.00
10.00
9.00

1
dV1
1
=
f (V1 ) +
I
dt
C1
C1 2
1
dI2
R
A
= V1 I2 + sin(2 f st)
dt
L
L
L

8.00

where the voltage-controlled nonlinear resistor is described

by IR f(VR).

fs / fd

7.00
6.00
5.00
4.00
3.00
2.00

R
+
+

1.00
C1

V1

VS

IR

2.00

4.00

6.00

8.00

10.00

fs (kHz)

VR

NR

Figure 24. Driven neon bulb relaxation oscillator.

Figure 25. Experimentally measured staircase structure of lockings

for a forced neon bulb relaxation oscillator. The winding number is
given by f s /f d, the ratio of the frequency of the sinusoidal driving signal to the average frequency of current pulses through the bulb.

238

CHAOTIC CIRCUIT BEHAVIOR

Forced neon bulb circuit

3.00

3.00

2.80

2.90

2.60

2.80

2.40

2.70

2.20

2.60
fs / fd

fs / fd

Forced neon bulb circuit

2.00

2.50

1.80

2.40

1.60

2.30

1.40

2.20

1.20

2.10

1.00

2.00
1.00

1.50

2.00

2.50

2.40

2.50

fs (kHz)

2.60

2.70

fs (kHz)

Figure 26. Magnification of Fig. 25 showing self-similarity.

The VI characteristic of the nonlinear resistor is as

shown in Fig. 32. The relationship may be written explicitly
as
f (VR ) = GbVR + 12 (Ga Gb )(|VR + E| |VR E|)
where Ga 2.2 mS, Gb 1 mS, and E 1.6875 V. This
element is readily implemented by means of a negative-resistance converter.
A complete circuit realization of the driven negative-resistance oscillator with a piecewise-linear nonlinear resistor is
shown in Fig. 33. A component list for the practical implementation of this circuit is given in Table 4. The behavior of
the circuit may be confirmed by SPICE simulation (see Figs.
34 and 35).

DRIVEN RL-DIODE CIRCUIT

D
R
L
VS

3
1
2
1

0
2
3
0

DIODE
15
10.0M
SIN(0 6 100K)

.MODEL DIODE D(IS=8.3FA RS=9.6 TT=4US CJ0=300PF M=0.4 VJ=0.75)

.TRAN 0.001US 2MS 1MS
.OPTIONS RELTOL=1.0E-5 ABSTOL=1.0E-5
.END

Figure 28. SPICE deck to simulate the behavior of the RL-diode circuit shown in Fig. 27.

DISCRETE-TIME CHAOTIC CIRCUITS

Driven RL-diode circuit

2

R
+
+

VS

IL

0
2
V3(V)

Although a discrete-time, discrete-state deterministic dynamical system may exhibit long periodic steady-state trajectories,
it cannot exhibit chaos. By contrast, a discrete-time system of
order one or more can exhibit chaos if it has continuous state
variables and is described by a nonlinear map. If the system

4
6
8

VD

Figure 27. Driven RL-diode circuit.

ID

10
12
8

0
V1(V)

Figure 29. Spice simulation of driven RL-diode circuit.

CHAOTIC CIRCUIT BEHAVIOR

R
+
+

L
I2

VS

V1

Table 4. Component List for the Practical Implementation

of Negative-Resistance Circuit Shown in Fig. 33

IR

VR

239

Element

NR

A1

R
L
C
R1
R2
R3
R4
D1
D2

Figure 30. Driven negative-resistance oscillator.

Driven negative-resistance circuit

0.006
0.004

Description
Op amp
(1/2 AD712 or equivalent)
Potentiometer
Inductor
Capacitor
1/4 W resistor
1/4 W resistor
1/4 W resistor
1/4 W resistor
Zener diode
Zener diode

Value

1 k
33 mH
68 nF
1 k
2.2 k
1 k
100
4.7 V
4.7 V

I2(A)

0.002

is first-order, then the nonlinear map must also be noninvertible.

0.002

Switched-Capacitor Chaotic Circuit

A continuous-state, discrete-time dynamical system of the
form

0.004
0.006
4

0
V1(V)

Figure 31. Simulation of driven negative-resistance circuit with

piecewise-linear resistor as in Fig. 32.

IR
(Gb Ga)E

Gb

Xk+1 = G(Xk )
can be implemented electronically using switched-capacitor
(SC) circuits. Such circuits may exhibit chaos if the map G is
nonlinear and at least one of the eigenvalues of DxG( ) has
modulus greater than unity in magnitude for some states X.
One of the most widely used deterministic random number generators is the linear congruential generator, which is a
discrete-time dynamical system of the form

Ga
E

VR

E
Gb

(Ga Gb)E

Figure 32. VI characteristic of the negative resistor in Fig. 30.

R
1

L
2

IR

+
_

VS

V1

+
A
_ 2

VR

V+
V-

5
_

NR

R3

I2

R2
R1

_
0

R4
4

where A, B, and M are called the multiplier, increment, and

modulus, respectively.
If A 1, then all equilibrium points of (1) are unstable.
With the appropriate choice of constants, this system exhibits
a chaotic solution with a positive Lyapunov exponent equal to
ln A. However, if the state space is discrete, for example, in
the case of digital implementations of (1), then every steadystate orbit is periodic with a maximum period equal to the
number of distinct states in the state space; such orbits are
termed pseudorandom.
By using an analog state space, a truly chaotic sequence
can be generated. A discrete-time chaotic circuit with an
analog state space may be realized in switched-capacitor technology.
Example: Parabolic Map. Figure 36 shows an SC realization
of the parabolic map
xk+1 = V 0.5x2k

D1
6
D2

Figure 33. Practical implementation of driven negative-resistance

oscillator using an op amp, resistors, and zener diodes to implement
the voltage-controlled nonlinear resistor.

which, by the change of variables Xk Axk B, with B 0.5

and A (1 1 2 V)/(4 V), and 0 V V 4 V, is equivalent to the logistic map
Xk+1 = PXk (1 Xk )
with P 1/(2A) in the range 2 P 4 (19).

240

CHAOTIC CIRCUIT BEHAVIOR

Driven negative-resistance circuit

DRIVEN NEGATIVE-RESISTANCE OSCILLATOR

0.006

* AD712 SPICE Macro-model

1/91, Rev. A
* Copyright 1991 by Analog Devices, Inc.
* (reproduced with permission)
*
.SUBCKT AD712 13 15 12 16 14
*
VOS 15 8 DC 0
EC 9 0 14 0 1
C1 6 7 .5P
RP 16 12 12K
GB 11 0 3 0 1.67K
RD1 6 16 16K
RD2 7 16 16K
ISS 12 1 DC 100U
CCI 3 11 150P
GCM 0 3 0 1 1.76N
GA 3 0 7 6 2.3M
RE 1 0 2.5MEG
RGM 3 0 1.69K
VC 12 2 DC 2.8
VE 10 16 DC 2.8
RO1 11 14 25
CE 1 0 2P
RO2 0 11 30
RS1 1 4 5.77K
RS2 1 5 5.77K
J1 6 13 4 FET
J2 7 8 5 FET
DC 14 2 DIODE
DE 10 14 DIODE
DP 16 12 DIODE
D1 9 11 DIODE
D2 11 9 DIODE
IOS 15 13 5E-12
.MODEL DIODE D
.MODEL FET PJF(VTO=1 BETA=1M IS=25E-12)
.ENDS

0.004
0.002
I2(A)

VS
1 0
SIN(0 2.0 5K)
R
1 2
660
L
2 3
33.0M
C
3 0
68.0N
* VOLTAGE-CONTROLLED NONLINEAR RESISTOR
V+ 111 0
DC 9
V 0
222 DC 9
R1
5 0
1K
R2
4 5
2.2K
R3
3 4
1K
R4
7 4
100
XA1 3 5 111 222 7 AD712
D1
4 6
ZENER4E7
D2
0 6
ZENER4E7
.MODEL ZENER4E7 D(BV=4.7)

0.002
0.004
0.006
4

In the case considered, V P(P 2)/2. For 0 V V 1.5

V, 2 P 3 and the steady-state solution of the SC parabolic
map is a fixed point. As the bifurcation parameter V is increased from 1.5 to 3 V, the circuit undergoes a series of period-doubling bifurcations to chaos. V 4 V corresponds to
fully-developed chaos on the open interval (0 Xk 1) in the
logistic map with P 4.
CONCLUDING REMARKS
We have illustrated a very limited selection of autonomous
and nonautonomous electronic circuits that exhibit chaos. So
many other electronic circuits and systems are now known to
exhibit complex nonlinear dynamical behavior, including
chaos, that it would be impossible to mention all of them. The
interested reader is referred to special issues of the IEEE
Transactions on Circuits and Systems (October 1993) and the

Figure 34. SPICE deck to simulate the transient response of the

driven negative-resistance oscillator. Node numbers are as in Fig. 33.
The op amps are modeled by the Analog Devices AD712 macromodel.

Figure 35. SPICE simulation of driven negative-resistance circuit.

V
.TRAN 0.1MS 60MS 10MS
.OPTIONS RELTOL=1.0E-5 ABSTOL=1.0E-5
.PRINT TRAN V(1) V(3)
.END

0
V1(V)

C/2

Xk

Xk

Figure 36. Switched-capacitor realization of the parabolic map

xk1 V 0.5X 2k. The switches labeled o and e are driven by the odd
and even phases, respectively, of a nonoverlapping two-phase clock.

CHAOTIC SYSTEMS CONTROL

Philosophical Transactions of the Royal Society London A (October 1995) on Chaos in nonlinear electronic circuits and
Chaotic behavior in electronic circuits, respectively.
Low-dimensional chaos is now well understood and is
finding applications in noise (dither) generation, targeting,
and wideband communications. Current research into chaos
in electronic circuits is aimed at developing hyperchaotic circuits (38), robust high-frequency chaos generators, and circuit
techniques for producing or suppressing chaos.

BIBLIOGRAPHY

241

22. A. C. Davies, Nonlinear oscillations and chaos from digital filter

overflow, Philos. Trans. R. Soc. London, 353: 8599, 1995.
23. R. Schreier, On the use of chaos to reduce idle-channel tones in
delta-sigma modulators, IEEE Trans. Circuits Syst. I, Fundam.
Theory Appl., 41: 539547, 1994.
24. T. S. Parker and L. O. Chua, Practical Numerical Algorithms for
Chaotic Systems, New York: Springer, 1989.
25. M. P. Kennedy, Basic concepts of nonlinear dynamics and chaos,
C. Toumazou (ed.), Circuits and Systems Tutorials, London: IEEE
Press, 1994, pp. 289313.
26. L. O. Chua, M. Komuro, and T. Matsumoto, The double scroll
family. Parts I and II, IEEE Trans. Circuits Syst., 33: 1073
1118, 1986.

1. D. Ruelle and F. Takens, On the nature of turbulence, Commun.

Math. Phys., 20: 167192, 1971.

27. L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear

Circuits, New York: McGraw-Hill, 1987.

2. J. M. T. Thompson and H. B. Stewart, Nonlinear Dynamics and

Chaos, New York: Wiley, 1986.

28. M. P. Kennedy, ABC (Adventures in Bifurcations and Chaos): A

program for studying chaos. J. Franklin Inst. (Special Issue: Chaos
Electron. Circuits, 331B: 529556, 1994.

3. E. Ott, Chaos in Dynamical Systems, Cambridge: Cambridge

Univ. Press, 1993.
4. B. van der Pol and J. van der Mark, Frequency demultiplication,
Nature, 120: 363364, 1927.
5. M. P. Kennedy and L. O. Chua, Van der Pol and chaos, IEEE
Trans. Circuits Syst., 33: 974980, 1986.
6. Y. Ueda and N. Akamatsu, Chaotically transitional phenomena
in the forced negative-resistance oscillator, IEEE Trans. Circuits
Syst., 28: 217224, 1980.
7. P. Linsay, Period doubling and chaotic behavior in a driven anharmonic oscillator, Phys. Rev. Lett., 47: 13491392, 1981.
8. J. Testa, J. Perez, and C. Jeffries, Evidence for universal chaotic
behavior of a driven nonlinear oscillator, Phys. Rev. Lett., 48:
714717, 1982.
9. A. Azzouz, R. Duhr, and M. Hasler, Transition to chaos in a simple nonlinear circuit driven by a sinusoidal source, IEEE Trans.
Circuits Syst., 30: 913914, 1983.
10. L. O. Chua, Global unfolding of Chuas circuit. IEICE Trans. Fundam. (Special Issue: Chaos, Neural Netw., Numerics), E76-A: 704
734, 1993.

29. M. P. Kennedy, Robust op amp realization of Chuas circuit,

Frequenz, 46(34): 6680, 1992.
30. J. M. Cruz and L. O. Chua, A CMOS IC nonlinear resistor for
Chuas circuit, IEEE Trans. Circuits Syst., 39: 985995, 1992.
31. A. Vladimirescu, The SPICE Book, New York: Wiley, 1994.
32. Analog Devices, Inc., SPICE Model Library, Norwood, MA, 1991.
Release C 1/91.
33. M. Vidyasagar, Nonlinear Systems Analysis, Englewood Cliffs,
NJ: Prentice-Hall, 1978.
34. M. P. Kennedy and L. O. Chua, Hysteresis in electronic circuits:
A circuit theorists perspective, Int. J. Circuit Theory Appl., 19:
471515, 1991.
35. L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronic
Circuits: Algorithms and Computational Techniques, Englewood
Cliffs, NJ: Prentice-Hall, 1975.
36. M. P. Kennedy, K. R. Krieg, and L. O. Chua, The devils staircase:
The electrical engineers fractal, IEEE Trans. Circuits Syst. 36:
11331139, 1989.

11. R. N. Madan, (ed.), Chuas Circuit: A Paradigm for Chaos, Singapore: World Scientific, 1993.

37. J. G. Lacy, A simple piecewise-linear non-autonomous circuit

with chaotic behavior, Int. J. Bifurcation Chaos, 6(11): 2097
2100, 1996.

12. M. P. Kennedy, Three steps to chaos. Part II: A Chuas circuit

primer, IEEE Trans. Circuits Syst. (Special Issue: Chaos Nonlinear
Electron Circuits, Part A: Tutorial Rev.), 40: 657674, 1993.

38. T. Matsumoto, L. O. Chua, and K. Kobayashi, Hyperchaos: Laboratory experiment and numerical confirmation, IEEE Trans. Circuits Syst., 33: 11431147, 1986.

13. R. W. Newcomb and N. El-Leithy, A binary hysteresis chaos generator, Proc. ISCAS 84, Montreal, Canada, 1984, pp. 856859.
14. T. Saito, On a hysteresis chaos generator, Proc. ISCAS 85, Kyoto,
1985, pp. 847849.
15. T. Saito and S. Nakagawa, Chaos from a hysteresis and switched
circuit, Philos. Trans. R. Soc. London, 353: 4757, 1995.
16. M. P. Kennedy, Chaos in the Colpitts oscillator, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 41: 771774, 1994.
17. M. P. Kennedy, On the relationship between the chaotic Colpitts
oscillator and Chuas oscillator, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 42: 376379, 1995.
18. T. Endo, A review of chaos and nonlinear dynamics in phaselocked loops, J. Franklin Inst., 331B: 859902, 1994.
19. A. Rodrguez-Vazquez et al., Chaos from switched-capacitor circuits: Discrete maps, Proc. IEEE, 75: 10901106, 1987.
20. D. C. Hamill and D. J. Jefferies, Subharmonics and chaos in a
controlled switched-mode power converter, IEEE Trans. Circuits
Syst., 35: 10591061, 1988.
21. D. C. Hamill, Learning about chaotic circuits with SPICE, IEEE
Trans. Educ., 36: 2835, 1993.

MICHAEL PETER KENNEDY

University College Dublin

326

CIRCUIT ANALYSIS COMPUTING

CIRCUIT ANALYSIS COMPUTING

Conventional circuit simulation usually means simulation
of small to medium-sized analog circuits. The most widely
known and used circuit simulation program is SPICE (simulation program with integrated circuit emphasis). This program was first written at the University of California at
Berkeley by Laurence Nagel in 1975. Research in the area of
circuit simulation is ongoing at many universities and industrial sites. Commercial versions of SPICE or related programs
are available on a wide variety of computing platforms, from
small personal computers to large mainframes. A list of some
commercial simulator vendors can be found at the end of this
article. The main focus of this article is the simulators themselves and the numerical methods employed in them. A few
examples are also given to illustrate some uses of the simulators.
PURPOSE OF SIMULATION
Computer-aided simulation is a powerful aid during the design or analysis of electronic circuits and semiconductor devices. While the main emphasis here is on analog circuits, the
same simulation techniques may, of course, be applied to digital circuits (which are, after all, composed of analog circuits).
The main limitation will be the size of these circuits because
the techniques presented here provide a very detailed analysis of the circuit in question and, therefore, would be too
costly in terms of computer resources to analyze a large digital system.
It is possible to simulate virtually any type of circuit using
a program like SPICE. The programs have built-in elements
for resistors, capacitors, inductors, dependent and independent voltage and current sources, diodes, metal oxide semiconductor field-effect transistors (MOSFETs), junction fieldeffect transistors (JFETs), bipolar junction transistors (BJT),
transmission lines, transformers, and even transformers with
saturating cores in some versions. Found in commercial versions are libraries of standard components that have all necessary parameters prefitted to typical specifications. These libraries include items such as discrete transistors, op amps,
phase-locked loops, voltage regulators, logic integrated circuits, and saturating transformer cores.
Computer-aided circuit simulation is now considered an essential step in the design of integrated circuits, because without simulation the number of trial runs necessary to produce a working integrated circuit (IC) would greatly increase
the cost of the IC. Simulation provides other advantages,
however:
The ability to measure inaccessible voltages and currents. Because a mathematical model is used, all voltages and currents are available.
No loading problems are associated with placing a voltmeter or oscilloscope in the middle of the circuit, with

measuring difficult one-shot waveforms or probing a microscopic die.

Mathematically ideal elements are available. Creating
an ideal voltage or current source is trivial with a simulator, but impossible in the laboratory. In addition, all
component values are exact and no parasitic elements
exist.
It is easy to change the values of components or the configuration of the circuit. Unsoldering leads or redesigning
IC masks are unnecessary.
Unfortunately, computer-aided simulation has its own set of
problems.
Real circuits are distributed systems, not the lumped
element models that are assumed by simulators. Real
circuits, therefore, have resistive, capacitive, and inductive parasitic elements present besides the intended components. In high-speed circuits these parasitic elements
are often the dominant performance-limiting elements in
the circuit and must be painstakingly modeled.
Suitable predefined numerical models have not yet been
developed for certain types of devices or electrical phenomena. The software user may be required, therefore,
to create his or her own models out of other models that
are available in the simulator. (An example is the solidstate thyristor, which may be created from an npn and
pnp bipolar transistor.)
The numerical methods used may place constraints on
the form of the model equations used.
There are small errors associated with the solution of the
equations. These errors, which are usually referred to as
truncation errors, are the result of discretizing the underlying differential equations using a finite number of
time steps.
CIRCUITS AND NET LISTS
Before we can consider simulation of a circuit, we must first
consider how to represent a circuit in a way that the computer
can understand. This is most easily done using a netlist. Figure 1 shows the circuit for a simple differential pair. The cir1
+ V3
R2

1k

R3

1k

5V

0
5

Q1

Q2

V1

2(V)

R1

V2

2(V)
1k

0
0
Figure 1. Circuit for differential pair.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CIRCUIT ANALYSIS COMPUTING

V1 4 0
V2 5 0
V3 1 0
R1 2 0
R2 3 1
R3 6 1
Q1 3 4
Q2 6 5
.model

2V
2V
5V
1k
1K
1K
2 m2n2222
2 m2n2222
m2n2222 NPN IS=1e-12 BF=100 BR=5 TF=100pS

tions are then solved using several different numerical techniques. The equations are constructed using Kirchhoff s voltage and current laws. The first system of equations pertains
to the currents flowing into each node. One equation is written for each node in the circuit (except for the ground node),
so the following equation is really a system of N equations for
the N nodes in the circuit. The subscript i denotes the node
index.

Figure 2. Netlist for differential pair.

cuit nodes are formed wherever two or more branches meet.

This particular circuit has seven nodes, which are numbered
zero to six. The ground or datum node is traditionally numbered as zero.
The netlist of a circuit provides description of the topography of a circuit. Most circuit simulation programs take the
netlist as the starting point for the simulation. The netlist is
really just a list of the branches (or elements) that make up
the circuit along with the nodes to which they are connected.
Normally the elements may be entered in any order and each
has a unique name, a list of nodes, and either a value or
model identifier. For the differential amplifier of Fig. 1, the
netlist is shown in Fig. 2. The format used here corresponds
to that used by SPICE. The first three lines define the three
voltage sources. The letter V at the beginning tells SPICE
that this is a voltage source element. The list of nodes (two in
this case) is next followed by the value in volts. In SPICE for
two terminal elements, the positive node is listed before the
negative node. The syntax for the resistor is similar to that of
the voltage source; the starting letter R in the names of the
resistors tells SPICE that these are resistors. SPICE also understands that the abbreviation k after a value means 1000.
For the two transistors Q1 and Q2 the starting letter Q indicates to SPICE a bipolar transistor. Q1 and Q2 each have three
nodes, and in SPICE the convention for their ordering is collector, base, emitter. So for Q1 the collector is connected to
node 3, the base to node 4, and the emitter to node 2. The
final entry m2n2222 is a reference to the model for the bipolar
transistor. (Note that both Q1 and Q2 reference the same
model.) The .model statement at the end of the listing defines this model. The model type is npn and a list of parameter=value entries follows. These entries define the numerical values of constants in the mathematical models that are
used for the bipolar transistor.
From the schematic of a small circuit it is a trivial process
to generate the netlist. Simply assign each node on the schematic a unique name (or integer value) and then create a list
of the elements in the circuit similar to Fig. 2. Most commercial circuit simulation packages come with schematic capture software, which allows the designer to draw the circuit
by placing and connecting the elements with the mouse. The
inverse process of creating a pleasing schematic from the netlist is much more difficult (and is the essence of the place and
route problem).

V)+
0 = F i = G i (V

In circuit simulators like SPICE, the circuits are represented

by a system of ordinary differential equations. These equa-

V)
Q i (V
Q
+ W i (t)
t

(1)

Variable V is an N-dimensional vector that represents the

voltages at the nodes. Variable Q is another vector that represents the electrical charge (in coulombs) at each node. The
term W represents any independent current sources that may
be attached to the nodes and has units of amps. The function
G(V) represents the currents that flow into the nodes as a
result of the voltages V.
For example, for the circuit of Fig. 3, which has two nodes,
we need to write two equations. At node 1:
0 = (V1 V2 )/R1 +

d(C1V1 )
+ I1
dt

We can clearly identify G1(V) as (V1 V2)/R; the term Q1(V)

is C1V1 and W(t) is simply I1. Likewise, at node 2 we can write
0 = (V2 V1 )/R1 + V2 /R2 + gmV1
In this equation only G2(V) appears. In this example G and
Q were simple linear terms; however, in general they will be
nonlinear functions of the voltage vector V.
These equations are quite easy to assemble in an automated fashion. Observe that each element that is attached to
a node makes a contribution to either G, Q, or W for that
node. To assemble the equation, we can use the following procedure:

For each element I{

For each terminal j of the element I{
Determine the node k to which
j is attached.
if (k 0) {
Compute the current Ij
at terminal j and sum
into G
Gk G k I j
Compute the charge at
terminal j and sum
into Qk
}}}

R1

C1

FORMULATION OF THE CIRCUIT EQUATIONS

327

R2

g mV 1

I1
0

Figure 3. Example circuit for nodal analysis.

328

CIRCUIT ANALYSIS COMPUTING

Vx
+

R1

L1

The equations for modified nodal analysis can be assembled

on an element-by-element basis just as with nodal analysis.
The only difference is that with modified nodal analysis, we
need to add new equations and variables for each voltage
source or inductor.

R2

R2

ACTIVE DEVICE MODELS

0

Figure 4. Circuit for modified nodal analysis.

Fortunately, it is easy to determine the node that each terminal is attached to from the netlist. The procedure outlined is
nodal analysis of a circuit.
MODIFIED NODAL ANALYSIS
Normal nodal analysis, which sums the currents flowing into
each node, cannot be used to represent ideal voltage sources
or inductors. This is so because the branch current in these
elements cannot be expressed as a function of the branch voltage. To resolve this problem, loop equations are written
around each inductor or voltage source. Figure 4 shows an
example of this procedure. In this figure, the unknowns to be
solved for are the voltage V1 at node 1, the voltage V2 at node
2, the voltage V3 at node 3, and the current flowing through
voltage source V1, which we shall call I(Vx), and the current
flowing in the inductor L1, which we shall call I(L1). The system of equations is

0 = V1 /R1 + I(Vx )
0 = V2 /R2 I(Vx ) + I(L1 )
0 = V3 /R3 I(L1 )
0 = V1 Vx + V2
0 = V2 +

d(L1 I(L1 ))
V3
dt

Modified nodal analysis effectively creates as new system

of equations that augments the original system produced by
nodal analysis. The second system pertains to the currents I
and magnetic flux flowing in any voltage sources or inductors that may be present. These equations result from the
application of the Kirchhoff voltage law equations around any
voltage sources or inductors in the circuit.
0 = Fi = Hi (I) +

Most circuits of interest contain active devices like transistors

or diodes that act as amplifiers. These devices are normally
described by a set of nonlinear equations and can become very
complex. For our discussion we shall consider a simple model
for the bipolar transistor, the Ebers-Moll model. This model
is one of the first that was developed, and while it is too simple for practical application it is useful for discussion.
A schematic of the Ebers-Moll model is shown in Fig. 5.
The model contains three nonlinear voltage-dependent current sources, Ic, Ibf , and Ibr and two nonlinear capacitances,
Cbe and Cbc. The currents flowing in the three current sources
are given by the following equations:

Ic = Is (exp(Vbe /Vt ) exp(Vce /Vt ))

Is
(exp(Vbe /Vt ) 1)
Bf
Is
=
(exp(Vbc /Vt ) 1)
Br

Ibf =
Ibr

The voltages Vbe and Vbc are the voltages between base and
emitter and the base and collector, respectively. Is, Bf , and Br
are three user-defined parameters that govern the dc operation of the BJT. Vt is the thermal voltage, or kT/q, which has
the numerical value of approximately 0.26 V at room temperature. Observe that in the normal forward active mode,
where Vbe 0 and Vce 0, Ibr and the second term in Ic vanish
and the current gain of the BJT, which is defined as Ic /Ib,
becomes numerically equal to Bf . Likewise, in the reverse
mode, where Vce 0 and Vbe 0, the reverse gain (Ie /Ib) is
equal to Br.
The EbersMoll model has a number of shortcomings. Observe that once we enter the forward mode, the current gain
is a constant Bf , which does not depend on the collector current or base collector voltage. Real transistors do not behave
this way. In real transistors as Vce becomes more negative,
the base collector depletion region consumes more of the base,
producing a narrower base with and higher current gain (the
early effect). As a result, a plot of Ic versus Vce shows positive

 i (I)
d
+ Ei (t)
dt

E(t) represents any independent voltages sources. In our examples, E(t) corresponds to the independent source Vx and the
magnetic flux corresponds to the term L1I(L1).
The use of modified nodal analysis does have the disadvantage of requiring that an additional equation be included for
each inductor or voltage source but has the advantage that
ideal voltage sources can be used. The total number of equations to be solved is therefore the number of nodes plus the
number of voltage sources and inductors. Modified nodal analysis has an additional advantage since it provides a method
of determining currents flowing in certain branches via the
insertion of zero voltage sources that function as amp meters.

Ibr

B
Ibf

C
+

Ic

+
Cbe

E
Figure 5. The EbersMoll model for the bipolar transistor.

CIRCUIT ANALYSIS COMPUTING

300 mA
Ib = 2.0 mA
Ib = 1.5 mA
Ib = 1.0 mA
Ib = 0.5 mA

Ib = 0
0A
0V
Ic(Q3)

5V

10 V

Figure 6. Collector curves for 2N2222 generated using the GummelPoon model.

slope in a real device (the collector has finite output resistance; see Fig. 6). In the EbersMoll model, however, the
slope of the Ic versus Vce curve is zero and therefore the collector resistance is infinite. Real devices also suffer gain degradation at low emitter injection (due to recombination) and at
high injection due to base pushout, resulting in gain reduction
at both low and high collector current. Notice how the collector curves become compressed as the base current increases
in Fig. 6. The GummelPoon model was created to address
these problems and produces more accurate BJT current
voltage (IV) characteristics.
The two capacitances in Fig. 5 contribute charge to the
emitter, base, and collector, and this charge is given by the
following equations:

Qbe = f Is (exp(Vbe /Vt ) 1) + Cje


Qbc = r Is (exp(Vbc /Vt ) 1) + Cjc

Vbe
0
Vbc
0

329

sured IV and capacitancevoltage (CV) data taken from real

transistors using a fitting or optimization procedure. The
GummelPoon model, on the other hand, has more than 40
parameters that must be adjusted to get a good fit to data in
all regions of operation.
Models for MOS devices are even more complicated than
the bipolar models. Modeling the MOSFET is more difficult
than the bipolar transistor because it is often necessary to
use a different equation for each of the four regions of operation (off, subthreshold, linear, saturation) and the drain current and capacitance are functions of three voltages (Vds, Vbs,
and Vgs) rather than just two (Vbe and Vce), as in the case of
the BJT. If the equations are to be accurate and result in good
convergence, the IV characteristics and capacitances must be
continuous and it is best if their first derivatives are continuous as well. Furthermore, many MOS models contain the
width (W) and length (L) of the MOSFET channel as parameters, and for the best utility the model should remain accurate
for many values of W and L. This property is referred to as
scalability.
Many commercial simulators contain other type of models
besides the traditional R, L, C, MOS, and BJT devices. Some
simulators contain behavioral models that are useful for
systems design or integration tasks; examples of these are
integrators, multipliers, summation, and LaPlace operator
blocks. Simulators may also contain prefitted models for commercially available operational amplifiers and logic chips.
Some simulators allow mixed mode simulation, which is a
combination of logic simulation (which normally allows only
a few discrete voltage states) with conventional circuit simulation.
TYPES OF ANALYSIS

(1 V /Vje )

m e

dv

(1 V /Vjc )m c dv

Qbe contributes positive charge to the base and negative

charge to the emitter. Qbc contributes positive charge to the
base and negative charge to the collector. The first term in
each charge expression is due to charge injected into the base
from the emitter for Qbe and from the collector into the base
for Qbc. Observe that the exponential terms in the charge
terms are identical to the term in Ic. This is so because the
injected charge is proportional to the current flowing into the
transistor. The terms f and r are the forward and reverse
transit times and correspond to the amount of time it takes
the electrons (or holes) to cross the base. The second terms in
the charge expression (the term with the integral) correspond
to the charge in the depletion region of the base-emitter junction for Qbe and in the base-collector junction for Qbc. Recall
that the depletion width in a pn junction is a function of the
applied voltage. The terms Vje and Vjc are the built-in potentials with units of volts for the base-emitter and base-collector
junctions. The terms mc and me are the grading coefficients
for the two junctions and are related to how rapidly the material changes from n-type to p-type across the junction.
This simple model has eleven constantsIs, Bf , Br, Cje,
Cjc, Me, Mc, Vje, Vjc, Tf , and Tr that must be specified by the
user. Typically these constants would be extracted from mea-

For analog circuits there are three commonly used methods

of analysis: dc, ac, and transient analysis. The dc analysis is
used to examine the steady-state operation of a circuit (that
is, what the circuit voltages and currents would be if all inputs were held constant for an infinite time). The ac analysis
(or sinusoidal steady state) examines circuit performance in
the frequency domain using phasor analysis. Transient analysis is analysis in the time domain and is the most computationally intensive of the three.
DC (STEADY-STATE) ANALYSIS
The dc analysis calculates the state of a circuit with fixed
(non-time-varying) inputs after an infinite period of time.
Such analysis is useful to determine the operating point (Qpoint) of a circuit, power consumption, regulation and output
voltage of power supplies, transfer functions, noise margin
and fanout in logic gates, and many other types of analysis.
In addition, dc analysis is used to find the starting point for
ac and transient analysis. To perform the analysis, the simulator assembles the circuit equations as usual but removes
the time-dependent terms from the equations (sets them to
zero). This procedure is equivalent to replacing all the capacitors with open circuits and replacing all the inductors with
short circuits.
Now we need a method to solve the system of equations.
Unfortunately, since the circuit elements will be nonlinear in

330

CIRCUIT ANALYSIS COMPUTING

most cases, a system of transcendental equations will normally result and it is therefore impossible to solve the system
analytically. We therefore resort to a numerical procedure,
and the method that has met with the most success is Newtons method or one of its derivatives.

For the small circuit of Fig. 3, analyzed in steady state

(without the capacitor), the Jacobian entries are

Newtons Method

For a passive circuit (i.e., a circuit without gain), the Jacobian

will be symmetric and for any row the diagonal entry will be
greater than the sum of all the other entries.
Newtons method converges quadratically provided that
the initial guess X i is sufficiently close to the true solution.
Quadratically it implies that if the distance between X i and
the true solution is d, then the distance between X i1 and the
true solution will be d2. Of course, this assumes that d is
small to start with. Still, programs like SPICE may require
50 or more iterations to achieve convergence because often
the initial guess is poor and quadratic convergence is not obtained until the last few iterations. There are additional complications, such as the fact that the model equations can become invalid for certain voltages. For example, the BJT model
will explode if a junction is forward biased by more than 1
V since exp(1/Vt) 5e16. Special limiting or damping methods must be used to keep the voltages and currents to within
reasonable limits. (See the section on Convergence Issues.)

Newtons method is actually quite simple. The problem is to

solve the system of equations F(X) 0 for X, where both F
and X are vectors of dimension N. F is the system of equations from modified nodal analysis and X is the vector of voltages and current to be solved for. Newtons method states
that given an initial guess for X i we can obtain a better guess
X i1 from the equation
J (X
X i )]1F (X
X i)
X i+1 = X i [J

(2)

Note that all terms on the right side of the equation are functions only of the vector X i. The term J(X) is an N by N square
matrix of partial derivatives of F called the Jacobian. Each
term in J is given by
J i, j =

Fi (X )
X j

The Jacobian matrix for the circuit is assembled at the same

time as the circuit equations. Normally analytic derivatives
are used; however, some simulators use numeric derivatives
via divided differences instead. This is referred to as the secant method.
The 1 in Eq. (2) indicates that it is necessary to invert
the Jacobian matrix before multiplying by the vector F. Of
course, we do not need actually to invert J to solve the problem; we only need to solve the linear problem F YJ for the
vector Y and then calculate Xi1 Xi Y. A direct method
such as lower-upper triangular (LU) decomposition is usually
employed to solve the linear system. More details on the
structure of J and the inversion process are given later in the
section on the Jacobian matrix structure. The equation assembly procedure including the Jacobian matrix becomes

For each element n{

For each terminal j of the element n{
Determine the node k to which
j is attached.
if (k 0){
Compute the current at j
and sum into Gk
For each terminal I of
the element n{
Compute the derivative for the
element:
Ij
gj, l=
Vl
Find the node m
which is attached
to terminal I
Sum in the Jacobian contribution:
Jk,m=Jk,m+gj,l
}}}}

J1,1 = 1/R1
J2,1 = 1/R1 + gm

J1,2 = 1/R1
J2,2 = 1/R1 + 1/R2

EXAMPLE SIMULATION
Most circuit simulators allow the user to ramp one or more
voltage sources and plot the voltage at any node or the current in certain branches. Returning to the differential pair of
Fig. 1, we can perform a dc analysis by simply adding a .dc
statement (see Fig. 7). The format for the dc statement is:
.dc Vname start stop step
where Vname is the source to be swept and the start, stop, and
step parameters control the sweep. For the circuit to be valid
for dc analysis:
A dc path to ground must exist from every node in the
circuit
No loops of voltage sources may exist
No cuts of current sources may exist
Each node must be connected to at least 2 elements
A plot of the differential output voltage (between the two
collectors) and the voltage at the two emitters is shown in

V1 4 0
V2 5 0
V3 1 0
R1 2 0
R2 3 1
R3 6 1
Q1 3 4
Q2 6 5
.model
.dc V1

2V
2V
5V
1k
1K
1K
2 m2n2222
2 m2n2222
m2n2222 NPN IS=1e-12 BF=100 BR=5 TF=100pS
1.0 4.0 0.01

Figure 7. Input file for dc sweep of V1.

CIRCUIT ANALYSIS COMPUTING

331

point. Therefore, before we can solve the ac problem, we must

calculate the dc bias point. Rearranging terms slightly, we
obtain

6.0 V

J + jC
C )1W ac
V ac = (J
Output

Emitters
1.0 V

0V

2.0 V

V(6)

4.0 V

V(2)

Figure 8. Output from dc analysis.

Fig. 8. Observe that the output voltage is zero when the

differential pair is balanced with 2.0 V on both inputs.
The output saturates at both high and low values for V1,
illustrating the nonlinear nature of the analysis. This simulation was run using the PSPICE package from MicroSim
corporation. The simulation runs in a few seconds on a type
486 PC.
AC ANALYSIS
The ac analysis is performed in the frequency domain under
the assumption that all signals are represented as a dc component Vdc plus a small sinusoidal component Vac.
V = Vdc + Vac exp( jt)
Here j 1, is the radial frequency (2f), and Vac is a
complex number. Expanding Eq. (1) about the dc bias point
Vdc (also referred to as the Q-point), we obtain

V ) = F (V
V dc ) + W dc + W ac +
F (V

+
t

Q

Q (V
V )
dc

V dc
V

G (V
V dc )
G
V ac
dc

V ac + V
V 2ac

The series has an infinite number of terms; however, if Vac is

sufficiently small, all terms above first order can be neglected.
The first two terms on the right-hand side are the dc solution
and when taken together yield zero. The third term Wac is the
vector of independent ac current sources that drive the circuit. The partial derivative in the fourth term is the dc Jacobian element and the derivative of Q in parentheses is the capacitance at the node. When we substitute the exponential
into the preceding equation each term will have an exponential term that can be canceled. The result of all these simplifications is the familiar result
CV ac
0 = W ac + JV ac + jCV
This equation contains only linear terms that are equal to the
partial derivatives of the original problem evaluated at the Q-

The solution at a given frequency can be obtained from a

single matrix inversion. The matrix, however, is complex but
normally the complex terms share a sparsity pattern similar
to the real terms. (See the section on the Jacobian structure.)
It is normally possible (in FORTRAN and C) to create a
suitable linear solver by taking the linear solver that is used
to calculate the dc solution and substituting complex variables for real variables. Since there is no nonlinear iteration, there are no convergence problems and ac analysis is
straightforward and foolproof. The same type of analysis can
be applied to the equations for modified nodal analysis. The
additional unknowns will, of course, be currents flowing
through the voltage sources:
J + jL
L )1E ac
I ac = (J
The only things that must be remembered with ac analysis
are the following:
1. The ac solution is sensitive to the Q-point, so if an amplifier is biased near its saturated dc output level the
ac gain will be smaller than if the amplifier were biased
near the center of its range.
2. This is a linear analysis, and therefore clipping and
slew rate effects are not modeled. For example, if a 1 V
ac signal is applied to the input of a small signal amplifier with a gain of 100 and a power supply voltage of 5
V, ac analysis will predict an output voltage of 100 V.
This is, of course, impossible since the output voltage cannot exceed the power supply voltage of 5 V.
Transient analysis should be used to include these
effects.
AC ANALYSIS EXAMPLE
In the following example we will analyze the differential pair
using ac analysis to determine its frequency response. To perform this analysis in SPICE we need only specify which
sources are the ac driving sources (by adding the magnitude
of the ac signal at the end) and specify the frequency range
on the .AC statement (Fig. 9). SPICE lets the user specify

V1 4 0 2V AC 1
V2 5 0 2V
V3 1 0 5V
R1 2 0 1k
R2 3 1 1K
R3 6 1 1K
Q1 3 4 2 m2n2222
Q2 6 5 2 m2n2222
.model m2n2222 NPN IS=1e-12 BF=100 BR=5 TF=100pS
.AC DEC 10 1e3 1e9

Figure 9. Input file for ac analysis.

332

CIRCUIT ANALYSIS COMPUTING

the range as linear or decade, indicating that we desire a

logarithmic frequency scale. The first number is the number
of frequency points per decade, the second number is the
starting frequency, and the third is the ending frequency.
Figure 10 shows the results of the analysis. The gain begins to roll off at about 30 MHz due to the parasitic capacitances within the transistor models. The input impedance
(which is plotted in kilohms) begins to roll off at a much lower
frequency. The reduction in input impedance is due to the
increasing current that flows in the base-emitter capacitance
as the current increases. SPICE does not have a method of
calculating input impedance, so we have calculated it as Z
Vin /I(Vin), where Vin 1.0, using the postprocessing capability
of PSPICE. This analysis took about 2 s on a 486-type PC.

20 nV

Output noise

Input noise
0V
1.0 kHz

1.0 MHz
Frequency

V(INOISE)

Noise Analysis
Noise is a problem in circuits that are designed for the amplification of small signals, like the radio frequency (RF) and
intermediate frequency (IF) amplifiers of a receiver. Noise is
the result of random fluctuations in the currents that flow in
the circuit and is generated every circuit element. In circuit
simulation, noise analysis is an extension of ac analysis. During noise analysis it is assumed that every circuit element
contributes some small noise component, either as a voltage
Vn in series with the element or as a current In across the
element. Since the noise sources are small in comparison with
the dc signal levels, ac small-signal analysis is an appropriate
analysis method.
Different models have been developed for the noise
sources. In a resistor thermal noise is the most important
component. Thermal noise is due to the random motion of the
electrons:
In2 =

4kT f
R

where T is the temperature, k is Boltzmanns constant, and

f is the bandwidth of the circuit. In a semiconductor diode
shot noise is important. Shot noise is related to the probability that an electron will surmount the semiconductor barrier
energy and be transported across the junction:
In2 = 2qId  f

15

1.0 GHz

V(ONOISE)

Figure 11. Noise referenced to output and input.

There are other types of noise that occur in diodes and transistors (examples are flicker and popcorn noise). Noise
sources, in general, are frequency dependent.
Noise signals will be amplified or attenuated as they pass
through different parts of the circuit. Normally, noise is referenced at an output point called the summing node. This
would normally be the output of the amplifier where we would
actually measure the noise. The gain between the summing
node and the current flowing in an element j in the circuit is
defined as Aj( f ). Here f is the analysis frequency since this
gain will normally be frequency dependent.
Noise signals are random and uncorrelated to each other,
so their magnitudes must be root-mean-square summed
rather than simply summed. Summing all noise sources in a
circuit yields
In ( f ) =



A2j ( f )I 2j ( f )

It is also common to reference noise back to the amplifier input, and this is easily calculated by dividing the preceding
expression by the amplifier gain. Specifying noise analysis in
SPICE is simple. All the user needs to do is add a statement
specifying the summing node and the input source. SPICE
then calculates the noise at each as a function of frequency
.noise V(6) V1

Gain

See Fig. 11 for example output. Many circuit simulators will

also list the noise contributions of each element as part of the
output. This is particularly helpful in locating the source of
noise problems.

Input
impedance

TRANSIENT ANALYSIS

0
1.0 KHz
V(6)

1.0 MHz
Frequency

1.0 GHz

0.001/I(V1)

Figure 10. Gain and input impedance calculated by ac analysis.

Transient analysis is the most powerful analysis capability

because the transient response of a circuit is so difficult to
calculate analytically. Transient analysis can be used for
many types of analysis, such as switching speed, distortion,
and checking the operation of circuits like logic gates, oscillators, phase-locked loops, or switching power supplies. Transient analysis is also the most CPU (central processing unit)

CIRCUIT ANALYSIS COMPUTING

intensive and can require 100 or 1000 times the CPU time of
dc or ac analysis.
Numerical Integration Methods
In transient analysis time is discretized into intervals called
timesteps. Typically the timesteps are of unequal length, with
the smallest steps being taken during intervals where the circuit voltages and current are changing most rapidly. The following procedure is used to discretize the time-dependent
terms in Eq. 1.
Time derivatives are replaced by difference operators, the
simplest of which is the forward difference operator (also
known as the forward Euler method):
Q(tk+1 ) Q(tk )
Q(tk )
=
t
h
where the timestep h is given by
h = tk+1 tk
This equation is easily solved for the charge Q(tk1) at the next
time point:
Gi (V
V (tk )) + W i (tk ))
Q (tk+1 ) = Q (tk ) h(G
using only values from past time points. This means that it
would be possible to solve the system simply by plugging in
the updated values for V each time. This can be done without
any matrix assembly or inversion and appears to be very efficient. (Note that for simple linear capacitors, V Q/C at
each node, so it is easy to get V back from Q). However, this
approach is undesirable for circuit simulation for two reasons:
(1) The charge Q, which is a state variable of the system, is
not a convenient choice since some nodes may not have capacitors (or inductors) attached, in which case they will not have
Q values; (2) a more serious problem is that forward (or explicit) time discretization methods like this one are unstable
for stiff systems, and most circuit problems result in stiff
systems. The term stiff system refers to a system that has
greatly varying time constants.
To overcome the stiffness problem, we must use implicit
time discretization methods, which in essence means that the
G and W terms in the preceding equations must be evaluated
at tk1. Since G is nonlinear we will need to use Newtons
method once again.
The most popular implicit method is the trapezoidal
method. The trapezoidal method has the advantage of only
requiring information from one past time point, and furthermore it has the smallest error of any method requiring one
past time point. The trapezoidal method states that if Ic is the
current in a capacitor, then
(t k+1 )

Ic

Q(Vc (tk+1 )) Q(Vc (tk ))

Q
=2
Ic (tk )
t
tk+1 tk

Therefore, we need only substitute the preceding equation

into Eq. (1) to solve the transient problem.
Observe that we are solving for the voltages V(tk1), and all
terms involving tk are constant and will not be included in the
Jacobian matrix. An equivalent electrical model for the capac-

333

Ic

Vc

h
2C

I c

2 C V c
h
Figure 12. Electrical model for a capacitor. The two current sources
are independent sources. The prime indicates values from preceding
time point.

itor is shown in Fig. 12. Therefore, the solution of the transient problem is, in effect, a series of dc solutions, where the
values of some of the elements depend on voltages from the
previous time points.
The procedure for transient analysis is as follows:

Compute dc solution to provide initial conditions

Repeat until (ttstop){
Compute time step h based on LTE
Repeat until converged{
For each element n{
For each terminal j of the element n{
Determine the node k to
which j is attached.
if (k0){
2
Compute Ickj+1=
h
(Qj(V(tk1))-Qj(V(tk)))
Sum into current vector:
Fm=Ij+Ickj+1-Ickj+Wj(tk+1)
Compute the current at
terminal j and sum into
Gk
For each terminal I of
the element n {
Compute the derivative
for the element:
Ij(V(tk)) 2 Qj(V(tk))
gj,l=
+
Vl
h
Vl
Find the node m which
is attached to terminal
I
Sum in the Jacobian
contribution:
Jk,m=Jk,m+gj,l
}}}
Solve X=JF
V=V-X
}
t=t+h
}
All modern circuit simulators feature automatic timestep
control. This feature selects small timesteps during intervals
where changes are occurring rapidly and large timesteps in
intervals where there is little change. The most commonly
used method of timestep selection is based on the local trun-

334

CIRCUIT ANALYSIS COMPUTING

large (say, five times the error criteria) the simulator will reduce the timestep (usually by 1/2) and go back and recompute
the point. In addition, most simulators select time points so
that they coincide with the edges of pulse-type waveforms.

3.0 V

TRANSIENT ANALYSIS EXAMPLES

2.0 V

0s

20 ns

40 ns

As a simple example, we return to the differential pair and

apply a sine wave differentially to the input (Fig. 13). The
amplitude (2 V peak to peak) is selected drive the amplifier
into saturation. In addition, the frequency (50 MHz) is set
high enough to see phase shift effects. The output signal is
therefore clipped due to the nonlinearities and shifted in
phase due to the capacitive elements in the transistor models.
The first cycle shows extra distortion since it takes time for
the zero-state response to die out. This simulation runs in
about a second on a type-486 computer.
As a final example, a phase-locked loop (PLL) circuit,
which is used as a 4 frequency multiplier, is simulated.This
circult is shown in Fig. 14 and includes digital, analog, and
behavioral components. This particular circuit is designed
primarily to illustrate the capabilities of simulation. Phaselocked loops are difficult circuits to simulate since they can
have greatly varying frequency components. The input to the
circuit is a 1 MHz signal (at node 1) and the output is a 4
MHz signal at node 9. Phase-locked loops have three main
components: a voltage controlled oscillatory (VCO), a phase
detector, and a loop filter. In this circuit the VCO is made up
of a summer, an integrator, and a ideal sine element, which
simply computes the sine of its input. Resistors R2 and R3
form a voltage divider and set the voltage at node 8 to 2.5 V.
The signal at node 9 of the VCO is therefore

60 ns

Time
V(6,3)

V(6,3)

Figure 13. Transient response V(6,3) of differential amplifier to sinusoidal input at V(4,5).

cation error (LTE) for each timestep. For the trapezoidal rule,
the LTE is given by
=

h d3x
( )
12 dt 3

and represents the maximum error introduced by the trapezoidal method at each timestep. The trapezoidal method is
a second-order method since the error is proportional to the
timestep cubed. The LTE for a time point can only be computed after the solution at that point is known. LTE timestep
control methods calculate the timestep for the next time point
from the LTE at the preceding time point by assuming that
the error at each step to be as close to a certain small fixed
value (usually 0.1%) as possible.

h=


12

d3x
dt 3

M1
3
2

V2

1.7 V

Sin

0V
R2

U9A
3 Qa
4 Qb
5 Qc
6 Qd
CLR

Ie7

2n
C1

and V(5) is the VCO control voltage. Note that PSPICE generates the integrator from a capacitor, a voltage-controlled current source (G) and a voltage-controlled voltage source (E).

S1

R1

S2
0

(V (5) + 2.5) dt
0

1k
V1

= sin(107 (V (5) + 2.5) t)

(We are assuming that the required h does not change much
from timestep to timestep.) If, after computing the solution at
a new time point, we find that the LTE at that point is very

V (9) = sin 107

1k

R3
1k

10

1
20

R4

R5
500

1k

5V

Q1

+ V4

11
V3

0
Figure 14. Phase-locked loop circuit.

R6

CIRCUIT ANALYSIS COMPUTING

to convert the analog input to a digital input and the digital

output to an appropriate analog signal.
Figure 16 shows the signal from output of Summer S1. The
PLL capture transient can be seen. Since the signals at V(1)
and V(7) are initially out of phase and at slightly different
frequencies, it takes some time for the PLL to lock onto the
input signal. The noise on V(4) is the high-frequency output
from the multiplier (V(1)V(7)). The PLL simulation requires
about 5 min of CPU time on a type-486 computer.

20$AtoD
U9A:QA
U9A:QC
U9A:QD

4.0 V

CONVERGENCE ISSUES

Sel>>
3.0 V
40 s

45 s
Time

V(7)

50 s

V(1)*5

Figure 15. Outputs from the PLL simulation.

The network of Q1, R4, R5, and R6 is an overdriven amplifier

that converts the sinusoidal signal at V(9) into a square wave
for driving U9A. Integrated circuit U9A is a 4-bit binary
counter. Voltage source V(3) applies a pulse at the start of the
simulation to UA9s Clear (CLR) input to zero the counters.
Since the output is taken at Qb, the signal at V(7) is at one
fourth the frequency of V(9). The free running frequency of
the signal at V(7) is therefore 2.57/2 or 0.9947 MHz. The
digital output at V(7) has Vh 3.6 V and VI 0.2 V. Summer
S2 is therefore used to shift the dc value of V(7) back to zero
volts for application to the phase detector. The phase detector
is a simple ideal multiplier (M1). The low-pass loop filter is
made up of resistor R1 and capacitor C1.
The output from the PLL simulation is shown in Figs. 15
and 16. Figure 15 shows waveforms from the last 10 s of the
50 s simulation. The bottom figure shows the signal from
U9A (the binary counter and the input signal at node 1). It
can be seen that the two signals are locked in phase as they
should be. The top figure shows the digital waveforms at input and outputs of U9A. It can be seen that the binary
counter is operating correctly. The model for U9A is a digital
block with high, low, and undetermined signal levels
rather than analog signal levels (The U9A model contains no
transistors.) Using digital models is much faster than using
the analog equivalent (which in this case would require close
to 100 transistors). The ability to mix analog and digital
blocks is known as mixed-mode simulation. Special conversion operators are applied at the inputs and outputs of U9A

2.6 V

2.3 V

335

0s

Time

V(4)
Figure 16. PLL output from loop filter.

50 s

Considering that a circuit can contain thousands of nodes requiring the solution of thousands of simultaneous nonlinear
equations, it is amazing that Newtons method can converge
at all. Unfortunately, there are many cases when Newtons
method needs help and we will address a few methods here.
Many convergence problems are caused by an initial guess
that lies far from the true solution. One way of improving the
initial guess is through projection. Projection does just as its
name implies and uses two previous solutions to calculate an
initial guess. In time-dependent simulations we can use the
following linear projection:
V i+1 = V i +

(V i V i1 )(t i+1 t i )
t i t i1

Higher-order methods can also be used, but linear projection

is the safest. A variant method uses the Jacobian matrix and
has the advantage that it can be used when only one past
solution is available, but it is more work to program and compute:
V i+1 = V i + J(V i )1

F i+1
(t
ti )
t

Projection can also be used for calculating dc solutions by

combining it with the continuation method, discussed next.
Computing the first dc solution to a fully powered is a difficult task. It would be much easier if we could start from
some known solution and gradually move to the true solution.
Techniques that do this are referred to as continuation methods. A common method is source stepping, which in effect
ramps up the power supplies and gradually turns the circuit
on. The method is as follows:
Source Stepping Algorithm
1. Modify all independent voltage and current sources so
that their value is the original value multiplied by the
continuation constant ki. Here the superscript i is the
continuation iteration counter.
2. Start with k0 0 so that all independent voltage and
current sources set to zero. The solution to this problem
will be that all voltages and currents everywhere must
also be zero.
3. Set k1 0.1 or other small number and solve using the
solution from step k0 as the initial guess.
4. If the Newton sequence converges, set i i 1, increase k, and solve again using the solution from ki1 as
the initial guess. If the Newton sequence does not converge, reduce k to a smaller value (usually (ki

336

CIRCUIT ANALYSIS COMPUTING

ki1)/2) and try again. The projection techniques described previously can be applied simply by replacing t
with k.
5. Repeat step 4 until k 1, at which point all the dependent voltage and current sources will be at their correct values.

M3

M4

R1

R2

Vdd

While it would appear that this method should be foolproof, it can be shown that source stepping will fail for certain
circuits. Consider a circuit consisting of a voltage source driving an element with an IV characteristic similar to that of
Fig. 17. The locus of solutions is the intersection of the vertical line in the figure with the curve. Convergence would typically fail at point A since the solution jumps abruptly to point
B. The only way to proceed beyond point A is to convert the
voltage source to a current source and continue on by stepping in current. This would, in effect, change the vertical line
to a horizontal line, in which case there are no abrupt transitions.
There is no method of solving nonlinear equations that is
always guaranteed to work. A particularly serious convergence problem is caused by bad conditioning of the Jacobian.
A matrix is badly conditioned if its determinate is close to
zero. Since the inverse of a matrix is related to the inverse
of its determinate, if the Jacobian is badly conditioned small
changes in F(V) result in very large changes in V, which can
make convergence difficult. Bad conditioning results from
nodes that are isolated or nearly isolated. Consider the circuit
in Fig. 18, which contains two resistors. The Jacobian matrix is
1/R1
1/R1

1/R1
(1/R1 + 1/R2 )

As R2 approaches infinity, the two rows become identical and

(or, more precisely, linearly dependent) and the determinate
that is 1/(R1R2) becomes zero. Another way of looking at the
problem is that with infinite R2, R2 disappears and nodes 1
and 2 can be assigned any voltage (as long as both are the
same) and a valid solution will result.
An example of a real circuit that exhibits bad conditioning
is the CMOS logic gate shown in Fig. 18. Node 1 is attached
to the gates of the second invertor and the drains of the first.
In a dc simulation, the MOSFET gates that have only capacitance function as an open circuit. If the power supplies and

Current I

A
Voltage V
Figure 17. A case that will not converge.

M1

M2
0

Figure 18. Two badly conditioned circuits.

all nodal voltages are set to zero (as we would do for source
stepping), all the MOS devices would be biased with Vgs 0
or Vgs Vth (i.e., in the off state). In many MOS models, if the
device is off, the drain current and the drain conductance
(Id /Vds) are zero. This causes node 1 to be isolated and
causes bad conditioning, which can make it impossible to find
a solution.
Observe that improving the initial guess will not help in
the case of convergence failure due to bad conditioning. A possible solution might be to improve the accuracy of the linear
solver by the use of pivoting or scaling schemes, but there is
usually a CPU penalty involved. A common solution is to connect a small conductance from every node of the circuit to
ground, thereby eliminating isolated nodes. However, if the
conductance is made too large, it effectively alters the circuit,
which can produce incorrect results (in SPICE this conductance is referred to as Gmin). For the CMOS circuit, once the
circuit is biased at full power, at least one of the MOSFETs
will be in the conducting state and node 1 will no longer be
isolated. This suggests that if we use the source-stepping algorithm, we could use a large conductance during the early
phase when k is small and nodes may be isolated and gradually reduce Gmin as k approaches 1. Note, however, that some
CMOS circuits (for example, those containing a transmission
gate) can have isolated nodes even with full power applied.
THE JACOBIAN MATRIX STRUCTURE AND LINEAR SOLUTION
The form of the Jacobian matrix of a circuit depends on how
the nodes are connected by the circuit elements. Each element
introduces a dependencythat is, if an element connects
node i to node j then the current at node j depends on the
voltage at node i and vice versa. Therefore, an element Ji, j
will be nonzero only when there is an element connected between nodes i and j.
The exception to this rule are the diagonal entries that indicate how the current at a node depends on its own voltage.
In most cases, the diagonal entries will be nonzero. A circuit
element with two terminals such as a resistor or capacitor
will make four nonzero contributions to the Jacobian matrix.
If the resistor is connected bewteen nodes i and j, it will contribute a conductance of G 1/R to the Jacobian entries
Ji, j and Jj,i and will contribute G 1/R to the diagonal entries
Ji,i and Jj, j. An element with three terminals, like a bipolar
transistor, will contribute to nine entries in the Jacobian
(three on the diagonal), and a MOSFET with four terminals
will contribute to 16 Jacobian entries.

CIRCUIT ANALYSIS COMPUTING

Most circuits do not have elements connecting every node

to every other node. Typically, as circuits grow larger the ratio of connections at each node to the number of total nodes
becomes smaller. As a result in most circuits the Jacobian
matrix is very sparse, meaning that most of its entries are
zero. Due to this sparseness, the number of nonzero elements
normally depends linearly on the number of total nodes
rather than quadratically, as would be expected for a full matrix. Circuit simulation programs employ a sparse matrix
storage system that only stores the nonzero elements. Typical
systems use three vectors. The first vector A contains the
floating-point nonzero entries in the matrix. The second vector IA contains the integer row indices. The third vector JA
contains pointers to the location of the start of each column
in IA. Consider the following example matrix:

1.0
0
0
5.0

3.0
4.0
0
0

0
0
7.0
0

0
9.0
6.0
8.0

The vector A contains [1.0, 5.0, 3.0, 4.0, 7.0, 9.0, 6.0, 8.0]. The
vector IA contains [1, 4, 1, 2, 3, 2, 3, 4], and JA contains [1,
3, 5, 6, 9]. There are other storage systems (for example, some
programs store the matrix row wise rather than column wise;
it is also common to store the diagonal entries in a separate
floating-point array or force the matrix to be symmetric by
padding with zeros and then only use pointers to the upper
1/2).
Solving the linear problem Ax b for a full matrix is normally performed using the LU decomposition followed by forward and back solve operations. The LU decomposition factors the matrix A into the product of two matrices L and U.
L is lower triangular, meaning that all entries above the diagonal are zero. U is upper triangular meaning that all its entries below the diagonal are zero. Thus Ax b becomes
LUx b or Ly b followed by Ux y. Since L and U are
triangular, these are easy to solve. The code for a full matrix
is easy to program for the LU decomposition:

for(i=1 to n-1 ) {
for(j=i+1 to n) {
a(j,i)=a(j,i)/a(i,i)
}
for(j=i+1 to n) {
for(k=i+1 to n) {
a(j,k)=a(j,k)-a(j,i)*a(i,k)
}
}
}
The preceding code is Dolittles method and computes the LU
decomposition in place, meaning that the computes L and
U are written over the original elements in A. The forward
solve is
for(i=1 to n-1) {
for (j=i+1 to n) {
b(j)=b(j)-a(j,i)b(i)
}
}

337

And the back solve is

for (i=n to 2){

b(i)=b(i)/a(i,i)
for (j=1 to i-1) {
b(j)=b(j)-a(j,i)b(i)
}
}
b(1)=b(1)/a(1,1)
The forward and back solve are also done in place so that
when the process is finished, x resides in b. Observe that the
decomposition step can result in the creation of nonzero
entries where previously there were zeros [For example, if
a(i, j) 0 but a( j, i) and a(i, k) are not zero.] These newly
generated elements can generate additional nonzero elements, causing the nonzeros to propagate. This process is
referred to as creating fill and occurs only within the
bandwidth of the matrix A (i.e., new nonzeros are generated
only at locations between existing elements in A and the
diagonal). The fill terms can increase the computer memory
and CPU requirements. Fortunately, the bandwidth of the
matrix and resulting fill can be reduced by proper reordering of the circuit equations. The number of nonzero entries
in the Jacobian and result of the solution is independent
of how the nodes are numbered (assuming ideal arithmetic),
but the locations of the nonzero entries will depend on
the node ordering. A number of algorithms exist for this
renumbering process.
Double precision arithmetic is used throughout most circuit simulators. In some cases it may be desirable to use partial pivoting to improve the accuracy of the linear solution.
Recent research has focused on the use of iterative linear
solvers instead of the directed solver, which was outlined previously. The simplest of these is Gauss-Sidel, but modern versions often used preconditioned gradient or minimization
techniques. Iterative solvers may be faster, more accurate,
and use less memory than the direct solver but can introduce
additional convergence problems of their own since now iteraction is involved in the linear as well as nonlinear solution.
Iterative solvers are often more sensitive to bad conditioning
of the Jacobian matrix than the LU decomposition.

FAST SIMULATION METHODS

As circuits get larger simulation times become longer. In addition, as integrated circuit feature sizes shrink, second-order
effects become more important, and many circuit designers
would like to be able to simulate large digital systems at the
transistor level (requiring 10,000 to 100,000 nodes). Numerical studies in early versions of SPICE showed that the linear
solution time could be reduced to 26% for relatively small circuits with careful coding. The remainder is used during the
assembly of the matrix, primarily for model evaluation. The
same studies found that the CPU time for the matrix solution
was proportional to n1.24, where n is the number of nodes. The
matrix assembly time, on the other hand, should increase linearly with node count. Circuits have since grown much bigger, but the models (particularly for MOS devices) have also
become more complicated.
Matrix assembly time can be reduced by a number of
methods. One method is to simplify the models; however, ac-

338

CIRCUIT ANALYSIS COMPUTING

curacy will be lost as well. A better way is to precompute the

charge and current characteristics for the complicated models
and store them in tables. During simulation the actual current and charges can be found from table lookup and interpolation, which can be done quickly and efficiently. However,
there are some problems:
1. To ensure convergence of Newtons method, both the
charge and current functions and their derivatives must
be continuous. This rules out most simple interpolation
schemes and means that something like a cubic spline
must be used.
2. The tables can become large. A MOS device has four
terminals, which means that all tables will be functions
of three independent variables. In addition, the MOSFET requires four separate tables (Id, Qg, Qd, Qb). If we
are lucky, we can account for some parametric variations (like channel width) by a simple multiplying factor. However, if there are more complex dependencies,
as is the case with channel length, oxide thickness, temperature, or device type, we will need one complete set
of tables for each device.

If the voltages applied to an element do not change from

the past iteration to the present iteration, then there is no
need to recompute the element currents, charges, and their
derivatives. This method is referred to as bypass or taking
advantage of latency and can result in large CPU time
savings in logic circuits, particularly if coupled with a
method that refactors only part of the Jacobian matrix. The
tricky part is knowing when the changes in voltage can be
ignored. Consider, for example, the input to a high gain op
amp. Here ignoring a microvolt change at the input could
result in a large error at the output. Use of sophisticated
latency determining methods could also cut into the CPU
time savings.
Another set of methods are the waveform relaxation techniques, which increase efficiency by temporarily ignoring couplings between nodes. The simplest version of the method is
the GaussSeidel method which is as follows. Consider a circuit with n nodes that requires m time points for its solution.
The circuit can be represented by the vector equation
Fi (V (t)) +

dQi (V (t))
=0
dt

Using trapezoidal time integration gives a new function.

Wi (V (k)) = (Fi (V (k)) + Fi (V (k 1))) b
+ 2[Qi (V (k)) Qi (V (k 1))] = 0
We need to find the V(k) that makes W zero for all k 1 to
m time points at all i 1 to n nodes. The normal method
solves for all n nodes simultaneously at each time point before
advancing k. Waveform relaxation solves for all m time points
at a single node (calculates the waveform at that node) before
advancing to the next node. An outer loop ensures that all the

individual nodal waveforms are consistent with each other

(global convergence):

Iterate on j global convergence is obtained{

for node i=1 to n{
for timepoint k=1 to m{
Iterate on l until convergence is obtained{
Vli(k,j)=Vli-1(k,j)
Wi(V1(k,j-1),V2(k,j-1);Vli-1(k,j),Vn(k,j-1))
W/Vi(k,j)
}}}}
Observe that the innermost loop (on l) uses Newtons
method to solve the nonlinear equation. However, only a single variable is solved for. In addition, W and its derivative are
functions only of (Vl1
i (k, j)); all the other terms are constant
during iteration on l. Waveform relaxation is extremely efficient as long as the number of outer loops (on j) is small. The
number of iterations of j will be small if the equations are
solved in the correct order (that is, starting on nodes that are
signal sources and following the direction of signal propagation through the circuit). This way the waveform at node i
1 will depend strongly on the waveform at node i, but the
waveform at node i will depend weakly on the signal at node
i 1. The method is particularly effective if signal propagation is unidirectional, as is sometimes the case in logic circuits. During practical implementation, the total simulation
interval is divided into several subintervals and the subintervals are solved sequentially. This reduces the total number of
time points that must be stored in central memory. Variants
of the method solve small numbers of tightly coupled nodes
as a group; such a group might include all the nodes in a
transistortransistor logic (TTL) gate or in a small feedback
loop. Large feedback loops can be handled by making the simulation time for each subinterval less than the time required
for a signal to propagate around the loop. The efficiency of
this method can be further improved by using different timesteps (h) at different nodes yielding a multirate method. This
way during a given interval, small time steps are used on
active nodes, whereas long steps are used at inactive nodes.
Waveforms at nodes may also be computed in parallel on a
multiprocessor computer since waveforms at iteration j depend only on voltages at other nodes from iteration j1 (the
i 1 to n loop can be parallelized).
COMMERCIALLY AVAILABLE SIMULATORS
The simulations in this article were performed with the evaluation version of PSPICE from Microsim. The following vendors market circuit simulation software. The different programs have strengths in different areas, and most vendors
allow users to try their software in-house for an evaluation
period before they buy.
SPICE2-SPICE3, University of California Berkeley, CA
PSPICE, Microsim Corporation, Irvine, CA
HSPICE, MetaSoftware, Campbell, CA
ISPICE, Intusoft, San Pedro, CA
SABER, Analogy, Beaverton, OR
SPECTRE, Cadence Design Systems, San Jose, CA

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

TIMEMILL, Epic Corporation, Sunnyvale, CA

ACCUSIM II, Mentor Graphics, Wilsonville, OR
BIBLIOGRAPHY
On General Circuit Simulation
J. A. Connelley and P. Choi, Macromodeling with SPICE, Engelwood
Cliffs, NJ: Prentice-Hall, 1992.
P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1977.
K. Kundert, The Designers Guide to SPICE and SPECTRE, Kulwer
Academic, 1995.
L. Nagel, SPICE2: A Computer Program to Simulate Semiconductor
Circuits, Ph.D. Thesis, University of California, Berkeley, 1975.
A. E. Ruehli (ed.), Circuit Analysis, Simulation and Design, Part 1,
North Holland: Elsevier Science Publishers, 1981.
P. W. Tuinenga, SPICE, A Guide to Circuit Simulation and Analysis
Using PSPICE, Englewood Cliffs, NJ: Prentice-Hall, 1988.
J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and
Design, New York: Van Norstand Reinhold, 1983.
A. Vladimiresch, The SPICE Book, New York: Wiley, 1994.
On Modern Techniques
A. E. Ruehli (ed.), Circuit Analysis, Simulation and Design, Part 2,
North Holland: Elsevier Science Publishers, 1981.
On Device Models
P. Antognetti and G. Massobrio, Semiconductor Modeling with
SPICE2, 2 ed. New York: McGraw-Hill, 1993.

J. GREGORY ROLLINS
MTS, Antrim Design Systems

339

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

Computing dc operating points is an essential task in simulating electronic circuits. It involves solving systems
of nonlinear algebraic equations. Traditional methods for solving these equations often fail, exhibit convergence
difficulties, and seldom find all the solutions. Recent application of parameter embedding methods, also called
continuation and homotopy methods, proved successful in solving circuit nonlinear equations and, thus, in
computing dc operating points of circuits that pose simulation difficulties and could not be simulated using
more conventional techniques. The usefulness of the parameter embedding methods depends on the type of
a circuits descriptive equations. Such methods are an order of magnitude slower than conventional methods,
but their speed can often be improved by careful implementation. They are becoming a feasible alternative to
the existing options in circuit simulators, where they can be used to resolve convergence difficulties and to find
multiple solutions.

Dc Behavior of Nonlinear Electronic Circuits

An understanding of circuits dc behavior is crucial for the analysis and design of electronic circuits. Numerous
electronic circuits employ nonlinear elements. Dc equations that describe such electronic circuits are systems
of nonlinear algebraic equations. Such equations often have multiple solutions, which are called the circuits
dc operating points. For example, inherently nonlinear bistable circuits that possess two stable isolated equilibrium points are used in a variety of electronic designs, such as static random-access memory cells, latches,
flip-flops, and shift registers. The operation of a Schmitt trigger is also intimately related to the circuits ability to possess multiple dc operating points. Oscillator circuits employ structures that require the presence of
nonlinear components. All these circuits exhibit a rich variety of nonlinear behaviors and can possess multiple
operating points.
Recent advances in computer-aided design (CAD) tools for circuit simulation have set designers free from
the need to perform lengthy and tedious, but often only approximate, calculations to compute circuit currents
and voltages. The SPICE circuit simulator (1,2,3) has become an industry standard, and many SPICE-like CAD
tools are in use today. Nevertheless, the problem of computing the dc operating points of transistor circuits can
be a difficult task. The exponential nature of the diode-type nonlinearities that model semiconductor devices
can cause computational difficulties, and the fact that the equations describing transistor circuits can have
multiple solutions causes concern that the correct solution has not been found.

Achieving Convergence in Circuit Simulators

Most SPICE-like circuit simulators compute dc operating points by using the NewtonRaphson (NR) method
or one of its variants. These methods are robust and quadratically convergent when a good starting point,
sufficiently close to a solution, is supplied. Variant schemes, such as the damped Newtons method, have been
1

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

proven globally convergent only under unrealistically restrictive conditions (4,5). They sometimes fail because it
is difficult to provide a starting point sufficiently close to an unknown solution. It has been proven that Newtons
method converges in the case of arbitrary single-transistor networks, and certain circuit-theoretic sufficient
conditions are given that guarantee convergence in the case of n-transistor networks (6). The extension of this
result beyond the one-transistor case, even for such special cases as multitransistor circuits having no feedback
structure (7) and thus possessing a unique operating point, is still an open problem (8).
To help dc convergence, experienced designers of analog circuits use several ad hoc techniques (9) that
still rely on NR methods for solving nonlinear circuit equations. In the source-stepping algorithms, a ramping
function is used for the sources and the circuit simulator provides a series of operating points until the response
to the original set of driving voltages is obtained. In the temperature-sweeping procedure, the temperature is
swept starting from a certain value (usually zero) and a dc operating point of the circuit is found. Then, using
this value as a starting point, the temperature is increased and the new dc operating point calculated. The
process is repeated until the dc operating point at the desired temperature is found. In another technique,
known to the design community as Gmin -stepping, small conductances are placed between every circuit node
and ground. The initial value of the conductances is chosen large enough to ensure (if possible) the convergence
of the NR method. The added conductances help convergence, since they contribute to the diagonal elements
of the circuits Jacobian matrix and can force it to become row or column sum dominant. If the operating point
of the circuit is found, it is used to set initial node voltages for the next step. The auxiliary conductances are
further decreased until a default minimum value is reached.
Another known method for improving dc convergence that is used by circuit designers is pseudotransient
analysis (10). The original resistive network is transformed into a dynamical network by adding pseudo
capacitors and inductors to the original circuit. The excitation is set to a ramped function that saturates at the
desired dc value. Therefore, a set of nonlinear algebraic equations

describing the resistive circuits is replaced by a set of singular perturbed differential equations

The time-domain response of the circuit is found and the analysis performed until the circuits transient
response vanishes. Unfortunately, this type of embeddings can produce stiff problems and cause various
stability problems that can fail to produce the desired solution.
The described methods implicitly exploit the idea of embedding or continuation: a variation of a parameter
over a range of values until it reaches the value for which the operating point is desired. The methods often
work because each subsequent dc operating point is found by using the previous result as the starting point for
the NR method. Nevertheless, in many circuits that possess multiple dc operating points, these ad hoc methods
fail because of the presence of bifurcations in the continuation path leading to the solution.

Parameter Embedding, Continuation, and Homotopy Methods

Parameter embedding methods (11), also known as continuation methods and homotopy methods, have shown
promise in resolving the computational difficulties often encountered in transistor network simulations (12,13,
14,15,16,17,18,19,20). To employ a continuation method we embed a continuation parameter in the circuits
nonlinear equations. By setting the parameter to zero, the system is reduced to one whose equations can be
solved easily or whose solution is known. The solution to this simple problem becomes the starting point of
a continuation path. The augmented equations are then continuously deformed, as the parameter is varied,

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

until they finally describe the originally posed difficult problem. For example, let

be the nonlinear equation to be solved, where

Let us create a homotopy mapping

We then solve the equation

while varying .
An example of a simple homotopy is

where R1 is the continuation parameter, a Rn is the starting vector for the homotopy path, and F(x) = 0
is the nonlinear equation to be solved. This homotopy mapping H(x, ) has the following properties:

If the nonlinear equations satisfy certain coercivity conditions (21), homotopy methods can be made
globally convergent and bifurcation free; that is, they will converge to a solution from an arbitrary starting
point (22). By exploiting the passivity (23) and no-gain (24) properties of the circuit elements, transistor circuit
equations can be shown to satisfy such conditions (25). It has also been proven that other forms of equations
describing transistor circuits also satisfy such conditions (20).
Continuation methods described here rely on the continuous characteristics of the nonlinear circuit
elements. An alternate approach to solving circuit equations is provided by simplicial methods, which deal with
piecewise-linear characteristics of circuit elements (26). Simplicial methods provide alternative techniques for
following a homotopy path and the underlying homotopies are very similar. One of their disadvantages is that
in practice, models of nonlinear circuit elements come in continuous form.

Homotopies for Solving a Circuits Dc Equations

Various homotopics can be constructed from the circuits nodal or modified-nodal formulation. They can often
find all the solutions to a circuits dc equations.
The fixed-point homotopy is based on the equation

where, in addition to the parameter , a random vector a and a new parameter (a diagonal matrix) G Rn
Rn is embedded. With probability one a random choice of a gives a bifurcation-free homotopy path (22). This

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

homotopy has an interesting circuit interpretation. If F(x) describes a transistor circuits nodal equations, this
homotopy represents equations written for an augmented circuit. A branch consisting of a conductance Gk (1
)/ connected in series with a grounded voltage source ak is connected to every node for which a nodal equation
is written. At = 0, the starting point of the homotopy path, the added branches contain only a voltage source
and hence force the nodal voltages to be equal to the elements ak of the random vector a. As increases, the
added conductances come into play. When = 1, the added branches get disconnected from the circuit and the
augmented circuit reverts to the original circuit.
The variable-stimulus homotopy is based on the equation

where the node voltages of the nonlinear elements are multiplied by . The starting point of the homotopy
corresponds to the setting of all voltages across the nonlinear elements to zero, and hence it is the solution to
a linear circuit.
The fastest converging homotopy for bipolar circuits is the variable-gain homotopy:

where is a vector consisting of transistor forward and reverse current gains. These current gains are multiplied
by . Setting = 0 forces all transistor current gains to zero at the beginning of the continuation process. This
solution point corresponds to the dc operating point of a circuit consisting of resistors and diodes only. Such a
circuit always possesses a unique dc operating point, and its dc equations can be solved easily. For example,
an efficient way to find the starting point of the homotopy path is to employ the variable stimulus homotopy to
solve the nonlinear circuit consisting of resistors and diodes only. Then the variable-gain homotopy is used to
find the dc operating points of the original circuit. Through small and carefully selected changes of , the circuit
is slowly deformed and the coupling of the transistors pn junctions is introduced. For each instance of , the
circuit equations are solved (i.e., a dc operating point is found). The original circuit and its dc operating point
is obtained when = 1. This combination of variable-stimulus and variable-gain homotopy has been named
the hybrid homotopy.
The modified variable-stimulus homotopy, chosen for its simplicity and ease of implementation, has been
used in a production version of a circuit simulator (15,16):

Choosing a good starting point for the homotopy method is essential to ensure fast convergence of the
algorithm. In circuit terms, a good starting point may be a solution to a linear circuit or to a nonlinear circuit
that has a unique solution. The choice of the starting point is important because it will influence the length of
the path and the number of iterations needed to reach the destination. It is advantageous to choose a starting
point that is easy to compute and that is physically related to the final state of the circuit, such as that which
results by setting all transistor current gains to zero. This new circuit consists of resistors and diodes only.
It has been proven that the equations describing such a circuit are diffeomorphisms, and hence a modified
Newton method (4) can be used to solve these equations and to produce a good starting point for the homotopy
algorithm.
The usefulness of the parameter embedding methods depends also on the type of a circuits descriptive
equations. SPICE-like simulators use modified-nodal formulations where the unknowns are nodal voltages
and currents. Embeddings for modified nodal equations do not always have convenient circuit interpretations
such as the kind that fixed-point homotopy embedding (9) has when applied to nodal equations. Modified nodal

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

equations with embeddings that cause the presence of nonphysical circuit elements (e.g., occurrence of negative
resistors) can sometimes pose numerical difficulties and will have worse performance than the nodal equations
(16). For such equations the embedding of a parameter should be done in a manner that avoids nonphysical
network instances (e.g., occurrence of negative resistors).
An important issue in using homotopies to find dc operating points is the type of nonlinear functions that
characterize nonlinear circuit elements. Most homotopy algorithms require that these nonlinear functions be at
least c2 continuous. Furthermore, the passivity and the no-gain properties of the models used for semiconductor
devices should be preserved, since they prove essential in ensuring that the conditions required by the pathfollowing algorithms (21) will be satisfied (25). The transistor models implemented in circuit simulators often
satisfy these properties.
Example: Schmitt Trigger Circuit. We illustrate the application of homotopy methods by solving
nonlinear equation that describe the Schmitt trigger circuit shown in Fig. 1. A set of nonlinear equations
describing the circuit, based on the modified-nodal formulation (27), is:

Bipolar-junction transistors are modeled using the EbersMoll transistor model (28):

where

and

For transistor T 1

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

Fig. 1. Schmitt trigger circuit whose equations were solved by using homotopy method. The circuits possess three dc
operating points. All three solutions to the circuits modified nodal equations were successfully found by using the fixedpoint homotopy (9). Circuits parameters are: V cc = 10 V, R1 = 10 k, R2 = 5 k, R3 = 1.25 k, R4 = 1 M, Rc1 = 1.5 k,
Rc2 = 1 k, Re = 100 . The two bipolar transistors are identical with parameters: mf df = mr dr = 10 16 A, f = 0.99, r
= 0.5, and n = 38.78 1/V.

and for transistor T 2

For npn transistors, which were used in the example, me < 0, mc < 0, and n < 0.
By using the fixed-point homotopy of Eq. (9) we can find all three solutions to Eq. (13) for the circuits
node voltages and the current flowing through the independent source. The elements of the diagonal matrix G
were set to 10 3 , and the starting vector a was chosen by a random number generator. The solutions for the
circuits node voltages are listed in Table 1. The solution paths for voltages x1 through x4 , and the current x7
versus the homotopy parameter , are shown in Fig. 2(a) and 2(b), respectively. The three solutions are found
when the paths intersect the vertical line corresponding to the value = 1.

Practical Implementations
Several techniques for tracking homotopy paths are implemented in publicly available software packages (29,
30,31). The dependence of the homotopy parameter on the path length s was implemented in the HOMPACK
software package (31).
HOMPACK solves a set of nonlinear algebraic equations of the form F(x) = 0 that describes the dc behavior
of a nonlinear circuit. HOMPACK provides a curve-tracing option, which allows formulating a customized
homotopy. Various embedding functions can be constructed from the circuit modified nodal formulation and
used with the homotopy curve tracing option. We constructed homotopies that require minimal modifications
to the matrices obtained from the circuit simulator and, hence, ensure the simplicity of the interface.

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

Fig. 2. Homotopy paths for (a) the four node voltages x1 through x4 , and (b) the current x7 of the Schmitt trigger circuit.
The paths were obtained by solving the circuits modified nodal equations with a simple homotopy embedding (9). The plots
show solutions of the homotopy equations versus the value of the homotopy parameter . The three solutions are found
when the homotopy paths intersect the vertical line corresponding to the value = 1.

Three methods for solving nonlinear systems of equations are implemented in HOMPACK. Corresponding
differential equations are created based on the ordinary differential equations, the normal flow algorithms, and
the augmented Jacobian matrix algorithms. They differ by their robustness, and their convergence depends on
the smoothness of the nonlinear functions used to model transistors and diodes.

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

Homotopy methods have been used (15,16) to simulate various circuits that could not be simulated using
conventional methods available in simulators. The software package HOMPACK (31) was interfaced to SPICElike simulators such as ADVICE (AT&T) (15), the TITAN (Siemens) (16), and SPICE 3F5 (UC Berkeley) (17)
simulators engines. When existing methods for finding dc operating points fail, the dc operating points of
a transistor circuit are obtained using HOMPACK. Dc operating points of various circuits that could not be
simulated using conventional methods available in simulators were successfully found using homotopies. These
circuits are often highly sensitive to the choice of parameters and the biasing voltages.

BIBLIOGRAPHY
1. L. Nagel SPICE2: A Computer Program to Simulate Semiconductor Circuits, ERL Memorandum No. ERL-M520, Univ.
California, Berkeley, May 1975.
2. A. Vladimirescu The Spice Book, New York: John Wiley & Sons, 1994.
3. R. Kielkowski Inside SPICE, 2nd ed., New York: McGraw-Hill, 1998.
4. R. E. Bank D. J. Rose Global approximate Newton methods, Numer. Math., 37: 279295, 1981.
5. J. M. Ortega W. C. Rheinboldt Iterative Solutions of Nonlinear Equations in Several Variables, New York: Academic
Press, 1969, pp. 161165.
6. A. N. Willson, Jr. Some aspects of the theory of nonlinear networks, Proc. IEEE, 61: 10921113, 1973.
7. R. O. Nielsen A. N. Willson, Jr. A fundamental result concerning the topology of transistor circuits with multiple
equilibria, Proc. IEEE, 68: 196208, 1980.
8. Lj. Trajkovic A. N. Willson, Jr. Theory of dc operating points of transistor networks, Int. J. Electron. Commun., 46 (4):
228241, 1992.
9. P. Yang, ed. Circuit simulation and modeling, IEEE Circuits Devices Mag., 5 (3): 50, 1989; 5 (5): 4849, 1989; 6 (2):
810, 1990.
10. W. T. Weeks et al. Algorithms for ASTAP-a network-analysis program, IEEE Trans. Circuits Syst., CAS-20: 628634,
1973.
11. E. L. Allgower K. Georg Numerical Continuation Methods: An Introduction, New York: Springer-Verlag, 1990,
pp. 115.
12. I. A. Cermak DC solution of nonlinear state-space equations in circuit analysis, IEEE Trans. Circuit Theory, CT-18:
312314, 1971.
13. L. O. Chua A. Ushida A switching-parameter algorithm for finding multiple solutions of nonlinear resistive circuits,
Int. J. Circuit Theory Appl., 4: 215239, 1976.
14. M. Hasler J. Neirynck Nonlinear Circuits, Norwood, MA: Artech House, 1986, pp. 143151.

HOMOTOPY METHODS FOR COMPUTING DC OPERATING POINTS

15. R. C. Melville et al. Artificial parameter homotopy methods for the dc operating point problem, IEEE Trans. Comput.
Aided Des. Integr. Circuits Syst., 12 (6): 861877, 1993.
16. Lj. Trajkovic W. Mathis Parameter embedding methods for finding dc operating points: formulation and implementation,
Proc. NOLTA 95, Las Vegas, NV, December 1995, pp. 11591164.
17. Lj. Trajkovic E. Fung S. Sanders HomSPICE: Simulator with homotopy algorithms for finding dc and steady state
solutions of nonlinear circuits, Proc. IEEE Int. Symp. Circuits and Systems, Monterey, CA, TPA 10-2, June 1998.
18. D. Wolf S. Sanders Multiparameter homotopy methods for finding dc operating points of nonlinear circuits, IEEE Trans.
Circuits Syst., 43: 824838, 1996.
19. K. Yamamura K. Horiuchi A globally and quadratically convergent algorithm for solving nonlinear resistive networks,
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 9 (5): 487499, 1990.
20. K. Yamamura T. Sekiguchi Y. Inoue A globally convergent algorithm using the fixed-point homotopy for solving modified
nodal equations, Proc. Int. Symp. Nonlinear Theory and its Applications, Kochi, Japan, 463466, Oct. 1996.
21. S. Chow J. Mallet-Paret J. A. Yorke Finding zeroes of maps: homotopy methods that are constructive with probability
one, Math. Computat., 32 (143): 887899, 1978.
22. L. T. Watson Globally convergent homotopy algorithm for nonlinear systems of equations, Nonlinear Dynamics, 1:
143191, 1990.
23. B. Gopinath D. Mitra When are transistors passive? Bell Syst. Tech. J., 50: 28352847, 1971.
24. A. N. Willson, Jr. The no-gain property for networks containing three-terminal elements, IEEE Trans. Circuits Syst.,
CAS-22: 678687, 1975.
25. Lj. Trajkovic R. C. Melville S. C. Fang Passivity and no-gain properties establish global convergence of a homotopy
method for dc operating points, Proc. IEEE Int. Symp. Circuits Syst., New Orleans, LA, May 1990, pp. 914917.
26. J. Katzenelson An algorithm for solving nonlinear resistor networks, The Bell System Tech. J., 16051620, Oct. 1965.
27. C. W. Ho A. E. Ruehli P. A. Brennan The modified nodal approach to network analysis, IEEE Trans. Circuits Syst.,
CAS-22: 504509, 1975.
28. J. J. Ebers J. L. Moll Large scale behavior of junction transistors, Proc. IRE, 17611772, December, 1954.
29. M. Kubicek Dependence of solution of nonlinear systems on a parameter, ACM Trans. Math. Softw., 2 (1): 98107, 1976.
30. W. Rheinboldt J. V. Burkhardt A locally parameterized continuation process, ACM Trans. Math. Softw., 9 (2): 215235,
1983.
31. L. T. Watson S. Billups A. Morgan Algorithm 652: HOMPACK: a suite of codes for globally convergent homotopy
algorithms, ACM Trans. Math. Softw., 13 (3): 281310, 1987.

LJILJANA TRAJKOVIC
Simon Fraser University

456

PIECEWISE-LINEAR TECHNIQUES

PIECEWISE-LINEAR TECHNIQUES
Simulation programs play an important role in the design of
integrated electronic systems. They allow the designer to collect information on the performance of the system that is being designed before that the system is actually realized. To do
so, the circuit is described as a collection of separate modules
that are connected in some way. Depending on the type of
circuit, these modules are of a different nature (e.g., transistors, logic gates, behavioral models), each with their own corresponding data structure and typical solution algorithm.
Within a certain application, modules of different complexity
can also be used to supply variable detail in the resolution of
the circuit response that must be calculated. For fast and efficient simulation, the algorithms to solve the set of equations
describing the modules behaviors are highly optimized with
respect to storage requirements, accuracy, or convergence
speed. As a result, it is nearly impossible to combine the analysis for all different aspects in one single run using conventional analysis methods.

Often an approach is followed to construct and apply some

artificial interfaces between the different types of modules
that allow for separate analysis of each subsystem but also
serve as an interconnection for exchanging the response data
between the modules. Well known practical solutions are simulation back planes or close coupling of a circuit level simulator with a digital simulator. In general, these methods suffer
from large storage requirements, diverging iterations, and
slow computational speed. Furthermore, they lack the necessary flexibility to be applied to a broad class of problems.
The creation of a mathematical description that approximates the systems functionality is called modeling and the
description itself the model description or simply the model.
The aforementioned problems can be avoided to a large extent
when a common model is used that has a single solution algorithm to solve the overall system response. The mathematical
description of such model has to be flexible enough to cover
the input-output description of a broad class of modules (e.g.,
device modules at the voltage-current level, logic modules at
the Boolean level, behavioral modules). A model description
that could deal with a large range of nonlinear multidimensional functions is suitable for that purpose when it permits
the formulation of the relevant equations and its linked to a
suitable solution strategy. The standard approach in circuit
level simulation is to use analytical functions for the relations, and the key algorithm for the solution process is the
well-known NewtonRaphson (NR) iteration. This method
generates a sequence of iterates that (it is hoped) converges
to the required solution using derivatives of the modules
equations. The limitations of the use of an NR scheme are
various, and the important ones are the local behavior of the
method (not all solutions can be obtained); a sufficient close
guess for the solution, which is required as a starting point;
and the computational burden of a repetitive inversion of
the derivatives.
Many of the aforementioned problems can be prevented or
solved using a different type of modeling, the so-called
piecewise linear (PL) modeling. Here the nonlinear behavior
of the modules analytical expression is replaced by a collection of linear relations in a sequence of adjacent intervals.
The immediate advantage of a piecewise linear approach is
that the local relation between the variables is always linear
except at the boundaries, which may simplify further computations. The close mathematical relation of PL modeling and
linear algebra can be beneficial in nonlinear network theory.
An obvious drawback is the limited precision obtained, which
can only be avoided by increasing the number of linear relations to approximate the nonlinear behavior at the cost of a
higher computational load. The use of PL modeling results in
a special data structure that makes it possible to use solution
algorithms with a global convergence behavior. In the case of
computing the direct current (dc) operating point of a circuit,
this results in less restrictions on the initial guess of the
starting point. Furthermore, this property is advantageous
when a circuit with many dc operating points is to be analyzed. It is due to these properties that piecewise linear techniques are used today in modern simulators to find dc operating points.
PIECEWISE LINEAR MODEL DESCRIPTIONS
Confronted with the question to develop a piecewise linear
model for nonlinear components in electrical circuits, one ob-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

PIECEWISE-LINEAR TECHNIQUES

viously starts to look for the most simple extension to the

well-known linear components like resistors and linearly controlled sources. This extension should in one way supply us
with a kind of basic nonlinearity, but in another way this nonlinearity should be as simple as possible, with the expectation
of extending this approach to more general nonlinearities
later on. The first component that will come up to satisfy
those conditions seems to be the semiconductor diode. It
surely is one of the most simple nonlinear elements and has
been used for a long time already to synthesize or reproduce
nonlinear transfer functions in analog computers by realizing
piecewise continuous approximations. One can try to idealize
the behavior of a diode. An ideal diode draws no reverse current when polarized into reverse bias and does not need any
forward bias voltage to conduct an arbitrary forward current.
Such an idealization yields a v-i relation that consists of only
two branches, one described by v 0 and i 0 and one by v
0 and i 0. For reasons of symmetry, we will reverse the
voltage reference polarity of the ideal diode with respect to
the normal convention such that the characteristic now reads
v, i 0 and v i = 0

voltage of the battery. The consecutive independent sources

increase in voltage (i.e., e1 e2). This means that an increasingly higher voltage is required as the input to include the
parallel branches that are placed more to the right in the figure. However, in case these branches start to conduct, the
total resistance is decreasing (increasing) when the resistors
value is positive (negative) and hence the slope of the currentvoltage characteristic is increasing (decreasing), leading to
the v-i characteristic as also depicted in Fig. 2. This fairly
simple network will hereafter be treated as a nonlinear resistor with a piecewise linear behavior.
If we are able to describe the electrical behavior of the network of Fig. 2, we will obtain a mathematical description of a
one-dimensional PL function without any further restrictions.
Should this network description result in an explicit solution,
this would yield an explicit PL function. However, it will always produce at least an implicit description. From arguments from electrical network theory, we know that it is possible to construct a dual electrical network that has the same
functional relation with the roles of current and voltage interchanged. Hence we immediately conclude that the description
that we are looking for will not be unique.
In the preceding situation it is fairly easy to produce an
explicit description of the v-i relation at the input terminals
using basic mathematical functions. To this purpose consider
the following expression:

(1)

Figure 1 shows the relation between the characteristics of an

actual diode, an ideal electrical diode, and the ideal diode as
used in the context of PL. Note that the characteristic of the
ideal diode can also be considered as being piecewise linear
by itself, with 2 being the minimum number of PL segments
necessary to differentiate the diode from fully linear elements. In this respect this diode indeed seems very basic.
In any actual electrical network application, this element
can only exist in one of two possible statesit either conducts
with zero voltage, representing a closed connection between
its terminals, or it blocks the current in the reverse mode,
behaving as an open circuit. This means that any linear circuit containing ideal PL diodes only changes its topology
when these diodes switch from the conducting state (i.e.,
switch from short to open circuit, or the other way around).
Therefore, the response of the network will remain linear in
any conducting state of the diodes, but for different conduction states the response will be different since we deal with a
network with switches that can change the topology. As the
switching occurs in the point v i 0, the response will
automatically be continuous for the applied excitations. This
property is essential and will be used to advantage in the context of the finding of all dc operating points of networks.

x =

ik = Gk v ek  with Gk = 1/Rk

(2)

(3)

Application of Eq. (3) and summation over all branches immediately yields
i = G1 (v e1 ) +

n


Gk v ek 

k=2

or
i = G1 (v e1 ) +

n
n
1
1
Gk (v ek ) +
G |v ek |
2 k=2
2 k=2 k

(4)

which, for the example of Fig. 2, leads to

Figure 2 shows a fairly simple network in which a number of

resistors, independent voltage sources (batteries), and diodes
are connected in parallel. In each parallel branch, the ideal
diode starts to conduct when the input voltage exceeds the

1
(x + |x|)
2

which realizes a ramp function with the breakpoint at x 0.

Based on our previous discussion, using Eq. (2) the current in
branch k satisfies for k 0

Explicit Piecewise Linear Models

457

i =v

3
3 3
|v 1| + |v 2|
4 4
4

(5)

Figure 1. The transformation of an actual diode

characteristic into the ideal electrical behavior and
into the ideal behavior as defined in Eq. (1).

458

PIECEWISE-LINEAR TECHNIQUES

i
R2 =
2/3

Figure 2. A circuit example with ideal diodes. The

circuit can be represented as a nonlinear resistor
with a piecewise linear behavior as defined by the
v-i characteristic representing the behavior as seen
from the port nodes.

f (xx ) = a + Bxx +

i , x
i |
c i |

i
+

R1 =
1

1.5

e2 = +
1V

e3 = +
2V

0.5
1

In a more general mathematical expression, the model description for the PL function f : Rn Rm is given by

R3 =
2/3

and that the second-order base function looks like



u2 = f 2 (x) + a21  f 1 (x)

(6)

i=1

where B Rmn, a, ci Rm, i Rn, and i R1 for i 1,

. . ., and which is the basic model description as proposed
by Chua and Kang (13). In the model description, hyperplane Hi is expressed as
i , x
i = iT x i = 0

(7)

This hyperplane Hi divides the domain space into two regions, R1i and R2i. The normal vector of the plane is defined
by i. The hyperplane reflects the operation of the ideal diode
i, one region corresponding to the situation in which this diode conducts and the other to its blocking state. This can also
be seen from Eq. (4), in which each absolute-sign operator
refers to an ideal diode in the network. Using the model definition, the domain space Rn is divided into a finite number of
polyhedral regions by hyperplanes Hi of dimension n 1.
When crossing Hi, the Jacobian matrix J of Eq. (6) changes
with the amount
J = J1i J2i = (cc i Ti ) (cc i Ti ) = 2cc i Ti

Then it can be proven that using this extension any two-dimensional function or two-port electrical network can be modeled (4,5). Here we assume that the functions f i(x), i 1, 2
are affine functions. Figure 3 shows a geometrical interpretation of these base functions. In a two-dimensional situation,
hyperplanes may cross each other and a hyperplane itself
may eventually be piecewise linear under the condition that
the breakpoint is defined by a hyperplane described by a base
function of order one. In a similar way, we can define base
function i

ui =  f i (x) +

i1


aik uk 

(9)

k=1

and with this set of base functions it can be proven that any
PL function or any multiport can be modeled (6,7). However,
the function or network should be of class P, a property we
will discuss later.

(8)
Implicit Piecewise Linear Models

Notice that this amount is independent of the position in Rn

where the hyperplane is crossed. This property is known as
the consistent variation property and plays an important role
in piecewise linear modeling (3).
Each one-dimensional function or any one-port electrical
network with ideal diodes and linear elements can be realized
by Eq. (6), and there exists a one-to-one relation between the
parameters in Eq. (6) and the given piecewise linear function
or network. Consider again the nonlinear resistor in Fig. 2,
and notice that all elements of the network describing the
nonlinear resistor are used exactly once in the model Eq. (5).
However, in more dimensions hyperplanes can cross each
other, and geometrical constraints might exist, such that not
all multidimensional functions can be represented by this
model description. In terms of an electrical network this
means that not only linear components are used but, for instance, also controlled sources.
Therefore, people have tried to extend this model description to allow modeling of higher-dimensional piecewise linear
functions. Assume that Eq. (2) can be considered as a base
operation of order one, given as
u1 =  f 1 (x)

We can consider the circuit in Fig. 2 as a special case of a

linear memoryless electrical multiport network that is loaded
at some of its ports by the previously defined ideal diodes.
The network may contain resistors and fixed and controlled
sources and, for later convenience, all of its ports are partitioned in two different sets, port set 1 and port set 2. Figure

f1(x)
f2(x) + a21f1(x)
u1 = f1(x)

u2 = 0

f1(x)
u2 = 0
f2(x)

u1 = 0
u2 = f2(x) + a21f1(x)

u2 = f2(x)

Figure 3. The first- and second-order base functions with respect to

their hyperplane(s). In the case of second-order base functions, hyperplanes may be piecewise linear. In each half-space, the functions
value is given and for each hyperplane the normal vector is given
also.

PIECEWISE-LINEAR TECHNIQUES

The complete set of Eq. (11) describes a PL mapping that is

defined on a collection of polytopes. The boundaries of each
polytope Km will be formed by a set of bounding hyperplanes
Hmi according to

y
+
x

Port set 1

i
Hm
= {xx|cc imx + gim = 0}, i {1, . . ., k}

Memoryless
j

Multiport

(12)

which is a generalization of Eq. (10). Equation (12) defines a

collection of half-spaces Vmi given by

+
Port set 2

459

Vmi = {xx|cc imx + gim 0} and Km =

Vmi

(13)

Figure 4. A memoryless electrical multiport loaded at port set 2 with

ideal diodes. The voltage (current) across (through) each diode is represented by u( j). Port set 1 represents the independent variables x
and the dependent variables y.

The row vectors cmi in Eq. (13) are the normal vectors on
the hyperplanes that bound the polytope Km and point in the
inward direction. They all can be considered as rows of a matrix Cm such that the polytope Km is equivalently given by
Km = {xx|Cmx + g m 0}

4 shows such a network. Assume that port set 1 contains m

ports and port set 2 contains k ports. For port set 2 all its
ports are loaded by ideal diodes; thus the voltage u over the
diodes and the current j through the diodes can be represented by k-dimensional vectors (i.e., u, j Rk). Then, based
on the previous discussion, the conducting states of the diodes
will depend on the m currents and m voltages at port set 1.
Next assume (without loss of generality) that the port set 1 is
excited by voltage sources. In the light of the PL model that
we are required to construct, we map the port variables at
port set 1 on new vectors x, y Rm according to x v and y
i.
Diode k has only two states that are separated by the condition ukjk 0. The diode now also separates the space
spanned by x and y into two half-spaces, one in which the
diode conducts and one in which it blocks. The boundary between the two half-spaces is a hyperplane and, as stated before, is determined by ukjk 0. Since in any conducting state
the response of the network will remain linear in terms of the
applied voltage excitation, the components of the vectors y,
u, and j are all linear relations in the components xi of the
vector x. Hence the hyperplane can be rewritten such that a
linear combination of the components xi of x are equal to zero.
That is,
ct x + g = 0

(10)

All the diodes together separate the complete input space

into 2k polyhedral regions, called polytopes. Within each polytope, all diodes remain in one of their states; some will conduct and others will block. Within each polytope, we have a
linear relation between x and y. Crossing a hyperplane means
that the diode corresponding to this hyperplane changes its
state and hence we have an other topology, defined by the
polytope in which we enter after crossing the boundary. Again
we are confronted with a linear network.
Consider the situation that we have k diodes or hyperplanes, and therefore 2k polytopes. For each polytope, denoted
by Km, we have a linear mapping representing the topology of
the network for that polytope:
y = Am x + f m

m = 1, 2, . . ., 2k

(11)

(14)

Define each polytope Km by determining on which side of each

hyperplane Hi it is situated. Note that for the hyperplanes
the subscript m is removed to express that we only have a
single set of hyperplanes Hi, i 1, . . ., k, which can partition the space into a maximum of 2k polytopes. This exactly
fits with our network with ideal diodes. The k diodes can define at most 2k topologies into which the network can be divided. Therefore, for any polytope Km and each hyperplane
Hi we either have one of two possibilities:
Ci x + g i 0 or Cix + g i < 0

(15)

Because the normal vectors of the hyperplanes were considered to be rows of Cm and thus also for Ci, we may collect
all normal vectors into a single matrix C. The same holds for
vector g. Once a partitioning of the space is given, the various
matrices Am and vectors f m in Eq. (11) also have to be defined
in accordance with Eq. (15). We are, of course, looking for a
compact description of the piecewise linear function as defined by the network with ideal diodes. From a network point
of view it is clear that the network is continuous and hence
the underlying piecewise linear function. As a result, the matrices and vectors in Eq. (11) become related and may not
freely be chosen. This dependency is the same as expressed
by Eq. (8), yielding in this situation (assuming separation
hyperplane Hp)
Ai = A j +

( f i f j )C p
gp

(16)

which fully determines the relation between two mappings

from adjacent regions. Now the piecewise linear function is
described completely by relation Eq. (11) together with the
description of the state space. Again consider the network of
Fig. 4, from which we learned that its response is a piecewise
linear function that could be used to derive a closed form expression for a piecewise linear mapping. From the v-i curves
of the ideal diodes as given in Eq. (1), we recall that for each
diode at port set 2 we have
u, j 0 u T j = 0

(17)

460

PIECEWISE-LINEAR TECHNIQUES

with the inequalities taken component wise. Furthermore, we

assume that the electrical behavior of the network within the
solid box at its outside ports can be described by a port-admittance matrix H, resulting in
  
   
i1
H11 H12 v 1
f
=
+
g
i2
H21 H22 v 2

and which is a format similar to Eqs. (21) and (22). We can

easily show that for any one-dimensional one-to-one function
this property holds.

Renaming i1 and v1 into y and x and the variables of port set

2 into u and j (because they are related to the diodes) and
substituting Eq. (16) yields

Definition 1. Let z, u, j Rn and let the n-dimensional vector function ( ) be given as (z)k h(zk), where the subscript k denotes the kth element of a vector and h( ) is a
scalar function. For a strictly increasing h: R R and
h(0) 0, the transformation z u, j defined by u (z
z), j (z z) is called the modulus transformation.

u+ f
y = Axx + Bu

(18)

u +g
j = Cxx + Du

(19)

u, j 0 u T j = 0

(20)

which is known as the state model of a PL mapping f : x

y (8). Equation (18) determines the input-output mapping of
x onto y. The remaining two equations determine the state of
the mapping from the electrical state of the ideal diodes.
These diodes form a kind of state variables, which, together
with the input vector x determine the output y comparable to
the situation in a state-space model of a linear dynamic system. The conditions in Eq. (20) are called the complementary
conditions and u and j are complementary vectors. It is obvious that some algebraic mechanism will be needed to be able
to use the PL mapping in an efficient way. Storage and updating of the description of the mappings as well as the calculation of the mapping itself can then be performed by standard
operations from linear algebra.
A few years after the publication of this model description,
a new model was introduced in which the hyperplanes were
allowed to be situated in the image space. However, the matrix in front of the state vector u in the state equation should
then be the identity matrix, resulting in the description
u+f =0
Iyy + Axx + Bu

(21)

u +g
j = Cxx + Dyy + Iu

(22)

where Eq. (20) still holds (9).

By now it should be clear that any piecewise linear memoryless electrical multiport can be described by Eqs. (18) to
(20). However, many networks can be handled by the description of Eqs. (21) and (22), which has some advantages with
respect to analysis. To allow efficient analysis, it is important
that after a diode changes its conductivity and hence the topology of the network is changed, the new description of the
network can be obtained efficiently (10). Because the state
matrix in front of the state vector u in Eq. (22) is the identity
matrix, only Eq. (21) has to be modified during a topology
change of the network. As modeling example, consider the
model description of Eqs. (18) to (20) for the nonlinear resistor
in Fig. 2, which can be written as


3 3

u=0
i + (1)v +
2 2
 
 
1
1
(23)
u+
j=
v + Iu
1
2

u, j 0 u T j = 0

Relations Between Piecewise Linear Model Descriptions

To compare explicit and implicit model description in order to
rank them, let us define the modulus operator:

The modulus transformation automatically guarantees

that u 0, j 0,uTj 0, which exactly matches Eq. (20). If
we define h( ) as h(t) t. Corollary 1 immediately follows
from Definition 1:
Corollary 1. The modulus transform for h(t) t is equivalent to the mapping u, j z satisfying z (u j)/2 and
z (u j)/2, with z R and u, j R.
By this corollary we have an operator to compare the implicit model description, which uses complementary vectors,
with the explicit model description, as described by absolutesign operators. Each explicit model description can be rewritten into a format similar to Eqs. (18) to (20) (10). To compare
the descriptions, we only have to compare the obtained matrix
in front of the state vector u. Doing so leads to the conclusion
that all explicit model descriptions are a subclass of the description Eqs. (18) to (20). If we have a description using base
functions Eq. (9), it covers at maximum any PL function for
which the matrix D in Eq. (19) is of class P:
Definition 2. A matrix D belongs to class P if and only if
z Rp, z 0, k: zk (Dz)k 0.
Class P is alternatively defined by the property that all
principal minors of D are positive. The model description of
Eqs. (21) and (22) is also a subclass of Eqs. (18) to (20) but
covers a larger class than Eq. (6). Note that the description of
Eqs. (18) to (20) also allows modeling of functions not being
of class P. As an example, consider the one-to-many mapping

x1}

x1
x0
x0}

f (x) = 0
f (x) = x + 1
f (x) = 1

for which the description yields

u + (1)
y = (1)x + (1 1)u
   


 
j1
1
1
1
1
=
x+
u+
j2
1
1 1
0
having a matrix D not of class P. Such a function cannot be
described by any explicit model description.
Although each model format does not change with respect
to the function or network to be modeled, the model size is

PIECEWISE-LINEAR TECHNIQUES

strongly related to the number of ideal diodes in the network

or linear segments in the function. The more linear descriptions are used to approximate the nonlinear behavior, the
larger the data storage will be, and this relation yields a linear behavior. However, the complexity to solve the model to
obtain an output for a given input later on increases exponentially with the number of ideal diodes in the network. In the
explicit models this can be seen from the evaluation of the
absolute-sign operators and for the implicit models from the
evaluation of the complementary conditions. In both situations we have to check the two sides of each diode that is
added to the network.
For many practical situations, piecewise linear models for
the electrical elements can be obtained easily (11). This holds
for a device element described at the current-voltage level,
but also for digital components in terms of Boolean algebra or
behavioral models of, for example, complete analog to digital
(AD) or digital to analog (DA) converters. Also, time-dependent elements such as capacitors or even differential equations can be described when we modify the implicit model descriptions (9,11). Although most PL models are generated by
hand, automatic model generators do exist for several functions (12,13).
SOLUTION ALGORITHMS
When we are using explicit model descriptions, we only have
to solve the absolute-sign operators, which is an evaluation
task. However, in the case of an implicit model, which is more
powerful and is therefore more used in circuit modeling, we
have to obtain the internal state variables by solving the state
equations. Without any restrictions, we assume that the electrical network is described in terms of Eqs. (21) and (22) and
that we know that the description is valid for u 0. Then we
may use the linear mapping to eliminate the output vector in
the state equation, yielding
u + (g
g Df )
j = (C DA)xx + Iu

(24)

which can be transformed into

u +q
j = Iu

(25)

where q (C DA)x (g Df). This equation is a special

case of
u+q
j = Mu
u 0, j 0, u T j = 0

461

mension of M. A more efficient approach is to construct algorithms that use an extension of a local solution estimate to
find the required result. Note that the dimension of M depends on the number of linear segments used to approximate
the nonlinear behavior of a function.
The most well-known method for this purpose is the homotopy algorithm by Katzenelson (16). Katzenelson introduced
this method in 1965, and the method is still extensively used
in piecewise linear simulation programs (10,17,18). Being a
homotopy method, a continuous path through the space is created by extending the LCP of Eq. (26) according to
u + q 0 + (q
q q 0 )
j = Mu

(27)

where we assume that q0 is known with u 0, j 0 for is

zero. We are looking for the solution for a q*. The homotopy
parameter is to be increased from zero to one. The procedure is to gradually increase parameter until a component
jm becomes zero, because [q0 (q* q0)]m qm becomes
zero. Just a small increase of is needed to let um 0, thus
preventing jm from becoming negative, which is not allowed
according to the complementary conditions. In terms of the
electrical network, this means that diode m is changing its
state and the network topology is changing. We have to perform a pivoting operation with again a system of equations
according to Eq. (27). The pivot is the diagonal element Mmm,
which we assume to be positive. As a result, variables jm and
um will change place and Eq. (27) changes into a new form
given by
w + q 0 + (q
q q 0 ),
v = Mw

v , w 0, v T w = 0

(28)

in which w 0 and v q0 m(q* q0) now will be a

solution. This process of increasing is repeated until 1
is reached, in which case the solution for the LCP has been
obtained. It can be shown that can always be increased
when the diagonal elements of M needed as a pivot are always positive. Moreover, if the matrix M belongs to class P,
the Katzenelson algorithm will always find the unique solution (15,19).
As an example, consider a fairly simple network, consisting of a linear resistor in series with a nonlinear resistor
that has a characteristic as defined in Fig. 2 and for which
the model is given by Eq. (23). This network is excited by a
voltage source E. The topological relation yields
E = Ri + v

(29)

(26)

where for a given q the complementary vectors u and j should

be solved.
The problem defined by Eq. (26) is known as the linear
complementary problem (LCP) and the solution to this problem is the key operation in the evaluation of a PL function
based on Eqs. (18) to (20) or Eqs. (21) and (22). The LCP has
been known as a basic problem for quite some time and is
mainly studied for applications in game theory and economics
(14,15). In the past 20 years a number of algorithms have
been developed to solve the LCP, which in its most general
form is known to be an NP-complete problem. The solution
can be found by going through all possible so-called pivotisations of matrix M, which number is exponential in the di-

For this network we intend to find the dc operating point for

E 9 V and R 4 . According to the theory given previously, we can write the complete network in terms of its
input variable E and its output variable i by combining Eq.
(23) with Eq. (29), yielding






3
3
1
u=0
E+

i+
5
10 10
 
 
 
(30)
1
4
1
j=
u
E+
i + Iu +
1
4
2
where we leave out the complementary conditions for convenience. Because of the definition of the elements of the network, (i, E0) (0, 0) is a solution of the network. However,

462

PIECEWISE-LINEAR TECHNIQUES

we intend to obtain the dc operating point for Ee 9 and

therefore we may define the homotopy path as E Eo
(Ee E0) 9. We are now able to rewrite the state equation
in Eq. (30) into a form similar to Eq. (27), yielding
 
 
1
15
u
j=
1 9 + Iu +
2
5
Note that the LCP matrix is the identity matrix and thus
of class P. Katzenelsons algorithm will always obtain a solution. Increasing to let um 0 to prevent jm from becoming
negative results in 5/9 for the first state equation. Let
u1 and j1 interchange and Eq. (30) will be updated to






3 3
3
1
E+
u+ =0
i+
2
2 2
2
 
 
 
(31)
1
4
1
u+
j=
E+
i + Iu
1
4
2
where u1 and j1 interchanged names also to achieve a model
similar to Eq. (30). Note that 5/9 means that E 5, i
1, and therefore v 1, which is indeed a breakpoint of the
nonlinear resistor characteristic (see Fig. 2). By further increasing E, the diode in the second branch of the subnetwork
representing the nonlinear resistor starts to conduct as v increases. The complete network topology will now change and
is described by the new mapping equation in Eq. (31). For this
new situation Eq. (28) now yields
 
 
1
5
u+
j=
9 + Iu
1
4
from which it can be observed that we may not increase the
homotopy parameter further. The alternative is to decrease
this parameter and hope that we may increase it afterward
to reach 1. It can be proved that this extension to the
original method of Katzenelson is allowed (19). Doing so, we
obtain 4/9 in the second state equation, which corresponds to the diode in third branch of the subnetwork representing the nonlinear resistor starting to conduct. Pivoting
and updating the model results in






3
3
3
1
E+

u+
=0
i+
5
10 10
10
 
 
 
1
4
1
u+
j=
E+
i + Iu
1
4
2
and the algorithm yields
 

j=

1
5
1
5


u+
9 + Iu

1
5
45

from which it is clear that we may increase the homotopy

parameter reaching 1. We now have obtained the dc operating point of this network, (i, E) (3/2, 9), and the voltage
over the nonlinear resistor is v 3 V.
In the literature, an adaptation to the Katzenelson algorithm is presented in which a single homotopy parameter
path is extended to a multiparameter path (20). The homo-

topy parameter may be complex. The advantage is that difficult points in the characteristic, such as the hysteresis curve,
can be handled with more care than with the straightforward
method. Another extension is treated in Ref. 17 that allows
us to find the dc operating point of a network having a discontinuous behavior.
Over the years, several algorithms have been developed to
solve the LCP and they can roughly be categorized into four
groups:
1. Homotopy Algorithms. Besides the algorithm of Katzenelson, Lemke (21) and van der Panne (22) developed
pivoting algorithms based on homotopy methods. The
advantage of the latter two algorithms is that they are
able to handle a larger class of LCP matrices than can
Katzenelson, which is only guaranteed for class P problems. The price to be paid is a more complex algorithm,
and therefore it is mainly the Katzenelson algorithm
that is used in (PL) simulators.
2. Iterative Algorithms. These methods solve some equivalent multidimensional optimization problem. This optimization problem is most often quadratic (23). Equation
(26) can be reformulated as minimizing 
xT Mx qT x
under the condition that x 0, which yields a solution
satisfying Eq. (26). The required solution can be obtained by applying efficient gradient search methods
from the nonlinear optimization theory.
3. Contraction Algorithms. The algorithms in this class
solve some equivalent nonlinear algebraic problem by
iteration using, for example, contraction or NewtonRaphson iteration. One important member of this class
is the modulus algorithm (8). This method will yield a
polynomial solution algorithm for matrix M from a certain limited class such as positive definitive matrices.
4. Polyhedral Algorithms. These methods perform operations on the polyhedrons in which the domain space is
divided by the collection of hyperplanes. We will discuss
two algorithms of this class in more detail in the following section because this class of algorithms allows us to
find all dc operating points of a network.
MULTIPLE DC OPERATING POINTS
In the previous section algorithms were discussed to obtain a
single dc operating point of the electrical network. However,
many circuits do have multiple operating points. We discussed how a solution algorithm (in this case Katzenelson)
can be applied to solve a network of piecewise linear components (i.e., how to find a single operating point for a given
excitation). In general, this means that using a homotopy
method, we are able to find a single solution of a piecewise
linear function starting from an initial condition. Determining all solutions would require trying all possible initial conditions, thus posing a severe drawback. The problem of finding
all solutions of a system of piecewise linear (or, in general,
nonlinear) equations is extremely complex. Because a
piecewise linear function might have a solution in every region, any algorithm that claims to find all solutions must scan
through all possible regions. The efficiency of an algorithm is
therefore mainly determined by the efficiency with which it
can remove regions that do not have a solution from the list of

PIECEWISE-LINEAR TECHNIQUES

all regions. Finding all solutions of a piecewise linear function

means solving
f (xx ) = 0

(32)

To obtain all solutions of a piecewise linear function, we

can use the brute force method. Knowing the linear map y
a Bx for each region, it is easily checked in which region
the operating points are and what they are. However, this
means solving 2k linear equations, which can be a rather large
number in general. Therefore, this is called the brute force
method of solving Eq. (32). Hence it is worthwhile to develop
methods that can reduce the computational effort of the task.
For finding all solutions of a piecewise linear function, we
must find an efficient way to exclude regions that do not contain a solution.
We will discuss several techniques that exploit some properties of the piecewise linear model to obtain rather efficiently
all dc operating points of a network. To compare the methods,
we will use one example throughout this section. We will consider the same network as in the previous section but with R
6 and E 6 V.
Exploiting the Lattice Structure
In 1982 Chua explored a special property of Eq. (6) to find all
solutions in a more efficient way than the brute force method
(24). This property is the fact that for functions described by
Eq. (6) all regions in the domain space are separated only by
horizontal and vertical hyperplanes. Notice that this property
only holds for the one-level nested operator. Therefore, this
method is not applicable for higher-order nesting of this operator, like in the model description based on higher-order base
functions. Function f for our example is given by
f (v) = 0 =

7 3
3
7
v |v 1| + |v 2|
6
4 4
4

(33)

which is obtained by combining Eq. (5) with the topological

relation of Eq. (29). Now consider the domain space of f,
which in this case is partitioned by 2 or, in general, by hyperplanes into 4 or 2 regions, respectively. Note their special
property: They are parallel to one of the axis. Such a structure is called a lattice structure. For each region we have a
linear map of f. We can also generate the partitioning of the
image or the range space by applying map f on the regions.
Because we are searching for the solutions of Eq. (32) or (33),
we can see from the range space which regions must be considered, and they simply must contain the origin. Let x1 be an
, the
arbitrary point in region R and let its image be y1 in R
k:
image of R. Consider also hyperplane Hk and its image H

k , x
k = 0
Hk :
H k : k , x
k = 0

k.
because y1 and the origin must lie on the same side of H
. If
This procedure must be repeated for all sides of region R
,
this so-called sign test fails on any of the boundaries of R
then this region contains no solution of Eq. (32). Due to the
sign test, we do not have to solve all linear equations, but
only those for which we know in advance that they contain a
solution. Therefore, this method is more elegant than the
brute force method. In Ref. 24 Chua described an efficient
implementation of the sign test.
Applying this technique to Eq. (33) yields the dc operating
points (i, v) (, ), (i, v) (, ) and (i, v) (,
), which can
be verified by adding the load line, defined by Eq. (29) to the
characteristic in Fig. 2.
Separable Piecewise Linear Functions
Yamamura (25) developed a method that is based on the assumption that one considers the function f to be separable:
f (xx ) =

n


f i (x)

where f i : R1 Rn. It can be shown that many practical resistive circuits exploit this property and hence this assumption is not too strict (26,27). Further, it is known that a
piecewise linear approximation of a separable mapping can
be performed on a rectangular subdivision. This means that
if f was nonlinear, it is transformed into a piecewise linear
function by approximating the function linearly within each
rectangle. Hence a piecewise function will be the result. It
also means that the following procedure results in an approximation of the exact solution: The finer the rectangular subdivision, the better the approximation solution of f. If, however, f was already piecewise linear and, in particular, in
accordance with Eq. (6), we can choose the subdivision such
that it fits with the polytopes of the mapping. In case of Eq.
(6) we choose the lattice structure as rectangular subdivision
and the exact solutions will be obtained. If this is not possible,
we can again approximate this piecewise linear function on a
chosen rectangular subdivision following the procedure as if
the function was nonlinear. So in this subsection we assume
that f in Eq. (37) is either nonlinear or piecewise linear.
Let us subdivide the solution space into rectangular regions. To this purpose we define two vectors
l = (l1 , l2 , . . ., ln )T and u = (u1 , u2 , . . ., un )T

(38)

so that a particular n-dimensional rectangle is given by

Ri = {xx Rn |li xi ui },

(34)

n



max{ fji (li ), fji (ui )} 0

i=1
n



(35)

and this must be equal to


sgn k , y 1
k )

(37)

i=1

i = 1, 2, . . ., n

(39)

Then for this region Ri we define the following sign test:

, then
If the origin is located in region R


sgn k , 0
k = sgn( k )

463

(36)

j = 1, 2, . . ., n

(40)

min{ fji (li ), fji (ui )} 0

i=1

where f represents the linear approximation of f in the rectangle under consideration. Equation (40) means that in each
rectangle only two function evaluations per region have to be
performed. This is because the function within the rectangle

464

PIECEWISE-LINEAR TECHNIQUES

is linear and hence the function evaluation on the boundaries

of the rectangle provides enough information. For instance, if
we consider the one-dimensional case, then Eq. (40) reduces
to

max{ f1 (l), f1 (u)} 0

min{ f1 (l), f1 (u)} 0

(41)

which means that at one boundary of the rectangle the function value is positive while at the other boundary the function
value is negative. Indeed, somewhere within the boundary
the function must pass the origin and hence a solution is obtained. If Eq. (40) does not hold for some j, the function does
not possess a solution in that rectangle.
This test is very simple, simpler than the one proposed by
Chua (24), where first the image of all boundaries must be
computed. In the case of Yamamura, per region it requires
only 2n(n 1) additions and n(n 2) comparisons. After the
sign test, we solve linear equations on the regions that passed
the test. The problem with this method is that the test has to
be applied on each rectangle. We can significantly reduce the
number of tests by exploiting another propertynamely, the
sparsity of the nonlinearity. In general, each equation is nonlinear or piecewise linear in only a few variables and is linear
in all other variables. Suppose that the function f is nonlinear
in x1 and linear in x2; then we do not have to define a subdivision in R2 but only in R. Now we can apply the same sign test
of Eq. (40) to this structure, which has a complexity of a lesser
degree than we had previously. We can show that the total
complexity is on the order O(n3).
We can apply this technique to our example assuming that
f is given by Eq. (33). Let us define the rectangular division
as [0, 1], [1, 2], and [2, 3], which coincides with the lattice
structure of Eq. (33). For the first rectangle Eq. (41) results
in

where xj, j 1, 2, . . ., n represents a breakpoint in the characteristic and x, x represents some points at the left-most
and right-most segment (28). Equation (42) describes a PL
mapping with the parameters consistent with the complementary conditions as given in Eq. (43). We did not mention this
model description in the previous sections because it has no
direct relation to an electrical network. The nonlinear resistor
as defined by the network in Fig. 2 can be given in terms of
Eqs. (42) and (43)

     
 
 
3
i
1
1
12 +
+ 2 +
=
+
+
v
1
1
1
0 1

+
1 1 = 1

(44)

+ , , +
1 , 1 0

+
1 1 = = 0

and the topological equation of Eq. (29) can be rewritten as

i

1 6) v

(6

(45)

where is a slack parameter. We can now substitute Eq. (44)

into Eq. (45), yielding a system of the following form:

9
1

0
1

2
1

7
1

+
1


1
1+

1

(46)

or, in general,

max{ f1 (0), f1 (1)} = max{1, 16 } 0

min{ f1 (0), f1 (1)} = min{1, 16 } 0

(M

and therefore contains a solution of the network. In a similar

way, we can observe that the other two rectangles fulfill the
conditions, and working this out results in the three dc operating point as obtained previously.
Finding all Solutions Using Polyhedral Methods
In essence, these methods transfer the original problem into
a form of the LCP and solve the new problem with very powerful methods. Any one-dimensional PL mapping can be written according to

x = x0 + x + (x1 x0 )+
n

+
(xk 2xk1 + xk2 )+
k1

+ = 0, +j j = 0

which in the literature is known as the generalized linear complementary problem (28,29) with w, z, 0 and the complementary condition still valid. This set of equations can be
solved using the modified Tschernikow method. The term generalized is used because the matrix is not of dimension Rnn,
as in the LCP discussed previously, but can have any dimension, i.e. Rnm, n m. Hence it can represent an underconstrained set of equations that indeed can possess more than
one solution.
Tschernikow developed a method to find all solutions of the
problem
Axx b ,

+ (x+ 2xn + xn1 )+

n
+j , j , + , 0

(47)

(42)

k=2

+j j = + j,

w

q) z = 0

j = 1, 2 . . ., n
(43)

x Rn ,

A Rmn ,

nm

(48)

which in any case with the introduction of some slack variables can always be transformed into
u 0, u 0
Bu

B Rk p

(49)

PIECEWISE-LINEAR TECHNIQUES

The solution space of Eq. (49) describes all nonnegative solutions of Eq. (48). The method starts to define a start tableau

1
1
1

T = (T 1 |T 2 ) =
0

..

0 b11
..
.
1 b1 p

bk1
..

.
bk p

(50)

where T11 is a unity matrix, forming a base in the

p-dimensional space, and T21 is composed by placing a row of
Eq. (49) as column in Eq. (50). For each row in T11 we define
S(i), i 1, 2, . . ., p as the collection of columns in T11 with a
zero in row i. In a similar way, we define S(i1, i2) as the collection with both zeros in i1 and i2. We now randomly choose a
column j in T21 with at least one nonzero element. We consider
two rows, i1, i2, from the tableau with opposite sign in column
j and consider the corresponding S(i1, i2). If S(i1, i2) S(i), i
i1, i i2, then the linear combination of rows i1, i2 such that
a zero in column j is created is of importance. It is precisely
this combination that generates a boundary in the solution
space. Only on one side of this hyperplane, solutions of the
problem do exist that are consistent with the space as defined
in T11 and the equation as defined by column j corresponding
to row j of Eq. (49). Obviously, this new row must be introduced in the new tableau matrix. It must be clear that all
rows having a zero or negative entry in column j are also
transferred to the new tableau matrix. They automatically
fulfill the inequality condition in Eq. (49) for axis j. In the
same way tableau Ti can be found from Ti1, and the procedure stops when all columns in the right part are treated or
we end up with only columns in the right part, which are
strict positive. In the latter case there does not exist a solution to the problem except the trivial solution. In the first
situation we end up with the following tableau:

T end

c11
.
end
end
= (T1 |T2 ) =
..
ct1

c1 p
..
.
ct p

(51)

with the nonnegative solution for Eq. (49)

u=

t


p i ci ,

with ci = (ci1 , . . ., ci p )

(52)

i=1

and pi a nonnegative parameter. The set (c1, . . ., ct)T describes the corners of the convex solutions space. If the problem is written as
Axx = b ,

xR ,
n

AR

mn

nm

(53)

as in Eq. (47), then only a small modification in the previously

outlined procedure is needed. Only rows having a zero entry
in column j are directly transferred to the new tableau matrix. For a detailed outline, we refer to the works of Tschernikow (3032). For the generalized LCP, the procedure outlined
previously has to be only slightly adapted: Now the complementary conditions must also be fulfilled, so after each generation of a new tableau we have to check these conditions. We
simply check each row in the columns in the left part of the
tableau matrix for whether the conditions are fulfilled or not.

465

If not, the corresponding row must be removed from the tableau and we can generate a new tableau (29).
The start tableau in our example of Eq. (46) looks like

1
0

0
0

1
1

Taking the first column of the right-hand part, we can make

two combinations of rows having opposite sign. All can be
transferred to the next tableau, yielding

0
0

16

1
8

which finally yields (because many combinations do not fulfill

the complementary conditions)

2
0

16

14
7

(54)

We now consider the first equation in Eq. (54), which tells us

that 1 
( 1). Combining this with Eq. (44) leads to (i,
v) (, ), which is indeed one of the dc operating points. In
a similar approach, the other two operating points can be obtained from Eq. (54).
The outlined approach can be slightly modified to handle
model descriptions as defined by van Bokhoven directly, leading to a broad class of problems that can be solved (33). Here
first the transfer characteristic of each element is determined
after which the topological relations are used to solve a set of
equations similar to Eq. (47) but now being a pure LCP. The
advantage of this method over the treated method is that restriction on the variables can be taken into account. This can
be of interest when only solutions in a special subspace are of
interest or when the network is extended with other components later. In that case, not the whole procedure must be
restarted but only parts of it for the new added components.
Obviously, this will save computational effort.
Polyhedral Methods and Linear Programming
For a long time the relation between LCP and linear programming (LP) has been known. Each LP problem can be transformed into an LCP using the duality property of the LP (29).
On the other hand, it is possible to treat a piecewise linear
network as a polyhedral function, which can then be solved
using LP (34). We mentioned that the state equation describes a set of polyhedral regions in the space, called polytopes. For each polytope a linear relation describes the local
behavior of the function. We can also combine these two relations when we treat the piecewise linear function as a polyhedral element. The polyhedral elements, in general, do not
have a correspondence with a physical device, but they consti-

466

PIECEWISE-LINEAR TECHNIQUES

tute a mathematical tool. Each polyhedral element consists of

a set of polyhedral regions. For our nonlinear resistor in Fig.
2, one of the polyhedral sections would yield

 
 
 
 
3
1

i
0
1
= p1
+ p2
+ p3 2 =
p iw i
v
0
1
2
i=1
p1 + p2 + p3 = 1
p1 , p2 , p3 0
describing the triangular area defined by the first two segments and a virtual line segment. We can use this description
together with the topological equations to obtain a set similar
to
Km
M 


m
pm
i (wi tkm ) = rk for k = 1, . . ., M

m=1 i=1
Km


m
pm
i = 1, pi 0

i=1

where t and r define the topological relations, M is the number of polyhedral elements in the network, and Km is the number of polyhedral regions per element. This system of linear
equations and inequalities may be regarded as the constraints of a linear programming problem. The solution for
each polyhedral region is a dc operating point for the original
problem. To find all operating points implicates that, in principle, all polyhedral regions have to be solved. However, when
we set up a genealogical tree, a reasonable reduction in
computation can be obtained. A certain node in this tree represents a specific polyhedral element. If a certain node does
not contain a solution, some other nodes in the tree may be
discarded. In Ref. 35 a detailed discussion can be found.
Comparison of the Methods
From the preceding discussions it follows that the method
used first depends on the model descriptions used. When the
network is described using an explicit model, then we can
apply the method of Chua or Yamamaru, where the latter has
the advantage of efficiency but demands separability of the
network, which is not always the case. We know that explicit
model descriptions are less powerful than implicit model descriptions and hence the polyhedral methods of Vandeberghe
and Leenaerts can be applied to a larger class of problems.
However, in situations where the network components are
one-port elements, these methods are overkill with respect to
the computation of the solutions. On the other hand, in the
general case they are more powerful and do not require restrictions on the problem. The method of Pastore is not well
accepted yet, mainly because it demands that all piecewise
linear elements first have to be rewritten into polyhedral elements, which is not always a trivial task. Second, the problem
must be solved using LP techniques, which does not well fit
within a simulation environment. This latter drawback may
also apply to the method of Yamamura. The methods of Chua,
Vandeberghe, and Leenaerts fits very well within an existing
simulation environment because they can handle the existing
models directly and use techniques that are already available
within the simulator to analyze the network in the time
domain.

BIBLIOGRAPHY
1. L. O. Chua and S. M. Kang, Section-wise piecewise linear functions: Canonical representation, properties and applications,
Proc. IEEE, 65: 915929, 1977.
2. S. M. Kang and L. O. Chua, A global representation of multidimensional piecewise linear functions with linear partitions,
IEEE Trans. Circuits Syst., 25: 938940, 1978.
3. L. O. Chua and A. C. Deng, Canonical piecewise linear representation, IEEE Trans. Circuits Syst., 35: 101111, 1988.
4. G. Guzelis and I. Goknar, A canonical representation for
piecewise affine maps and its application to circuit analysis,
IEEE Trans. Circuits Syst., 38: 13421354, 1991.
5. C. Kahlert and L. O. Chua, A generalized canonical piecewise
linear representation, IEEE Trans. Circuits Syst., 37: 373382,
1990.
6. T. A. M. Kevenaar, D. M. W. Leenaerts, and W. M. G. van Bokhoven, Extensions to Chuas explicit piecewise linear function descriptions, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.,
41: 308314, 1994.
7. D. M. W. Leenaerts, Further extensions to Chuas explicit
piecewise linear function descriptions, Int. J. Circuit Theory Appl.,
24: 621633, 1996.
8. W. M. G. van Bokhoven, Piecewise Linear Modelling and Analysis,
Deventer, The Netherlands: Kluwer Technische Boeken, 1981.
9. W. M. G. van Bokhoven, Piecewise linear analysis and simulation, in A. E. Ruehli (ed.), Circuit Analysis, Simulation and Design, Amsterdam: North-Holland, 1986, pp. 129166.
10. T. A. M. Kevenaar and D. M. W. Leenaerts, A comparison of
piecewise-linear model descriptions, IEEE Trans. Circuits Syst. I,
Fundam. Theory Appl., 39: 9961004, 1992.
11. W. Kruiskamp and D. Leenaerts, Behavioral and macro modeling
using piecewise linear techniques, Int. J. Analog Integ. Circuits
Signal Process., 10: 6776, 1996.
12. P. Veselinovic and D. M. W. Leenaerts, A method for automatic
generation of piecewise linear models, Proc. ISCAS, Atlanta, GA,
1996, Part III, pp. 2427.
13. L. O. Chua and A. Deng, Canonical piecewise linear modeling,
IEEE Trans. Circuits Syst., 33: 511525, 1986.
14. C. E. Lemke, On complementary pivot theory, in J. B. Rosen,
O. L. Mangasarian, and K. Ritter (eds.), Nonlinear Programming
(Proceedings of a Symposium), New York: Academic, 1968, pp.
349384.
15. S. Kamardian, The complementarity problem, Math. Program., 2:
107129, 1972.
16. J. Katzenelson, An algorithm for solving nonlinear resistor networks, Bell Syst. Tech. J., 44: 16051620, 1965.
17. P. Pejovic and D. Maksimovic, An algorithm for solving piecewise
linear networks that include elements with discontinuous characteristics, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 43:
453460, 1996.
18. K. Kawakita and T. Ohtsuki, NECTAR 2, a circuit analysis program based on piecewise linear approach, Proc. ISCAS, Boston,
1975, pp. 9295.
19. M. J. Chien and E. S. Kuh, Solving piecewise linear equations for
resistive networks, Int. J. Circuit Theory Appl., 4: 324, 1976.
20. D. M. Wolf and S. R. Sanders, Multiparameter homotopy methods for finding DC operating points of nonlinear circuits, IEEE
Trans. Circuits Syst. I, Fundam. Theory Appl., 43: 824838, 1996.
21. C. E. Lemke, On the complementary pivot-theory, in G. B. Dantzig and A. F. Veinott, Jr. (eds.), Mathematics of Decision Sciences,
Part I, Providence, RI: AMS, 1968, pp. 95114.

PIEZOELECTRIC ACTUATORS
22. C. van der Panne, A complementary variant and a solution algorithm for piecewise linear resistor networks, SIAM J. Math.
Anal., 8: 6999, 1977.
23. C. W. Cryer, The solution of a quadratic programming problem
using systematic overrelaxation, SIAM J. Control., 9: 385, 1971.
24. L. O. Chua and R. L. P. Ying, Finding all solutions of piecewiselinear circuits, Int. J. Circuit Theory Appl., 10: 201229, 1982.
25. K. Yamamura, Finding all solutions of piecewise-linear resistive
circuits using simple sign tests, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 40: 546551, 1993.
26. K. Yamamura and M. Ochiai, An efficient algorithm for finding
all solutions of piecewise-linear resistive circuits, IEEE Trans.
Circuits Syst. I, Fundam. Theory Appl., 39: 213221, 1992.
27. K. Yamamura, Exploiting separability in numerical analysis of
nonlinear systems, IEICE Trans. Fundam. Electron., Commun.,
Comput. Sci., E75-A: 285293, 1992.
28. L. Vandeberghe, B. de Moor, and J. Vandewalle, The generalized
linear complementarity problem applied to the complete analysis
of resistive piecewise linear circuits, IEEE Trans. Circuits Syst.,
36: 13821391, 1989.
29. B. de Moor, Mathematical concepts and techniques for modelling
of static and dynamic systems, Ph.D. thesis, Katholieke Universiteit Leuven, Belgium, 1988.
30. S. N. Tschernikow, Lineare Ungleichungen, Berlin: VEB
Deutscher Verlag der Wissenschaft, 1971 (translation from Lineinye neravenstva, 1968, by H. Weinert and H. Hollatz into
German).
31. D. M. W. Leenaerts, Applications of interval analysis to circuit
design, IEEE Trans. Circuits Syst., 37: 803807, 1990.
32. D. M. W. Leenaerts, TOPICS, a contribution to design automation, Ph.D. dissertation, Department of Electrical Engineering,
Technical University Eindhoven, The Netherlands, 1992.
33. D. M. W. Leenaerts and J. A. Hegt, Finding all solutions of
piecewise linear functions and the application to circuit design,
Int. J. Circuit Theory Appl., 19: 107123, 1991.
34. V. Chvatal, Linear Programming, New York: Freeman, 1983.
35. S. Pastore and A. Premoli, Polyhedral elements: A new algorithm
for capturing all equilibrium points of piecewise linear circuits,
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 40: 124
132, 1993.

DOMINE M. W. LEENAERTS
Technical University Eindhoven

467

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

CIRCUIT ANALYSIS COMPUTING

BY WAVEFORM RELAXATION
Conventional exact circuit simulation algorithms, as they are
implemented in SPICE (1) and ASTAP (2) and in the followon programs, are limited by excessive compute time for the
time domain analysis. The difference between the number of
transistors that can be simulated and the number of transistors in a very-large-scale integrated (VLSI) circuit is an everyincreasing quantity. For large circuits, the compute time increases roughly as O(n1.3) to O(n1.8) depending on the circuit
under analysis, where n is the number of circuit nodes. This
has led to new approaches for the solution of these problems.
The waveform-relaxation method (WR), which is such a technique, is an iterative approach for the exact solution of large
VLSI circuits in the time domain.
The waveform relaxation technique, as it is presented in
this article, aims at the same accuracy level as the widely
used SPICE program (1). Often, however, in VLSI design,
timing simulators are used to obtain solutions where accuracy
is sacrificed for speed. These techniques are not considered in
this article. However, three examples of such algorithms can
be found in the references. The ITA algorithm (3) is based on
timepoint relaxation, whereas the SPECS algorithm (4) uses
piecewise constant waveforms. Another technique that uses
piecewise linear waveform approximations together with a

339

highly damped explicit integration scheme is implemented in

ACES (5).
A waveform method was first applied to VLSI circuit analysis problems in 1980. The starting point was the one-way
circuit analysis formulation by Ruehli, Sangiovanni-Vincentelli, and Rabbat in 1980 (6), which ignored the gate-to-drain
capacitive feedback in metal oxide semiconductor (MOS) transistors. Subsequently, the WR process for circuit simulation
was invented by Lelarasmee, Ruehli, and SangiovanniVincentelli to address this shortcoming (7). Different versions
of WR-based circuit solvers were first developed at the University of California at Berkeley (8) and at IBM Research
Laboratories (9) and later at several other locations. Numerous improvements and new applications have been discovered
by the engineering and mathematical communities. On the
mathematical aspects, Miekkala and Nevanlinna and Odeh
(10) contributed much early on to the understanding of the
convergence issues of WR.
Researchers now apply the WR approach to a wide range
of problems from semiconductor device calculations (11), to
nonlinear parabolic problems (12), and to multibody problems
(13). In this article we will give only a limited set of references
that highlight key advances in WR for both scalar and multiprocessor machines. A complete set of references up to 1986
are given in Ref. 14. A large chapter in Burrages book (15)
is dedicated to the application of WR to mostly homogeneous
problems such as boundary value problems. It includes an extensive set of references on more recent WR work. The terminology homogeneous and heterogeneous is actually due to
Gear. Homogeneous means problems that can be described by
a single set of equations in which the domains have relatively
uniform properties. The solution efficiency for homogeneous
problems is a very strong function of the basic WR algorithm,
which hereinafter will be referred to as the internal algorithm.
However, the focus of this article is on the heterogeneous
VLSI circuit analysis problem. Heterogeneous problems consist of a multitude of different aspects such as linear and nonlinear parts. All these parts may have a mixture of different
models embedded such as the conventional macromodels representing semiconductor devices. It is clear that a simple solution technique will be very inefficient for these problems. For
the WR approach to be efficient the internal algorithms must
be embedded in another layer, which we call the external algorithms.
The external WR solution algorithm can be characterized
by the following steps:
1.
2.
3.
4.
5.

Partitioning of a circuit into small subcircuits

Ordering of subcircuits
Scheduling of subcircuits for analysis
WR iteration until convergence of waveforms
Storing of waveforms in database

Before presenting the WR algorithms, it is appropriate to

give some insight into the fundamental reasons why WR can
be faster than a conventional time point circuit solver. Here,
we assume that the circuits are sufficiently large that they
can be partitioned into a reasonable number of subcircuits.
First, in WR a large number of small matrices are solved
rather than a single large one. For the usual modified nodal
analysis circuit formulation (MNA) (16), the size of the matrix

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

is driven by the number of nodes in a circuit. The average

solution time growth rate is O(n1.5) for a circuit solver using
sparse matrix techniques. It is obvious that the speedup due
to matrix partitioning increases as the number of subcircuits
increases, which is generally an increasing function of circuit
size. This is obviously one of the factors why WR is fast for
very large circuits. Also, each matrix can be solved using different time steps. The fact that the time steps in the subcircuits are different is called the multirate factor. The evidence
that in large circuits the waveforms are most likely very different in different parts of a circuit points to the fact that this
multirate behavior is another factor that increases strongly
with the number of subcircuits. However, the speedup is reduced by the number of times the average subcircuit is evaluated due to WR iterations. Hence, it is obvious that the strategy is to keep the average number of WR iteration as small
as possible. One of the factors that greatly helps is that a
waveform solution error of 102 to 103 is sufficient for the
circuit simulation problem. The typical number of WR iterations is between 3 and 4 for a well-partitioned circuit, while
the WR iterations may vary between 2 and 20 for a typical
heterogeneous circuit. Smaller errors, like those required for
most homogeneous boundary-value problems, would demand
a much larger number of WR iterations. For this type of problem, the convergence rate, considered later, is a much more
important factor than for the circuit WR problem we consider here.
STRUCTURE OF VLSI CIRCUITS
Special-purpose solvers gain much of their efficiency from utilizing the specific structure of the problem at hand. VLSI circuit solvers are no exception. In fact, we hope that it will be
clear from this section that a general-purpose WR solver without special partitioning algorithms would perform very poorly
for VLSI circuits. We want to identify key properties of large
VLSI circuits that make them good candidates for WR. Todays parallel computers make the analysis of circuits with less
than several million transistors excellent candidates for WR.
As will be explained below, the partitioning step subdivides these very large circuits into small subcircuits, containing one to several hundred nodes. Figure 1 shows an example structure of a very large VLSI circuit. Each of the
blocks may represent a functional unit of a VLSI chip with
hundreds to thousands of transistors. It is immediately evident that these circuits should be partitioned into smaller

Number of subcircuits

340

350.00
300.00
250.00
200.00
150.00
100.00
50.00
0.00

5.00
Level

10.00

Figure 2. Width of a DRAM circuit as a function of the logic level,

starting from the input.

units that may include one or more functional blocks depending on the block size. The connections between blocks
shown in Fig. 1 may involve multiple paths. However, the
external connections are usually sparse compared with the
connections within the functional units. It is very important
to recognize that the number of fanout connections of a circuit
output is in general very sparse (e.g., 16). However, we have
also encountered circuits with a fanout of 4000.
Each block has the property that the number of logic levels
or the logical circuits that are connected in series must be
limited to meet delay time limits or the system clock cycle.
Hence, most functional units in Fig. 1 are relatively shallow
in the number of levels. The functional units become wider
as the number of transistors increases. An example is the error detection or correction circuitry of a 16 Mbyte dynamic
random access memory (DRAM) design, shown in Fig. 2. The
unit contains over 16 103 transistors; however, the number
of logic levels is only 11. As can be seen from the figure, the
width of the unit averages over 200 gates with a large potential for parallel processing. More insight into this will be
given in the section entitled Parallel Waveform-RelaxationBased Circuit Simulation.
It is evident that the multirate factor increases rapidly as
circuit size exceeds the size of a functional unit since the
waveforms may have little correlation especially if they come
from different functional units.
INTERNAL WR ALGORITHMS
In this section we examine the WR iteration process, assuming that a circuit has already been divided into subcircuits by
the external partitioning algorithms considered in the section
entitled External Global WR Algorithms. The situation that
we explore focuses on the local iteration between two neighboring subcircuits that are part of a large global circuit environment.

Functional units

Fundamental WR Techniques
Inputs

Outputs

Width
Levels
Figure 1. Basic structure of a large VLSI circuit as a set of blocks
which are interconnected sparsely.

The waveform iteration process consists of an approximation

to the solution of a set of nonlinear differential equations by
a sequence of convergent waveforms. In the equations that
follow, (w) is used to indicate the WR iteration index. It is
assumed that subsystems or subcircuits are generated by the
previously mentioned external partitioning and scheduling
techniques. The internal algorithm is designed to solve subcircuit equations that are formed using the MNA approach as
C(x)x(t)
= g(x, t)

(1)

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

where x [v, i]T, v are node voltages, and i are selected currents. The nonlinearities in C(x) are in part due to the transistor and integrated-circuit capacitances. To ensure that the
solution is unique and that convergence for WR can be
achieved, the capacitor and transistor models are designed
with care so that they do not have discontinuities. The required properties of C(x) and g(x, t) are considered later in
more detail in the section entitled Convergence for the Nonlinear Case. We also do not want to consider the general differential algebraic equations (DAE) that result from general
MNA equations since the resultant equations are more complex than the ordinary differential equations (ODE) case considered here, although it has been shown by several researchers that a solution is possible for the DAE case, for example,
in Ref. 17.
Consider the scalar equation
x(t)
= f (x, t)

(2)

where f(x, t) C1g(x, t) with the initial condition x(0) x0,

where C 0 is a constant capacitor. We gain some insight
into the waveform iterative solution by considering the PicardLindelof (PL) iteration technique. In this method, the
following waveform iteration is suggested:
x (w+1) (t) = f (t, x(w) (t))

(3)

x(w1)(t0) x0, where x0 is the initial value, which is the same

for all iterations. It is assumed that we want to find the solution in a window in time t [ta, tb], where ta is the window
start time and tb is the window end time. For convenience we
take the window to be t [0, T], where T is the window size.
In the PL technique, the solution of the problem is obtained
by simply integrating the equation as
x(w+1) (t) = x0 +

f ( , x(w) ( )) d

(4)

where the initial waveform may be constant in the time window with x(0) x0 and subsequent iterations yield new waveforms x(1)(t),x(2)(t),x(3)(t), . . ..
As an example, if the subsystem of equations is simplified
by assuming that g(x, t) Gx(t), where G represents a linear resistor R, or G 1/R, then Eq. (1) is reduced to
x(t)
+ x(t) = 0

(5)

where 1/(RC) is the magnitude of the eigenvalue or inverse time constant. If we apply the PL iteration algorithm to
this RC circuit problem we can make the following statement
about the convergence of the iterative solution:

341

Proof: Applying the PL iteration Eq. (4) to Eq. (5) we can find
the solution to be
x(w) (t) = 1 t + (1)w

(t)w
w!

(7)

This is the Taylor-series expansion for the solution x*(t)

et, where 1/RC and Eq. (6) is found from the error term
in Taylors theorem.
From this, we gain insight into the behavior of the solution
of PL iterations for VLSI circuits that involve RC subcircuits
with capacitances to ground. First, we observe what is called
the early-time convergence property of the solution, which
shows that it converges faster for small times. Also, the accuracy of the solution increases by one order for each iteration.
By inspecting Eq. (6) we find that the time window [0, T]
must be kept small in relation to the number of waveform
iterations such that w T, to ensure uniform convergence.
Hence, it may be desirable to subdivide the total analysis
time into smaller subintervals or time windows for which convergence is obtained in fewer iterations. It is clear that the
waveforms must be converged even at the end of the window
at t T so that the previous solution will provide a good
starting point for the next window. We will visit this question
in more detail in the section entitled Convergence for RC
Circuits.
One-Way Systems and Gauss-Jacobi and Gauss-Seidel WR
For WR we assume that the system equation (1) has been
split or partitioned according to the techniques described
later in the section on partitioning. To study local convergence, we focus attention on the behavior between two connected subcircuits, and we temporarily ignore all interactions
with other subcircuits. This is not representative of the real
WR iteration scheme or schedule that involves all subcircuits.
The local convergence situation is depicted in Fig. 3 where all
other WR variables due to partitioning with respect to other
subcircuits are assumed to be external (known) sources as
shown. Hence, we assume that only the system variables x1
and x2 are relevant for the local convergence situation.
Local convergence of WR algorithms has been studied by
many researchers [e.g., Lelarasmee, Ruehli, and SangiovanniVincentelli (7), White and co-workers (18,19), and Debefve,
Odeh, and Ruehli (14)]. We will look at the convergence issue
in the next three sections. First, we give the most important
features of the two main algorithms, the GaussJacobi WR
and GaussSeidel WR. They are best explained using the
model in Fig. 3, where subcircuit 1 is excited by an input and
coupling exists between the subcircuits in both directions, or
x1 (t) = f 1 (x1 , x2 , u(t))
x2 (t) = f 2 (x1 , x2 )

(8)

Theorem 1. If we apply the PicardLindelof method to Eq.

(5) on the interval t [0, T], then the global error bound is
given by

|x (t) x

(w)

(t)(w+1)
(t)|
(w + 1)!

where x*(t) is the converged or the exact solution.

(6)

SCkt 1

SCkt 2

x1(t)

x2(t)

Figure 3. Two subcircuits shown to illustrate the local WR iteration process.

342

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

where x1(0) x10 and x2(0) x20 and u(t) represents the
inputs.
A special case exists if the connection from subcircuit 2 to
subcircuit 1 is missing, or x1(t) f 1(x1, u(t)) only. In this case,
we have a so-called one-way connection. If we solve the system by solving subcircuit 1 first, followed by subcircuit 2, the
exact solution is obtained in one forward iteration (6). An example of such a system consists of two metal oxide semiconductor (MOS) transistor inverters without gatedrain feedback capacitances. Since most logic circuits are highly
directional even during switching transients, it is evident
that it is always advisable to solve the circuit in the direction
of large coupling.
In the general case, with coupling in both directions, several iterations are necessary to obtain a solution. The Gauss
Jacobi WR iteration algorithm is given by

x1(w+1) (t) = f 1 (x1(w+1) (t), x2(w) (t))

x2(w+1) (t) = f 2 (x1(w) (t), x2(w+1) (t))

(9)

where x1(w1)(t0) x10 and x2(w1)(t0) x20. The iteration sequence

or schedule for this case is given by alternate evaluations of
subcircuits 1 and 2, or 1, 2, 1, 2, . . . until convergence. In
the GaussJacobi (GJ) algorithm, all subcircuits are solved at
iteration (w 1) using inputs from iteration (w). In contrast,
the GaussSeidel (GS) WR method is given by

x1(w+1) (t)
x2(w+1) (t)

=
=

f 1 (x1(w+1) (t), x2(w) (t))

f 1 (x1(w+1) (t), x2(w+1) (t))

(10)

where x1(w1)(t0) x10 and x2(w1)(t0) x20. In this approach, results that are computed in the solution of subcircuit 1 at iteration (w 1) are used in the solution of subcircuit 2 in the
same iteration. This ordering and the immediate use of newly
computed results allows the GS algorithm to take fewer iteration steps to converge than the GJ algorithm. For this reason,
the GS method is generally preferred even though it puts a
larger burden on the external WR algorithms such as ordering and scheduling, which have to select the subcircuit analysis sequence. It is not always possible to update all the variables as required for GS WR. For this case we will use what
we call a mostly GS algorithm that instantaneously updates
as many variables as possible. We will revisit this issue later
in the section entitled External Global WR Algorithms.

The idea of accelerating the solution by overestimating the

update vector is used for most iteration techniques, including
WR. The basic over-relaxation scheme (SOR) for GS WR takes
a similar form as in the conventional scheme. A new set of
waveform variables are introduced, which we call y(t). With
this the GS SOR WR scheme can be written as

y1(w+1) (t) = f 1 (y1(w+1) (t), x2(w) (t))

y2(w+1) (t) = f 2 (x1(w+1) (t), y2(w+1) (t))

I1

+
V1

+
R1

R3

V3

Figure 4. Resistive circuit to illustrate the iteration process if the

circuit is partitioned at R2.

The first practical application of SOR WR to VLSI circuit

problems was done by Carlin and Vachoux (20). They applied
under-relaxation to a stiff high-gain problem and showed that
convergence could be improved by using 1. The definition
of a stiff problem is one with a large difference in eigenvalues
or time constants.
Convergence of WR SOR has been studied theoretically by
Miekkala and Nevanlinna (21). It has also been applied to a
semiconductor device problem by Reichelt, White, and Allen
(22). They used a frequency-dependent over-relaxation factor
( f) that was applied to the time domain through a convolution operator. The general time window under- and over-relaxation WR technique applied to VLSI circuit problems most
likely can benefit greatly from a time-dependent factor (t)
for t [0, T].
Convergence for a Resistance Circuit
The convergence of the WR has been studied extensively for
the linear circuits by several researchers, for example, Miekala and Nevanlinna (21) and Desai and Hajj (23). In this
section, we look at the static case of the small resistance circuit, in Fig. 4, which is important for the partitioning step.
The exact solution for this problem is given by
v3 = I1 R1

R3
R1 + R2 + R3

(11)

x2(w+1) (t) = y2(w+1) (t) + (1 )y2(w) (t)

where y1(w1)(x0) x10 and y2(w1)(t0) x20. The over- or underrelaxation factor is usually in the range 0 2.

(12)

which can be found by inspection.

For the iterative solution we define the forward gain gf
R3 /(R2 R3) and the backward gain gr R1 /(R1 R2), which
are simply the voltage divider ratios. This corresponds to
splitting the circuit at R2. The voltage dividers lead to the
following voltage ratios: v3 gf v1 and v1 grv3. The iterative
solution yields
v1(1) = I1 R p1 , v3(1) = gf v1(1) , v1(2) = v1(1) + gr v3(1) +

Successive Under- and Over-Relaxation WR

x1(w+1) (t) = y1(w+1) (t) + (1 )y1(w) (t)

R2

(13)

with Rp1 (R1R2)/(R1 R2). With this, the iterative solution

is given by
v1(w) = v1(1) [1 + gf gr + ( gf gr )2 + + ( gf gr )w ]

(14)

The contraction factor is given by gf gr. For convergence

within a few iterations this factor needs to be 1. Assume
as an example that R1 1, R2 10, R3 5. Then gf 
and
gr 
, which leads to 
. In this case convergence is
reached in very few iterations to a very high accuracy. Also,
directionality of coupling can be assigned, even with this simple circuit, as we observe since gf gr. From the logic signal
flow it is evident that in the directionality is assigned in the
high-gain direction (14).

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

Convergence for RC Circuits

As was mentioned earlier, the convergence of WR for general
circuits has been studied from the very beginning, and the
impact of the capacitors on the convergence is considered a
key issue. In the early work on WR it was assumed that each
node in the circuit was required to have a capacitor to ground.
More relaxed conditions have been established recently by
Desai and Hajj (23) and Gristede, Ruehli, and Zukowski (24).
Specifically, the convergence of RC-type circuits has been investigated by several researchers, for example, Miekkala,
Nevanlinna, and Ruehli (25), Leimkuhler, Miekkala, and
Nevanlinna (26), Ruehli and Zukowski (27), and Leimkuhler
and Ruehli (28).
At first, it seems that many different RC circuit topologies
need to be considered to gain an understanding of the WR
behavior of RC circuits. However, in VLSI circuits there are
two circuit topologies that appear many times as basic building blocks. The first involves a capacitor connected between
two nodes, in which this capacitance may represent a gate-todrain capacitance. To study its impact, the worst-case RCR
situation is considered in Fig. 5(a), where only resistances are
connected to the ground nodes. It should be noted that the
usual sufficient conditions for WR convergence for example,
Ref. 4 or 15, do not include this case.
It was shown in Ref. 25 that, even for the RCR circuit in
Fig. 5(a), convergence can be achieved under certain conditions. The WR iteration equations for the case where we assume that a current source is connected to the left node in
circuit in Fig. 5(a) are given by
v 1(w+1) (t) +

1
I (t)
v1(w+1) (t) = 1
+ v 3(w) (t)
R1C2
C2

(15)

1
v(w+1) (t) = v 1(w) (t)
R3C2 3

(16)

v 3(w+1) (t) +

These local mapping functions show that the derivatives at

one of the partitioned nodes v1 or v3 are a function of the derivative at the other end of the partition v3 or v1, respectively.
It is intuitively obvious that for this case not only the input
forcing functions but also the derivatives must be continuous
for the WR iteration to converge. In actual VLSI circuits this
issue is somewhat moderated since the gate-to-drain capacitances for the MOS field-effect transistors (MOSFET) have
at least some capacitances to ground at each end. Again, the
partitioning of the capacitance between gate and drain is very
desirable in spite of the difficulties since a MOS transistor is
a perfect one-way device if the capacitive coupling is ignored.
This analysis emphasizes the requirements for the smooth-

C2

R2

ness of the MOS capacitance models. It is confirmed by the

mathematical analysis in Ref. 25 that slow WR convergence
can be achieved for the limiting case in Fig. 5(a) in terms of
Sobolev norms, which measure the derivatives as well as the
functional values.
The second basic RC circuit is the low-pass CRC circuit,
Fig. 5(b), which was analyzed by Ruehli and Zukowski (27)
for simple cases, and for more complex RC circuits by Leimkuhler and Ruehli (28). Unlike the above RCR circuit, the
CRC circuit seems to lend itself well to partitioning. However,
there seems to be a problem in that it is hard to give a static
argument for partitioning at the resistor R2 as was done in
the previous section for resistive circuits. The voltage transfer
function for the case in which we excite the circuit with a
voltage source Vs in series to C1 is given by

1
1
v(w+1) (t) =
v(w) (t) + V s (t)
R2C1 1
R2C1 3
1
1
v(w+1) (t) =
v(w) (t)
v 3(w+1) (t) +
R2C3 3
R2C3 1
v 1(w+1) (t) +

R3

(a)

C1

(w+1)
(w)
(sII + M )v
(s) = N v (s)

(b)

Figure 5. Two fundamental circuit topologies for partitioning as part

of a VLSI circuit.

(18)

where M and N are evident from Eqs. (17) and (18). We can
rewrite Eq. (18) as
(w+1)
(w)
(s) = K (s)v
v

(19)

where the meaning of the symbol K(s) is evident from comparing the last two equations. The following theorem from Miekkala and Nevanlinna (10) is applied to the problem to find the
spectral radius.
Theorem 2. Assume that the eigenvalues of M have positive
real parts. Then the spectral radius of K(s) is (K)
maxR( jI M)1N. For this case we have

1
0

sR2C1 + 1

K (s) =
(20)

1
0
sR2C3 + 1
and it is clear that the minimum occurs for s 0 where
(K(0)) 1, which indicates that the convergence problem
could occur at s 0.
In Refs. 27 and 28 it is shown that this problem does not
occur for a finite time window. For convenience, we set both
time constants to unity by choosing C1 C3 R2 1. Then
we can find the iterative solution to be

v1(w) (t) = et
C3

(17)

This can be written in the Laplace domain as

w1

m=0

R1

343

t 2m
(2m)!

(21)

With (2m)! 2(2m)2m1/2e2m the error term is




et 
t 2m 1
Error[v1(w) (t)] =

2 m=(w) 2m
m

(22)

From this we can derive the rapid convergence of the partitioned circuit provided that the window is small enough.

344

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

Theorem 3. The WR sequence converges rapidly in a time

window T after the wth iteration for w T/2.

First, we assume that the transistor nonlinearities satisfy

the Lipschitz continuity condition

We can see from this that for our normalization R1C2 1 and
R3C2 1 the convergence is very fast for w T/2. Hence,
the larger the time constants of the two partitioned circuits,
the larger the time window T for which rapid convergence
occurs for a particular number of WR iterations w. It should
be noted that this type of partitioning can again be done statically in the partitioning process by choosing an appropriate
value of the time window T and the approximate number of
WR iterations.
Another important observation can be made from this
analysis on convergence behavior for windowing. First, most
realistically modeled nodes for VLSI circuits, with the exception of the gate-to-drain capacitances, can be represented by
the basic circuit in Fig. 5(b). Hence, the convergence behavior
shown in this section given by Eq. (22) is quite typical. It
shows that if the window T is chosen too large or equivalently, the number of WR iterations w are chosen to be insufficient, then the solution may be quite poor since the rapid
convergence regime has not been reached. Specifically, at the
window boundary t T, the approximation and, even more
important, the derivatives of the solution are approximated
very poorly. Then, multistep integration techniques, such as
the popular BDF2 method (29), that utilize solution points
from the previous window are used to continue the solution
in the next time window. This obviously represents a very
poor starting condition for the solution in the next time
window.

G(x1 , t) G(x2 , t) Kx1 x2 

Convergence for the Nonlinear Case

Key aspects of VLSI circuits are the nonlinear MOSFETs and
capacitances associated with the devices as well as the onsilicon diffusion wires and diodes. This requires a nonlinear
analysis of the convergence, which has been available since
the start of WR, for example, Lelarasmee, Ruehli, and Sangiovanni-Vincentelli (7), White et al. (18), White and Sangiovanni-Vincentelli (19), and Debefve, Odeh, and Ruehli (14).
However, the nonlinear WR convergence proofs have become
more general in recent years. The proofs by Schneider (17)
and Gristede, Ruehli, and Zukowski (24) take the DAE (differential-algebraic equation) for the MNA circuit formulation
(17) into account. Also, more useful bounds have been derived
with a one-sided Lipschitz constant by in t Hout (30) and in
Burrages book (15). Here, we give an interesting and relevant
proof of Taubert and Wiedl (31) that illuminates the nonlinear convergence in terms of a time window T. The vector u is
given by u (u1, u2, . . ., um), and the two relevant norms
are u maxi1,. . .,m ui and zT maxt[0,T] z(t).
The circuit equations for a MOSFET circuit including the
voltage-dependent capacitors are given as [similar to Eq. (1)]
C(x)x(t)
= G(x, t)

(24)

for the allowed values of t, x1, x2. Second, the nonlinear behavior of the m m capacitance matrix with respect to the real
vector z of length m must satisfy several conditions. Each element of the capacitance matrix C(z) must satisfy another
Lipschitz continuity condition with a constant L that applies
for all j for the real vectors u, v:
m


|cjk (u) cjk (v)| Lu v

(25)

k=1

A further condition is imposed on the capacitances. We assume that there exists a constant 0 such that for all real
vectors, u, v where u 0 we have
[C(z)u]i ui u2

(26)

This condition can be viewed as being related to the instantaneous energy in the system of capacitances C, which is given
by 1/2uTCu 0 for u 0. For a nodal capacitance matrix,
this implies diagonal dominance. For the nonlinear case, the
requirements in Eq. (26) are somewhat more restrictive than
what is required for the multiple capacitances for which
z u.
The WR equations for two subcircuits in which each subcircuit is represented by a single equation are given by

c11 (x1(w+1) , x2(w) )x1(w+1) (t) + c12 (x1(w+1) , x2(w) )x2(w+1) (t)
= G1 (x1(w+1) (t), x2(w) (t), t)
c21 (x1(w+1) , x2(w+1) )x1(w+1) (t) + c22 (x1(w+1) , x2(w+1) )x2(w+1) (t)

(27)

= G2 (x1(w+1) (t), x2(w+1) (t), t)

where the contribution of the nonlinear capacitances is evident. The initial conditions are x1(w1)(t0) x10 and x2(w1)(t0)
x20. Note that in terms of capacitances c11 C1 C2, c12 c21
C2, and c22 C2 C3, where the circuit consists of three
capacitances with the same topology as the circuits in Fig. 5.
All three capacitances C1, C2, and C3 can be nonlinear.
Now, we are ready to state the very interesting condition
for nonlinear convergence in a time window [0,T].
Theorem 4. The sequence of approximate solutions given by
the WR iterations x(w1) converges uniformly to the solution
x* of Eq. (23) in [0,T] for which the following condition holds:
KT LTx T 0

(23)

with the initial value x(0) x0. All the conditions below are
assumed to apply in a window in time, which we choose to be
t [0,T]. The voltage excursion must be contained for the
semiconductor devices such that the nonlinearities can be described by a valid circuit model. Hence, we assume that limits
are also applied on the particular values of x so that the conditions of the theorem are met.

Proof. Here, we only give an outline of the proof. The uniqueness of the solution of Eq. (23) is guaranteed by the conditions
given earlier in a time window t [0,T]. For any continuous
differentiable function x(t) with the initial condition x(0)
x*(0), we form the difference
A(x, x ) = C(x)x C(x )x G(x, t) + G(x , t)

(28)

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

which can be expanded by adding and subtracting the quantity C(x)x*. For t [0,T] we form the quantity
A(x, x )i (t)(x x )i (t)

(29)

Using also the fact that

xi(w) (t) = xi0 +

t
0

xi(w) (s) ds

(30)

and using the Lipschitz conditions in the expanded form of

Eq. (29) with K, L from above, we can show the inequality in
Theorem 4. We assume that the size of the time windows T
is adjusted during the transient analysis.
It is evident from this that both the nonlinearities of the
capacitances and the devices can reduce the maximum size of
the time window during the highly nonlinear transitions of
the devices for which usually the smallest time windows T
occur. This transition time is usually a small part of the transient analysis time. Also, the transition is the time where the
circuit solver will take very small time steps, so that T includes a reasonable number of time steps.
Newton Variant of WR
Given Eq. (2), in a general form, the WR schemes considered
so far first partition the system at the differential equation
level. Then the nonlinear equations are solved separately for
each subcircuit using Newtons method. Van Bokhoven (32)
considered a variation on WR by essentially interchanging
the waveform loop with the Newton linearization of the equations. Hence, the Newton variant of WR starts by linearizing
Eq. (2) for the entire circuit. The system of equations rewritten in a functional form is
F (x) = C(x, t)x(t)
g(x, t) = 0

(31)

(32)

where JF(x) is the Frechet derivative of F and where n is the

nonlinear or Newton iteration index. This method has been
explored by many researchers [e.g., (18,19,3234)]. It can be
shown that the resultant scheme
x(n+1) Jn x(n+1) = f (x(n) ) Jn x(n)

much larger number of WR iterations are required than for

the circuit simulation problem.
Other issues are of importance for a large VLSI circuit
problem for which the general WR algorithm offers several
advantages over the Newton waveform approach. First, for
the conventional WR, circuits are partitioned at the schematic
level into self-contained subcircuits that are analyzed independently using a conventional circuit solver. Furthermore,
the interaction between subcircuits and functional units, at
all levels, simply consists of the exchange of segments of
waveforms of various sizes. Other techniques such as the hierarchical WR techniques (35) and parallel WR discussed
later benefit greatly from the simplicity of the conventional
WR approach.
EXTERNAL GLOBAL WR ALGORITHMS
In this section we consider the overall environment that is
required for a heterogeneous VLSI circuit WR solver where
the circuit structure may be extremely nonuniform. This is
especially true for mixed analog-digital circuits. To make the
issue more complex, feedback loops in logical circuits may require more WR iterations than the local WR interfaces require to converge. It is evident from this that all aspects of a
WR program must be implemented carefully to obtain maximum overall efficiency. Furthermore, it is very unlikely that
the optimal number of WR iterations is uniformly the same
for all local interfaces between the subcircuits. Before we can
consider these global convergence issues at the end of this
section, we first must introduce other fundamental concepts
such as partitioning, ordering, and scheduling. A detailed description of the concepts is given in Ref. 14. A key aspect of
the external environment is the storage of the waveforms. As
will be evident below, the waveforms for iterations w and
w 1 must be available for computations.
Partitioning

This form can be linearized using the Newton scheme as

x(n+1) = x(n) JF1 (x(n) )F (x(n) )

345

(33)

is another splitting of the circuit matrix of the entire circuit

(15). If we apply only a single Newton iteration n 1, we
can partition the resultant circuit matrix and we can use an
external waveform relaxation loop. At this level, all the necessary algorithms such as windowing are applied.
The Newton waveform technique has been successfully applied to the homogeneous semiconductor problems by Lumsdaine and White (11). These problems do not require a complex partitioning procedure as is the case for heterogeneous
systems. For homogeneous problems the Newton waveform
approach is preferred for its quadratic convergence behavior.
However, this is more of an issue for the solution of homogeneous systems since much more accuracy and therefore a

The partitioning of a circuit into small subcircuits is clearly a

heuristic process for heterogeneous systems. One of the key
driving factors for partitioning is that convergence of the internal WR algorithms must be enhanced by the partitioning
process. This has been recognized since the beginning of VLSI
WR, and much work has been dedicated to this issue throughout the evolution of WR [e.g., Carlin and Vachoux (36) White
and Sangiovanni-Vincentelli (37), Cockerill et al. (38), and
John, Rissiek, and Paap (39).
Definition 1. Partitioning means subdividing a large circuit
(Ckt) into small subcircuits (SCkts). The SCkts are chosen in
such a way that coupling between subcircuits is minimized
and that convergence is enhanced.
It should be noted that this type of partitioning is also known
as multisplitting or diacoptics. Most partitioning algorithms
are static; the partitions are defined before a transient analysis is performed. In fact, it is the first step in the overall WR
scheme. Some exploratory work on dynamic partitioning has
been done by Dumlugol, Cockx, and DeMan (40) for specific
circuit structures in which the partitions are altered during
the iteration process. It is evident that for large heteroge-

346

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

a
2

b
b
c
c
(a)

(b)

Figure 6. (a) A MOS transistor circuit partitioned into three subcircuits; (b) A directed graph corresponding to Fig. 6(a), which shows
the main logic signal flow.

neous circuits static partitioning is preferred since it can be

designed for all types of structures.
Two of the most popular methods are pointwise and block
partitioning. Pointwise partitioning breaks the circuit at each
node, generating subcircuits with one node each. This scheme
does not control the coupling between subcircuits. On the
other hand, block partitioning groups one or more nodes into
SCkt based upon estimates of the coupling of the circuit elements that connect between them. The techniques in the previous sections entitled Convergence for a Resistance Circuit
and Convergence for RC Circuits are applied to see if two
nodes should be in the same SCkt by evaluating the potential
coupling. The nodes of the resultant SCkt are then ensured
not to be strongly coupled to other SCkts at least in one direction. This direction is away from the SCkt for an output and
into the SCkt for an input. Hence, block or subcircuit partitioning leads to much faster WR convergence.
Most WR programs also use graph theoretic partitioning
algorithms like the strongly connected or dc connected components (14). An example of a circuit that has been partitioned
into dc connected components is shown in Fig. 6(a). In Fig.
6(b), a directed graph is shown that corresponds to the circuit
in Fig. 6(a).
Next, we consider in more detail the decision process for
the assembly of nodes into SCkts. One of the algorithms used
is the diagonally dominant Norton (DDN) algorithm by White
and Sangiovanni-Vincentelli (37), which is based on techniques given in the section on resistance-circuit convergence
for static partitioning. This algorithm is based on the idea
that two nodes may either be coupled only resistively or capacitively. The simple circuit in Fig. 4 provides a model for
applying this algorithm. Consider the resistor R2 to represent
all parallel conducting paths between any two nodes. These
include all resistive and inductive elements as well as worstcase values for the nonlinear conductances of semiconductor
devices. The inductance voltage drops are set to zero for the
conductance between nodes. The resistances R1 and R3 represent the equivalent resistance of all local paths to ground.
Again, this is done by ignoring all capacitance in the circuit
for these two nodes. If the convergence factor gf gr is
greater than some threshold value, usually chosen to be between 0.3 and 0.95, the two nodes are considered to be
strongly coupled and are placed into the same subcircuit.

Since the model is set up using the worst case for nonlinear
resistances, a slightly higher value of the threshold is used
since the gain estimates are conservative. It should be noted
that the same technique can be used for a circuit that includes only capacitors in exactly the same way as in the section on convergence for RC circuits in which the equivalent
resistance values used are given by R 1/C. All pairs of
nodes that are directly connected to one another are considered in the partitioning process, and the algorithms just described will decide whether to place them in the same subcircuit or not. Hopefully, the resultant SCkts are small so that
each has only a few nodes. However, if too many single-node
subcircuits result, it may be advantageous to merge some
subcircuits into larger ones. Merging or condensing will reduce the number of WR iterations at the expense of having to
solve larger subcircuits. An example of a situation where it
may be advisable to condense subcircuits occurs when global
feedback loops exist in the circuit. This will be explained in
more detail in the next section.
Ordering and Scheduling
Definition 2. Ordering is defined as the process of labeling
the subcircuits in an increasing order starting with the one(s)
that should be solved first.
It is evident from the example of a one-way inverter chain,
Fig. 7, in which the gate-drain capacitances are ignored, that
the solution starting from input to output leads to convergence in one WR iteration. On the other hand, if the subcircuits are ordered from output to input, m inverters require m
WR iterations for convergence. It was shown in the first section that large VLSI circuits that are simulated by WR techniques have many parallel paths, which can result in the
same ordering in each of the paths or chains of SCkts.
Ordering becomes more difficult for circuits with feedback
loops. There are two possible choices for dealing with feedback. An example is given in Fig. 6(a) for a circuit with feedback. This is apparent from the graph in Fig. 6(b). For small
feedback loops involving only a few SCkts like that given in
this example, it may be more efficient to form a larger SCkt
by merging all the SCkts in a feedback loop into a single
SCkt. For larger loops, it may be better to cut the feedback
loops (14). Application of these techniques results in a new
set of SCkts without cycles. The feedback-loop-cutting algorithm can also be viewed as a mostly GaussSeidel approach
in which the values at the feedback input nodes are specified
at iteration (w 1) by using feedback values from x(w) as is
done for all variables in the GaussJacobi technique. All the
other nonfeedback variables are updated in the GS fashion.
So-called strongly connected component techniques (41) are
used to detect the inputs to the feedback loops, which are the

Figure 7. Chain of MOSFET inverters which is used to illustrate

different scheduling techniques.

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

GJ variables. An ordering for the resultant circuit in terms of

the SCkts is found by the leveling algorithm.
Leveling Algorithm.
Input: SCkt graph
Output: Assignment of Ckts to ordering levels
Function LevelizeSubCircuits
{
LevelNumber = 0;
Assign inputs to LevelNumber = 0;
REPEAT
FOR each SCkt s in LevelNumber {
FOR each SCkt k in fanout set for s {
NumberOfOrderedInputs =
NumberOfOrderedInputs + 1;
IF NumberOfOrderedInputs ==
NumberOfInputs
assign SCkt k to LevelNumber + 1;
}
}
LevelNumber = LevelNumber + 1;
UNTIL Level with LevelNumber is empty;
}
For scalar WR it is sufficient to order the SCkts in such a way
that the transient analysis of each SCkt in a lower level is
scheduled before the next higher-level SCkt is so that all the
input variables at iteration (w 1) are available before the
transient analysis for a SCkt is performed.
Definition 3. Scheduling means the scheduling for analysis
of a subcircuit according to the ordering until WR convergence is achieved.
Most existing WR-based circuit solvers use what is called
basic scheduling. However, other scheduling methods may be
more efficient than this approach. Here, we consider a simple
chain of ordered SCkts to illustrate the different techniques.
To make the example applicable to all scheduling techniques
of interest, we use a special circuit for which we can overlap
some of the nodes of any pair of SCkts. The overlap means
that a subset of nodes in a subcircuit may be shared between
two neighboring subcircuits. We take the chain of five inverters in Fig. 7 as a simplified example and order it from input
to output as is shown in Fig. 7:
1

For a basic schedule, the SCkts are analyzed according to the

ordering starting from the input, and a basic analysis schedule is given by
1
1
1

2
2
2

3
3
3

4
4
4

5
5
5

where we assume in this example that global convergence has

been reached in three WR iterations. If there are several time
windows in the analysis, we execute this schedule for each of

347

the windows separately. It is well known that the number of

WR iteration for convergence is very nonuniform for the different time windows due to the switching activities of the
transistors.
To properly explain the overlap scheduling technique, we
assume that each of the subcircuits has several nodes unlike
the very simple inverter chain in Fig. 7, which has only one
node per subcircuit. It is intuitively obvious that if we could
overlap or share some of the nodes of the neighboring SCkts
during the local WR iteration, then the convergence would be
enhanced at the cost of having to analyze the shared nodes
twice as many times at each iteration. Here we assume that
each SCkt now has three nodes instead of one. We still assume that we have a chain a five SCkts, where the labels of
the three internal nodes per SCkt are given as
11 12 13 21 22 23 31 32 33 41 42 43 51 52 53
It is evident that many different overlaps can be chosen in
this example even if only the boundary nodes are shared between subcircuits. To illustrate the fact that the overlap does
not even have to be symmetrical we give the following overlap example:
11 12
51
11 12
51

13 21
51 52
13 21
51 52

21 22 23 31 31 32 33 41 41 42 43
53
21 22 23 31 31 32 33 41 41 42 43
53

Specifically, we chose an overlap in which one node of the

next SCkt is taken into account while analyzing a SCkt. However, we assume that it is a waste of compute time to also
take the corresponding node from the previous subcircuit into
account. An example for symmetric overlap for subcircuit 2
would be 13 21 22 23 31. From this it is evident that the
number of nodes in each SCkt analysis can grow rapidly with
overlap scheduling. Hence, the reduced number of WR iterations must be balanced against the analysis of larger subcircuits. We observed experimentally that overlap scheduling
does not work well for circuits in which the coupling is sufficiently weak as is the case for an inverter chain. Its main
application is for situations in which the coupling is strong
for a large number of nodes such that large subcircuits result.
Overlap scheduling works well even if the circuits are very
strongly coupled. Hence, it is best applied to severe coupling
situations. Overlap scheduling has been applied in different
forms since the beginning of WR. The first paper applying
overlap scheduling was by Mokari-Bolhassan, Smart, and
Trick (42), and a thorough mathematical analysis and further
extension were given by Jeltsch and Pohl (43). For heterogeneous circuits overlap scheduling is especially applicable to
the situation in which the coupling is very strong such that
some very large subcircuits would result. In this situation,
the additional cost of the overlap is offset by other gains in
compute time.
Another important method with the potential to improve
the overall efficiency of WR is scheduling by Odeh, Ruehli,
and Carlin (44). To show how the method works we consider
the coupling in a matrix system rather than a system of differential equations. A typical form for the systems is
(L + E)x = b

(34)

348

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

where L is a lower triangular invertible matrix representing

strong forward coupling and E is a matrix with a sparse array
of small coupling terms of O() and zeros in all other locations.
For simplicity we assume that the small couplings in E can
be arranged in a vector, which we again call E (v1, v2, v3,
. . .) to retain meaning. For a given m we divide the vector
into two parts, E E1 E2, where E1 (v1, v2, v3, . . ., vm2)
and where E2 is the remainder of the vector. We need to note
that the feedback element vs corresponds to the variable
Xx1. With this we can see that if we ignore the feedback from
the variables xj, j m one simply has to set all elements in
E2 to zero. We denote by y the variables of the truncated system corresponding to Eq. (34); then the new system is
(L + E1 )y = b

(35)

We now can define the error vector e x y, which is due to

the truncation of the O() feedback variables. The following
will give an indication of how the errors propagate in both the
forward and backward directions.
Theorem 5. For a system of size N, the components of the
error e for the truncated system, Eq. (35), in comparison with
the fully coupled system, Eq. (34), is given by ek O(Nk) for
the backward direction 0 k m 1. The error in the forward direction is given by ek O() for k m.
The proof of this theorem is given in Ref. 14. It gives us a
clear indication of how the scheduling can be changed to improve global convergence. One key observation is that the errors decay rapidly in the back direction due to the backcoupling. This implies that a very good result can be obtained for
the present SCkt even if we have not analyzed all the SCkts
with a higher order. On the other hand, once an error has
been committed somewhere along the chain it will propagate
forward to all SCkts with a higher order until the error has
been corrected with further iterations.
We can utilize this result to come up with a scheduling
that we call scheduling, for now-obvious reasons. The
schedule is applied locally and it propagates forward, making sure that convergence is achieved locally after all the WR
iterations have been executed. For the inverter chain example
an schedule is given by
1 2
1 2 3
2 3 4
3 4 5
4 5
Techniques such as overlap scheduling and scheduling
clearly are more difficult to apply for complex circuits with
complicated fanout situations due to the complicated partitioned circuits and logical signal flow. We give results for an
inverter chain, which is the simplest circuit with which to
illustrate these concepts. We consider chains with 16, 32, and
64 inverters that are partitioned into SCkts where each SCkt
has two inverters. This partition was found to give the best

Table 1. Conventional Circuit Analysis vs. WR Analysis

Time (s)
Ckt
Name

No.
Trans.

Conventional

Basic
Sched. WR

-sched.
WR

Ch8
Ch16
Ch32

16
32
64

26
118
635

41
100
270

34
48
171

results in all cases. Table 1 compares a conventional circuit

analysis result with a basic and -schedule WR analysis.
These results give insight into the general behavior of the
solution gain for WR over conventional circuit simulation.
First we observe that very small circuits have little multirate
and matrix overhead, so one would expect the conventional
SPICE type solution to be faster than WR, which is indeed
the case. The other interesting comparison is between different scheduling algorithms for which the difference is a nonmonotonic function. We did not try to apply overlap scheduling to this since the coupling for the inverter chain is
moderate. It would not be a fair test for overlap scheduling,
which excels in strongly coupled situations, with a weakly
coupled example. Finally, we would like to point out that the
scheduling techniques can be combined. For example, overlap
and scheduling can be used for different parts of the same
circuit.
Global Convergence
With the techniques described previously we are ready to consider the difficult global convergence issues. The local convergence between two SCkts has been examined extensively earlier in the section entitled Internal WR Algorithms. Global
convergence deals with the interaction of thousands of SCkts
with different waveform interfaces. The gain or loss of efficiency due to the global algorithms can be considerable. A
single local waveform interface with poor partitioning can
slow down the convergence of a large circuit. The well-known
example is the one-way inverter chain for basic scheduling,
where the local feedback 0, with the exception of the
mth stage which has a feedback of . This may be SCkt m
3 in the example of Fig. 7. In this case, the best number of
WR iterations is given by one iteration up to circuit m 1
2. Then, the local iteration between SCkts 2 and 3 should be
iterated to convergence. Finally, all the circuits following
SCkt 3 again require only one iteration. It is evident that a
brute-force global analysis using a basic overall schedule
would be much more costly than an analysis with the best
possible global schedule outlined here.
The general situation for a subcircuit may be very challenging due to the potentially complex interconnections. A
SCkt m with its variables xm corresponding to Eq. (1) is represented with all the potentially connected variables corresponding to other subsystems as
m


(w+1)
(w)
(w) (w+1)
Cml (x1(w+1) , . . ., xm
, xm+1
, . . ., xM
)xl

l=1

M


(w+1)
(w)
(w) (w)
Cml (x1(w+1) , . . ., xm
, xm+1
, . . ., xM
)xl

l=m+1
(w+1)
(w)
(w)
f m (x1(w+1 , . . ., xm
, xm+1
, . . ., xM
, u) = 0

where the system is of size M.

(36)

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

The updating in this equation is of the GS type. It is clear

that the challenge is to partition a large circuit in such a way
that similar local convergence factors result for all the variables involved. A relatively uniform basic schedule can then
be used without large inefficiencies. This is complicated by
the presence of feedback loops. Feedback loops have been investigated by several researchers like Juan and Gear (45) and
Johnson and Ruehli (46). The work in Ref. 42 uses a theoretical model, while the work in Ref. 43 is based on numerical
experiments. Experimental evidence shows that tight feedback situations, which do not include many subcircuits inside
a feedback loop as they exist in flip-flop circuits, lead to a
much larger number of WR iterations than loops that involve
more SCkts. This is due to the instantaneous and highly nonlinear interactions of the SCkts in tight loops. More details on
this issue will be given later in the section entitled Parallel
Waveform-Relaxation-Based Circuit Simulation.
WINDOWING AND OTHER EFFICIENCY IMPROVEMENTS
Windowing
It was shown in the section entitled Fundamental WR Techniques that convergence is a function of the analysis time
interval. Specifically, the local convergence can be accelerated
by subdividing the total analysis time into a series of sequential unequal time windows. All subcircuits need to be solved
to convergence within a time window before moving on to the
next window. The time window needs to be as large as possible to allow the SCkts to operate with independent time steps
such that the multirate factor is maximized. In contrast to
this it has been observed in Theorem 4 that the larger the
nonlinearities or equivalently the Lipschitz constants K and
L, the smaller we must choose the window sizes T. Fortunately, the time step may also be several orders of magnitude
smaller during the high-gain nonlinear transition where K
and L are large such that the number of time steps per window is not drastically decreased during the highly nonlinear
transitions. Hence, we can still expect to obtain a reasonable
multirate factor.
Time-windowing algorithms have been suggested by several authors [e.g., (14,19,47)]. Peterson and Mattisson (47)
suggest a time-windowing scheme that initially creates windows whenever an input waveform changes state. Then as the
analysis proceeds, windows may be truncated based on the
convergence rate of the subcircuits and the number of accumulated time points. By limiting the number of time points
within a window, memory requirements can easily be managed and controlled.
In general, it is very hard to come up with heuristic windowing algorithms for heterogeneous circuits. The best window size is not only determined by the local convergence rate
but also by strong feedback loops such as a flip-flop or a ring
oscillator loop. Hence the dynamics of the local situation plays
a major role in the choice of the window size as we will illustrate later. We again use the same complementary MOS
(CMOS) inverter chain in Fig. 7 for the windowing examples
as we did for the partitioning and scheduling. We note from
the data in Table 2 that the best results are only weakly dependent on window size. The dependence is much stronger for
circuits with a complex fanout structure and for strong feedback situations such as a ring oscillator. In this case, the pe-

349

Table 2. Effects of Window Size

Ckt Name

No. Trans.

Analysis time
(ns)

Best Window
(ns)

Ch8
Ch16
Ch32

16
32
64

4.5
8
16

4.5
2
4

riod of the oscillator determines the best window size, as is

shown by Urahama and Kawane (33).
Latency
Efficiency improvements in the WR method have been pursued almost since its beginning. Waveform convergence may
be measured by different weighted norms based on or on
the 2 norm, which may lead to a more sensitive criterion.
This issue was first reported by Debefve, Hsieh, and Ruehli
(48).
Some of the additional convergence testing concepts lead
to considerable reduction in compute time. For a large circuit,
there usually exist some subcircuits that do not need to be
analyzed, because their surrounding subcircuits do not
change over a particular window in time T. This situation is
stated in the next paragraph in some detail.
For a given subcircuit SCkt, we call all the associated
waveforms x(t). They include the external waveforms xE(t) and
the internal waveforms xI(t), corresponding to nodal voltages
or current external or internal to the given subcircuit SCkt,
respectively.
Definition 4. A SCkt is said to be latent if
1. The SCkt has been analyzed at least once for the present time window T.
2. All external waveforms XE(t) associated with the SCkt
do not change between iterations (w) and (w 1) in the
present time window T. This change is measured by
comparing
xE(w) (t) xE(w1) (t) A + R max xE(w1) 
t[0,T ]

(37)

where A is the absolute waveform error and R is the

relative waveform error.
Then the subcircuit SCkt is declared latent and is not analyzed until either the inputs xE(t) change or the analysis
moves on to a new time window. Essentially, latency is the
limiting form of partial waveform convergence considered in
the next section. The application of latency can lead to an
appreciable improvement in overall solution efficiency. For
example, the solution of a 4-bit ALU with 282 FET transistors
analyzed on a small IBM RS/6000 workstation required 249
central processing unit (CPU) seconds without the above latency algorithm invoked, as compared with 101 CPU seconds
with the latency algorithm used.
Partial Waveform Convergence
This algorithm represents a more elaborate form of latency.
It was recognized that many waveforms were rejected toward

350

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

the end of the time window T due to the nonuniform convergence of the WR process. This nonuniform convergence was
considered earlier. The partial waveform convergence is given
by the following algorithm.
Definition 5. A SCkt is said to be partially converged or t
partially latent if
1. The SCkt has been analyzed at least once for the present time window T.
2. All waveforms xE(t) associated with the SCkt do not
change up to the time point t for (w) and (w 1). This
change is measured as
xE(w) (t) xE(w1) (t) A + R max xE(w1) 
t[0,t]

(38)

where A is the absolute waveform error and R is the

relative waveform error.
Then the subcircuit SCkt does not need to be re-solved over
the entire interval [0, T] for iteration (w 1), but only over
the shorter interval [t, T].The application of partial waveform
convergence can lead to an appreciable improvement in overall efficiency. For example, the solution of a clock-signal-generation circuit containing 1059 FETs run again on a small
IBM RS/6000 workstation required 2861 CPU seconds when
partial waveform convergence was not used, versus only 2430
CPU seconds using the partial waveform convergence just
mentioned.
Coupled and Preconditioned WR
The WR approach has the potential to be used in many different ways due to its iterative basis. Here, we consider two different important aspects on how a WR circuit solver can interact with other circuit solvers. Several circuit simulators
must cooperate together in a multilevel simulation environment. A higher-level simulator may have to be coupled to a
WR circuit solver. A multirate waveform interface (49,50) is
a very good way to couple tools together by exchanging waveforms during each time window. However, the coupled waveforms may have to be subjected to some processing such that
the waveforms fullfill the appropriate smoothness conditions.
The WR solver will supply the appropriate master time
windows.
Another approach has been proposed by Burrage (15) in
which the waveforms are preconditioned with some other
waveforms. Very good waveforms may be obtained from a
faster more approximate circuit simulator. We did some informal studies of the preconditioning process by distorting the
solution waveforms obtained from a WR solver. We discovered
two different regimes. Very rapid convergence to the exact
waveforms was observed, provided that the distortion was not
too large. For the case in which the distortion was large, the
starting waveforms seem to have little impact on the convergence behavior. It should be noted that many other situations
are relevant. For example, in a hierarchical situation as is
shown in Fig. 1 only a few waveforms need to be known at an
interface between the functional units to enable the analysis
of other functional units using existing waveforms for WR.

PARALLEL WAVEFORM-RELAXATION-BASED
CIRCUIT SIMULATION
Parallel implementations of WR have been investigated by
many researchers (47,5157) since the approach is ideally
suited for parallelization. Many of the techniques developed
for parallel WR are detailed in the book by Banerjee (58). Because each subcircuit is solved independently, subcircuits can
be distributed among multiple processors and solved concurrently. During every iteration, each processor must have access to the input waveforms for each subcircuit that it is to
solve. Once waveforms are available, a processor can then
solve a subcircuit over a time window T. Only after a subcircuit has been solved is there a need to share data among processors. This results in infrequent sharing of relatively large
blocks of data among processors. Generally the time to solve
each subcircuit is relatively long compared with the time
needed to communicate results among processors. This implies that the ratio of time for computation to communication
will be high, and good parallel speedups are possible. Moreover, as circuit size increases, the size of each subcircuit often
remains relatively constant, while the number of subcircuits
generally increases. Therefore as circuit size increases, the
opportunities for parallelism also increase.
Architecture Considerations
Parallel-processing machines can be grouped into two classes:
single-instruction, multiple-data (SIMD) and multiple-instruction, multiple-data (MIMD). In a SIMD machine, each
processor executes the same instructions on different data
streams. In a MIMD machine, each processor executes different instructions on different data streams. Parallel WR solves
different subcircuits on each processor, and therefore each
processor will in general be executing different instructions
on different data, which implies that parallel WR is best
suited for a MIMD architecture. Additionally, both SIMD and
MIMD machines can be implemented using either shared or
distributed memory. In a shared-memory machine, each processor is capable of accessing all memory in the machine. It
is usually the programmers responsibility to make sure no
two processors attempt to access the same memory locations
simultaneously. The Cray C-90
and SGI IRIS Challenger

are examples of shared memory MIMD machines. In a distributed memory machine, each processor has its own local
memory, which cannot be accessed by other processors. Sharing of data is accomplished through message passing between
processors. One form of distributed memory machine is a network of workstations using MPI to share data over a network.
The IBM SP2
, Intel Paragon
, and Cray T3D
are examples of more closely coupled distributed-memory MIMD machines. One advantage of distributed-memory machines is
that no single processor needs to have enough memory to hold
all of the data for analysis. This becomes increasingly important as circuit sizes increase. On the other hand, shared memory permits faster exchange of data among processors.
As stated above, a MIMD architecture is well suited for
WR where parallelism is applied at the subcircuit level with
each processor solving its own set of subcircuits. Either
shared or distributed memory can be used, each with its own
advantages and disadvantages. In a shared-memory environment, it is easier to balance work load among the processors,

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

because each processor has complete access to all data relative to the analysis. As each processor completes an analysis
of a subcircuit, it solves the next subcircuit that is ready to
be processed (51). In this way, slower processors will automatically take on less work, while faster processors will do more.
One associated disadvantage is that a relatively complicated
locking mechanism must be implemented to prohibit different
processors from trying to read and write the same data at the
same time. Another is that all input data and computed results must fit within the globally shared memory.
Distributed memory eliminates problems relating to simultaneous access of data and the need to have all data fit within
one global memory. However, because all data are not easily
accessible to all processors, it is harder to balance work load.
Most implementations statically assign subcircuits to processors at the beginning of an analysis using a combination
of heuristics to attempt to predict and balance work load and
communication patterns (56). Dynamic work load balancing
(59) requires the transfer of subcircuits and their state from
one processor to another, which may be several thousands of
bytes. If these transfers cannot be done quickly or they must
be done often, it may be faster to stay with a suboptimal subcircuit to processor assignment. In addition, performance may
be affected by the time required to share data among processors. Fortunately, windowed WR at the subcircuit level requires infrequent sharing of data among processors. Nevertheless, the time to communicate results may be a significant
portion of total job time. Consequently, most MIMD implementations attempt to minimize communication by assigning
subcircuits that share data to the same processor and to
hide communication overhead by overlapping communication and computation, that is, by continuing to compute additional results while communication is progressing. The underlying assumption is that parallel WR is applied to very large
circuits that partition into many subcircuits, and that there
are many more subcircuits than processors. Therefore, each
processor will generally have sufficient work to remain active
while data are being shared among processors.
Algorithm Selection
It was shown earlier that the GS relaxation algorithm will, in
general, converge in fewer iterations than the GJ algorithm,
and is usually the favored implementation for sequential processing. However, the faster convergence rate of the GS algorithm is derived from an ordering and scheduling of subcircuits that limits parallelism. Parallelism is limited by the
number of subcircuits that can be scheduled at each Seidel
level. Circuits that partition into long chains of subcircuits
with little fanout will have little parallelism to exploit,
whereas circuits like the DRAM error correction circuit shown
in Fig. 2 offer a great deal of potential parallelism. In contrast, parallelism using the GJ algorithm is limited only by
the number of subcircuits. With the GJ algorithm, during
waveform iteration (w 1) all subcircuits are solved using
input waveforms computed during iteration (w). Hence no ordering of subcircuits is necessary. This implies that once all
subcircuits have been solved for an iteration, all data are
available to schedule all subcircuits for the next iteration.
Consequently, the GJ algorithm has the potential for parallelism that is equal to and increases linearly with the number
of subcircuits.

351

Although the parallel GS method will retain a faster convergence rate over the GJ method (fewer iterations), because
of the limits on available parallelism, the time to complete
those iterations may actually be longer than the time to complete the GJ iterations. If the number of available processors
is large, the GJ algorithm will in general be able to use all of
them. The GS algorithm, on the other hand, will only be able
to use effectively a number of processors equal to the maximum number of subcircuits scheduled at any Seidel level.
Therefore, the GS algorithm is not necessarily the best algorithm for parallel processing. However, if the number of processors is smaller than the average number of subcircuits at
each Seidel level, then the GS method is probably the better
choice. In such cases parallelism will be limited by the number of processors, and the faster convergence rate of the GS
algorithm will result in a faster solution. In most applications
the number of processors is limited, whereas the number of
subcircuits and their relationship to one another is circuit dependent. The best implementation would be to include both
algorithms with automatic selection of the GS or GJ algorithms based upon circuit topology and the number of processors available to solve the problem.
Another implementation consideration is memory usage.
In order to determine convergence, at any iteration (w 1),
both GS and GJ algorithms require storage to hold computed
waveforms for iterations (w) and (w 1). For each subcircuit,
complete waveforms must be retained for all computed waveforms for two iterations. For a single processor, this implies
that all waveforms must be stored twice. However, on a multiprocessor system, each processor only needs to store iteration
(w) and (w 1) values for those waveforms that are actually
computed on that processor, along with waveforms for either
the (w) or (w 1) iteration of inputs solved on other processors. Input waveforms are needed for iteration (w) when using
the GJ algorithm and for iteration (w 1) when using the
GS algorithm. With the GS algorithm, newly computed waveforms can be shared with other processors immediately. However, unless each processor maintains storage for inputs for
both iterations (w 1) and (w), the GJ algorithm must delay
sharing newly computed waveforms among processors until
all processors have completed each waveform iteration. Otherwise, data for iteration (w 1) may overwrite data expected
to be for iteration (w). Consequently, the parallel GS method
can be implemented to use less storage per processor than the
GJ method. The alternative is to defer sharing of data until
all processors have completed an iteration. This can result in
communication bottlenecks and substantially reduce performance, especially for distributed-memory machines.
With the GS algorithm, data must be shared among processors throughout the analysis of a time window in order for
the solution to proceed. If input waveforms are not available
to solve a subcircuit, a processor may have to wait for data to
be computed on another processor. So not only does the GS
algorithm limit parallelism, it also may introduce bottlenecks
and adversely affect load balance among processors. In an attempt to reduce these effects, Zukowski and Johnson (60)
have reported implementation of a mixed SeidelJacobi or
bounded-chaotic algorithm that attempts to solve all subcircuits using the GS algorithm. However, if a processor is idled
due to lack of input waveforms for the current iteration, a
subcircuit is chosen to be solved using whatever waveforms
are available. Some inputs may be from the current, while

352

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

others may be from the previous iteration. The algorithm is

bounded in that waveforms can be at most one iteration behind the current iteration, like the Jacobi algorithm. The
hope is that a solution will be completed faster if processors
remain busy, even if all of the input waveforms do not meet
strict Seidel ordering. For circuits with large fanouts that permit the effective use of a large number of processors, this implementation retains the faster convergence rate of the GS
algorithm. For circuits with less fanout, this technique should
take no longer than the GJ algorithm in which all input waveforms are from the previous iteration.
Implementations
Parallel WR may be implemented using either a master
slave or a data-driven paradigm. In a masterslave implementation, one processor serves work to the others and synchronizes each iteration of the analysis. The masterslave
setup is well suited for a shared-memory machine, because
all data are available to all processors, and therefore the master can quickly assign any work item to any processor without
the need to transmit large quantities of data. In addition, the
master can maintain data integrity by only permitting one
processor to access a specific data item at a time.
In a data-driven implementation, each processor solves its
assigned subcircuits as soon as input waveforms are available. Synchronization is required only to determine convergence, update window boundaries, and prepare output files.
A data-driven implementation will function equally well on
either shared- or distributed-memory machines.
Efficiency Improvements
With either implementation, whenever input data are available to solve a subcircuit, the circuit can be scheduled for
analysis. In general, there will be many more subcircuits than
processors, and each processor will have more than one subcircuit that can be solved at any time. Under such conditions,
a choice must be made as to the order in which the subcircuits
are solved. When using the GJ algorithm, the choice is unimportant. However, when using the GS algorithm, this choice
may greatly affect overall performance and throughput. The
subcircuits for which data are available should be sorted and
solved in order based upon the level at which their outputs
are needed. For example, consider the situation in which a
processor has two subcircuits that can be solved. One has outputs that are needed as inputs to another subcircuit at level
4, while the other subcircuits outputs are not needed until
level 5. The subcircuit whose outputs are needed at level 4
should be solved first. This will permit the outputs to be communicated to other processors while the second subcircuit is
being solved. Hopefully the data will arrive before the second
processor finishes the subcircuits it is currently solving, and
the processor will not have to wait for data.
In the previous section Ordering and Scheduling, options
were discussed for dealing with feedback loops. However, the
choice of whether to break feedback loops into SCkts is different when using a multiprocessor system (46). One of the primary goals of parallel WR is to keep all of the processors busy
most of the time. Feedback loops that are merged into a single
subcircuit maintain strict GS ordering, but they create larger
subcircuits. This has a negative impact on load balancing,
matrix size, and the multirate speedup. However if feedback

Table 3. Timing Results

Time (s)
Ckt. Name

All Loops Cut

Only Long Loops Cut

Ckt1
Ckt2
Ckt3
Ckt4
Ckt5
Ckt6
Ckt7
Ckt8
Ckt9
Ckt10
Ckt11
Ckt12
Ckt13
Ckt14
Ckt15
Ckt16

28
33
46
90
103
106
113
142
155
159
195
226
229
537
477
1025

116
162
134
246
242
297
278
175
285
288
355
316
352
815
1111
1509

loops are cut such that two (or more) similarly sized subcircuits are created, these subcircuits can be distributed among
the processors. Since we expect cut feedback loops to result in
additional WR iterations, it is advantageous to iterate multiple times during each WR iteration among subcircuits resulting from cut feedback loops. Table 3 gives timing results
for 16 circuits ranging in size from under 300 to over 93,000
transistors when all feedback loops are cut versus only cutting long loops where the feedback loop extends over several
subcircuits. These results were obtained using the experimental Victor, V256 processor described in Ref. 56, with the larger
circuits using all 256 processors.
SUMMARY AND CONCLUSIONS
We summarize the state of the waveform-relaxation techniques in this article. WR is a very active area of research as
is evident from the publications listed here, which are only a
fraction of all the work done in this area. Also, there are many
more relevant works on WR that are of interest. To mention
just a few topics of interest, there are the faster sensitivity
computations by Chen and Feng (61) and the related error
measuring technique by Gristede, Zukowski, and Ruehli (62).
Other work of importance is hierarchical WR by Saviz and
Wing (35). We hope that it is evident from this article that
WR is an interesting area of research with potential for further innovations as well as applications.
The WR approach shows a clear speed advantage for very
large circuits over conventional circuit solvers. However, even
today a fast workstation is required to run circuits that are
large enough to show substantial gains. This may be of interest for a large company or to a university, but it is of a lesser
interest to the average user of a circuit solver like the many
SPICE-like tools that may run on a small machine. We expect
that the WR approach will become much more popular with
the next generation of high-performance workstations, which
include multiple processors at a more moderate price. As is
evident from this article, the gains in compute time will be
substantial. We expect that the availability of parallel computing for a wider audience will make the WR algorithms of
more interest to EDA companies.

CIRCUIT ANALYSIS COMPUTING BY WAVEFORM RELAXATION

BIBLIOGRAPHY
1. L. W. Nagel, SPICE2, a computer program to simulate semiconductor circuits, Memo UCB/ERL M520, University of California,
Berkeley, May 1975.
2. W. T. Weeks et al., Algorithms for ASTAPa network analysis
program, IEEE Trans. Circuit Theory, CT-20: 628634, 1973.
3. R. Saleh, S-J. Jou, and A. R. Newton, Mixed-mode simulation and
analog multi-level simulation, Norwell, MA: Kluwer, May 1994.
4. C. Visweswariah and R. A. Rohrer, Piecewise approximate circuit
simulation, IEEE Int. Conf. Comput.-Aided Design ICCAD, November 1989.
5. A. Devgan and R. A. Rohrer, Adaptively controlled explicit simulation, IEEE Trans. Comput.-Aided Des. ICs Syst., CAD-13: 746
762, 1994.
6. A. E. Ruehli, A. L. Sangiovanni-Vincentelli, and G. Rabbat, Time
analysis of larger scale circuits containing one-way macromodels,
IEEE Trans. Circuits Syst., CAS-29: 185191, 1982.
7. E. Lelarasmee, A. E. Ruehli, and A. L. Sangiovanni-Vincentelli,
The waveform relaxation method for the time-domain analysis of
large scale integrated circuits, IEEE Trans. Comput.-Aided Des.
Integr. Circuits Syst., CAD-1: 131145, 1982.
8. J. White and A. Sangiovanni-Vincentelli, Relax2: A Modified
Waveform Relaxation Approach to the Simulation of MOS Digital
Logic, IEEE Proc. Int. Symp. Circuits Syst., Newport Beach, CA,
1983.
9. J. F. Beetem et al., A large scale mosfet circuit analyzer based
on waveform relaxation, Conf. Comput. Des., 1984, pp. 507514.
10. U. Miekkala and O. Nevanlinna, Convergence of waveform relaxation method, IEEE Int. Conf. Circuits Syst., ISCAS-88, 1988,
pp. 16431646.
11. A. Lumsdaine and J. White, Accelerating waveform relaxation
methods with applications to parallel semiconductor device simulation, Numer. Funct. Anal. Optimiz., 16 (34): 395414, 1995.
12. S. Vandewalle and R. Piessens, Numerical experiments with nonlinear multigrid waveform relaxation on parallel processor, Appl.
Numer. Math., 8: 149161, 1991.
13. B. Leimkuhler, Estimating waveform relaxation convergence to
parallel semiconductor device simulation, SIAM J. Sci. Comput.,
14: 872889, 1993.
14. P. Debefve, F. Odeh, and A. Ruehli, in A. Ruehli (ed)., Circuit
Analysis, Simulation and Design, New York: Elsevier, North-Holland, 1987.
15. K. Burrage, Parallel and Sequential Methods for Ordinary Differential Equations, Oxford, UK: Oxford Science, 1995.
16. C.-W. Ho, A. Ruehli, and P. Brennan, The modified nodal approach to network analysis, IEEE Trans. Circuits Syst., CAS-22:
504509, 1975.
17. K. R. Schneider, A remark on the waveform relaxation method,
Int. J. Circuit Theory Appl., 19: 101104, 1991.
18. J. White et al., Waveform relaxation: Theory and practice, Trans.
Soc. Comput. Simulation, 2 (2): 95133, June 1985.
19. J. White and A. Sangiovanni-Vincetelli, Relaxation Techniques for
the Simulation of VLSI Circuits, Norwell, MA: Kluwer, 1987.
20. C. H. Carlin and A. Vachoux, How to Use Underrelaxation to
Improve Waveform Relaxation Convergence, Proc. Int. Conf. Comput.-Aided Des. ICCAD-87, November 1987.
21. U. Miekkala and O. Nevanlinna, Sets of convergence and stability regions, BIT, 27 (4): 554584, 1987.
22. M. Reichelt, J. White, and J. Allen, Waveform Relaxation for
Transient Two-Dimensional Simulation of MOS Devices, Proc.
Int. Conf. Comput.-Aided Des. ISCAS-89, November 1989, pp.
412415.

353

23. M. P. Desai and I. N. Hajj, On the convergence of block relaxation

methods for circuit simulation. IEEE Trans. Circuits Syst., 36:
948958, 1989.
24. G. D. Gristede, A. E. Ruehli, and C. A. Zukowski, Convergence
properties of waveform relaxation based circuit simulation methods, to appear in IEEE Trans. Circuits Syst. 45 (7): July, 1998.
25. U. Miekkala, O. Nevanlinna, and A. E. Ruehli, Convergence and
Circuit Partitioning Aspects for Waveform Relaxation, in D. W.
Walker and Q. F. Strout (eds.), Proc. 5th Distrib. Memory Comput.
Conf., Los Alamitos, CA: IEEE Comput. Soc. Press, 1990, pp.
605611.
26. B. Leimkuhler, U. Miekkala, and O. Nevanlinna, Waveform relaxation for linear RC circuits, Impact Comp. Sci. Eng., 3 (2):
123145, 1991.
27. A. E. Ruehli and C. A. Zukowski, Convergence of Waveform Relaxation for RC Circuits, in X. Odeh et al., Semiconductors Part
I-II), IMA Volumes in Mathematics and Its Applications, New
York: Springer, 1992.
28. B. Leimkuhler and A. Ruehli, Rapid convergence of waveform relaxation, Appl. Numer. Math., 11 (3): 211224, 1993.
29. C. W. Gear, Numerical Initial Value Problems in Ordinary Differential Equations, Englewood Cliffs, NJ: Prentice-Hall, 1971.
30. K. J in t Hout, On the convergence of waveform relaxation methods for stiff nonlinear ordinary differential equations, Appl.
Numer. Math., 18: 175190, 1995.
31. K. Taubert and W. Wiedl, Waveform relaxation und ein Storungssatz fur akkretive operatoren in der maximumnorm, ZAMM Z.
angew. Math. Mech., 73 (7/8): 925927, 1993.
32. W. M. B. van Bokhoven, An Activity Controlled Modified Waveform Relaxation Method, IEEE Proc. Int. Conf. Circuits Syst., ISCAS, 1983, pp. 765768.
33. K. Urahama and Y. Kawane, Circuit simulation using eventdriven waveform relaxation-Newton method. Trans. IEICE, 71
(1): 13, 1989.
34. D. J. Erdman and D. J. Rose, A Newton Waveform Relaxation
Algorithm for Circuit Simulation, Proc. Int. Conf. on Comput.Aided Des., November 1989, pp. 404407.
35. P. Saviz and O. Wing, Pyramida hierarchical waveform relaxation-based circuit simulation program, IEEE Int. Conf. Comput.Aided Des., 1988, pp. 442445.
36. C. H. Carlin and A. Vachoux, On Partitioning for Waveform Relaxation Time-Domain Analysis of VLSI Circuits, IEEE Proc. Int.
Symp. Circuits Syst. ISCAS, 1984, pp. 701705.
37. J. White and A. L. Sangiovanni-Vincentelli, Partitioning Algorithms and Parallel Implementations of Waveform Relaxation Algorithms for Circuit Simulation, IEEE Proc. Int. Symp. Circuits
Syst. ISCAS-85, 1985, pp. 10691072.
38. T. J. Cockerill, et al., Toggle: A Circuit Analyzer for MOSFET
VLSI, Proc. Int. Conf. VLSI and Comput. COMP-EURO87, Hamburg, Germany, May 1987.
39. W. John, W. Rissiek, and K. L. Paap, Circuit Partitioning for
Waveform Relaxation, Proc. Eur. Des. Automat. Conf. EDAC, The
Netherlands, February 1991, pp. 149151.
40. D. Dumlugol, J. Cockx, and H. DeMan, Segmented waveform
analysis for computation of accurate starting waveforms in circuit simulation, Tech. Report Katholieke Universitiet Leuven,
1984.
41. A. V. Aho, J. E. Hopcroft, and J. D. Ullman, Data Structures and
Algorithms, Reading, MA: Addison-Wesley, 1983.
42. M. E. Mokari-Bolhassan, D. Smart, and T. N. Trick, A New Robust Relaxation Technique for VLSI Circuit Simulation, IEEE
Proc. Int. Symp. Circuits Syst., ISCAS-85, November 1985.

354

CIRCUIT ANALYSIS COMPUTING OF SEMICONDUCTOR PACKAGES AND SYSTEMS

43. R. Jeltsch and B. Pohl, Waveform relaxation with overlapping systems, Report No. 91-02, Seminar fur Angewandte Mathematik,
ETH Zurich, 1991.
44. F. Odeh, A. Ruehli, and C. H. Carlin, Robustness Aspects of
an Adaptive Waveform Relaxation Scheme, IEEE Proc. Int.
Conf. Comput. Des., ICCD, Rye, NY, October 1983, pp.
396399.
45. F. L. Juan and C. W. Gear, Accuracy increase in waveform Gauss
Seidel, Comp. Sci. Dept. Report 1518, University of Illinois, Urbana-Champain, 1989.
46. T. A. Johnson and A. E. Ruehli, Parallel Waveform Relaxation of
Circuits with Global Feedback Loops, Proc. 1992 Des. Automat.
Conf., Anaheim, CA, June 1992, pp. 1215.
47. L. Peterson and S. Mattison, The design and implementation of a
concurrent circuit simulation program for multicomputers, IEEE
Trans. Comput.-Aided Des. Integr. Circuits Syst., 12: 1004
1014, 1993.
48. P. Debefve, H. Y. Hsieh, and A. E. Ruehli, Wave Convergence
Algorithms for the Waveform Relaxation Method, IEEE Proc. Int.
Conf. Comput. Aided Des., ICCAD, November 1984.
49. S. Skelboe, Stability properties of backward differentiation
multirate formulas, Appl. Numer. Math., 5: 151160, 1989.
50. M. Gunther and P. Rentrop, Partitioning and multirate strategies in latent multirate electric circuits, Int. Ser. Numer. Math.,
117: 3360, 1994.
51. D. Smart and T. Trick, Increasing Parallelism in Multiprocessor
Waveform Relaxation, Proc. Int. Conf. Comput.-Aided Des. ICCAD-87, November 1987, pp. 360363.
52. A. Sangiovanni-Vincentelli, Parallel Processing for Simulation of
VLSI Circuits, Amsterdam: Elsevier,1988.
53. S. Raman and L. M. Patnaik, HIRECS: Hypercube implementation of relaxation-based circuit simulation, Int. J. High Speed
Comput., 1 (3): 399432, 1989.
54. R. Saleh et al., Parallel circuit simulation on supercomputers,
Proc. IEEE, 77: 19151931, 1989.
55. P. Odent, L. Claesen, and H. DeMan, Acceleration of relaxationbased circuit simulation using a multiprocessor system, IEEE
Trans. Comput.-Aided Des., 9: 10631072, 1990.
56. T. A. Johnson, Waveform-relaxation-based circuit simulation on
the Victor V256 parallel processor, IBM J. Res. Devel., 35 (5):
707720, 1991.
57. A. D. Jalnapurkar, C. D. McCrosky, and H. C. Wood, Simulation
of MOS VLSI circuits using parallel processors, 1993 Wescanex,
1993, pp. 171176.
58. P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design,
Englewood Cliffs, NJ: Prentice-Hall, 1994.
59. L. Peterson and S. Mattisson, Dynamic Partitioning for Concurrent Waveform Relaxation Based Circuit Simulation, 1993 IEEE
Int. Symp. Circuits Syst., May 1993, pp. 16391642.
60. D. Zukowski and T. A. Johnson, Efficient Parallel Circuit Simulation Using Bounded-Chaotic Relaxation, 1992 IEEE Int. Symp.
Circuits Syst., May 1992, pp. 911914.
61. C.-J. Chen and W.-S. Feng, Transient Sensitivity Computations
of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Relaxation, Proc. 1994 Des. Automat.
Conf., San Diego, CA, June 1994, pp. 581585.
62. G. D. Gristede, C. A. Zukowski, and A. E. Ruehli, Measuring error propagation in waveform relaxation algorithms, IBM Res. Report, June 1997.

ALBERT E. RUEHLI
IBM Research Division

THOMAS A. JOHNSON
IBM Microelectronics Division

74

PERIODIC NONLINEAR CIRCUITS

PERIODIC NONLINEAR CIRCUITS

The steady-state analyses of nonlinear circuits are very important in the design of communication circuits such as amplifiers, oscillators, modulators, and so on. In the case of a
linear circuit driven by a periodic sinusoidal source, the circuit will eventually exhibit a periodic steady-state response
as a particular solution of the ordinary differential equation.
However, when the circuit is nonlinear and driven by a sinusoidal input, the steady-state waveform will contain many
higher harmonic components depending on the nonlinearities.
For the example of an RC amplifier, the circuit will behave
like a linear circuit for small sinusoidal input. When the input is increased, however, many higher harmonic components
will be contained in the output waveform because of the
strong nonlinearity. It is also known that the distortion of an
oscillator mainly depends on the choice of the dc operating
point.
Input signals of communication circuits usually contain
multiple frequency components, and modulators and mixers
are driven by multiple inputs whose output also contains
many frequencies by the linear combinations of the input signals. In these cases, if the input frequencies are related in
irrationally, the response is called a quasi-periodic solution
and does not have any period. Consider an amplitude modulator with two inputs, one of which is a high-frequency carrier
signal and the other a low-frequency input signal. Then, the
modulated response will behave as a quasi-periodic function
whose frequency spectrum is concentrated in the vicinity of
the carrier frequency.
Although the steady-state responses can be calculated by
the brute-force numerical integration technique (1), it requires considerable computation time (especially in weakly
damped circuits) since the transient term dies very slowly.
There are two basic approaches for calculating the periodic
steady-state responses, namely, the time-domain approach
(28) and the frequency-domain approach (912). The former
is based on the transient analysis, where the initial guess giving rise to the periodic steady-state response is first determined by the Newton method (25), whose Jacobian matrix
is estimated by transient analyses of the sensitivity circuit.
In this approach, the computational efficiency rapidly decreases for circuits having many state variables, which correspond to the inductor currents and capacitor voltages. Fortunately, in many practical circuits, some of the variables in the

sensitivity analyses are damped so fast that we can neglect

the effects without further computation (5). Extrapolation (6),
which predicts the initial guess from the sampled data of the
periodic points in the transient, is a very simple algorithm,
and has large convergence ratios for some kinds of circuits.
The computer algorithms (13,14) for calculating the quasiperiodic steady-state responses are much more complicated
when compared with those for finding periodic responses. The
former (13) finds the initial guess by the Newton method, and
the latter (14) is based on the Poincare map on the phase
plane. An amplitude modulator having a large carrier and a
sufficiently small signal can be calculated in two steps (15);
namely, first the response to the carrier is calculated by a
time-domain Newton method, and then that to the small signal can be calculated by solving the time-varying linear sensitivity circuit in the frequency domain. This method can also
be applied to noise analysis (16). Since all of the time-domain
methods are based on the transient analyses, they can be efficiently applied to circuits containing any kind of nonlinear
elements. In order to calculate the Jacobian matrix, we need
to solve the sensitivity circuit starting from different unit initial conditions, equal to the number of state variables. Therefore, this is rather time-consuming for large scale circuits containing many inductors and capacitors.
In the frequency-domain approach, the steady-state solutions are described by trigonometric-series representations,
and their coefficients are calculated by the method of balancing the responses between the linear and nonlinear subcircuits. For a linear circuit, the response can be easily calculated
by exploiting both the superposition theorem and the phasor
technique. However, in nonlinear circuits, the calculation of
the trigonometric-series coefficients is difficult compared to
the linear circuits, because superposition can no longer be applied. There are two basic methods based on the harmonic
balance method (9,10,17,18), and the relaxation method
(19,20). The harmonic balance method is efficient when the
number of nonlinear elements is relatively a few and the nonlinearities are not strong. For example, if we assume the
steady-state waveform contains a dc component and M frequency components for N nonlinear elements, there exist
N(2M 1) trigonometric coefficients to be determined. The
determining equation can be solved by the Newton method
(9,10) and/or the modified method (11). In particular, the
waveforms of circuits driven by multitone signals may have
many frequency components resulting from linear combinations of the input frequency components. Hence, when the
nonlinearities are strong, we must solve a system of large determining equations even for small circuits (21,22).
Conversely, relaxation methods (19,23) are very simple algorithms and are efficiently applied to large scale circuits if
they are partitioned into the linear subnetworks and the
small scale nonlinear subnetworks, where the variational values at each iteration can be calculated by the time-invariant
sensitive linear circuit. Although the algorithm is used for
weakly nonlinear circuits, it can be also efficiently applied to
the stiff circuits containing transistors and diodes if we introduce a compensatory technique (19) for weakening the nonlinearity.
At this point, we can conclude that the time-domain methods may be efficiently applied to small-scale circuits containing strong nonlinear elements. On the other hand, the fre-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

PERIODIC NONLINEAR CIRCUITS

quency-domain methods are useful for weakly nonlinear

circuits having few nonlinear elements.
Usually, large scale communication systems are composed
of many subsystems such as modulators, filters, and so on,
some of which may be classified into linear and nonlinear
subcircuits. Therefore, we recommend partitioning a given
large system into small-scale subcircuits and applying an appropriate algorithm to each subcircuit. The relaxation hybrid
harmonic balance method consists of different kinds of algorithms, where the linear and/or weakly nonlinear subcircuits
are solved by a frequency-domain approach and the strong
nonlinear subcircuits are solved by a time-domain approach
(20,23). Therefore, the large scale circuits can be efficiently
solved by the application of the circuit partitioning technique
and the relaxation hybrid harmonic balance method.

75

The schematic diagram is given in Fig. 1, where T denotes

the period. Now, apply the Newton method to Eq. (2).

1

F(x(0)) 
F(x j (0))
x(0) x(0)=x j (0)

j+1

(0) = x (0) =
j

(3)

The Jacobian matrix of Eq. (2) is given by

F(x(0))
x(T )
=1
x(0)
x(0)

(4)

Let (xj(t), yj(t)) be the solution at the jth iteration of Eq. (3).
To obtain the variational equation, set
x(t) = x j (t) + (t),

y(t) = y j (t) + (t)

(5)


(t)

f f f 
x=x j (t) = 0
x x y  y=y j
(t)

(6)

Then, we have from Eq. (1)

TIME-DOMAIN APPROACH

The transient responses of nonlinear circuits are uniquely decided once the initial guess x(0) of the state-variables is given.
Therefore, the steady-state response can be found if we can
find the solution satisfying x(0) x(T) 0. The equation is
efficiently solved by the Newton and extrapolation methods.
Forced Circuits
In the computer-aided analysis of nonlinear circuits with periodic inputs, the steady-state periodic response is found by
simply integrating the system equation from a given initial
point until the response becomes periodic, which is called a
brute-force method. In lightly damped systems, however, the
method requires much more computation time. In this section, the Newton algorithm (2) is shown which converges rapidly to the steady state.
Consider a set of the system equations
f(x,
x, y, t) = 0,

f() : Rn+m+1 Rn+m

(1)

where x is the state variable vector, y the nonstate variable vector. Then, the steady-state solution satisfies
the following determining equation:
n

f(x j , x j , y j , t) +

where it is assumed that f(xj, xj, yj,t) 0. Thus, we have

1 



f
f f
(t)

(t)
(7)
=
 x=x j
(t)

x y
y=y j x
We rewrite the first row of Eq. (7) into the following form:
(t) = A(t)(t)

Equation (8) is the linear time-varying system corresponding

to the sensitivity circuit. Let the fundamental matrix solution
be (t). Then, we have from Eq. (8)

(2)

(t) =  (t)(0)

(9)

x(T )
=  (T )
x(0)

(10)

which corresponds to

F(x(0)) = x(0) x(T ) = 0

(8)

In practice, the fundamental matrix solution (T) can be obtained by solving the time-varying sensitivity circuit from n
different unit initial values for the state-variables.
Example
Now, we show the efficiency of the shooting method for the
RC-amplifier shown in Fig. 2(a). A comparison between the
brute-force method and the shooting method are shown in
Fig. 2(b), where the transistor is modeled by the Ebers-Moll
model (24). We can calculate the steady-state response with
five iterations, where the error is defined by

x (t)

x (0)

x (T )

j =

(v (0) v
j
1

j
(T ))2
1

+ (v 2j (0) v 2j (T ))2 + (v 3j (0) v 3j (T ))2

Oscillator Circuits

Figure 1. Schematic diagram of steady-state periodic solution.

The steady-state periodic oscillation of an autonomous system

is usually calculated by the numerical integration technique
(1) from an initial state, which is also time-consuming for

76

PERIODIC NONLINEAR CIRCUITS

Eb
R7

R8

C1

C3

101

v3

102

T
R4
e

V1
R6

(11)

where x is the state variable vector and y the non-state variable vector. The period T is considered as a variable. It is
defined by the time difference between one of the state variables xk passing through the same value xk0 in the transient
response as shown in Fig. 3.
Thus, the steady-state response satisfies the following determining equation:
F(x(0), T ) = x(0) x(T ) = 0

(12)

Observe that since xk xk0 is fixed, the variables are given by

{x1 (0), . . ., xk1 (0), xk+1 (0), . . ., xn (0)}

C2
0

10
15
Iteration

(a)

lightly damped oscillators. Furthermore, there are many

kinds of coupled oscillators which have many modes oscillation (25), some of which may be stable and others unstable.
In this case, the orbits of unstable oscillations can never be
found by the numerical integration techniques. Now, we show
the time-domain shooting method for autonomous systems
that can be used to calculate both the stable and unstable
oscillations once the appropriate initial guesses are given.
Consider a system equation
f() : Rn+m Rn+m

v2

103
104

Figure 2. Steady-state response of the RC amplifier (a); C1

10 F, C2 50 F, C3 10 F, R4 2.2 k, R5 12 k; R6
1 k, R7 56 k, R8 10 k, R9 1 k, Eb 20 V; e(t) 0.1
sin 104t. (b) Convergence ratio.

f(x,
x, y) = 0,

Newton method

R9

+ R5

Transient response

(13)

The determining equation can also be solved by the Newton

method (3,4). We show an application of the algorithm for a
sample example of van der Pol oscillator.

(b)

Example
Consider an oscillator with a tunnel diode as shown in Fig. 4.
The system equation is given by

dvC
+ iL = 0
dt
di
L L vC = 0
dt

f (vC + E) + GvC +

f (vC + E) = 1 vC + 3 vC3 + I0 ,

(0)

t=0

Tj

(Tj)

t=Tj

xkj

(t)

The determining equation for calculating the steady-state oscillation is given by



 
 

F1 (vC (0), T )
v (0)
v (T )
= C
C
=0
F2 (vC (0), T )
iL (0)
iL (T )

(15)

Now, let us calculate the Jacobian matrix for the variables

(vc(0), T)

F1
v (0)
C

F2
vC (0)


F1 

t


F2 
t 

t=T

vC (t)
1 v (0)

C
=

iL (t)

vC (0)


vC (t) 

t


i (t) 
L

t

t=T

+
C vC

G
E

Figure 3. A definition T of an autonomous system.

(14b)

1 , 3 > 0

xkj

(14a)

where

iL

xkj

20

Figure 4. van der Pol oscillator.

PERIODIC NONLINEAR CIRCUITS

Now, apply the Newton method to Eq. (15).


 
v Cj+1 (0)
v Cj (0)
1
=

0
T j+1
Tj

77

Thus, the coefficient gk(0) can be solved as follows:



1
v Cj (0) v Cj (T j )
0
j
[J ]
i Lj (0) iL (T j )
0

g(0) =
1 X(T1 )

(21)

where

1
1
0

0
1
sin 2 T1

sin M2 T1
cos 2 T1

= 1
cos 22 T1
sin 22 T1

sin 2M2 T1

.....................................................
1 cos 2M2 T1 sin 2M2 T1 sin(2M)2 2 T1

g2,0 (0)

gn,0 (0)
g1,0 (0)

g2,1 (0)

gn,1 (0)
g (0)
g(0) = 1,1

. . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . ..
g1,2M (0) g2,2M (0) gn,2M (0)

j = 0, 1, 2, . . .
where

vC (t)
v (0)
C
Jj =
iL (t)
iL (0)


vC (t) 


dt


iL (t) 

t
t=T j

(16)

and using the relations

C

dvC
= iC ,
dt

x2 (0)

xn (0)
x1 (0)

x2 (T1 )

xn (T1 )
x (T )
X(T1 ) = 1 1

........................................
x1 (2MT1 ) x2 (2MT1 ) xn (2MT1 )

diL
= vL
dt

we have




1 
iL (t) 
1 
vC (t) 
i
v
=
,
=
L
t t=T j
C C t=T j
t t=T j
L t=T j

(17)

Thus, the first column of Eq. (16) is calculated by sensitivity

analysis starting from the initial state vC(0) 1, and the second column is equal to the transient response at the jth iteration. The iteration will be continued until the variation becomes sufficiently small.
Note that in the case of oscillators, the convergence ratios
of the time-domain method will usually be small compared
with those for the forced circuits. The slow convergence seems
to be due to the fact that although the period T is chosen as
a variable in the shooting algorithm, it has a different property from the state variables.

If x(t) is the steady-state solution of Eq. (18), it must satisfy

the following relation at t (2M 1)T1:

x((2M + 1)T1 ) = g0 (0) +

M

[g2k1 (0) cos(2M + 1)k2 T1

k=1

+ g2k (0) sin(2M + 1)k2 T1 ]

1 ]T
T2M+1
= X(T1 )T [

(22)

2M+1 = [1 cos((2M + 1)2 T1 ) sin((2M + 1)2 T1 )

cos(M(2M + 1)2 T1 ) sin(M(2M + 1)2 T1 )]

(23)

Thus, we have the determining equation for obtaining the

quasi-periodic steady-state response:

1 ]T
T2M+1 = 0
F(x(0)) = x((2M + 1)T1 ) X(T1 )T [

(24)

Quasi-Periodic Solutions
Now, consider a system with two input signals.
f(x,
x, y, 1 t, 2t) = 0

(18)

We assume that the ratio of 1 and 2 is an irrational number.

Then, the steady-state solution will be a quasi-periodic function, which can be described by 2-fold Fourier expansion as
follows:

x(t) = g0 (t) +

M

[g2k1 (t) cos k2t + g2k (t) sin k2t]

(19)

k=1

for a large M, where gk(t), k 0, 1, 2, . . ., 2M are period

functions of T1 2/1. Let us choose (2M 1) data at t
mT1, m 0, 1, 2, . . ., 2M time points. Then, the steady-state
solution satisfies the following relations:

x(mT1 ) = g0 (0) +

M

(g2k1 (0) cos mk2 T1

Now, we apply the Newton method to Eq. (24).

1 

F(x(0))

j+1
j
x
(0) = x (0)
F(x j (0))


x(0)
j
x=x (0)

j = 0, 1, 2, . . .

The Jacobian matrix is calculated by the fundamental matrix

solution (t) of the sensitivity circuit as follows:

F(x(0))
=  ((2M + 1)T1 )
x(0)

11 (kT1 ) 12 (kT1 ) . . . 1n (kT1 )

2M
(kT ) (kT ) . . . (kT )

1
22
1
2n
1
bk 21

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
k=0
n1 (kT1 ) n2 (kT1 ) . . . nn (kT1 )
(26)
where

k=1

+ g2k (0) sin mk2 T1 ) m = 0, 1, 2, . . ., 2M

(20)

(25)

[b0

b1

1 ]T
T2M+1
b2M ]T = [

78

PERIODIC NONLINEAR CIRCUITS

Extrapolation Method

Note that, to implement one iteration, we need to calculate

the transient response of Eq. (18) starting from xj(0), and n
times of the sensitivity analyses in the [0, (2M 1)T1] period.
The algorithm can be applied to the analysis of modulator
amplitude and FM modulator circuits.

Although the time-domain method mentioned above can be

applied to any kind of circuits, the efficiency will be decreased
when the number of state variables is increased, because we
need to solve the same number of sensitivity circuits as the
state variables.
In this section, we show a time-domain extrapolation
method (6) which only uses the transient response, without
the need for any sensitivity analysis. Namely, we calculate
x(T) by the numerical integration of Eq. (1) starting from
x(0). Thus, we have

Example
Consider the differential-pair amplitude modulator circuit
(26) shown in Fig. 5(a), where e1(t) and e2(t) denote the carrier
and signal input, respectively. The steady-state waveform is
shown in Fig. 5(b). The transistor is modeled by the EbersMoll model in the simulation.

x(T ) = P(x(0))

+VCC

(27)

+VCC

RL

C
+

T1

VO

T2

e1(t) +

T3
+

e2(t)

R1
VE
VCC
(a)

Vo

15.0

10.0

2T1

4T1

6T1

8T1

10T1

12T1

14T1

16T1

18T1

20T1

2T1

4T1

6T1

8T1

10T1

12T1

14T1

16T1

18T1

20T1

5.0

Veb

0.25

0.25
(b)
Figure 5. (a) Differential-pair amplitude modulator circuits; Vcc 10 V, VE 5 V, L 2 mH,
C 500 pF, RL 20 k; e1(t) 0.01 cos 106t and e2(t) 5.3 cos 0.115 106t, id 108(e40vd 1),
d 99. (b) Steady-state waveforms of v0 and veb of T1.

PERIODIC NONLINEAR CIRCUITS

where P( ) is called the Poincare map. Now, set x0(0)

x(0), x1(0) x(T), x2(0) x(2T), . . .. Then, we have the following contraction mapping:
x j+1 (0) = P(x j (0))

(28)

Observe that the contraction mapping is exactly the same as

the brute-force method. There are some acceleration techniques based on the extrapolation method. The -Algorithm
(6) is the simplest one as follows:
( j)
1
= 0,

k(n)

with undetermined coefficients (X0, X1, . . . , X2M1, X2M). Substituting Eq. (33) into Eq. (32), we consider the following
equation with the undetermined coefficients.

dxM
1
=
dt
T

(n1)
k1

j = 0, 1, 2, . . .

(n)
(n1)
+ 1/(k1
k1
)

k = 1, 2, . . .,

(29)

F0 () =

(30)

where we need to estimate the inverse of the vectors. The

Samelson inverse (27) is defined for a vector v
v

v v
= v /v
T

f(xM ( ), ) d

From Eq. (34), we have

Thus, the kth-order solution is given by

n 2k

n = k, k + 1, . . .

(n)
x k (0) = 2k
,

 T
M
1

+
cos kt
f(x)M( ), ) cos k d
2T k=1
0

 T
+ sin kt
f(xM ( ), ) sin k d
(34)

j = 0, 1, 2, . . .

0( j) = x j (0),

79

(31)

The extrapolation method is very easy to implement, and it is

efficient for the steady-state analysis of nonlinear circuits
with few reactive elements giving rise to slow decaying transients.

1
T

F2k1 () =

1
2T

F2k () =

1
2T

f(xM ( ), ) d = 0




(35a)

T
0

f(xM ( ), ) cos k d kX2k = 0

(35b)

f(xM ( ), ) sin k d + kX2k1 = 0

(35c)

T
0

k = 1, 2, . . ., M
where (X0, X1, . . ., X2M1, X2M). Suppose Eq. (35) has a
solution (X0, X1, . . ., X2M1, X2M). Then, the approximate
solution is given by

xM (t) = X0 +

M

( X2k1 cos kt + X2k sin kt)

(36)

k=0

FREQUENCY-DOMAIN APPROACH
The steady-state waveform of a nonlinear circuit can always
be described by a trigonometric polynomial. Each harmonic
component must respectively balance in the circuit equation.
Thus, if we consider the M frequency components plus the dc
component, we have a set of N(2M 1) algebraic equations
for N nonlinear elements. The equations can solved by the
Newton and/or the relaxation methods. Note that FFT (the
fast Fourier transformation) is often used for the Fourier
transformation in the frequency-domain approaches.

which is called the Galerkin approximation of order M, and

Eq. (35) is the determining equation of the Mth order Galerkin approximation. The existence of an exact isolated periodic
solution and the error bound is shown in Ref. 9.
Example
To understand the ideas of the harmonic balance method (10),
consider a simple LRC circuit with a nonlinear resistor as
shown in Fig. 6. Assume the characteristic of the nonlinear
resistor is given by

Harmonic Balance Method

The harmonic balance method is widely used in the frequencydomain approach of the steady-state analysis of nonlinear circuits. The ideas are based on the Galerkins procedure which
states that the periodic steady-state solution can be approximated by a finite number of trigonometric polynomial (9,17).
Now, consider a nonlinear periodic system
dx
= f(x, t)
dt

xM (t) = X0 +

k=0

(X2k1 cos kt + X2k sin kt)

(37)

and the input voltage sources given by

e(t) = Em cos(t + )

(32)

To determine the periodic solution of Eq. (32), we first take a

trigonometric polynomial
M

iG = G (v)

e(t)

C iL

(38)

iG

v(t)

(33)
Figure 6. Simple LRC circuit with a nonlinear resistor.

80

PERIODIC NONLINEAR CIRCUITS

Suppose the voltage at the nonlinear resistor is a trigonometric polynomial as follows:

v(t) = V0 +

M

(V2k1 cos kt + V2k sin kt)

where

JG,0,0 =

(39)

Then, the response of the linear subcircuit in the left-hand

side is easily calculated by the phasor technique
M

(IL,2k1 cos kt + IL,2k sin kt)

JG,2m1,2k

1
=
2T

JG,2m,2k1 =

(40)

k=1

JG,2m,2k

where

IL,1
IL,2k1

C(V2 + Em sin )
C(V1 + Em cos )
, IL,2 =
=
1 2 LC
1 2 LC
kCV2k1
kCV2k
, IL,2k =
=
1 (k)2 LC
1 (k)2 LC
k = 2, 3, . . ., M

On the other hand, the response of nonlinear resistor to v(t)

is described by a trigonometric polynomial as follows:

iG (t) = IG,0 +

M

(IG,2k1 cos kt + IG,2k sin kt)

(41)

k=1

The steady-state waveform needs to satisfy the following condition:

iL (t) + iG (t) = 0

IG,0 (V0 , V2 , . . ., V2M ) = 0

(42a)
(42b)

IL,2k (V2k1, V2k ) + IG,2k (V0 , V2 , . . ., V2M ) = 0

(42c)

j = 1, 2, 3, . . .
(43)

where V [V0, V1, . . ., V2M]T, IL(V) [IL,0, IL,1, . . ., IL,2M]T,

IG(V) [IG,0, IG,1, . . ., IG,2M]T, and JL diag[0, Y1(), Y2(2),
. . ., YM(M)] where

for yI (k) =

G
cos mt sin kt dt
v

G
sin mt cos kt dt
v

G
sin mt sin kt dt
v

(45)

m = 1, 2, . . ., M

Therefore, we must apply a total of (2M 1) times Fourier

expansions for getting the Jacobian matrix.
Note that the scale of the determining equations is
N(2M 1) for a circuit with N nonlinear elements. Hence,
the efficiency of the frequency-domain approach is rapidly decreased as the number of nonlinear elements increases and
their nonlinearities become strong.
Frequency-Domain Relaxation Method
To focus on the main idea of the frequency-domain relaxation
method, consider the circuit shown in Fig. 7(a), where NL denotes a linear subnetwork and G denotes a voltage-controlled
nonlinear resistor described by
(46)

Assuming the inputs have multiple frequencies 1, 2, . . .,

r, then the voltage across the nonlinear resistor can generally be assumed to have the form

v(t) = V0 +

M

(V2k1 cos k t + V2k sin k t)

(47)

k=1

It can be solved by the Newton Raphson method:


yI (k)
,
0

G
cos mt cos kt dt
v

k = 1, 2, . . ., M,

k = 1, 2, . . ., M

0
Yk (k) =
yI (k)

1
=
2T

iG = G (v)

IL,2k1 (V2k1, V2k ) + IG,2k1 (V0 , V2 , . . ., V2M ) = 0

1
2T

(42)

Thus, we have the following determining equations for each

frequency component:

V j+1 = V j [JL +JG (V j )]1 [IL (V j )+IG (F j )],

G
dt
v

T
0

1
JG,2m1,2k1 =
2T

k=1

iL (t) =

1
T

kC
1 (k)2 LC

On the other hand, the Jacobian matrix of the nonlinear resistor is given by

JG,0,1
JG,0,2M
JG,0,0
J
JG,1,1
JG,1,2M

JG G,1,0
(44)

.................................
JG,2M,0 JG,2M,1 JG,2M,2M

where
k = m1k 1 + m2k 2 + + mrk r

(48)

and the integers satisfy m1k B1, m2k B2, . . ., mrk Bk

for some sufficiently large B. Assuming that the original circuit in Fig. 7(a) has a unique steady-state solution described
by Eq. (47), then v(t) satisfies
F (v(t)) iL (t) + iG (t) = 0

(49)

where iL(t) and iG(t) denote the currents in the linear and nonlinear subnetworks in Fig. 7(b).
Let us calculate the steady-state solution using an iterational technique in the frequency-domain. Assume the solution at the jth iteration is given by

v j (t) = V 0j +

M


k=1

j
j
(V2k1
cos k t + V 2k
sin k t)

(50)

PERIODIC NONLINEAR CIRCUITS

iG

iL

e1 +

+
NL

iG

iL

e1 +

81

+
+

NL

v(t)

j(t)

j(t)

(a)

(b)

iG j+1

e1 +

+
NL

IGj

Goj

v j+1

NL

Goj

j(t)

j(t)

v(t)

(d)

(c)

Figure 7. Relaxation circuit: (a) Nonlinear circuit with a voltage-controlled resistor; (b) Partioning into a linear and a nonlinear subcircuit; (c) Approximation of the linear time-invariant equivalent circuit, where jj(t) G(vj) G0vj; (d) Sensitivity circuit.

To evaluate the solution at the ( j 1)th iteration, let

v j+1 (t) = v j (t) + v(t)

(51)

where

v(t) = V0 +

M

(V2k1 cos k t + V2k sin k t)

(52)

k=1

is some appropriate perturbation to be determined below.

Substituting vj1 from Eq. (51) into Eq. (49), and neglecting
the higher-order terms of v in the Taylor expansion of G(t),
we obtain for the weakly nonlinear system

F (v j + v) = L (v j + v) + S (e(t), j(t)) + G (v j + v)

L (v + v) + S (e(t), j(t)) + G (v ) + G (t) v
(53a)
j

L (v + v) + S (e(t), j(t)) + G (v ) +

j

G 0j

v
(53b)

where

G j (t)


M


G 
j
j
j
=
G
+
(G 2k1
cos k t + G 2k
sin k t)
0
v v=v j
k=1
(54)

The symbols L and S denote linear operators which transform the voltage v(t) and the sources (e(t), j(t)) respectively

into the time-domain responses of the linear subnetwork in

Fig. 7(b). Observe that since Eq. (53a) is a time-varying system, it is not easy to solve. Thus, we rewrite it as Eq. (53b),
where only G 0j is used instead of G j(t). It can be further written in the following form:
L (v) + G 0j v = L (v j ) S (e(t), j(t)) G (v j )

(55)

Observe that the convergence ratio will depend on the nonlinearity given by the difference G j(t) G 0j . Now, we define the
residual error current
 j (t) L (v j ) + S (e(t), j(t)) + G (v j )

(56)

Thus, we can obtain the equivalent circuits of Fig. 7(c) and (d)
from the relations Eq. (53b) and Eq. (55), respectively, where
j j (t) = G (v j ) G 0j v j
We call the circuits relaxation circuits, which can be easily
solved by the phasor technique for each frequency component.
The iteration will be continued until the variation satisfies
2M

|V kj V kj+1 | < 

(57)

k=0

for some prescribed small tolerance .

Remark: the frequency-domain relaxation method presented above can be efficiently applied to weakly nonlinear

82

PERIODIC NONLINEAR CIRCUITS

^
iG = iG(vG )

RC

i
+

vC

1
i = R vc
c

iG

i = f(v)

vG

v
Figure 8. Compensation technique: (a) Series compensation
by Rc; (b) a schematic diagram of weakening the nonlinearity.

(a)

circuits. However, many semiconductor devices such as diodes

and transistors are characterized by strong nonlinearities, so
that the convergence of our relaxation method may not be
guaranteed. In such cases, we recommend introducing compensation resistors Rc in series for the nonlinear subnetwork
and Rc for the linear subnetwork, which plays a very important role in weakening the nonlinearity, as shown in Fig. 8.

(b)

approximate periodic solution, and put

1 n1 , 2 n2 , . . ., r nr 
Then, the period is given by
T=

Hybrid Harmonic Balance Method

In the above section, we discussed a frequency-domain relaxation method, where each nonlinear element is replaced by
the time-invariant linear element with the associate source
at each iteration. Thus, every frequency component can be
calculated by the phasor technique. We propose here an efficient hybrid relaxation method based on both the time-domain
and the frequency-domain approaches (20,23). At the first
step, a given circuit is partitioned into subnetworks using
substitution sources (28), where one group N1 contains only
linear or weakly elements and the other N2 nonlinear elements, as shown in Fig. 9. From the computational efficiency,
we recommend to partition the circuit such that N1 contains
as many capacitors and inductors as possible, and N2 as many
resistive elements as possible. Thus, the steady-state responses of N1 are calculated by the frequency-domain method,
and those of N2 by a time-domain approach. If those two responses at the partitioning points have the same waveforms,
then the substitution sources give rise to a steady-state response. To understand the basic ideas behind the hybrid harmonic balance method, consider the simple circuit shown in
Fig. 9(a). Now, approximate the substitution voltage sources
in Fig. 9(b) as follows:

v(t) = V0 +

M

(V2k1 cos k t + V2k sin + kt)

(61)

2
;
n

n = GCM{n1 , n2 , . . ., r}

iN11
e(t)

(62)

iN21

+
v1(t)

N1

iN12

ip22

N2

+
v2(t)

j(t)

(a)

e(t)

iN11

iN21

v1(t)
iN12
ip22

N1

j(t)

N2

v2(t)
(b)

(58)

k=0

where v [v1, v2]T, V [V1, V2]T and k is equal to a linear

combination of the input frequencies 1, 2, . . ., r, namely
k m1k 1 + m2k 2 + + mrk r

(59)

where m1k, m2k, . . ., mrk are integers satisfying

|mik | Bk ,

i = 1, . . ., r;

k = 1, . . ., M

(v )

(vk)

(v )

(vk)

j
(t)
1

+
v1(t)
(v )
(v )

y211 k y212 k

j
(t)
2

y221 k y222
+
v2(t)

y111 k y112

(v )

y121 k y122

(vk)

(60)

Remark: if the relations among 1, 2, . . ., r are irrational,

v(t) in Eq. (58) will be a quasi-periodic function, and it is not
easy to solve the circuit. In this case, consider calculating an

(c)
Figure 9. Circuit partitioning: (a) A given circuit; (b) Partition into
two groups of N1 and N2; (c) The sensitivity circuit for calculating the
variation v1, v2.

PERIODIC NONLINEAR CIRCUITS

and the steady-state solution will satisfy the following determining equation:
F(v) = iN1 (v, e(t), j(t)) + iN2 (v) = 0

In order to determine the accuracy of the solution, we also

need to evaluate the residual error given by

(63)

j =

where F [F1, F2] , i [i1, i2] . Let us solve the steady-state

solution satisfying Eq. (63) by an iteration method, and assume the waveform at the jth iteration is expressed by
T

83

1
T

T
0

(iN1 (v j , e(t), j (t)) + iN2 (v j ))2 dt

|I2N1,k + I2N2,k |2

(71)

k=2M+1

v j (t) = V 0j +

M

j
j
(V 2k1
cos k t + V 2k
sin k t)

(64)

k=0

We first solve the subnetworks N1 with the frequency-domain

relaxation method. Of course, we can solve them by the phasor
technique if they are linear. The subnetworks N2 are solved
by some time-domain method. If the damping coefficient is
sufficiently large, we can solve it by the brute-force method.
Otherwise, we need to choose the Newton method (2) or the
extrapolation method (6). To calculate the solution at the ( j
1)th iteration, assume the solution
v j+1 (t) = v j (t) + v(t)

(65)

where v(t) is a variational voltage waveform described by

v(t) = V0 +

M

(V2k1 cos k t + V2k sin k t)

(66)

k=0

Substituting v j1(t) from Eq. (65) into Eq. (63), we obtain

F(v j + v) = iN1 (v j+1 , e(t), j(t)) + iN2 (v j+1 )

j
j
(v) + Y N2,0
(v) +  j (t) = 0
Y N1,0

Example

(67)

where the residual error j(t) is defined by

 j (t) iN1 (vv j , e (t), j (t)) + iN2 (v j )

=  0j +

M

j
(2k1
cos k t + sin k t)

(68)

k=0
j
j
(v) and YN2,0
(v) are the time-invariant linear operators
YN1,0
obtained from the sensitivity circuit at the jth iteration. Since
in many practical applications, the differences of the linear
operators in each iteration are small enough, we can approximate them with those at the zeroth iteration, which correspond to the incremental admittance matrices at the operating point. Thus, the variational values are calculated by

j
j
[ YN1,0 ( jk ) + YN2,0 ( jk )](V2k1 + jV2k ) =  2k1
+ j 2k

k = 1, 2, . . ., M
(69)
where Y is the complex conjugate. The iteration is continued
until the variation satisfies
V <
for a given small .

The hybrid harmonic balance method needs to apply the frequency-domain relaxation method to the weakly nonlinear
subnetworks N1, and the time-domain method to the nonlinear subnetworks N2 at each iteration. The variation v(t) can
be simply obtained by the use of the admittance matrices.
Therefore, the algorithm is very efficient compared with other
algorithms. The practical circuits are composed of many kinds
of subnetworks such as amplifiers, filters, multipliers and
pulse circuits, and so on. For example, consider a modulator
circuit composed of a multiplier, filter, and amplifier, where
the multiplier is only a nonlinear subnetwork, and the filter
and amplifier are the linear subnetworks for small signals
even if it contains nonlinear elements such as transistors. The
response of the linear subnetwork can be easily calculated by
the phasor technique such as the SPICE ac-analysis tool. Furthermore, it is sometimes possible to partition the circuits
into linear and nonlinear subnetworks such that the nonlinear subnetworks have large damping terms. In these cases,
we only need the time-domain analyses of the nonlinear subnetworks at each iteration. Thus, the algorithm (20) will become much more simple and efficient.

(70)

Consider a mixer circuit shown in Fig. 10. Let us partition

the circuit at (a, a) and (b, b). Then, the linear subnetworks
are only capacitors C1 and C2, and the rest is assumed to be
the nonlinear subnetwork. We used two periods of the bruteforce method for the time-domain analysis of the nonlinear
subnetwork. The convergence ratio is shown in Fig. 10(c), and
the frequency spectrum Fig. 10(b). Note that we obtained the
same result in 100 periods with the transient analysis of
SPICE. On the other hand, our hybrid method could calculate
the steady-state response in a total of 12 periods with the
time-domain brute-force method to the nonlinear subnetwork.

SMALL SIGNAL ANALYSIS METHOD FOR

PERIODIC NONLINEAR CIRCUITS
Among nonlinear circuits with multiple frequency excitations,
there is a significant class of circuits with two excitations
where one of the excitations is large and the other is small.
Frequency converters normally have two excitations; one is a
strong local oscillator (LO) signal, the other is a radio frequency (RF) signal. Modulators and switched capacitor filters
(SCFs) also belong to this class. Figure 11 shows a circuit
model of these circuits. Small signal responses for these circuits are one of the prime points of interest for circuit design.
This section describes numerically small signal analysis
methods for periodically operating nonlinear circuits with a
periodic large excitation.

84

PERIODIC NONLINEAR CIRCUITS

E1

Small
input

+
R1

Vout

R2

Tr2 Tr3

Linear Periodic Time-Varying Circuit

E2
e1 (t)
R3

E2

Figure 11. A circuit model.

Tr4

E2

Tr5

Output

Periodic excitation

Tr1

Nonlinear
circuit

Tr6

R4

E3

E3
C1
a1
e2(t)

C2
b1
R5

Small signal analyses for periodic nonlinear circuits can be

expected to be efficient if the circuits are modeled as the corresponding linear periodic time-varying (LPTV) circuits for
small signals as shown in Fig. 12. The LPTV circuit can be
obtained by applying the perturbation technique to the periodic steady-state solution of the nonlinear circuit without an
input signal (29).
Consider a nonlinear system with a periodic large excitation:

f(x(t), x(t))
= e(t)

(a)
102

(72)

where x(t) denotes the time derivative of x(t), and e(t) is a

large excitation of period T. The periodic large excitation
might be a clock signal for SCFs or an LO signal for mixer
circuits, for example.
It is assumed that the system represented by Eq. (72) has
a stable periodic solution xst(t) with period T for all t;

Frequency spectrum of v_out

V(V)

103

xst (t T ) = xst (t)

104

105
0.0

0.2

0.4

0.6
(GHz)

0.8

1.0

1.2

The steady-state periodic solution is computed using the

shooting method (2,5), harmonic balance method (10,11), or
simply using transient analysis.
Applying the perturbation technique to the periodic solution of the nonlinear system of Eq. (72), we have

g(t) x(t) + c(t) x(t)

= u(t)

(b)

(73)

where

u(t) = e(t)

101


f(t) 
x(t) x(t )=x (t )
st

f(t) 
c(t) =
x(t)
x (t )=x (t )

g(t) =

Variation

102

st

103

Equation (73) is an LPTV circuit as g(t) and c(t) are T-periodic.

104

105

Small
input

3
4
Iteration

Periodic
nonlinear
circuit

Output

(c)
Figure 10. (a) A mixer circuit R1 R2 100 , R3 R4 10 k,
C1 C2 10 nF, E1 5 V, E2 2.5 V, E3 12 V e1(t) 0.03 sin 2
0.11 109t, e2(t) 0.02 sin 2 0.1 109t. (b) Frequency spectrum
of output waveform; (c) Convergence ratio.

Small
input

Linear periodic
time-varying
(LPTV) circuit

Output

Figure 12. Modeling of a periodic nonlinear circuit by an LPTV

circuit.

PERIODIC NONLINEAR CIRCUITS

ej ot

e j t

H1( j )

H1( j )e

H0( j )

H0( j)e

H1( j )

H1( j)e

j( + o)t

j t

x(t)
j( + o )t

The periodic time-varying parameters are obtained during

numerical integration for one period of the periodic nonlinear
circuits. Fourier coefficients Hl() are calculated from LPTV
transfer functions at discrete times over one period.
Next, consider the calculation of LPTV transfer functions
at discrete times. Applying a unit complex sinusoidal signal
and evaluating Eq. (73) at t nT m, we have

gm x(nT + m ) + cm x(nT
+ m ) = ue j(nT + m )

e jot
Figure 13. Representation of a periodic time-varying transfer function by LTI filters and mixers.

The small signal response x(t) for Eq. (73) can be written
using the LPTV transfer function (30).
x(t) =

1
2

H( j, t)U( j)e jt d

where H( j, t) is the LPTV transfer function and U( j) is

the Fourier transform of the input signal. The transfer function is represented by a matrix whose dimension is the number of variables. For simplicity, we use one variable after this.
Assuming that a unit input signal is u(t) ejt, a steadystate response x(t) to u(t) becomes

gm +

cm
hm

J1
C
2

m=1

hm ,

m =

(76)

u
X1
X u


2

=



XP
JP
u

C1
J2

CP

(77)

where
Hl ()e

j(+l 0 )t

where o 2/T. The Fourier coefficients Hl() represent linear time-invariant (LTI) filters. Figure 13 shows a representation of an LPTV transfer function by LTI filters and mixers.
It can be considered that the first Fourier coefficient H0()
represents a transfer function without frequency translation,
while Hl() for l 0 represents transfer functions with frequency translation from to lo.
For example, H0() is used for the calculation of the baseband frequency characteristics of an SCF. H1() is used for
the calculation of conversion gain of an up-conversion mixer
circuit and H1() is used for down-conversion mixer circuits.
The Fourier coefficients Hl() of an LPTV transfer function
can be calculated by solving LPTV differential Eq. (73). There
are two major techniques. One is the frequency-domain
method using conversion matrices (3133) based on the harmonic balance technique. The other is the time-domain
method (16,34) using numerical integration. The time-domain
method is described briefly here.
In the time-domain method, an LPTV transfer functions at
discrete times, that is, H( j, m), m 1, 2, . . ., P, is calculated by using periodic time-varying parameters, where the
variable definitions are as follows:
P

cm
x(nT + m1 ) = ue j(nT + m )
hm
(75)

Substituting Eq. (76) into Eq. (75) gives

Xm = X(, m ) = H(, m )u
cm
cm
Jm = g m +
, Cm = e jh m
hm
hm

l=

T=

x(nT + m )

x(nT + m ) = H(, m )ue j(nT + m )

Expanding H(, t) into a Fourier series using the periodicity,

we have
x(t) =

The relationship between H(, m) and x(nT m) can be

written as

x(t) = H(, t)e jt

(74)

where gm g(nT m), cm c(nT m) and u is a vector

which indicates where the input signal is connected.
The differential Eq. (74) is numerically solved by applying
the backward Euler method to give

Transfer Function of LPTV Circuit

85

m


k=1

hk ,

p = T,

0 = 0

The discretization step hm is the numerical integration time

step in the transient analysis for the periodic steady-state response.
Examples
The first example is the eighth-order switched capacitor bandpass filter as shown is Fig. 14. This circuit was made by cascading a third-order elliptic low-pass filter with a cutoff frequency of 3.4 kHz and a fifth-order elliptic high-pass filter
with a cutoff frequency of 300 kHz. The sampling frequency
is 100 kHz. First, the steady-state response is computed for
the circuit with only clock excitation. Then, small signal frequency responses, that is H0(), are calculated. The small signal responses of this circuit are shown in Fig. 15. The parameters in Fig. 15 are the ON resistance values. The cross marks
show measured values. It is found that the high ON resistances of the switches cause attenuation in the lower stopband to deteriorate.
The second example is a direct conversion mixer circuit as
shown in Fig. 16. The local oscillator signal frequency is 280
MHz with an RF signal at 280 MHz plus several kilohertz.
The output frequency is several kilohertz. It is exceptionally
difficult to solve the steady-state response of this circuit by

86

PERIODIC NONLINEAR CIRCUITS

CH

C13

1
C12

In

C1

C11
C01

C32

C3

C2

Designed value (units)

C1 :6.23
C01 :7.04
C11A:1.00
C11B:1.00
C11T :6.00
C51 :6.48
C2 :28.02
C12 :33.50
C23 :37.26
C43 :1.00
C33 C4 :8.67
CD34:6.23
C34A:1.00
C34B:1.00
C34T :6.00
C5 :33.21
C45 :24.98

C21

2
1

C23

C31

Unit capacitor:0.2pF

C4

C1

C11B

C2

C01

C4

1
C45

C51

C34T
C34A

C9
C45

2
1

Out

CD34

C34 1

C12

C11A
C11T

C34

C34

Figure 14. Eighth-order switched capacitor bandpass filter.

the conventional transient analysis because of the large difference between the output frequency and the RF and LO signal frequencies. Here, an RF input signal can be considered
as a perturbation, because the circuit usually treats a small
RF input. First, the periodic response with the LO signal is
found. Then, the conversion gain from the RF input to the LF
output, i.e., H1(), is computed. Figure 17 shows conversion
gains and measured values for various levels of LO signal.

Measured

Gain (dB)

50k
10k

120
10

L

|Hl ( l0 )|2 s(
l0 )

(78)

l=L

30

90

This section describes noise analysis methods for periodic

nonlinear circuits modeled as linear periodic time-varying
(LPTV) circuits, such as mixer circuits, SCFs, and oscillators.
Assuming stationary noises, the output noise spectrum
density of an LPTV circuit is given by (16)

S() =

60

NOISE ANALYSIS METHODS FOR

PERIODIC NONLINEAR CIRCUITS

1k
100
ON resistance values

100

1k

10k

100k

Frequency (Hz)
Figure 15. Small signal responses of the eighth-order SC-BPF.

where s( lo) denotes a power spectral density of a certain

noise source, for example, s 4kTG for the thermal noise
source of a resistor R(G 1/R). Then, the noise current
source with an amplitude of 4kTG is connected in parallel
with the resistor. Hl( lo) indicates a Fourier coefficient of
an LPTV transfer function to the output from the noise
source. The Fourier coefficients can be calculated by using the
frequency-domain method (32,35) or the time-domain method
(16). H1( o) denotes up-conversion from o to and
H1( o) denotes down-conversion from o to . H0()
is not involved with any frequency translation. The power of
each Fourier component is summed up until l value of Eq.
(78) reaches L value specified by a user, or until its contribution become negligible. Figure 18 shows the noise power spectrum when the L value is 1. The total noise is calculated by
summing up power spectral densities from all noise sources.

PERIODIC NONLINEAR CIRCUITS

87

22k

0.1

LF

10k
22k
0.1

1.2k

1.2k
Vcc

1k

51k
940p

940p

LO

RF
470p
3.9k
100

1.1

Figure
circuit.

Conversion Gain (dB)

Simulation
Measured

20

15

15

LO level (dBm)
Figure 17. Conversion gain of the direct conversion mixer circuit.

( 0)

s( + 0)
s( )
s( 0)

mixer

Oscillator Noise

25

20
25

conversion

Noise analysis methods for LPTV circuits including cyclostationary noise sources have been described in previous
studies (16,34). Roychowdhury (35) discusses the frequencydomain method using the harmonic balance algorithm and
Okumura (16) presented a time-domain method.

35

30

16. Direct

H1( + 0)H *1( + 0)

S ()

H0( )H *0( )

H1( + 0)H *1( 0)

( 0)

Figure 18. Noise power spectrum of LPTV circuit.

Oscillators are also periodically operating nonlinear circuits,

though they have no external large excitation. The noise analysis method using the LPTV circuit model can be expanded
to autonomous systems (36).
Oscillator noise simulation is an important aspect of RF
circuit design. A model of oscillator phase noise spectra has
been proposed by Leeson (37). This model quantitatively
matches measured results. Phase and amplitude noises have
been analyzed using a simple oscillator model consisting of an
RLC resonator and a negative resistance (38). Using Kurokawas equation (38), phase and amplitude noises have been related to the resonators Q factor by Sweet (39). These results
are important for oscillators with resonators. However, oscillators without resonators, such as ring oscillators and multivibrators, cannot be evaluated by this method. Noise simulation methods using the LPTV circuit models for oscillators
with and without resonators are described in recent work
(36,40,41). In these methods, periodic steady-state solutions
of oscillators are calculated using the shooting method
(4,5,11), or the harmonic balance method (7,10,11). Output
noise spectral density of an oscillator modeled as an LPTV
circuit is also shown in Eq. (78). The Fourier coefficients in
Eq. (78) can be calculated by using the frequency-domain
method (31) or the time-domain method (36). If you use the
time-domain method, a loss-less integration method, e.g.,

88

PERIODIC NONLINEAR CIRCUITS

7.5V
2.2k 470p
R5
7.5k

470p

2.2k

Q2
Q1

Example
An example is a Wien bridge oscillator shown in Fig. 19. This
circuit oscillates at 141.655 kHz. Figure 20 shows the noise
spectral density of total noise and a line spectrum of the
steady-state oscillator output. Noise sources considered are
also thermal noise of resistors, shot noise, and flicker noise
of transistors. Flicker noise is approximated by a stationary
colored noise. The noise in this figure contains both amplitude
noise and phase noise. This realizes a situation similar to that
when the output is measured by a spectrum analyzer.

1.5k
R1

Step 3. Calculate Fourier components of LPTV transfer

function to the output from each noise source using the
LPTV parameters.
Step 4. Accumulate Fourier components with and without
frequency translation using Eq. (78).
Step 5. Compute total noise by summing up the power
spectral densities calculated in Step 4 from all noise
sources.

10

47u
R7
10

470

Figure 19. Wien bridge oscillator.

trapezoidal method, for numerical integration should be used

for oscillator simulation (36). It is clear that we have to take
into account down-converted noise as well as up-converted
noise from Eq. (78). For oscillators, it is well known that upconverted flicker noise dominates near the oscillation frequency. However, it was found that down-converted noises
may become dominant relative to noise near the oscillation
frequency for a hard oscillation circuit, e.g., multivibrator.
The noise analysis flow is as follows.
Step 1. Compute a periodic steady-state solution.
Step 2. Store LPTV parameters during the steady-state
analysis.

BIBLIOGRAPHY
1. L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronic
Circuits: Algorithms and Computational Techniques, Englewood
Cliffs, NJ: Prentice-Hall, 1975.
2. T. J. Aprille, Jr. and T. N. Trick, Steady-state analysis of nonlinear circuits with periodic input, Proc. IEEE, 60: 108114, 1972.
3. T. J. Aprille, Jr. and T. N. Trick, A computer algorithm to determine the steady-state response of nonlinear oscillators, IEEE
Trans. Circuit Theory, CT-19: 354360, 1972.
4. F. B. Grosz and T. N. Trick, Some modifications to Newtons
method for the determination of the steady-state response of nonlinear oscillatory circuits, IEEE Trans. Comput.-Aided Des., CAD1: 116119, 1982.
5. M. Kakizaki and T. Sugawara, A modified Newton method for
the steady-state analysis, IEEE Trans. Comput.-Aided Des., CAD4: 662667, 1985.
6. S. Skelboe, Computation of the periodic steady-state response of
nonlinear networks by extrapolation methods, IEEE Trans. Circuits Syst., CAS-27: 161175, 1980.
7. K. S. Kundert, J. K. White, and A. Sagiovanni-Vincentelli,
Steady-State Methods for Simulating Analog and Microwave Circuits, Boston: Kluwer Academic Publishers, 1990.

Output (VdB/ Hz)

Carrier spectrum

50

8. J. R. Parkhurst and L L. Ogborn, Determining the steady-state

output of nonlinear oscillatory circuits using multiple shooting,
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., CAD-14:
882889, 1995.
9. M. Urabe, Galerkins procedure for nonlinear periodic systems,
Arch. Ration. Mech. Anal., 20: 12152, 1965.
10. M. S. Nakhla and J. Vlach, A piecewise harmonic balance technique for determination of periodic response of nonlinear systems, IEEE Trans. Circuits Syst., CAS-23: 8591, 1976.

100

Noise spectrum
density

130k

140k

150k

Frequency (Hz)
Figure 20. Noise spectral density and carrier spectrum.

11. K. S. Kundert and A. Sangiovanni-Vincentelli, Simulation of nonlinear circuits in frequency domain, IEEE Trans. Comput.-Aided
Des. Integr. Circuits Syst., CAD-5: 521535, 1986.
12. H. Makino and H. Asai, Relaxation-based circuit simulation techniques in the frequency domain, IEICE Trans. Fundam., E76-A:
626630, 1993.
13. L. O. Chua and A. Ushida, Algorithms for computing almost periodic steady-state response of nonlinear systems to multiple input
frequencies, IEEE Trans. Circuits Syst., CAS-28: 953971, 1981.

PERMANENT MAGNETS
14. C. K. Petersen, Computation of quasi-periodic solutions of forced
dissipative systems, J. Comput. Phys., 58: 395408, 1985.
15. M. Okumura, T. Sugawara, and H. Tanimoto, An efficient small
signal frequency analysis method of nonlinear circuits with two
frequency excitations, IEEE Trans. Comput.-Aided Des. Integr.
Circuits Syst., CAD-9: 225235, 1990.
16. M. Okumura, H. Tanimoto, T. Itakura, and T. Sugawara, Numerical noise analysis for nonlinear circuits with a periodic large signal excitation including cyclostationary noise sources, IEEE
Trans. Circuits Syst., CAS-40: 581590, 1993.
17. Y. Shinohara, Galerkin method for autonomous differential equations, J. Math. Tokushima Univ., 15: 5385, 1981.

37. D. B. Leeson, A simple model of feedback oscillator noise spectrum, Proc. IEEE, 329330, 1966.
38. K. Kurokawa, Noise in synchronized oscillators, IEEE Trans. Microw. Theory Tech., MTT-16: 234240, 1968.
39. A. A. Sweet, A general analysis of noise in Gunn oscillators, Proc.
IEEE, 9991000, 1972.
40. F. X. Kaertner, Analysis of white and f noise in oscillators, Int.
J. Circuit Theory Appl., 18: 485519, 1990.
41. A. Demir and A. L. Sangiovanni-Vincenteli, Simulation and modeling of phase noise in open-loop oscillators, Proc. IEEE Custom
Integr. Circuits Conf., 1996.

18. A. Brambilla and D. DAmore, A filter-based technique for the

harmonic balance method, IEEE Trans. Circuits Syst. I, Fundam.
Theory Appl., CAS-43: 9298, 1996.

AKIO USHIDA

19. A. Ushida and L. O. Chua, Steady-state response of non-linear

circuits: A frequency-domain relaxation method, Int. J. Circuit
Theor. Appl., 17, 249269, 1989.

Toshiba Corporation

20. T. Sugimoto, Y. Nishio, and A. Ushida, SPICE oriented steadystate analysis of large scale circuits, IEICE Trans. Fundam., E79A: 15301537, 1996.
21. A. Ushida and L. O. Chua, Frequency-domain analysis of nonlinear circuits driven by multi-tone signals, IEEE Trans. Circuits
Syst., CAS-31: 766778, 1984.
22. K. S. Kundert, G. B. Sorkin, and A. Sangiovanni-Vincentelli,
Applying harmonic balance method to almost-periodic circuits,
IEEE Trans. Microw. Theory Tech., MTT-36: 366378, 1988.
23. A. Ushida, T. Adachi, and L. O. Chua, Steady-state analysis of
nonlinear circuits based on hybrid methods, IEEE Trans. Circuits
Syst. I, Fundam. Theory Appl., CAS-39: 649661, 1992.
24. J. J. Ebers and J. L. Moll, Large-signal behaviour of junction
transistors, Proc. IRE, 42: 17611772, 1954.
25. T. Endo and T. Ohta, Multimode oscillations in a coupled oscillator system with fifth nonlinear characteristics, IEEE Trans. Circuits Syst., CAS-27: 277283, 1980.
26. K. K. Clarke and D. T. Hess, Communication Circuits: Analysis
and Design, New York: McGraw-Hill, 1969.
27. P. Wynn, Acceleration techniques for iterated vector and matrix
problems, Math. Comput., 10: 301322, 1962.
28. L. O. Chua, Introduction to Nonlinear Network Theory, New York:
McGraw-Hill, 1969.
29. P. Penfield, Jr., Circuit theory of periodically driven nonlinear
systems, Proc. IEEE, 54: 266280, 1966.
30. L. A. Zadeh, Frequency analysis of variable networks, Proc. IRE,
32: 291299, 1950.
31. V. Rizzoli, C. Cecchetti, and A. Lipparini, Frequency conversion
in general nonlinear multiport devices, IEEE MTT-S Int. Microw.
Symp. Dig., pp. 483486, 1986.
32. V. Rizzoli and A. Neri, State of the art and present trends in
nonlinear microwave CAD techniques, IEEE Trans. Microw. Theory Tech., 36: 343365, 1988.
33. S. A. Maas, Nonlinear Microwave Circuits, Dedham, MA: Artech
House, 1998.
34. M. Kakizaki and T. Sugawara, An efficient numerical analysis
method for small signal frequency response from periodically operating circuits, Proc. IEEE Int. Symp. Circuits Syst., pp. 579
582, 1985.
35. J. S. Roychowdhury and P. Feldman, A new linear-time harmonic
balance algorithm for cyclostataionary noise analysis in RF circuits, Proc. Asia South Pac. Des. Auto. Conf., pp. 483492, 1997.
36. M. Okumura and H. Tanimoto, A time-domain method for numerical noise analysis of oscillators, Proc. Asia South Pac. Des.
Auto. Conf., pp. 477482, 1997.

89

Tokushima University

MAKIKO OKUMURA

PERIODIC STRUCTURES. See SLOW WAVE STRUCTURES.

INTERVAL ANALYSIS FOR CIRCUITS

673

in 1958 and the first monograph by Moore (2) was published

in 1966. Originating as a tool to control propagation of roundoff errors in computations on computers, interval analysis
presently covers a variety of problems in computational mathematics which are difficult to solve by traditional approaches.
The basic concept in classical mathematics is the concept
of a real number (a complex number can always, at least conceptually, be viewed as a pair of real numbers in a plane). In
contrast, the basic concept in interval analysis is that of an
interval. An interval is, geometrically, a bounded segment of
the real line. Interval analysis studies mathematical relationships between intervals. Intervals are also called interval
numbers. Interval numbers are generalizations of real numbers. Conversely, a real number can be viewed as a degenerate interval consisting of the real number itself. Similarly to
real numbers, intervals can be arguments of functions called
interval functions. The value of an interval function is an interval. One of the main objectives of interval analysis is to
study the properties of interval functions and to seek efficient
methods to evaluate them.
Various interval analysis methods have been developed for
solving numerous problems in linear and nonlinear mathematical analysis. In fact, nowadays an interval counterpart
exists for every significant problem and method encountered
in classical mathematics [interested readers may refer to references (25)]. These methods have a number of appealing
features (such as guaranteed accuracy, global convergence,
etc.) which makes them attractive for various applications in
science and engineering.

THE INTERVAL APPROACH

INTERVAL ANALYSIS FOR CIRCUITS

Interval analysis is a novel tool for investigating linear and
nonlinear lumped parameter circuits and systems. It is ideally suited to handle situations where the problem statement
involves uncertainties in the form of intervals. Interval analysis offers a variety of computer methods for solving such problems. The new methods have better performance than the traditional (noninterval) methods.
Presently, there are two conceptually different approaches
to investigating circuits and systems, the traditional approach and the interval approach. While the former is based
on models and methods using classical mathematics, the latter appeals to the concepts and computational techniques of a
branch of contemporary mathematics called interval analysis.
INTERVAL ANALYSIS
Interval analysis is a new and intensively developing area of
applied mathematics. The first paper (1) in the field appeared

The overwhelming majority of the mathematical models now

in use in circuit theory are based on the traditional approach.
This approach is quite natural and satisfactory if the initial
data about the electric circuit studied (parameters of passive
elements, of voltage or current sources, etc.) are known exactly. In this case, each item of the input data is represented
with reasonable accuracy as a real number. Because each real
number is viewed geometrically as a point on a real line, all
of the data related to the problem at hand is visualized as a
point in a space of appropriate dimensionality. Therefore, for
brevity of expression, a mathematical model based on such
an approach is termed [as in (6)] a point model. Although
intrinsically inaccurate, the point model is practically the best
model for tackling problems in which the uncertainty of input
data can be ignored. On the other hand, there are problems
where the uncertainty in the data is significant and cannot be
neglected. A typical example is the tolerance analysis problem
where one is interested in the range of the variations of an
output circuit characteristic (for instance, the variation of an
output voltage) resulting from the tolerances of the circuit parameters. In circuit theory, the basic approach to handling
such problems is to appeal to a probabilistic description of the
problem and to apply a certain statistical method to solve it.
This approach, however, is associated with the necessity to
determine experimentally some probability law describing the
probabilistic distribution of the input data. Another possibility is to resort to the theory of fuzzy sets. Once again, some
statistical information is needed to describe the fuzzyness
of the sets involved.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

674

INTERVAL ANALYSIS FOR CIRCUITS

An alternative for treating electric circuits with inaccurate

data is to apply the interval approach, that is, to employ the
concepts and methods of interval analysis. Because interval
analysis deals with intervals rather than points, it is ideally
suited for handling circuit problems where initial data are
allowed to take on values within some prescribed intervals. A
mathematical model based on the interval representation of
the input data is called, for brevity and in contrast to the
point model, an interval model. Furthermore, a method for
solving a particular applied problem which is based on an associated interval model and appeals to appropriate interval
analysis techniques is called an interval method. Interval
methods were introduced for the first time in the field of electrical circuits in the late seventies for tackling the tolerance
analysis problem [see (7,8)]. They have since been applied to
handling a number of problems arising in the domain of electric circuit analysis [see (68,11,12,1517)].

AREAS OF APPLICATION
At the present stage of their development, interval methods
have covered the following two major areas of application: (1)
robust analysis of linear circuits (and systems); (2) analysis
of nonlinear circuits with exact data. The former topic is characterized by uncertain parameters which take on values
within certain domains and most often these domains are
given as intervals. The objective of the analysis is to check
whether the circuit investigated is robust against the parameter variations, that is, to assess whether a certain output
characteristic of the circuit remains within prescribed bounds
for all possible variations of the uncertain parameters. More
specifically, interval methods have proved successful in solving the following robustness problems.
Tolerance Analysis
In this problem the output characteristic is typically the dc or
rms value of a voltage (current), and it is necessary to determine the voltage range under all admissible variations of the
parameters, that is to determine the tolerance on the output
characteristic given the tolerances on the input parameters.
Two statements of the tolerance problem are encountered: (1)
worst-case (deterministic) and (2) probabilistic statement.
In the former case, each parameter varies independently
from the rest within a given interval. Thus the tolerance on
the output variable accounts for the worst possible combinations of the admissible values of the input parameters.
In the latter case, the highly improbable combinations are
eliminated by introducing a suitable probabilistic law of distribution which takes into account the interdependence
among the parameter values.
Both tolerance problems are formulated as an associated
global optimization problem. The latter problem is solved by
various interval methods: zero-order method (using no derivatives of the functions involved), first- and second-order methods (using first- and second-order derivatives, respectively).
The worst-case tolerance problem is also formulated as a specific system of linear equations with independent or dependent interval coefficients. This mathematical model proves
more efficient than the global optimization formulation in the
case of electric circuits of increased size. Exact solution of the

dc tolerance problem and approximate solutions to the ac tolerance problem are thus derived.
Robust Stability
Now the objective of the analysis is to establish that the circuit investigated remains stable for all admissible independent parametric variations given as intervals. This basic
problem is extended to encompass various alternative formulations in which certain stability margins are introduced. Two
approaches to treating the robust stability problem are
known. According to the first, the stability of the circuit investigated is assessed by an associated characteristic polynomial
whose coefficients, in the general case, are nonlinear functions of the interval parameters. The second approach is associated with assessing the stability of a corresponding interval
matrix (a matrix whose elements are intervals). Extending
some known results on stability for exact data circuits, necessary and sufficient conditions and simpler sufficient conditions are thus obtained for checking the stability, instability,
or stability margin of linear circuits and systems with interval parameters.
Transient Analysis
This application area is concerned with transient analysis of
linear circuits with uncertain (interval) parameters. In fact,
the robust problem considered is a dynamic generalization of
the static, worst-case tolerance analysis problem. Unlike the
latter problem, the input interval data may, however, include
not only the circuit parameters, but also input exitations and
initial conditions. Each combination of these input parameters determines a corresponding output variable which is a
function of time. In the most general case, the objective of the
analysis is to verify whether the set of all output variable
functions related to the set of admissible input parameters
remains within a given preset funnel. Various special cases
are also possible. A well-known example is the problem where
the output variable should not exceed some prescribed threshold value (typically, the tolerated overshoot of the dynamic
system investigated) under all admissible parametric variations (therefore, in control engineering literature, the transient analysis problem is usually called the robust performance problem). A similar problem arises in setting relay
protections where the relay should not react to all responses
of the circuit protected caused by normal parametric variations but should do so under abnormal conditions. Once
again, determining the maximum value of the corresponding
circuit response under all possible parametric changes is of
paramount importance.
A basic assumption in solving the robust transient (performance) problem is the assumpton that the linear circuit investigated is robustly stable. This can be checked by an appropriate method for analyzing robust stability.
Various methods for exact or approximate solution of the
transient analysis problem have been proposed. In the simplest case, the relationship between the input parameters and
the output variable must be available in a closed explicit form
which is possible only for circuits of low complexity (circuits
whose transients are described by a differential equation of
first or second order). In this case, the transient analysis
problem is solved exactly. For circuits of higher complexity,
two alternative formulations have been suggested. The for-

INTERVAL ANALYSIS FOR CIRCUITS

mer formulation is in the frequency domain whereas the latter is in the time domain. Several methods for exact and approximate solutions have thus been developed.
Interval methods have also proved a reliable and efficient
tool for analyzing and simulating nonlinear circuits. For the
time being, they have mainly been applied to treating circuit
analysis problems with exact data.
Nonlinear Circuit Analysis
Nonlinear Resistive Circuits. Global analysis (locating all operating points) of nonlinear circuits is one of the most challenging nonlinear problems. The interval approach has made
possible the complete solution of the global analysis problem
relative to the class of nonlinear resistive circuits. This problem has two versions depending on whether the nonlinear resistors involved are modeled by piecewise-linear (PWL) functions or by continuously differentiable (CD) functions. The
traditional methods solve the former problem only in the case
where the resistive circuit equations are written in the socalled hybrid-representation form (9). Traditional methods do
not guarantee the location of all operating points for circuits
whose nonlinear elements are modeled by CD functions. In
contrast, existing interval methods find all operating points
infallibly within prescribed accuracy in the general case,
where the resistive circuit is described by a system of nonlinear equations of general form, and in the case of equations of
the hybrid form.
Nonlinear Dynamic Circuits. This class of circuits presents
a vast domain for interval analysis applications. Presently,
the interval approach has been employed to solve the following two problems. First, a global analysis problem of finding
all the periodic steady states of a given period arising in a
nonlinear electric circuit has been addressed. A method for
solving this problem in the case of circuits of low dimension
(described by nonlinear differentiable equations of up to second or third order) has been suggested. Second, the challenging problem of establishing the uniqueness of a periodic
steady state has also been considered. A new result has been
obtained for a special case of circuits for which the system of
nonlinear differential equations describing the circuit is of the
so-called separable form (6). A sufficient condition for uniqueness of the periodic steady state in this class of circuits is
suggested which reduces the original uniqueness problem to
that of checking the stability of an associated interval matrix.
The latter problem is efficiently solved by an approximate interval method.
VIRTUES AND DRAWBACKS OF THE INTERVAL APPROACH
Interval methods have a number of appealing features. One
of their fundamental virtues is that, unlike the traditional
methods where each computed output value is obtained as a
real number, they provide each output result as an interval.
The interval contains the result sought, thus guaranteeing
infallible bounds on the true value of the respective output
value. Using the so-called machine arithmetic, interval methods automatically account for roundoff errors when implemented by computer. For this reason they are often termed
self-validating methods. Interval methods are more reliable
than their noninterval counterparts. This is particularly true

675

for the class of iterative methods used to solve nonlinear problems. Interval iterative methods always converge globally in a
finite number of steps whereas their noninterval counterparts
sometimes do not. Also, natural stopping criteria exist for interval iterations. One simply iterates until the bounds are
sufficiently sharp (the resulting interval is narrow enough) or
no further reduction of the interval bounds is possible. The
latter occurs when rounding errors prevent further accuracy
improvement. Interval methods solve nonlinear problems
globally. Thus, these methods find all solutions of a set of nonlinear equations is a given rectangular region (a box). Similarly, they find the global optimum (s) of an (unconstrained
or constrained) optimization problem in a finite number of
steps with guaranteed accuracy. Using traditional (point)
methods, one faces the risk of terminating the computational
process prematurely before globality is reached or continuing
it uselessly in the hope of finding new solutions or better local
optima (long after globallity has actually been reached). Interval methods require shorter computational time in most of
the cases studied so far. However, the transcendent virtue of
the interval approach is that it solves problems which were
previously insoluble. For instance, before the use of interval
methods, it has been impossible to find with certainty all operating points in resistive nonlinear circuits described by CD
functions.
On the other hand, programming and using interval methods is presently less convenient than traditional methods. Indeed, all the interval operations involved in the method used
have to be programmed individually for every problem being
solved by the developer or user of the method. This lack of
convenience, however, is avoidable. High-level algorithmic
languages already exist (e.g., Pascal SC, Fortran SC, Ada,
C), which permit intervals to be declared as a special data
type. Special routines to do the interval arithmetic, however,
are also needed, as are codes to evaluate the elementary transcendental functions, etc. These facilities are presently available for only a few languages restricted to only a few computers. Good interval software for various applied problems is
often available. Portable codes are, however, comparatively
rare.
INTERVAL ARITHMETIC
Interval Numbers
Let a, b be real numbers and let X [a, b] denote a closed
bounded interval on the line of real number x, that is, a x
b, a b, and a, b . In interval analysis, such intervals
are called interval numbers, and the two terms interval
number and interval are used interchangeably. Thus, an
interval number X is a closed bounded compact set of real
numbers. To distinguish interval numbers from real numbers,
the former are designated most often by capital letters
whereas lower case letters are retained for real numbers.
Lower-case letters with superscript I are also employed to denote intervals explicitly whenever needed to avoid ambiguity.
Furthermore, if X is an interval, its lower (left) endpoint is
denoted by x or xL and its upper (right) endpoint by x or xR.
An interval can be regarded in two different ways, either as
a set of real numbers or an ordered pair of two real numbers
xL and xR. However, from a computational point of view, the
latter representation offers great advantages over the former

676

INTERVAL ANALYSIS FOR CIRCUITS

because it permits reducing operations with interval numbers

to operations involving only their endpoints, thus avoiding
the more cumbersome operations with sets.
An interval X is called degenerate if xL xR. The interval
number is a generalization of the real number. Indeed, in
terms of interval analysis, any real number x is considered a
degenerate interval x [x, x]. Two intervals X [a, b] and Y
[c, d] are equal if and only if (iff) their corresponding endpoints are equal, that is, X Y iff a c and b d. Intervals
are ordered in the following way: X Y iff b c. A useful
relationship for intervals is the set inclusion: X Y iff a c
and b d.
The width of an interval X is defined as the real number
w(X) b a. It is easily seen that w(X) w(Y) when X
Y. The midpoint (or center) of X is the real number m(X)
(a b)/2. Let r w(X)/2 and m m(X). An interval X is
defined either by specifying its endpoints a and b or, equivalently, in the form
X = m + [r, r] = [m r, m + r]

(1)

In interval analysis, the quantity r is called the radius of the

interval. In technical literature, r is termed tolerance and is
usually given in percents of the nominal value m(X).
Interval numbers are ordered as one-dimensional or twodimensional arrays to form interval vectors X (X1, . . ., Xn)
or interval matrices A Aij, i, j 1, . . ., n, respectively.
The relationships of equality (), inclusion () and ordering ( on ) introduced for interval numbers also remain valid
for interval vectors and interval matrices iff they are extended to all components. Thus, the notation X Y, where X
and Y are interval vectors, means that Xi Yi, i 1, . . ., n,
Xi and Yi being the components of X and Y, respectively. The
midpoint (center) m(X) of an interval vector X is defined by
the real vector m(X) (m(X1), . . ., m(Xn)). The width of X,
however, is given by the real number w(X) maxw(Xi), i
1, . . ., n.
Interval Arithmetic Operations
Let , , , / denote the operations of addition, subtraction,
multiplication and division, respectively, over real numbers.
Furthermore, let denote any one of these operations for the
real numbers x and y. Then the corresponding operation for
the interval numbers X and Y is defined as the set
X Y = {x y:

x X,

y Y}

(2)

Thus, the set X Y resulting from the operation considered

contains every possible number which can be formed as x y
for each x X and each y Y. A fundamental requirement
for X Y is to be an interval, that is the set X Y must be a
bounded set. This is always true for the first three operations.
Then the definition given by Eq. (2) produces the following
rules for generating the endpoints of X Y from the endpoints
of the two intervals X [a, b] and Y [c, d]:

X + Y = [a + c, b + d]
X Y = [a d, b c]

(3)

X Y = [min(ac, ad, bc, bd), max(ac, ad, bc, bd)]

The endpoints of the product are computed in a less expensive
way if the signs of the endpoints of X and Y are taken into

account [see (26)]. For brevity, the dot in the notation of the
product is often dropped. The operation of division is possible
only if Y is an interval not containing zero. In this case
1/Y = [1/d, 1/c] (0
/ Y ),

X /Y = X (1/Y ) (0
/ Y)

(4)

The restriction 0 Y is removed if the so-called extended

interval arithmetic [suggested by Hansen (5)] is used where
intervals are unbounded.
Properties of Interval Arithmetic
If X and Y are degenerate intervals, then Eqs. (3), (4) reduce
to the ordinary arithmetic operations over real numbers.
Thus, interval arithmetic is a generalization of real arithmetic. Therefore, it is normal to expect that the properties of
interval arithmetic are similar to those of real arithmetic,
which is really the case. However, there are several striking
dissimilarities that are stressed here. It is important to
underline that, unlike real arithmetic, X X 0 and X/X
1 when w(X) 0. Indeed, X X w(X)[1, 1] and X/X
[a/b, b/a] for X 0 or X/X [b/a, a/b] for X 0. Another
interesting property of interval arithmetic is the fact that the
distributive law
X (Y + Z) = XY + X Z

(5)

does not always hold. For example, [0, 1](1 1) 0 whereas

[0, 1] [0, 1] [1, 1]. We do, however, always have the
following inclusion:
X (Y + Z) XY + X Z

(6)

The property given by Eq. (6) is called subdistributivity. It

is to be stressed that, as seen from Eq. (6) and the previous
example, w(X(Y Z)) w(XY XZ). Therefore, it is always
advantageous to use the factored form X(Y Z) rather than
the expression XY XZ because the former form leads, in
general, to a narrower resultant interval. It is proved that Eq.
(5) remains true in several special cases [see (26)].
Another important property of interval arithmetic is inclusion monotonicity. It means that, if X Z, Y W, then X
Y Z W, X Y Z W, XY ZW, X/Y Z/W (if 0
W in the division formula). Inclusion monotonicity follows directly from the definitions of the interval arithmetic operations.
The arithmetic operations defined by Eqs. (3) and (4) are
called exact interval arithmetic operations. However, when
implementing these operations on a computer, we commit errors because of round-off. Therefore, we have to take special
measures so that the machine-computed interval result always contains the exact interval result. When computing with
interval arithmetic, if a left endpoint is not machine representable it is rounded to the nearest arithmetically smaller
machine number. A right endpoint is rounded to the nearest
arithmetically larger machine number. This is termed outward rounding. In what follows, various interval methods are
presented. For simplicity, only exact interval arithmetic is
used although the actual computer implementation of these
methods, naturally, require machine interval arithmetic.

INTERVAL ANALYSIS FOR CIRCUITS

INTERVAL FUNCTIONS
An interval function is an interval-valued function of one or
more interval arguments. The interval function F of interval
variables X1, . . ., Xn is denoted F(X1, . . ., Xn), and F transforms the set of intervals X1, . . ., Xn into the interval function
value Y, that is, Y F(X1, . . ., Xn). An interval function is
said to be inclusion monotonic if Xi Yi, i 1, . . . n, implies
F(X1, . . ., Xn) F(Y1, . . . Yn). It follows from Eq. (2) that interval arithmetic is inclusion monotonic, that is, if Xi Yi,
i 1, 2, then, (X1 X2) (Y1 Y2). The inclusion monotonicity
is a property often used in interval computations.
Interval Extensions
Interval functions are engendered by real functions. The corresponding interval function is called an interval extension of
the real function. More specifically, if F(X1, . . . Xn) is an interval extension of f(x1, . . . xn), then F reduces to f when all
arguments Xi become real variables, that is, F(x1, . . ., xn)
f(x1, . . ., xn). Consider, for example, a rational real function
of real variables (a function whose value is defined by a finite
sequence of real arithmetic operations over its arguments).
We obtain an interval rational function F engendered by the
real function f if we replace the real variables in f by corresponding intervals and the real arithmetic operations by their
interval counterparts. The resulting interval function F is
termed a natural interval extension of f. Similarly, we obtain
natural interval extensions of any real functions (containing
irrational terms).
It should be stressed that different expressions of one and
the same real function give rise to different interval extensions. For example, let f(x) x(1 x) x x x. The natural
extension for the first expression f(x) f 1(x) x(1 x) is
F1(X) X(1 X) whereas, for the second expression f(x)
f 2(x) x x x, the corresponding natural extension is
F2(X) X X X. Now, if we compute F1(X) and F2(X) for
X [0, 1], F1([0, 1]) [0, 1] whereas F2([0, 1]) [1, 1]. Obviously, F1(X) F2(X). Moreover F1(X) F2(X). This example
shows that, for polynomials, the nested form A0 X[A1
X(A2 . . . XAn) . . .] is never worse and is usually better
than the sum of powers A0 A1X A2XX . . . because of
subdistributivity. Henceforth, whenever we refer to the natural interval extension of a real function, we shall assume that
an expression of the function has already been chosen.
Mean-Value Form
The mean-value form is a particular form of interval extension applicable to any function f(x1, . . . xn) with continuous
first derivatives. Let X (X1, . . ., Xn) denote an interval vector, and let m m(X) be its center. By the mean-value theorem, for any y X,

f (y) = f (m) +

n


f
( )(y j m j ),
x j
j=1

FMV (X ) = f (m) +

n


j=1

Fj (X )(X j m j )

is called the mean-value form extension of f on X. The meanvalue form is inclusion monotonic if the functions F j(X), j
1, . . . n, are inclusion monotonic.
Range
The set of real points (i.e., vectors) x belonging to an interval
vector X with components Xi, i 1, . . ., n, form an n-dimensional parallelepiped with sides parallel to the coordinate
axes. This is why an interval vector is often referred to as a
box. Another important concept closely related to the interval
extension of a real function is the range of the function over
a box. The range f(X) of f over X is an interval defined by the
set f(X) f(x): x X. Obviously, the range is the union of
all function values f(x) for all x from X. Enclosing the range
of a multivariate function by an interval is a fundamental
problem encountered in numerous applications. It is a standard problem in the field of robustness analysis. It is proved
that
f (X ) F (X )

(7)

(8)

where F(X) is an inclusion monotonic interval extension of

f(x). Consider the following example. Let f(x) x(1 x). The
range of f(x) over X [0, 1] is easily computed to be
f([0, 1]) [0, 0.25]. From the previous example, F([0, 1])
F1([0, 1]) [0, 1]. Thus, f([0, 1]) F([0, 1]).
The inclusion in Eq. (8) is one of the basic results of interval analysis. We find infallible bounds on the range of f(x)
over X by just computing the interval extension F(X). However, the bounds thus found, typically, are not very sharp,
especially when the box X is fairly large. One of the central
problems in interval analysis is finding a good estimate of
f(X) with a reasonable amount of computation. In two special
cases, the range is found in a straightforward way [see (25):
1. The function f is a monotonic (in the classical sense)
function of one variable for x X [a, b]. For monotonically increasing functions, such as x, exp x, log x etc.,
f(X) [f(a), f(b)]. For a monotonically decreasing function, f(X) [f(b), f(a)].
2. The function f is a multivariate function such that each
variable xi occurs not more than once and to the first
power. Then f(X) is found directly by computing F(X)
only once (provided no division by an interval containing zero occurs) because F(X) f(X) in this case.
Excess
In general, the interval extension is a wider interval than the
range. To measure the closeness of F(X) to f(X), we use the
so-called excess E[F(X)] w[F(X)] w[f(X)]. Let d w(X). It
has been proved that, if F(X) is a natural interval extension
of a function f, then
E[F (X )] = 0(d)

If F j(X) denotes the (natural) interval extension of f /xj(x)

for x(x1, . . ., xn) X, then the interval function

677

(9)

(the above symbol means that E becomes proportional to d as

d tends to zero). If the mean-value form FMV(X) is used as the
interval extension of f, then
E[FMV (X )] = 0(d 2 )

(10)

678

INTERVAL ANALYSIS FOR CIRCUITS

(in this case E is second order in d). It should be noted that

Eqs. (9) and (10) are asymptotic. They are useful expressions
only when d is small. For large width d of the box X
(X1, . . ., Xn) and large number n of interval arguments Xi,
the excess is significant. This is a drawback of the interval
analysis approach which is referred to as overestimation.
Nowadays, there are a number of methods to reduce the excess. However, they usually involve numerous evaluations of
F(X(v)) for different subregions X(v) of X and sometimes are prohibitively expensive.
INTERVAL METHODS FOR LINEAR EQUATIONS
Consider the system of linear equations
Ax = b

(11)

where A and b is a real (n n) matrix and a real vector, respectively. In many applications (tolerance analysis is a typical example), the elements of A and/or the components of b
are not precisely known. If we know an interval matrix AI
bounding A and an interval vector B bounding b, we can replace the system in Eq. (11) by the family of linear systems
Ax = b,

A AI ,

bB

(12)

For brevity, Eq. (12) is written in the form

AI x = B

(13)

In what follows, we assume that AI is a regular matrix. AI is

regular if each A AI is nonsingular. The solution set of Eq.
(13) is the set
S = {x:

x=A

b,

AA,
I

b B}

This set has a very complicated shape and therefore is impractical to use. Instead, it is common practice to settle for an
interval vector X which contains S. In some cases we would,
that still
however, like to find the narrowest interval vector X
contains S. The vector X is called the interval solution of Eq.
is called the optimal solution. Figure 1 shows
(13) whereas X
for the case
a set S and the corresponding optimal solution X

where n 2. It should be stressed that X (and moreover X)

is not a solution in the classical sense. Indeed, if we replace x

in Eq. (13) and perform the interval multiplications and
by X
, in general, is
additions, the resulting interval vector Y AIX
not equal to B.
Interval Solution
A variety of methods exist for solving Eq. (13). Only three
such methods are considered here.
Gaussian Elimination. There are several variants of a
method for solving linear equations with exact data which are
labelled Gaussian elimination. An interval version of any one
of them is obtained from a standard one (using ordinary real
arithmetic) by simply replacing each ordinary arithmetic step
by the corresponding interval arithmetic step. If the coefficient matrix A and the right-hand side b are real (noninterval), then the interval version of Gaussian elimination simply
bounds rounding errors. If the elements of the coefficient matrix and the right-hand side vector are intervals, then the solution vector X bounds the solution set S. Unfortunately, the
bounds tend to widen rapidly because of accumulated overestimation at each step of the method. Thus, the solution obtained is generally far from sharp.
Preconditioning. To improve the performance of the
Gaussian elimination, a technique suggested by Hansen (5),
called preconditioning, is often used. The improvement is substantial for relatively small widths of AI and B. Let Ac denote
the center of AI. First we compute (using, for example, real
Gaussian elimination) an approximate inverse L of Ac. Then
we multiply both sides of Eq. (13) by L to get the preconditioned set of equations
MIx = R

with MIx LAI and R LB. Now Eq. (14) is solved by the
interval Gaussian elimination method. The preconditioning
method involves, however, about six times as many operations as ordinary interval Gaussian elimination.
The GaussSeidel Iteration. If a crude initial enclosure X
(X1, . . ., Xn) for S is known, it is possible to solve the modified
Eq. (14) more efficiently. The ith equation of Eq. (14) is
Mi1 x1 + . . . + Min xn = Ri
Solving for xi and replacing the other components by their
interval bounds, we obtain the new bound


n


Yi = Ri
Mi j X j /Mii
(15)

x2

j=1
j = i

~
X

The intersection

Xi = Xi Yi
0

(14)

x1

Figure 1. A two-dimensional example illustrating the smallest possi.

ble inclusion of the solution set S in the optimal interval solution X

(16)

now replaces Xi. We successively computer X i using Eqs. (15)

and (16) with i 1, . . ., n. The intersection, given by Eq.
(16), is done at each step so that the newest bound is used in
Eq. (15) for each variable with j i. It should be noted that
extended interval arithmetic must be used to encompass the
case where Mii contains zero.

INTERVAL ANALYSIS FOR CIRCUITS

The Optimal Solution

679

The Interval Newton Method. From the mean-value theorem

Gaussian elimination and GaussSeidel iteration yield the

only in some rather special cases [see (2
optimal solution X
has been suggested by
6)]. A general method for finding X
Rohn (10). Analogous due to Eq. (1), AI and B are written as
AI = [Ac , Ac + ],
B = [bc ,

bc + ],

0

where Ac and bc are the center of AI and B, respectively, and

and are their radii (here and later on, the sign for equality, inequality, inclusion or absolute value relating vectors or
matrices is meant componentwise). Let W denote the set of
all n-dimensional vectors whose components are either 1 or
1. Thus, W consists of 2n vectors. For each w W, let Tw
denote a diagonal matrix whose diagonal is w. To each n-dimensional real vector y, we assign the vector sign y whose
components are 1 if yi 0 and 1 otherwise. Hence y
W. For any w, z W, we form Awz Ac TwTz, bw bc
Tw. Consider the system

Awz x = bw

(17a)

Tz x 0

(17b)

It has a unique solution xw (x1w, . . ., xnw) for every w. The

system given by Eq. (17) is to be solved 2m times (once for
each w W). Then it is proved that the endpoints of the opti i are found as follows:
mal solution components X

w W}

X iR

w W}

max{xw
i ,

(18)

The solution xw is found using the following algorithm.

Sign-Accord Algorithm. The sign-accord algorithm comprises the following steps:
0. For a given w find z sgn(A1
c bw)
1. Solve the system of linear equations Awz x bw.
2. If Tz x 0, terminate. In this case xw : x (the symbol
: has the usual meaning of assignment). Otherwise go
to the next step.
3. Find the index k for which zj xj 0 for the first time.
Let zk zk, and return to Step 1.
It is proved by Rohn (10) that the sign-accord algorithm terminates in a finite number of iterations. Very often, if AI is
narrow enough, it actually converges in only one iteration.
INTERVAL METHODS FOR NONLINEAR EQUATIONS
Nonlinear Equations of One Variable
Let f be a continuously differentiable scalar function of a single variable x. We consider the problem of finding all the zeros
of f(x) 0 in a given interval X0. Among the various interval
methods suggested for solving this problem, the interval modification of the Newton method is currently superior to its
rivals.

(19)

where is some point between x and y. If y is a zero of f, then

f(y) 0 and from Eq. (19)
y = x f (x)/ f  ( )

X iL = min{xw
i ,

f (x) f (y) = f  ( )(x y)

(20)

Let X be an interval containing both x and y. Then X and

hence f() F(X) where F is some interval extension of f.
Denote N(x, X) x f(x)/F(X). It follows from Eq. (20) that,
if y is a zero of f in X, then y N(x, X) and hence it is also in
the intersection X N(x, X). The interval Newton method is
based on this fact and has the following algorithm for finding
a zero of f in X:

N(xk , Xk ) = xk f (xk )/F  (Xk )

Xk+1 = Xk N(xk , Xk ),

k0

(21a)
(21b)

with xk Xk. Usually, xk is taken as the center of Xk. The

above algorithm was derived by Moore (2) for the case where
0 F(X0). It was extended by Hansen (5) to allow 0
F(Xk). In the latter case, N(xk, Xk) is computed by extended
interval arithmetic. Then Xk1, as computed from Eq. (21),
consists of two intervals. Whenever this occurs, one of these
is stored in a list L and processed later. This algorithm is
called the extended interval Newton algorithm [a detailed description of the steps of the algorithm is given in (5)].
Properties of the Extended Algorithm. We list some of the
basic properties of the extended-interval Newton algorithm
which illustrate its reliability and efficiency.
1. The algorithm is globally convergent. Every zero of f in
the initial interval X0 is always found and correctly
bounded within a given accuracy after a finite number
of iterations (if f and f have a finite number of zeros
in X0).
2. If there is no zero of f in X0, the algorithm computationally proves this fact after a finite number of iterations
(when the intersection in Eq. (21b) becomes empty and
the list L contains no further subintervals to be processed).
3. If 0 F(Xk), then a zero (if any) of f in Xk is unique
(simple).
4. If 0 F(Xk) for some k 0, then the asymptotic rate
of convergence to a (simple) zero of f in Xk is quadratic
(in the sense that w(Xk1) c[w(Xk)]2, c being a constant).
5. If 0 F(Xk), and xk is the center of Xk, then at least
half of Xk is eliminated in the next step. Thus, convergence is rapid even at the initial iterations when w(Xk)
is still large.
Systems of Nonlinear Equations
Now we change to vector notation x (x1, . . ., xn)T and f
( f1, . . ., f n)T. We wish to solve the system of equations
f (x) = 0

(22)

680

INTERVAL ANALYSIS FOR CIRCUITS

globally, that is, to find and bound all of the solution vectors
of Eq. (22) in a given box X(0). For noninterval methods, it is
sometimes difficult to find one solution, quite difficult to find
all solutions, and most often impossible to know whether all
solutions are found. In contrast, it is a straightforward matter
to find all solutions in a given box by interval methods in a
finite number of iterations, proving automatically, at the
same time, that there is no other solution in the initial box.
Various interval Newton methods exist for solving Eq. (22)
globally. Similarly to the case of a function of one variable,
they all iteratively solve a linear interval approximation of
Eq. (22). They differ in the choice of the linearization and the
way the linearized equations are solved. Most often, Eq. (22)
is linearized in the following way. Let J(x) denote the Jacobian matrix of f(x). Similarly to the scalar case [see Eq. (19)],
it can be shown that
f (y) = f (x) + J( )(y x)

(23)

Let J(X) be the interval extension of J(x) in X. It follows from

Eq. (23) that, if y is a zero of f in X, then y is also in the
solution set S of the system
f (x) + J(X )(y x) = 0

retrieved from L. It is renamed X(0) and Eqs. (25), (26)

are resumed with X(0).
2. The sequence X(k) converges to a box X* whose width is
larger than 1. In practice, the procedure is stopped
when the reduction in the volume of two current boxes
X(k) and X(k1) becomes smaller than a constant 2. In this
case, X(k1) is split along its widest side into two boxes
XL and XR (left and right). The right box is stored in the
list L for further processing. The left box is renamed
X(0) and the iterative process continues with X(0).
3. At some k, Y(k) X(k) . This is an indication that Eq.
(22) has no solution in X(k), and X(k) is discarded (not
stored in L). A box is retrieved from L (if L is not
empty), and the computation process continues as
before.
The above algorithm [presented in detail in (46)] preserves all of the remarkable properties of the extended-interval Newton algorithm considered before: global and rapid convergence, guaranteed location of all solutions to Eq. (22)
contained in the initial region X0, computational proof of existence, uniqueness or absence of a solution in X(0).

(24)
TOLERANCES OF LINEAR CIRCUITS

which is a system of linear interval equations with respect to

y (x is fixed and is usually the center of X). Let Y denote an
interval solution of Eq. (24), that is, a box containing S. The
interval Newton method for solving Eq. (22) is based on the
following procedure:
X (k+1) = X (k) Y (k) ,

k0

(25)

J(X (k) )(y x(k) ) = f (x(k) )

(26)

where Y(k) is an interval solution of

with respect to y. Because the linear interval system given by

Eq. (26) is to be solved repeatedly (for different boxes X(k)),
approximate methods are used to solve it (the computation of
would require an unacceptably large
the optimal solution Y
amount of computation). The existing interval Newton methods differ from one another, basically, in the way Eq. (26) is
solved. In the earlier versions, the interval Gaussian elimination was used. Since then, many other possibilities have been
investigated. Thus, in Hansens method (5), Eq. (26) is first
preconditioned using the inverse of the center of J(X(k)). The
resulting modified system
M(X (k) )(y x(k) ) = r(x(k) )

(27)

is then solved in a GaussSeidel way.

The interval Newton method generates a list L of boxes
awaiting processing. The iterative process is terminated when
the list is empty. Indeed, the procedure defined by Eqs. (25),
(26) results in one of the following three outcomes:
1. The sequence X(k) converges to a solution x(s) as k increases. Actually, the iterations are stopped whenever
the width of X(k1) becomes smaller than a constant 1
(accuracy with respect to x). Now x(s) is approximated by
the center xc of X(k1). If the list L is not empty, a box is

Various tolerance problems can be formulated in the class of

linear electric circuits depending on the type of the circuit
studied (dc or ac circuits, with independent or dependent
sources, etc.), the nature of variation of the input parameters
(independent or dependent variations) and the number and
type of the output variables [see (6,11,12)]. For simplicity,
only some basic worst-case tolerance problems are presented
here.
dc Circuits
Consider a linear dc (resistive) circuit of uncoupled resistors
and independent voltage sources. Let m be the number of
branches and (n 1) be the number of nodes. One of the
nodes (say, the (n 1)th node) is grounded. The worst-case
tolerance analysis problem for this class of circuits is formulated as follows: given the nominal values of the branch resistors and source voltages and their tolerances, find the tolerances on the branch currents and/or the nodal voltages.
[Several more general dc tolerance problems (including circuits with dependent parameters) are considered in (6).]
To solve the problem considered here, we first need to set
up an appropriate system of linear interval equations. With
this in mind, using Kirchhoff s law, we write the following
system of real equations in vector form
Ay = b

(28a)

with

r
A=

,
0

 
i
y=
,
v

 
u
b=
0

(28b)

where r is a diagonal matrix formed by the branch resistances r , is the (reduced) incidence matrix, and i and u are
the vectors of the branch currents r and source voltages u ,

INTERVAL ANALYSIS FOR CIRCUITS

respectively. Because the nominal values of r , u and their

tolerances are given, each input parameter belongs to the respective interval R or U , that is,
r R ,

u U p

(29)

We seek the intervals of possible values of all currents and

all ungrounded node voltages. Thus, we have n m n output variables and 2m input parameters. When the components of r and u vary in the intervals given by Eq. (29), Eq.
(28) becomes an interval linear system
AI y = B

(30a)

with

AI =


i
y=
,
v

(30b)

of the tolerance probExact Solution. The exact solution Y

lem considered is found by the general Rohn method presented earlier. However, its numerical efficiency is improved
substantially, if the interval matrix AI from Eq. (30) is inverse-stable, that is, if A1 0, A AI [simple sufficient
conditions for establishing the inverse-stability of AI are given
in (6,10)]. In this case, the set W from Eq. (18) reduces from
2n to 2n vectors Wi which are determined as follows:

Wi =

are assumed to have zero tolerances. The problem is to find

the intervals of all branch currents ik, k 1, . . ., m, and the
intervals of all node voltages Vk, k m 1, . . . n [the last
(n 1)th node is grounded, i.e., V17 0].
is obtained by the simplified version of
The solution Y
Rohns method because the interval matrix AI associated with
the circuit studied is inverse-stable. Additionally, the signaccord algorithm converges every time in one iteration. Thus,
is found by solving only 2n 32 real
the optimal solution Y
linear systems of type Eq. (17a). In contrast, the Monte Carlo
method currently used in practice require solving Eq. (28)
thousands of times to attain the same accuracy.
AC Circuits


U
B=
0

where R and U are the interval counterparts of r and u, respectively. It is important to emphasize that all components
of R and U are independent intervals. This requirement is
crucial because most of the existing interval methods solve
only such linear interval systems exactly.

sgn(A1
c )i ,

681

i = 1, . . . n,

Wi = sgn(A1
c )i , i = n + 1, . . ., 2n
1

where (A1
c )i is the ith row of Ac . Thus, Y is found by solving
the auxiliary Eq. (17) only 2n times.

Example 1. We consider the circuit showed in Fig. 2. Each

resistor has one and the same nominal resistance rck 100,
k 1, . . ., m, and an equal tolerance radius k w(Rk)/2
2. The source voltages are ec1 ec2 100V, ec5 ec7 10V and

In this case, the input parameters xi additionally include inductances L (mutual inductances M) and capacitances C. We
assume that we are interested in one single output variable y
and that the relationship y f(x) between y and the parameter vector x (x1, . . ., xn) is explicitly known. Typically, y is
the rms value of some output voltage or transfer function and
(0)
(0)
(X(0)
xi X(0)
i [i, i], x X
1 , . . . Xn ). Thus, the worstcase tolerance problem considered is formulated as follows:
given the multivariate function f(x) in a given box X(0), find
the range f(X(0)) of f over the box X(0).
Let f(X(0)) [f L, f R]. The endpoint f L is sought as the global
solution of the following minimization problem:
f L = min f (x1 , . . . xn ),

i xi i , i = 1, . . ., n

(31a)

Similarly
f R = min[ f (x1 , . . . xn )],

i xi i ,

i = 1, . . ., n (31b)

Three interval methods for solving Eqs. (31) have been suggested in (5): the zero-order method (using no derivatives of
f), the first-order method, and the second-order method (resorting to first- and second-order derivatives, respectively).
They are all based on an algorithm due to Skelboe (13).
Skelboes algorithm (for bounding f L):
1. Set X X(0).
2. Bisect X along its widest side into two subboxes X and
X of equal width.
3. Evaluate F L(X) and F L(X).

+
e5

4. Set b minF L(X), F L(X)

r6
r3

5. Enter the subboxes X and X in a list L.

r9

1
r3
+

r4

r1

r2

e1

e2

e7
r10

r11

r7
r8

Figure 2. Tolerance analysis of all branch currents and node voltages of the dc circuit shown for a 2% tolerance on the circuit resistors.

6. Retrieve from L the subbox X with the lowest F L(X),

that is, that box for which F L(X) F L(X), . Set
X X() and remove X from L.
7. If w(X) where is a prescribed accuracy, return to
step 2. Otherwise proceed to the next step.
8. Set b F L(X). Terminate.
On exit from the above algorithm, the real number b obtained
is a lower bound on F L. If the algorithm is applied to (f)
then, upon termination, b is an upper bound on f R. We illustrate the ac tolerance problem by the following example.

682

INTERVAL ANALYSIS FOR CIRCUITS

Example 2. Consider a second-order active RC filter shown

in Fig. 3. Its voltage transfer function is given by

L
+

i3

i1
s

T ( j) = 1/[1 2 R1 R2C3C4 + jC3 (R1 + R2 )]

The tolerance on the amplitude T( j) was determined for
various tolerances on all four parameters of the circuit by an
improved first-order method [see (6), sec. 2.4.2]. The numerical evidence shows that the improvement over earlier versions of the first-order method is substantial.
An alternative approach to the ac worst-case tolerance
problem is to formulate it as a system of linear equations with
complex coefficients. Approximate solutions are thus obtained
in (6,11, and 12).
The approach based on global optimization also solves the
ac tolerance problem in its probabilistic formulation when the
circuit parameters satisfy the Gaussian distribution law [see
(6), sec. 2.5]. This problem is computationally more difficult
than the worst-case tolerance problem. Nevertheless, numerical evidence shows that the best interval methods are considerably more efficient than the traditional statistical methods
as regards computer time requirements.

TRANSIENT TOLERANCE ANALYSIS

Tolerance analysis of transients in linear electric circuits creates a great variety of problems depending on the mathematical descriptions of the transients, on the one hand, the number and nature of the input parameters, and the number of
output variables, on the other. Presently, three basic approaches to formulating (and solving) transient tolerance
analysis problems are known [see (6)].
Explicit Form Formulation
In this case, there is only one output variable which is some
transient current or voltage in the circuit studied. The input
parameters are component values, amplitudes of dc or ac excitations and values of initial conditions. The relationship between the input parameters and the output variable must be
available in a closed explicit form. Obviously, this is possible
only for circuits of a low order of complexity.

R2
+
C1

i2
C

Figure 4. Determination of the dynamic tolerance I3(t) on branch

current i3(t) for given tolerances on R, L, C, and v.

Example 3. The circuit studied is shown in Fig. 4 [the supply

v is constant and vc(0) 0]. The dynamic tolerance analysis
problem considered is to find for fixed (but arbitrary) time t
the interval I3(t) of all possible values of the branch current
i3(t) when L, C, R, and v belong to some prescribed intervals
LI, CI, RI, and vI. We assume that the quantity
=

1
1

R2 C 2
LC

(32)

is positive for all R RI, L LI, and C CI. Then the solution
i3(t) is given by the formula


1
v
1+
(ek 1 t ek 2 t )
i3 (t) =
R
2CR
where is defined by Eq. (32) and k1, k2 are given by k1,2
1/(2RC) . Let p (R, L, C, V) and P (RI, LI, CI, VI).
The interval I3(t) is determined by the range of i3(t) f(t, p)
when p P. This is done by using some of the methods for ac
tolerance analysis with global optimization.
Based on this example, it is straightforward to present the
explicit formulation of the transient analysis of circuits with
interval data. Let p (p1, . . ., pn) denote the parameter vector which determines the (scalar) transient x(t, p), and let
p P (P1, . . ., Pn). We assume that the circuit is stable for
all p P. This assumption is verified by interval analysis
methods [see (6), Chap. 4]. Then the set of time functions
X (t) = {x(t, p): p P,

t [0, )}

is called the interval transient because X(t) is an interval for

each fixed t. In practice, X(t) is determined for a series of discrete times tk.
Frequency-Domain Formulation

C2
R1

This is an alternate explicit form for a special dynamic tolerance problem when x(t, p) is the response to a step excitation
and the circuit has zero initial conditions. In this case [Kolev
(6)]

x(t, p) =
Figure 3. Worse-case tolerance analysis of the voltage transfer function amplitude of a low-pass active filter for various tolerances on the
circuit elements.

r(, p)
sin t d

(33)

where r(, p) is the real part of frequency response F( j, p)

of the circuit investigated for a fixed parametric vector p. Because Eq. (33) expresses the relationship between the output

INTERVAL ANALYSIS FOR CIRCUITS

variable x(t, p) and the input parametric vector p in explicit

form, the interval solution X(t) is determined as the range of
x(t, p) over P for each t. In practice, the integration in Eq. (33)
is approximated by a sum applying (say) Simpsons integration rule. Three illustrative examples with circuits containing
up to four interval parameters are thus solved in (6, Examples 5.25.4).

forth in (46)]. In this method the interval vector Y(k) participating in Eq. (25) is computed as follows:
Y = b(x) + x + [E J(X )](X x)

x = Ax + b(t),

t [0, ],

<

with initial conditions x(0) c. In the most general case, the

elements aij of A, bi of b and ci of c all depend on the input
parameter vector p. Thus
x = A(p)x + (t)b(p),

t [0, ]

x(0) = c(p)

(34)

where aij(p), bi(p) and ci(p), i, j 1, . . ., n, are generally nonlinear functions of p. Therefore, the solution x(t, p) of Eq. (34),
which is now a vector, also depends on p. Once again, we assume that the circuit is stable for all possible p P. The
tolerance problem is to determine the solution vector X(t)
[X1(t), . . ., Xn(t)] which corresponds to x(t, p) when p P.
This problem is extremely difficult to solve. Therefore, it is
simplified in practice by assuming that aij, bi, and ci are independent and lie in some intervals aIij, bIi , cIi (these intervals are
in fact some extensions or the ranges of aij(p), bi(p), and ci(p),
respectively, in P). Numerical examples with n varying from
2 to 5 are given in (6, Examples 5.55.9).
GLOBAL ANALYSIS OF NONLINEAR dc CIRCUITS
We consider the problem of finding all dc operating points
(global dc analysis problem) of nonlinear electric circuits for
the case where the nonlinear elements are modeled by continuously differentiable functions.

(36)

where E is the identity matrix. In the third version M3 suggested by Alefeld and Herzberger (4), the Jacobian matrix
J(X) is represented as the sum of two matrices as follows:

Time-Domain Formulation
In this formulation, the transients are described implicitly by
a system of differential equation (in vector form)

683

J(X ) = D(X ) B(X )

where D is formed by the diagonal elements of J, and B includes the remaining elements (with changed sign). Then the
vector Y(k) involved in the iterative process Eq. (25) is computed as
Y = x D1 (X )[B(X )(x y) + f (x)]

(37)

As seen from Eqs. (36) and (37), the last two methods circumvent the necessity of solving the linear interval Eq. (26) and
are therefore computationally more efficient than method M1.
Hybrid Form Representation
It is assumed that the circuit investigated allows the so-called
hybrid representation [Chua and Lin (8)], that is,
(x) Hx s = 0

(38)

where H and s are constant matrix and vector, respectively,

and i(x) i(xi), i 1, . . ., n. Equation (38) could be solved
by the general methods mentioned previously. Their computational efficiency, however, is limited to circuits of low dimension n. Indeed, they involve recursive splitting of the initial
box X(0) into subboxes X(v), and the number of X(v), and hence
the computational effort needed to locate all real solutions of
Eq. (38) in X(0) grows exponentially with n. On the other hand,
the specific form of Eq. (38) permits elaborating two specialized, more efficient interval methods (referred to as M4 and
M5) for global analysis applicable to nonlinear dc circuits of
larger size [see (6, sec 6.1.2)]. Method M4 is based on the following iterative procedure:

General Form Description

Y (k) = 1 [X (k) ] L[X (k) ]

In this case, the nonlinear dc circuit is described by the vector

equation
f (x) = 0

(35a)

The components xi of x (branch currents, branch or nodal voltages) are bounded in practice within some admissible intervals, that is xi X(0)
i , i 1, . . ., n or in vector notation
x X (0)

(35b)

where X(0) is an initial box with components X(0)

i . The global dc
analysis problem is formulated as follows: given the vector
CD function f and the initial box X(0), find all the real solutions of Eq. (35).
So far, three versions of the interval Newton method have
been used for global dc analysis. The first version (denoted
M1) appeals to Hansens method [given by Eqs. (25) and (27)].
The second version M2 implements Krawczyks method [set

X (k+1) = Y (k) {H 1 [(Y (k) )] s],

k0

where L(X) HX s. The fifth method M5 is a modification

of method M3 which takes into account that now
D(X ) = diag{i (Xi ) hii ,

i = 1, . . ., n}

whereas B(X) is a constant matrix B hij, j i, i, j 1,

. . ., n. Thus, the iterative process defined by Eq. (25) takes
on the form

Yi(k)

xi(k)

i (xi ) hii xi si

i1


hij X j(k+1)

j=1

n


hij X j(k)



D(Xi(k) )

(39a)

j=i+1

Xi(k+1) = Xi(k) Yi(k) ,

k0

(39b)

684

INTERVAL ANALYSIS FOR CIRCUITS

Furthermore, in the previous methods x is the center of

the current box X. In method M5, two new points xi and xi
(other than xi) are computed and used in Eq. (39a) at every
iteration which improves additionally the numerical efficiency
of the method.
Using the five methods presented, numerous examples are
solved in (6, sec. 5.1.3) with n changing from 2 to 4. The numerical evidence shows that Method M5 has the best performance characteristics. To illustrate its efficiency, consider the
following example:

reduced to several ac tolerance analysis problems related to

the open-loop transfer function.

Example 4. The circuit investigated contains four transistors

and is described by the vector Eq. (38) with i(xi) 109(e40xi
1), i 1, 2, 3, 4. The circuit has nine operating points.
Using Method M5, they are all found within accuracy 0.01
after N 79 iterations ( is the width of each solution box
containing an operating point). For comparison, N 207 and
N 143 for Methods M2 and M4, respectively.

where is a T-periodic function in t, we seek all the T-periodic solutions of Eq. (40) when the initial conditions vector x0
belongs to a box X(0). An interval method for solving the problem, suggested by Kolev (6), is based on an equivalent transformation of the original problem to that of finding all fixed
points of the system x0 f(x0) in X(0). The latter is solved by
an interval method of zero order. In its present implementation, the method is rather time-consuming and is applicable
only to circuits of low dimension (n 3).
The challenging problem of establishing the uniqueness of
a T-periodic steady state in nonlinear electric circuits has also
been considered. A new result has been obtained for the special case where the function from Eq. (40) is of separable
form, that is x (x) b(t). It has the form of a sufficient
condition: the T-periodic solution is unique if an associated
interval matrix is stable. The latter problem is handled by
some of the methods for assessing robust stability.

ALTERNATIVE APPLICATIONS
The scope of the interval approach would be incomplete if we
do not include the so-called robust stability problem and some
aspects of the global analysis of dynamic nonlinear circuits.
ROBUST STABILITY
In the field of electrical, electronics and control engineering,
it is of paramount importance to guarantee the stability of
the circuit investigated (whatever its functions) even in the
presence of some uncertainties about the values of various
component parameters. Two basic approaches are known for
assessing the robust stability: (1) stability of polynomials with
interval parameters and (2) stability of interval matrices.
A famous theorem due to Kharitonov (14) establishes the
robust stability of polynomials in the simplest case where the
polynomial coefficients are independent intervals. Several attempts to extend Kharitonovs approach to more general stability problems have been made in recent years. In (15), Kharitonovs theorem is generalized to polynomials which have all
their zeros in a given sector of the complex plane. A second
extension which guarantees that the corresponding dynamic
system has only aperiodic behavior is obtained in (15). In a
more realistic formulation, the polynomial coefficients are
nonlinear functions of a certain number of physical parameters. The problem of assessing the robust stability or certain
stability margin in this case is equated to a corresponding
global minimization problem [see Kolev (6) and the references
cited there]. Interval methods are vastly superior to their
point counterparts in solving the latter problem.
Interesting results have also been obtained for the case
where the robust stability of the system studied is assessed
by the stability of an associated interval matrix [see Kolev (6)
and the references cited there]. The stability criteria suggested by Kolev (6) are simple and easy to implement on a
computer.
Finally, the interval extension of the Nyquist criterion in
(6) is a most effective means for robust stability analysis of
feedback circuits or systems. Indeed, the assessment of the
gain or phase margin of stability of the closed-loop system is

Dynamic Nonlinear Circuits

The interval approach has been applied to solve the following
problem from global analysis of nonlinear dynamic circuits:
given the system
x = (x, t)

(40)

PERFORMANCE CHARACTERISTICS
Interval methods have proved reliable for solving numerous
problems arising in electrical and electronics engineering.
Some of these problems (such as global analysis of systems of
nonlinear equations, global optimization) which, in their most
general form, were previously intractable, are now routine
practice. A convincing example is the global analysis of dc
nonlinear circuits. Even in the simple case of resistive circuits
containing only one-port nonlinear elements, traditional
methods provide misleading conclusions concerning the total
number of dc operating points in the circuit studied. Thus,
Yamamura (16) suggests a method for finding all solutions of
piecewise-linear (PWL) resistive circuits and applies it for
global analysis of resistive circuits whose nonlinear elements
characteristics are described by continuously differentiable
functions. He illustrates his approach by several examples.
Example 3 deals with a circuit containing 10 tunnel diodes
described by a system of 10 nonlinear equations. Each tunnel
diode characteristic is approximated fairly well by 10 linear
segments. Yamamuras method locates seven dc operating
points in a given box X(0). Application of an interval method
[Kolev and Mladenov (17)] shows that this result is incorrect:
the total number of operating points for the same circuit and
the same box X(0) has been computationally proved equal to
nine and all operating points have been located within an accuracy of 104. In another example from (16) (Example 4 dealing with the Hopfield neural network that comes from a layout problem of printed boards), the number of solutons
changes from 15 to 19 when the number of the approximating
linear segments is increased from 30 to 100. In contrast, interval methods never go wrong.

INTERVAL ANALYSIS FOR CIRCUITS

For most problems solved to date, interval methods require

reasonable amounts of computer time which are usually
smaller than those needed by traditional methods [see
6,11,12). Theoretically, the complexity of some interval methods, and hence computer time required, may grow exponentially with the dimension n of the problem and the size of the
initial box where solutions are sought. This is the case of the
exact Rohns method for dc tolerance analysis, tolerance analysis methods based on global optimization, and global analysis of nonlinear circuits. Judging from the available experimental evidence this difficulty has, however, not occurred in
practice.
It should also be borne in mind that some interval methods
for global solution of nonlinear problems of higher dimension
require relatively larger memory volumes. Typically, this occurs in the case of zero-order methods (using no derivatives
of the functions involved), such as the original Skelboe algorithm. At the earlier iterations of the computation process,
the current box X (starting with the initial box X(0)) is, most
often, split into two halves. Each half is, subsequently, subdivided again which generates a long list L of subboxes
awaiting processing. If the dimension n of the problem considered and the size of X(0)) are large enough, the storage of L
requires a bigger memory volume. However, for the type of
problems tackled so far, this has not caused any difficulties.
Another peculiarity of the interval methods for global nonlinear analysis (and global minimization) is the so-called cluster effect [e.g., see (18)]. Ideally, for each point solution xs, an
interval method should provide one single interval solution,
that is, a small box Xs of width ( being the solution accuracy) which covers xs. However, if clustering occurs, on termination of the computation, there are a certain number of
small boxes Xs1, Xs2, . . ., Xsk (of the same width ) around
each Xs. Unlike Xs, these boxes do not contain the solution xs
and should not be identified as interval solutions. Clustering
appears, essentially, because the method does not delete
small enough boxes around a solution. The cluster effect
grows stronger as the problem dimension n increases. On the
other hand, for one and the same problem, the cluster effect
decreases if the method used converges better toward a solution. Therefore, clustering is reduced or even completely
avoided if higher order methods are employed. This has been
observed experimentally with the known interval methods for
global dc analysis when n exceeds some critical value
(which, depending on the problem solved and the method
used, varies from n 4 to around n 10). In the present
implementation of the nonlinear analysis methods, clustering
is detected manually by inspection of all point solutions xs
and exclusion of those caused by the cluster effect.
IMPROVED NUMERICAL EFFICIENCY
The drawbacks of most interval methods are caused, essentially, by overestimation. The drawbacks are reduced to a
great extent or completely overcome if improved interval extensions are used. Two such techniques aiming at obtaining
interval extensions of smaller excess are mentioned here.
Modified Mean-Value Forms
The mean-value form given by Eq. (7) can be modified in a
number of ways to ensure a narrower extension. The first im-

685

provement is the so-called monotonicity test form [Moore (1)]

FMT (X ) = [ f (u), f (v)] +

Fi (X )(Xi mi )

(41)

iS

where S is the set of integers i such that F i(X) properly contains zero and ui xLi , vi xRi , if F i(X) 0, ui xRi , vi xLi if
F i(X) 0 and ui vi mi if i S. In Eq. (7) and Eq. (41),
the interval extensions F i(X) F i(X), . . . Xn) depend, generally, on all of the intervals Xi. Hansen (5) has introduced an
improvement in which part of the arguments become real
numbers. Because of inclusion monotonicity, this leads to narrower F i(X) and, hence, to narrower extensions. Further improvements (introduction of lower and upper poles, sequential evaluation of the derivatives, choice of the bisection
direction, etc.) are suggested by Kolev (6), secs. 2.2 and 2.4).
In accordance with the theoretical predictions, the numerical
evidence shows that the best mean-value forms lead to methods of enhanced efficiency.
Interval Slopes
Interval slopes were introduced in interval computations by
Krawczyk and Neumaier (19) for rational functions of a single
variable. Computation of interval slopes (in fact, of interval
extensions of the slopes) in the case of multivariate functions
is based on the so-called slope arithmetic [see (20)]. The extension of interval slopes to irrational functions is suggested
by Kolev (21). This permits a more efficient analysis of nonlinear dc circuits containing transistors (and diodes) if the EbersMoll model of transistors is used.
The slope of a function f of one variable x at x, z is defined
as


f [x, z] =

[ f (x) f (z)]/(x z), x = z

f (x),
x=z

(42)

The interval slope S(X) is either some interval extension

F[X, z] or (better) the range f[X, z] of f(x, z) with respect to x
in X. Let D(X) denote the interval derivative of f in X. The
following important property is then valid:
S(X ) D(X )

(43)

and the inclusion is usually proper. The above inclusion motivates the use of interval slopes rather than interval derivatives in all of the interval methods for nonlinear circuit analysis. The improved numerical efficiency of the approach based
on interval slopes is established experimentally in (17,1921)
where nonlinear systems involving up to 10 equations with
nine solutions are solved.
TRENDS FOR FUTURE DEVELOPMENT
Interval approach is expected to develop in two directions.
First, it is expected that the scope of the interval approach
will be enlarged. So far, interval approach covers basic problems relative to: (1) robustness analysis of linear circuits and
(2) global analysis of nonlinear circuits. Many other applications are, however, conceivable in the domain of circuit analysis, such as tolerance analysis of nonlinear circuits, robust

686

INVERTER THYRISTORS

stability of certain types of nonlinear systems (for example,

Lures systems), and analysis of chaos in nonlinear circuits.
It is expected that interval approach will also be applied
to solve problems in circuit synthesis [such an example is considered in (6), p. 276]. It has already been employed (though
in a rather restricted manner to ensure high accuracy of computation when all input data are exact) for the designing of
control systems (22).
Some of the interval methods suggested for solving electric
circuit analysis problems exploit the specific structure of the
class of circuits considered to devise algorithms of improved
numerical efficiency. On the other hand, many of the electric
circuit analysis problemstolerance analysis via global optimization, robust stability and performance analysis, and
global nonlinear analysis in the case of equations of arbitrary
formare more general. The methods developed for solving
these latter problems can, therefore, be applied (directly or
after minor modifications) to tackle similar problems arising
in systems of arbitrary physical constituency. For this reason,
it is hoped that these more general interval methods will also
be useful to control engineers, mechanical engineers, system
analysts and other specialists striving to employ modern computer methods in their research or application areas.
The second expected development is improvement of the
interval methods efficiency. The existing interval methods for
circuit analysis are based on the present state of the art of
those interval analysis techniques that are related to the topics considered. However, interval analysis is presently undergoing a period of rapid development, and new improved mathematical tools (methods for obtaining narrower interval
extensions, for solving more efficiently linear and nonlinear
equations, global optimization problems, linear and nonlinear
differential equations, etc.) are constantly emerging. Incorporating such new techniques into the body of interval methods
for solving electrical and electronics engineering problems is
expected to lead to substantial improvement in the numerically efficiency of thse methods. Progress in their software
and hardware implementation (implementation of interval
methods by parallel computation techniques, development of
user-friendly versions, hardware realization of machine interval arithmetic, etc.) will help disseminate the interval methods among more and more specialists in various fields of science and engineering.
BIBLIOGRAPHY
1. T. Sunaga, Theory of an interval algebra and its application to
numerical analysis, RAAG Memoirs II, Tokyo: Gakujutsu Bunken Fukyu-kai, 1958.
2. R. E. Moore, Interval Analysis, Englewood Cliffs, NJ: PrenticeHall, 1966.
3. R. E. Moore, Methods and Applications of Interval Analysis, Philadelphia: SIAM, 1979.
4. G. Alefeld and J. Herzberger, Introduction to Interval Computation, New York: Academic, 1983.
5. E. Hansen, Global Optimization Using Interval Analysis, New
York: Marcel Dekker, 1993.
6. L. V. Kolev, Interval Methods for Circuit Analysis, Singapore:
World Scientific, 1993.
7. S. Skelboe, True worst-case analysis of linear electrical circuits
by interval arithmetic, IEEE Trans. Circuits Syst., 26: 874879,
1979.

8. K. Madsen and H. Jacobsen, Algorithm for worst-case tolerance

optimization, IEEE Trans. Circuits Syst., 26: 775783, 1979.
9. L. O. Chua and P. M. Lin, Computer Aided Analysis of Electronic
Circuits: Algorithms and Computational Techniques, Englewood
Cliffs, NJ: Prentice-Hall, 1975.
10. J. Rohn, Solving interval linear systems, Freiburger Intervall-Berichte 7: 1, 1984.
11. K. Okumura and S. Higashino, An interval method for worst-case
analysis of ac linear networks, Proc. Int. Symp. on Electr. Eng.,
ISTET95, Thessaloniiesis, Greece, 1995, pp. 446449.
12. W. Tian and X. T. Ling, Novel methods for circuit worst-case tolerance analysis, IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., 43: 272278, 1996.
13. S. Skelboe, Computation of rational interval functions, BIT, 14:
8795, 1974.
14. V. L. Kharitonov, On a generalization of a stability criterion,
Akad. Nauk. Kazakhsoi SSR Izv. Ser. Phys.-Mat., 1: 5357, 1978.
15. C. B. Soh and C. S. Berger, On the stability properties of polynomials with perturbed coefficients, IEEE Trans. Autom. Control,
33: 351, 1988.
16. K. Yamamura, Finding all solutions of piecewise-linear resistive
circuits using simple sign tests, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 40 (8): 546550, 1993.
17. L. Kolev and V. Mladenov, Use of interval slopes in implementing
an interval method for global nonlinear dc circuit analysis, Intern. J. Circ. Theory and Appl., 25: 3742, 1997.
18. A. P. Morgan and V. Sapiro, Box bisection for solving seconddegree systems and the problem of clustering, ACM Trans. Math.
Software, 13: 152167, 1987.
19. R. Krawczyk and A. Neumaier, Interval slopes for rational functions and associated centred forms, SIAM J. Number. Anal. 22:
604616, 1985.
20. S. Zuhe and M. A. Wolfe, On interval enclosures using slope
arithmetic, Appl. Math. Comput., 39: 89105, 1990.
21. L. V. Kolev, Use of interval slopes for the irrational part of factorable functions, Reliable Computing, 3: 8393, 1997.
22. G. Ludyk, Computer-Aided Design of Dynamic Systems, Berlin:
Springer-Verlag, 1990.

LUBOMIR V. KOLEV
Technical University of Sofia

INTERVAL MEASUREMENT. See TIME MEASUREMENT.

INVERTERS. See DC-AC POWER CONVERTERS (INVERTERS).
INVERTERS, NEUTRAL POINT CLAMPED. See BATTERY STORAGE PLANTS.

INVERTERS, STEPPED-WAVE. See BATTERY STORAGE

PLANTS.

SYMBOLIC CIRCUIT ANALYSIS

219

SYMBOLIC CIRCUIT ANALYSIS

Circuit simulation is an integral part of tools used in circuit
design. The principle of symbolic analysis is to derive analytic
(or symbolic) functions describing the circuit responses, using
symbols representing (all or some) circuit parameters rather
than their numerical values. These parameters may be of a
different nature. In the case of most common alternating current (ac) analysis, element parameters and frequency are represented in symbolic form. Evaluation of these symbolic functions for specific values of symbols provides, if required,
numerical responses of the circuit. In the symbolic approach,
network functions are determined from the knowledge of network elements, their nature, and their connections (network
topology). For that reason, symbolic analysis is sometimes
called topological analysis.
The primary domains of symbolic analysis are direct analysis using either graph-based (topological) or matrix approach,
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

220

SYMBOLIC CIRCUIT ANALYSIS

hierarchical analysis, and approximation techniques. Although the most traditional domain of symbolic computeraided design (CAD) is ac analysis of lumped, linear, time-invariant networks, the symbolic approach is present in various
domains of circuit design starting with the formulae for manual calculations or spreadsheets used in the design process.
Different applications have been developed based on the symbolic approach. These include speed-up of calculation in domains like circuit optimization and statistical analysis; design
automation; device characterization; and structural synthesis.

L = 3H
Vi

Vo
R = 2

C = 5F
(a)
L
Vi

Vo
R = 2

C
(b)
L

BASIC CONCEPTS
Most of the well-known programs of circuit simulation exist
in the numerical version. It means that a numerical value
should be given for any circuit parameter, and the simulated
circuit functions are presented as numerical tables or plots.
For instance, in ac analysis for each frequency point, the complex value of voltage or current is calculated. For symbolic
analysis, there is no need to specify element values when
analysis starts. Element parameters are present as symbols
in simulation results and are valid for any numerical value of
these parameters. The numerical results can thus be obtained
by simple function evaluation for a specified set of parameter values.
Symbolic results of circuit analysis may be generated in
different forms depending on whether all or only some of network elements are characterized by symbolic parameters.
For linear, lumped, and stationary (LLS) circuits, the symbolic network functions can be presented in the form of rational functions of complex frequency s

H(s) =

N(s, x1 , . . ., xn )
D(s, x1 , . . ., xn )

(1)

where x1, . . ., xn are parameters of circuit elements.

In Eq. (1), coefficients of the polynomials N and D are the
sums of products of circuit parameters and can be expressed
as follows:

P(s, x1 , . . ., xn ) =

m

i=0

ni



xk

(2)

Vi

Vo
R

C
(c)

Figure 1. Three levels of symbolic analysis.

Example 1. Let us calculate the voltage transfer function

Vo /Vi of circuits presented in Fig. 1(ac). The small signal
analysis gives following expressions.
1. For the circuit in Fig. 1(a), the complex frequency s is
the only symbolic parameter. The transfer function is a
rational function of s with real coefficients:
2
Vo
=
Vi
30s2 + 3s + 2

(5)

2. In Fig. 1(b), capacitor C and inductance L are symbolic

while R 2 . This is the case of partially symbolic or
semisymbolic network function:
2
Vo
= 2
Vi
2s CL + sL + 2

(6)

3. In Fig. 1(c), all circuit parameters are represented by

symbols. This is the case of fully symbolic network function:
R
Vo
= 2
Vi
s CLR + sL + R

(7)

j=1 kKij

HISTORY OF SYMBOLIC METHODS

This format is called the classical sum-of-products (SOP)
form. If each product of symbols appears only once in this
expression, we have the case of a canonic SOP form. Equation
(2) can also be presented as a product of two or more polynomials. In this case, we have a nested form of symbolic results.
A nested polynomial is called cancellation-free, if its expansion yields a canonic form. An example of canonic SOP and
nested form of symbolic results follows.
Canonic SOP form:
Canonic nested form:

s2C1C2 + sC1 G2 + sC2 G1 + G1 G2

(sC1 + G1 )(sC2 + G2 )

(3)
(4)

Methods of symbolic analysis started in the nineteenth century with Kirchhoff s work. Symbolic methods were intensively developed in the 1960s and 1970s in parallel with the
growing popularity of computer programs of circuit analysis. Different computer programs for direct symbolic analyses
were then developed. The limitation of direct methods came
from the exponential growth of the number of terms in generated expressions with circuit size. To overcome this problem, decomposition techniques were proposed. Instead of analyzing the network as a whole, the network is cut into
parts, each part is analyzed separately, and partial results
are combined to form a description of the whole network. An-

SYMBOLIC CIRCUIT ANALYSIS

Element

Equations

Admittance
a

ib = y(vb va)

Directed graph

ia = y(va vb)

VCCS
a +

Current voltage graphs

y
vb

va
a

y
a

c
io=yv

ia = 0 ib = 0
ic = y(va vb)

y
y

va

vc

y
b

id = y(vb va)
b

Coates graph

221

vb

vd

Figure 2. Different graph representations of circuit elements.

other approach to overcoming the complexity of symbolic results is the technique of approximation of symbolic expressions. In this case, the less significant terms of the function
are discarded. A controlled error of such truncated results is
admitted as a cost of important simplification of symbolic expressions. With the progress in the methods of symbolic function generation, new application domains emerged simultaneously. To the primary advantages of the symbolic approach
[e.g., better understanding of circuit operation (so-called insight into circuit behavior) or speed-up of circuit simulation
in repetitive analysis] were added new ones like automated
generation of analytic models, transistor sizing, exploration of
new topologies, and various automated design methods based
on the availability of symbolic description of circuit topology.
DIRECT SYMBOLIC METHODS
When symbolic functions are obtained directly from the representation of the whole network, we have the case of direct
symbolic analysis, which is also called flat analysis. A different approach is presented with the hierarchical analysis of
decomposed networks. This second approach is essentially
oriented for the analysis of larger circuits.
Two basic approaches are used to derive symbolic functions: graph-based methods and algebraic methods. For simplicity, only networks having the admittance representation
will be considered in the following presentation. The extension to any circuit topology can easily be done by introducing
auxiliary circuit elements in much the same way as adding
new variables allows modified nodal admittance (MNA). Different graph representations for two basic admittance elements of electrical networks are presented in Fig. 2.
A simple circuit representing a small signal model of bipolar transistor presented in Fig. 3 will be used as an example
to illustrate different methods of topological analysis.
gb

Graph-Based Methods
In the graph-based (or topological) methods, symbolic functions are derived by topological operations on some graph representation of the circuits. These operations consist mainly in
generation of specific subgraphs such as, for instance, spanning trees and multitrees or sets of paths and loops. Detailed
description of graph-based methods and an important list of
references is provided by Chen (1).
Pair of Conjugate Graphs. A currentvoltage graph is the
most common circuit representation using a pair of conjugate graphs.
For a circuit composed of admittance-type elements [passive admittance elements and voltage-controlled current
source (VCCS) only] a currentvoltage pair of graphs (GI, GV)
is determined as follows:
1. The sets of nodes (identical for two graphs) correspond
to circuit nodes.
2. The passive element with an admittance y connected
between nodes i and j is represented by a pair of
branches with weight y. In both graphs, these branches
have the same direction [e.g., from node i to j (or from j
to i)].
3. The VCCS source with the controlling voltage between
nodes i () and j () and the current source between
nodes k (outgoing) and p (incoming) is represented by a
branch from i to j in the voltage graph and a conjugate
branch from k to p in the current graph. The weight of
this branch is equal to the transconductance controlling
coefficient (gm).
The pair of currentvoltage graphs for the circuit from Fig. 3
is presented in Fig. 4.

C
g mV

V
g

g0

y1 = gb, y2 = g + sC, y3 = sC, y4 = g0, y5 = gm

Figure 3. Small signal model of bipolar transistor.

Figure 4. Pair of currentvoltage graphs based on the bipolar transistor model.

222

SYMBOLIC CIRCUIT ANALYSIS

Another popular circuit description leading to a two-graph

representation is the nullatornorator network. Two additional singular elements (nullator and norator) are used in
this circuit representation. Nullator is a two-terminal element with i 0 and v 0 and norator a two-terminal element with undefined i and v. A nullatornorator pair is called
nullor. This type of representation is particularly convenient
for circuits with ideal operational amplifiers, which can be
represented as a nullatornorator pair. The pair of conjugate
graphs is obtained by short-circuiting nullators and opening
norators (one graph) and by short-circuiting norators and
opening nullators (another graph). The analysis of nullator
norator networks was proposed by Davies (2).
Circuit functions can be expressed using determinants and
cofactors of the admittance matrix Y. The following topological formulae can be used to calculate necessary determinants
and cofactors of the circuit represented by a pair of conjugate
graphs.

Y =
sign(t) val(t)

method, the network is represented with a single directed

graph Gd and its determinant is calculated by enumeration of
directed trees of this graph.
Directed graph Gd, for a given circuit, is determined as
follows:

1. The set of graph nodes corresponds to the set of network

nodes.
2. The passive element with an admittance y connected
between the node i and j is represented by a pair of
directed branches with the weight y (one from i to j and
another from j to i).
3. The VCCS source with the controlling voltage between
nodes i () and j () and the current source between
nodes k (outgoing) and p (incoming) is represented by a
set of four branches connected as follows: p to i and k to
j with the weight gm and k to i and p to j with the
weight gm.

tT

Yii =

sign(t) val(t)

tTi,0

Yij = (1)i+ j

(8)

sign(t) val(t)

tTij ,0

where T is the set of common trees of current and voltage

conjugate graphs, sign(t) is the sign of a common tree t and is
a product of the signs of t in GI and GV, which are defined as
determinants of tree incidence matrices, val(t) is the product
of all branch weights (admittances) from the tree t, TX,Y is the
set of common 2-trees such that nodes from the set X and Y
are in the disjoint parts, and 0 is the reference node.
Let us calculate the input admittance of the circuit from
Fig. 3. Input admittance Yi can be expressed using the following formula:
Yi =

Y
Y11

(9)

According to Eq. (8), we should calculate trees and 2-trees of

the pair of graphs in Fig. 4. The set of trees of the voltage
graph is equal (1, 2, 3), (1, 2, 4), (1, 5, 3), (1, 5, 4), (1, 3, 4).
Because the tree (1, 5, 4) is not a tree in the current graph,
the set of common trees is equal to (1, 2, 3), (1, 2, 4), (1, 5,
3), (1, 3, 4). The set of common 2-trees T1,0 is equal to (1, 3),
(1, 4), (2, 3), (2, 4), (3, 4), (3, 5). All signs of trees and 2-trees
are positive, including those with branches corresponding to
active elements like (1, 5, 3) and (3, 5). With the Eqs. (8) and
(9), the symbolic input admittance of the circuit in Fig. 3 can
be presented as follows:

y1 ( y2 y3 + y2 y4 + y5 y3 + y3 y4 )
y1 y3 + y1 y4 + y2 y3 + y2 y4 + y3 y4 + y3 y5
g [( g + sC )sC + ( g + sC) g0 + sC gm + sC g0 ]
= b
gb sC + gb g0 + ( g + sC )sC
+( g + sC) g0 + sC gm + sC g0

A subgraph Td is said to be a directed tree of Gd, rooted at

node r, if and only if:
in Td, node r has no outgoing branches and each remaining node has exactly one outgoing branch;
the resultant undirected subgraph T is a tree of the resultant undirected graph G after all branch directions removed.

A subgraph Ti, j is said to be a directed 2-tree of Gd, with roots

i and j, if and only if:
each component (possibly an isolated node) of Ti, j is a directed tree with node i and j as the root;
the resultant undirected subgraph is a 2-tree of the resultant undirected graph G after all branch directions removed.

If some nodes have to be in the same component as the root

node, their symbols will be added to the root subscript.
Determinant and cofactors of the admittance matrix can
be calculated as follows:

Y =

val(t)

tT

Yii =

Yin =

val(t)

tTi,0

(10)

Directed Graphs. The main goal of directed graph formalism was to eliminate cumbersome sign calculations necessary
in the conjugate graph approach. In the directed graph

Yij = (1)i+ j

(11)
val(t)

tTij,0

where T is the set of directed trees of the graph Gd, val(t) is

the product of all branch weights with their signs from the
tree t, TX,Y is the set of directed 2-trees, and 0 is the reference node.

SYMBOLIC CIRCUIT ANALYSIS

y2 gm

y1

. . ., Pk(i, j) is the weight of the kth path from the node zj to

xi, and k is calculated as without any loops touching the
path Pk(i, j).

y2

y1
y3

y3 + gm

223

y4 y + g
4
m

The Coates graph Gc is associated with a square n n

matrix A according to the following rules:

(a)
y1

y1

1. The graph has n nodes associated with the matrix rows

(unknowns).

y2

y2
y4 + gm
y1

2. Each nonzero element aij generates a branch from j to i

with a weight aij.

y4 + gm
y2 gm
y3

(b)
Figure 5. (a) Directed graph of bipolar transistor model and (b) its
set of directed trees.

The directed graph for the circuit from Fig. 3 is presented

in Fig. 5(a). The set of directed trees of that graph is presented in Fig. 5(b).

Let us denote W as a set of pairs of nodes in the Coates graph

W (v1, r1), . . ., (vk, rk) where vs vm, vs rm, rs rm, for
s m.
k-connection (multiconnection) of graph Gc, defined by a
set W, is a subgraph pW composed of k node-disjoint directed
paths and node-disjoint directed loops incident with all graph
nodes. The initial node of ith path is vi, and the terminal node
is ri (pairs of nodes from the set W). 0-connection (or connection) is denoted by p. When vi ri, a multiconnection has an
isolated node vi.
The sign of k-connection p PW is equal to

sign(p) = (1)n+k+l p ord(v1 , . . ., vk )ord(r1 , . . ., rk )

Signal-Flow Graph. Signal-flow graph (SFG) formalism was
introduced by Mason (3) and is a popular technique to visualize and solve problems in various domains of engineering.
Slightly modified equivalent representation was proposed by
Coates (4). Both formalisms are used in topological analysis.
Let us consider a system of n linear equations in a form
X = AX + BZ

(12)

where X is the n 1 vector of unknowns, Z m 1 vector

of input variables, and A and B are the coefficient matrices
n n and n m, respectively.
Mason signal-flow graph Gm representing a system of Eq.
(12) is a weighted directed graph built with the following
rules:
1. Graph nodes represent variables X and Z (knowns and
unknowns).
2. Each nonzero term aij is represented by a branch ( j to
i) with a weight aij.
3. Each nonzero term bik terms is represented by a branch
(k to i) with a weight bik.
An nth-order loop in Mason graph is a set of n nontouching
loops.
Mason Rule. Any transfer function Tij xi /zj can be calculated as follows:

Pk (i, j)k

Tij =

(13)

where 1 (sum of all loop weights) (sum of all secondorder loop weights) (sum of all third-order loop weights)

= (1)l p sign(PW )

(14)

where

ord(x1 , x2 , . . ., xk ) =

when the number of permutations

ordering the set is even
otherwise

n number of graph nodes

lp number of loops in k-connection p.
Note that for all k-connections of the type PW, the sign can be
calculated as a product of a common term sign(PW) and a
term (1)lp depending on the number of loops in the k-connection.
Determinant and cofactors of the admittance matrix represented by a Coates graph Gc can be calculated as follows:

Y =

sign(p)val(p) = sign(P)

pP

Yii =

(1)l p val(p)

pP

sign(p)val(p) = sign(P{(i,i)} )

pP{ (i,i )}

Yij = (1)i+ j


(1)l p val(p)

pP{ (i,i )}

sign(p)val(p) = (1)i+ j+n+1sign(P{(i, j)} )

pP{ (i, j )}

(1)1 p val(p)

(15)

pP{ii, j )}

where P (PW) is the set of connections (multiconnections) of

the graph Gc, val(t) is the product of all branch weights with
their signs from the tree t, and lp is the number of loops in a
connection (multiconnection).

224

SYMBOLIC CIRCUIT ANALYSIS

y 1 + y 2+ y 3
y1

the two-port scheme. The admittance matrix Y of the augmented network can be expressed as follows:

y3 + y4
y1

y3

y1

y3 + gm

Figure 6. Coates graph of bipolar transistor model with reference

node eliminated.

1 ys
2
0

Y =Y + .
..

The Coates graph of the circuit in Fig. 3 is presented in

Fig. 6.
Symbolic topological methods are closely linked with the
graph theory, its methods, and its algorithms. In fact, after a
graph representing the network is generated, the main difficulty of topological analysis consists in determining various
subgraphs like trees, multitrees, paths, connections, and
multiconnections. An important bibliography concerning this
subject can be found in Refs. 1 and 5.
An important aspect of generation algorithms is the problem of term cancellations. The cancellation of terms can be of
two types: additive cancellation, in which two equal terms
with opposite sign cancel, or multiplicative cancellation, in
which a numerator and a denominator factors cancel. In the
direct symbolic approach, canceling terms can be eliminated
with no loss of accuracy, but their generation and further
treatment cause an unnecessary complication of the procedure. The main problem with canceling terms is thus the efficiency of the generation method, rather than precision,
which is the main preoccupation in the case of the numerical
approach. Anyway, the inherently cancellation-free methods
are preferred in symbolic simulators.
Two-Port Analysis
Let us consider a two-port network. Any network transfer
function can be expressed with the determinant and cofactors
of the node admittance matrix. Topological Eqs. (8), (11), and
(15) show how to calculate these functions for different topological representations of the network. This operation involves generating different sets of trees and multitrees (connections and multiconnections) of the graph. It is possible to
simplify these calculations and obtain all necessary characteristic functions with one generation of trees or connections
of so-called augmented network. This procedure avoids the
separate generation of different kinds of trees and multitrees
(respectively, connections and multiconnections) and in particular avoids the cumbersome calculation of the multitrees
and multiconnections sign. An augmented network is created
by adding some symbolic elements to the initial network. In
Fig. 7 an admittance ys and VCCS gm have been connected to

y's

2
Vo

g'mVo
0
Figure 7. Augmented network.

2
gm
0

3
gm
0
..
.

4
0

...

(16)

The evaluation of the determinant of such a matrix gives

Y  = Y + ys Y11 + gm (Y12 Y13 )

(17)

where Y and Yij are determinant and cofactors of the initial

admittance matrix Y.
A symbolic determinant of the augmented network is calculated keeping all added elements as symbols. Obtained
terms can be sorted with respect to the added symbols, and
the determinant and cofactors can easily be extracted. Other
elements can also be added to calculate the different cofactors
needed. Beside the simplification of the generation procedure,
the augmented network approach also reduces the necessary
calculation effort. In fact, a large part of generation is identical for different cofactors and is executed only once with the
previously presented approach.
Algebraic Methods
Interpolation Method. The interpolation method is particularly convenient for the case when s is the only variable kept
as a symbol. The admittance matrix determinant as well as
cofactors necessary to describe network functions can be expressed as polynomial functions in s. The degree of these polynomials can be easily determined from the types of elements
in the network. In the case of the polynomial of the degree
n, P(s) a0 a1s . . . ansn, polynomial coefficients a0,
a1, . . ., an can be determined by evaluating the function P
at (n 1) distinct values of s and then solving the system of
equations:

1
1

.
.
.
1

s0
s1
..
.
sn

...
..
.

sn0
P(s0 )
a0

sn1
a1 P(s1 )

=
.. .. ..

. . .

...

snn

an

(18)

P(sn )

For small n (n 20), real values of s can be chosen to simplify

the calculation. In the case of greater n, the use of real s value
leads to ill-conditioned equations. It was shown by Singhal
and Vlach (6) that it is best to use complex values of s, uniformly distributed on a unit circle. Using the linear property
of network polynomials toward every network parameter, the
interpolation method can be extended to handle the problem
when there are other symbolic variables beside s. Nevertheless, in this case, the same result can be obtained in a simpler
manner with the parameter extraction method.
Parameter Extraction Method. Efficiency of direct graphbased methods does not depend on number of symbolic parameters but on the network complexity. Interpolation methods can handle large networks but are essentially limited to
one symbolic parameter s. The combination of two methods

SYMBOLIC CIRCUIT ANALYSIS

allows the analysis of larger networks with a reasonable set

of parameters. A common point of different contributions on
this subject is that the variable parameters are extracted
from the networks determinant and cofactors. The extraction
procedure can combine topological or algebraic (numerical)
approach.
In the case of k symbolic parameters x1, x2, . . ., xk, network polynomials can be presented in the following form:

G1

225

G2
(a)

P(s, x1 , x2 , . . ., xk ) = P0 (s) + [P1 (s)x1 + P2 (s)x2 + + Pk (s)xk ]

+ [P12 (s)x1 x2 + P13 (s)x1 x3 + ]
+ + P12...k (s)x1 x2 . . . xk

(19)

The extraction process consists of determining the polynomials P0, P1, . . ., P12. . .k. For each polynomial, a corresponding
cofactor can be identified by deleting some rows and columns
in the admittance matrix and setting to zero some of the parameters. After this operation, the cofactor can be determined
with numerical methods. This approach provides an important advantage when many network branches are characterized by numerical values. Of course, when more and more
elements are represented by symbols, the process can attain
similar or even greater complexity than topological methods.
The following conclusions can be obtained by comparing
the direct methods presented here:
1. Topological methods are most suitable to obtain fully
symbolic functions of small networks.
2. Parameter-extraction methods are most suitable for obtaining partially symbolic network functions where only
a small part of the network elements are characterized
by symbolic parameters.
3. Interpolation methods can be used for large networks
when the complex frequency s is the only symbolic parameter.

B1

B2

(b)
Figure 8. (a) Graph bisection and (b) its block graph.

two parts and the block graph of this bisection are presented
in Fig. 8.
The complexity of symbolic analysis of decomposed network depends not only on the size of blocks, but also on the
complexity of the block graph. In the case of larger networks,
a simple (one-level) decomposition may be ineffective. It may
result in either elementary blocks that are too large or a block
graph that is too complex. When simple decomposition is applied to subgraphs, we deal with hierarchical decomposition.
An example of hierarchical decomposition is presented in
Fig. 9. The graph G1 was first decomposed into two parts G2
and G3. In the following step, G2 was decomposed into G4, G5
and G6, and G3 into G7 and G8.
The hierarchical decomposition structure can be illustrated by a tree of decomposition. If a subgraph Gk was ob-

DECOMPOSITION AND HIERARCHICAL ANALYSIS

Calculating symbolic results with the direct methods already
presented is very often limited to the small and medium class
of circuits or to the case when a number of parameters kept
as symbols is limited. In fact, the number of terms in fully
symbolic function grows exponentially with the size of the circuit characterized by a number of nodes and/or number of
elements. The number of terms also grows exponentially with
the number of symbolic elements. To overcome this difficulty
and perform full symbolic analysis of a larger network, a decomposition (partitioning, tearing) technique was proposed.
In much the same way as direct methods, analyzing a decomposed network can be based on topological or algebraic approach.
In the node decomposition, which is most often used in
symbolic decomposition methods, the network (or its graph)
is partitioned into edge-disjoint parts called blocks. Nodes
common to two or more blocks are called block nodes. A decomposed graph can be represented as a block graph. A particular case of node decomposition is decomposition into two
parts, which is called bisection. Any decomposition can be represented as a sequence of bisections. A graph decomposed into

G1

G2

G3

G4
G7

G5
G8
G6
Figure 9. Hierarchical decomposition.

226

SYMBOLIC CIRCUIT ANALYSIS

teristic functions of the total initial network are expressed as

a sequence of expressions (nested-form).

G1
G2
G4

G5

G3
G6

G7

Properties of Hierarchical Analysis

G8

Figure 10. Tree of decomposition.

tained during decomposition of a subgraph Gi, then there is

an edge from node Gi to node Gk in the decomposition tree. In
the decomposition tree, we have one initial node, which is the
root of the tree. Terminal nodes are leaves of the tree. All
nodes that are not terminal nodes are middle nodes. For middle nodes, we determine the decomposition level, which is
equal to the number of nodes in the path from the initial node
to that node. The range of hierarchical decomposition is equal
to the maximal decomposition level. Every middle node has
its descendants, and every node except the initial one has its
ascendant. Figure 10 shows the tree of the decomposition presented in Fig. 9.
Topological Hierarchical Analysis
The hierarchical analysis of decomposed network consists of
two parts: terminal block analysis and middle block analysis.
It starts with the initial node (first level of decomposition)
and proceeds down to the next levels according to the connections in the decomposition tree. On each intermediate level,
the type of necessary functions to be calculated at the next
level are determined. At the terminal node, the enumeration
of necessary trees and multitrees (or multiconnections) of the
terminal block is realized. It is possible to organize the exploration of the decomposition tree in such a way that no multiple passes through the hierarchical structure are necessary.
Symbolic results of terminal blocks have a classical sum of
products form. Middle block analysis results are combinations of functions calculated at superior decomposition level.
These functions are not developed and provide final network
description in a nested form. The case of topological approach
to the hierarchical analysis of decomposed Coates graph and
associated algorithms were presented by Starzyk and Konczykowska (7).
Hierarchical Analysis with the Sequence
of Expression Technique
Hierarchical analysis based on matrix approach was presented by Hassoun and Lin (8) and called the sequence of expressions approach. This methodology uses the Reduced Modified Nodal Analysis (RMNA) technique, which allows the
network to be characterized in terms of only a small subset of
the network variables (external variables). The decomposed
network is represented by a binary decomposition tree. During the terminal block analysis, all internal variables are suppressed leaving only external variables necessary for the next
level of processing. This operation, performed analytically, results in symbolic RMNA equations of the terminal block. For
each middle block, the combination of results obtained from
the descendant block produces RMNA equations for the new
block. After this operation is realized, the new block is treated
as a terminal block. As a final result of this procedure, charac-

The hierarchical decomposition approach drastically reduces

the time of analysis and the complexity of symbolic results.
This last aspect is crucial for the further utilization of symbolic expressions (e.g., function evaluation). The total number
of operations (multiplications and additions) necessary for the
evaluation of characteristic functions of the initial network
serves as an evaluation criterion of the decomposition quality.
Another interesting aspect of the decomposition approach
is that large parts of calculations can be realized independently. These parallel processing properties make the decomposition technique very suitable for implementation on multiprocessor machines.
Closely related to the hierarchical analysis of a decomposed network is the problem of network or graph partitioning. The main criterion for evaluating the decomposition
quality is the low complexity of obtained results. Although a
reasonable analysis time should also be preserved, most often
this post-processing time should be minimized after the results are generated and then exploited for multiple evaluations. In the case of hierarchical decomposition being a sequence of bisections, optimal results are theoretically
obtained if each bisection divides the graph into two equal or
similar in size parts. A decomposition tree should be regular
(2n1 blocks on nth level of the decomposition). The minimization of the number of common block nodes for each bisection
is very important, especially in the case of the topological approach, where formulae are particularly simple in the case of
two common block nodes. The number of decomposition levels
depends on the size of the initial network and how sparse it
is. An additional constraint for the decomposition procedure
is the identification of blocks having identical structures. In
the case when multiple block have an identical topology, the
symbolic analysis and storage of results can be executed only
for one of such isomorphic blocks. Of course, the automated
generation of optimal decomposition is a final, unfortunately
not yet achieved, goal. In practical cases, only heuristic strategies are known.
It is possible to realize symbolic hierarchical analysis without decomposition. Starzyk and Zou (9) proposed such an approach based on Coates graph representation. A node exploding technique locally simplifies the graph by node elimination.
Iterative repetition of this step allows us to obtain result for
the total network. Pierzchala and Rodanski (10) developed a
similar method based on the algebraic approach. Internal
variables are suppressed using Gaussian elimination. Locally
optimal pivoting strategy allows us to minimize the number
of symbolic operations of the final sequence of expressions.
APPROXIMATION TECHNIQUES
The hierarchical approach provides a solution for the symbolic analysis of large networks. The exact results are obtained in the nested form. Nevertheless, for some applications, this form of results is not adequate. In many design
problems, identifying dominant elements and their role in
global performance is essential. The interpretation of results
in nested form is not easy. Exact symbolic network functions

SYMBOLIC CIRCUIT ANALYSIS

^
VDD1

227

log Zo

Io = 0.5 mA

^
VDD2

^
R2 = 10 k
^
Q1

Vo^
Zo^

1 gm2
g01 g1

^
CB = 100pF

1/g01

^
Q2

Vi +

g2
CB

^
R1 = 500

gm2
CB

Figure 13. Output impedance

interpretation of symbolic results.

VSS

log f

g2
g1
of

bipolar

cascode

stage

Figure 11. Bipolar cascode stage.

in expanded (flat) form are complex expressions characterized

by a large number of terms even in the case of medium size
networks. Approximation techniques propose to tackle this
problem.
It can be observed that for exact symbolic expressions of
large network, considering given frequency range and order
of magnitude (or range) of element values, the magnitude of
terms can vary significantly. The symbolic approximation
technique consists of discarding smaller terms while keeping
the error (difference between exact and simplified function)
under control. In this approach a trade-off between accuracy
and simplicity of results must be realized. Note that this kind
of strategy is a common practice for the manual design of analog circuits.
Example 2 [proposed by Gielen and Sansen (11)]. Let us
consider a bipolar cascode stage with bootstrap capacitor CB
as presented in Fig. 11. A plot of output impedance for a given

Spice 2G5 Result

Output impedance (log )

109

set of numerical values, as obtained with numerical simulation, is presented in Fig. 12 (bipolar transistors are modeled
with r, gm, and go elements only). Although overall behavior
of the function can be apprehended, it is difficult to predict
the influence of various elements and in particular of the capacitor CB on the output impedance even in the case of such
a simple circuit. Fully symbolic analysis of this network produces a result in the form of the rational function with 36
symbolic terms in the numerator and 14 terms in denominator. Interpretation of such function is not easy. If a 10% maximal error (see next paragraph for precise definition) is accepted, the simplified function has the following form:
Zo(10%) =

gm1 ( gm2 + g1 )( g2 + sCB )

g01 g 1 [ g2 ( gm2 + g1 ) + sCB ( g1 + g 2 )]

(20)

If a 25% error is allowed, the output impedance is given by

Zo(25%) =

gm1 gm2 ( g2 + sCB )

g01 g 1 ( g2 gm2 + sCB g1 )

(21)

The impedance levels and pole and zero estimations can be

easily retrieved from Eq. (21).

gm1
g 1 g01
g
z
= 2
CB
g g
p
= m2 2
g1 CB
g
gm1 gm2

Zo (high f) =
= m2 (low f )
g 1 g01 g1
g1
Zo (low f )
=

108

107

(22)

The general form of impedance magnitude as well as the influence of different parameters is summarized in Fig. 13.
106
101

102

103

104

105

106

107

108

109

Frequency (log Hz)

Figure 12. Output impedance of bipolar cascode stageresults of

numerical simulation.

The principle of approximation (or simplification) involves

finding an expression that is as simple as possible, which, for
a given range of parameter values, reproduces the behavior
of the original function with an error below a specified level.

228

SYMBOLIC CIRCUIT ANALYSIS

The approximation amplitude and phase errors (A and p) can

be expressed as follows:
H(s, x)| |H (s, x) A |H(s, x)|

|\H(s, x) \H (s, x)| p

(23)

for s j, (1, 2), and xi (xi1, xi2), where H(s, x) is the

exact circuit function and H*(s, x) is the approximating
function.
The majority of the approximation methods proposed to
date use a simplified criterion, where the error is measured
only for a given set of circuit parameters x0, called the nominal design point.
Network characteristic functions are expressed as rational
functions in the complex frequency s, with coefficients being
the sums of products of symbolic parameters. The most natural way of approximation seems to use only the most significant terms present in the exact expression. Although it is
easy to define an error of a real coefficient by eliminating
some composing terms, it is more difficult to derive univocal
conclusions concerning the general approximation criteria. In
fact, the function characteristics depend strongly on the position of poles and zeros, and this error should be closely monitored during the simplification process.
Existing approximation strategies can be classified as
follows:
simplification after generation (SAG) and
simplification during generation (SDG).
The SAG [known also as approximation after computation
(AAC)] approach consists of generating the exact symbolic expression and then eliminating the less significant terms. An
obvious disadvantage of such an approach lays in the necessity of generating a large number of unnecessary terms that
not only lengthen the analysis but require a storage space to
save a huge amount of terms for further comparison and elimination.
The SDG [known also as approximation during computation (ADC)] methods were developed to avoid these inconveniences. The generation of symbolic terms in a decreasing order of magnitude is the basis of these methods. The
generation is stopped when the error reaches the specified
level. Proposed methods use the Gabow (12) algorithm of ordered spanning trees generation. In the case of a frequencydependent circuit, this procedure should be applied separately to different powers of s. Reference 13 shows that
mathematical formalism of matroids is well suited to describe
problems of SDG. The approximation techniques were developed by Wambacq et al. (14) and Yu and Sechen (15). More
details on this subject can be found in Ref. 16.
Another category of approximation methods, when simplification starts before the generation process, is called simplification before generation (SBG). A method, proposed by Yu
and Sechen (15) and called sensitivity-based two-graph simplification, involves eliminating some graph branches weakly
contributing to the final results. In the approach presented by
Sommer et al. (17), the simplification starts on the equation
level. Algorithms are proposed, allowing us to eliminate some
terms in the system of equations and in the corresponding
matrix. Because of this simplification, less significant terms
are not generated. The SBG methods can be defined as an

equation (or graph)-based approach, whereas SAG and SDG

are considered as solution-based methods.
Note that a specific procedure should be applied for approximation in cases when matching elements are present in
the network. In fact, some terms may either cancel or result
in a new term with weight largely different than the original
ones. In many situations, better interpretation and understanding of results can be obtained by introducing explicitly
the mismatching between device parameters. For instance,
instead of two symbolic parameters x1 and x2, which are considered as matching ones, the two new parameters x and x
can be used, with x1 x and x2 x x.
DIFFERENT TYPES OF SYMBOLIC ANALYSIS
Sensitivity Analysis
In the practical design process, it is necessary not only to obtain desired circuit performance at the nominal point but also
to control the effect of parameters deviation on this performance. This is especially important in the integrated circuit
design where only limited precision of device parameters is
guaranteed and the postfabrication tuning is, in general, not
possible. Unnormalized sensitivity of a network characteristic
function H with respect to a device parameter x is defined as
H/x. The normalized sensitivity, denoted as SxH, is defined
as
SH
x =

H x
x H

(24)

H is a rational function with numerator and denominator being linear functions with respect to x and can be presented as
H=

N + xNx
N
= 0
D
D0 + xDx

(25)

where No, Nx, Do, Dx are polynomials in s not containing the

variable x.
After the derivation of Eq. (25), we obtain
SH
x =x

N

Dx
D


(26)

The analytical formula for sensitivity can thus be calculated

by adequate sorting of terms in the symbolic expressions for
numerator and denominator.
Switched-Capacitor Networks
Linear sampled-data or time-discrete systems can be described and analyzed using a z-transform. The symbolic approach presented earlier can be extended to such systems.
Switched-capacitor (SC) networks are a specific case of periodically varying sampled-data systems. These SC networks
are composed of capacitors, operational amplifiers, and
switches. For simplicity, let us consider two-phase clocking
scheme. The generalization to a multiphase case can easily
be done.
In the two-phase case, with period T 1/f c, the SC circuit
is observed at times tn nT/2. Because of varying positions
of switches, two different topologies are obtained, one for even
and another for odd switching moments. The behavior of such

SYMBOLIC CIRCUIT ANALYSIS

networks can be described using voltages and charges of capacitors. Using e and o superscripts for even and odd circuit
configurations, the following equations in the z domain describe circuit behavior:

Be I e = 0
De V e = 0
I e = C(V e z1V o )

Bo I o = 0
DoV o = 0
I o = C(V o z1V e )

K.Ch.L.
K.V.L.

(27)

where K.Ch.L. and K.V.L. identify Kirchhoff s charge and

voltage laws, I is the element charge vector, V is the element
voltage vector, B is the fundamental cut-set matrix, D is the
fundamental loop matrix, and C is the diagonal capacitance
matrix.
Symbolic analysis of switched-capacitor networks was proposed by Bon and Konczykowska (18). For each SC circuit, an
equivalent, time-invariant substitute network can be constructed in the following way:
Two time-invariant networks Ne and No correspond to the
SCN in the even and odd time slot, respectively. They
are connected by a common reference node. Currents and
voltages of the new network correspond to charges and
voltages of the initial network (in the even and odd parts,
respectively).
Each switch is replaced by a short-circuit or an opencircuit in Ne and No according to the controlling switching
pattern.
Each capacitance Ci is replaced by a conductance Ci in
both Ne and No.
In parallel with each conductance Ci of Ne (respectively
No), a voltage-controlled current source with a controlling
coefficient Ci z1 is connected. It is controlled by the voltage across the twin capacitance in No (respectively Ne).
The input and output ports of the initial network are
doubled and correspond to ports in each switching phase.
Such a linear, time-invariant network is described by exactly
the same set of Eq. (27) as the initial SC network. Any symbolic method of analysis can be applied to such a network.
Transfer functions H are the rational functions of z2, and a
multiplicative term z1 is present in even to odd and odd to
even transfers. Frequency analysis can be done with z
esT/2.
It is possible to obtain a more general symbolic description
taking into account the finite gain of operational amplifiers.
The only modification consists in replacing the operational
amplifier in both parts of the network by a voltage-controlled
voltage source (VCVS) with a symbolic finite gain A.
Another generalization involves considering a clocking
scheme as symbolic. In this case, instead of replacing switches
by a short- or open-circuits, we replace them with the symbolic conductances. A switch considered as symbolic is replaced by the conductances: Se in the even and So in the odd
part. From the well-known bilinear property of the transfer
functions of linear time-invariant networks, we deduce that
every polynomial involved in the transfer function can be
written as
P(z) = P00 (z) + P10 (z)S + P01 (z)S + P11 (z)S S
o

where P00, P10, P01, P11 are independent of Se and So.

(28)

229

The function
P(z) = P10 (z)S + P01 (z)(1 S)

(29)

is a symbolic expression for the polynomial P covering both

even and odd switching schemes for the selected switch. S is
a binary variable defined as

0 for an odd switching scheme
S=
(30)
1 for an even switching scheme
Functions P00 and P11 are not used in the Eq. (29) and correspond to trivial switching schemes, when the switch is either
open (P00) or short-circuited (P11) in both phases.
Other Types of Symbolic Analyses
Different types of circuit analyses can also be realized in a
symbolic way.
Noise analysis is most often calculated using a small signal
regime. The noise sources must be included in the circuitequivalent scheme. Transfer function from a particular noise
source to the output can be calculated symbolically as any
other transfer function. Total output noise density or total
equivalent input noise density need the calculation of the output variable using multiple noise sources. This type of analysis leads often to complex expressions, and application of approximation techniques is necessary.
Knowledge of poles and zeros is often useful in analog circuit design. Symbolic poles and zeros extraction techniques
were proposed using the pole-splitting hypothesis. A symbolic
Newton iteration can be then applied to refine the pole/zero
location.
Symbolic analysis of weakly nonlinear circuits with multiple or harmonic distortion can also be realized in a symbolic
way. These analyses are based on the Volterra series method.
The functions describing nonlinear elements are expanded
into power series truncated after the first few terms. Higherorder responses are calculated as a correction of the lowerorder responses.
Symbolic analysis of nonlinear circuits in direct current
(dc) domain is presented in Ref. 19.
More details on different types of symbolic analysis and a
large biography on this subject can be found in Refs. 11, 16,
and 20.
APPLICATIONS OF SYMBOLIC ANALYSIS
There are two main types of applications of symbolic methods.
For the first type, the speed-up of calculation is sought when
multiple analyses for the same topology are needed. The second category includes a large variety of situations. The main
interest lays here in the symbolic nature of produced results
and the possibilities of symbolic treatment and reasoning on
these results. The new design methodologies exploit these features more efficiently.
Calculation Speed-Up for Repetitive Circuit Evaluation
Classical applications of symbolic analysis (e.g., statistical
analysis, design centering, and optimization) are the result of
the possibility of the calculation speed-up. The availability of

230

SYMBOLIC CIRCUIT ANALYSIS

symbolic formulae allows us to reduce a computation effort

where multiple calculations for the same topology are required. After the symbolic expressions are generated for a
given circuit structure, the calculation of circuit responses involves evaluating formulae for a new set of parameters. Depending on the necessary flexibility, symbolic functions can
be either compiled and linked to the software (for fixed topology), or generated and evaluated in an on-line way.
Insight Into Circuit Behavior
Symbolic characteristic functions are expressed as analytical
formulae where device parameters are kept as symbols. Contrary to the numerical analysis, where the circuit behavior is
calculated for a particular set of parameter values, the impact
of elements on the circuit performance can be observed directly. In order to be exploited by a designer, a compact, legible form of results is necessary. This often can be achieved
with approximation techniques where the most significant parameters and their role in the circuit are identified. Symbolic
approach may be useful for beginning analog designers helping in evaluation of various topologies and for more experimented ones in their work on new architectures. It can replace the cumbersome manual calculations in the circuit
design process.
One of traditional applications of symbolic simulation is
the support that is offered to the education activities in the
domains of circuit theory and circuit design [see Huelsman
(21)]. The understanding of circuit behavior and the role
played by its elements is crucial in the education process.
Model Generation and Automated Sizing
Working with building-blocks and using libraries of models
can speed up the design process of analog and mixed-signal
circuits. Symbolic simulation can be helpful in establishing
such libraries. The derivation of analytic macromodels, which
when realized manually is a tedious, time-consuming task,
can be done automatically. An approximated version can be
useful for evaluting the functionality and sizing, an exact formulae can serve for the more accurate, final simulation.
These analytical formulae can be further transformed by the
equation manipulation program. They can be automatically
ordered to optimize the efficiency of evaluation or organized
in a sequence of subsets with a minimum number of simultaneous variables, easing the task of solving the design equations. Such an automated analog design using compiled symbolic blocks was presented by Gielen (16). Reference 19
presents behavioral model generation based on approximated
nonlinear symbolic analysis.
Device Modeling and Characterization
Device modeling and characterization is a computationally intensive process that benefits greatly from the use of symbolic
analysis. Parameter extraction involves adjusting values of
model parameters in order to minimize the difference between measured and simulated device characteristics. Two
extraction techniques are generally used: direct extraction
and simulation-based extraction. In direct extraction, model
parameters are determined from linear approximation of experimentally measured data. These data are most often acquired in the form of S parameters and transformed to Z or

Y matrices. On the other hand, analytic expressions for Z or

Y matrices can be obtained with the symbolic analysis of a
small signal scheme. Approximation of these characteristics
(real and imaginary part are used) gives necessary formulae
for direct extraction. These two operations (generation and
approximation of analytic expressions), when done manually,
are cumbersome and error prone and must be repeated for
each modification of the model topology and even when
ranges of parameter values change (approximate formulae
must be verified). Symbolic simulators producing an approximated form of results can be of great help for this purpose. In
the simulation-based iterative extraction, a circuit simulator
is used to provide circuit responses. In this method, repeated,
time-consuming simulations are necessary for the optimization procedure. For the linear extraction, instead of repeating
the analysis for each iteration, it is possible to derive circuit
responses in symbolic form. For each iteration, objective and
error functions can be calculated using these expressions with
different variable values. In this case, the exact value of circuit function is necessary. As rapidity of evaluation is here an
essential goal, a compact, nested form, minimizing the number of operations is sought.
Direct extraction is rapid and simple to execute, but some
nonlinear parameters are difficult to extract so that precision
may be a problem. Iterative methods are very flexible: different devices realized in various technologies can be modeled
with the same tool, and it is easy to include all parasitic, access, and packaging elements in the extraction procedure. On
the other hand iterative methods are time-consuming, depend
on the starting point, and need a robust global optimization
methods, which additionally increases the calculation time.
To obtain an efficient characterization methodology, most often a combination of both methods is necessary. More details
on realizations of extraction tools and methodologies using
symbolic tools, can be found in Ref. 22.
Structural Synthesis and Optimization
Structural synthesis and optimization involve determining
the most advantageous circuit topology in a generally specified class of structures to achieve a given design goal. When
the optimization objective function is specified in an analytical form, symbolic simulation is necessary for objective evaluation. In the case of a classical, numerical objective, a numerical optimization of each examined topology is included in the
procedure. Beside the objective function, which expresses
technical performance of the circuit, the cost of each structure
expressing its complexity must also be evaluated. In the
structural optimization process, a combination of an
objective/cost goal is used most often. More details on the goal
specification and structural synthesis and optimization strategy can be found in Ref. 16.
A specific class of circuit structure optimization is the systematic exploration of a given class of topologies to find the
one best suited for a specified application. Konczykowska and
Bon (23) presented an exhaustive evaluation of integrators
realized using switched-capacitor technique. The goal was to
find integrators most suitable for the high-frequency operation. In design terms, it meant to find integrator structures
with reduced influence of the finite amplifier gain. The symbolic simulation was first necessary to identify all integrator
structures (objective specified in symbolic form) in the class

SYMBOL INTERFERENCE

of circuits composed of one operational amplifier and three

capacitors. Then for all integrators found, an error caused by
finite amplifier gain was symbolically calculated and compared. This procedure allows us to identify structures with
inherently low sensitivity to the finite amplifiers gain.
Other Applications
Different other applications were developed using the symbolic technique for which the symbolic nature of results is essential. Analog circuit design automation with the use of symbolic programs is presented in Refs. 11, 24, and 25. Fino,
Franca, and Steiger-Garcao in Ref. 16 developed a system for
analysis and synthesis of discrete-time circuits and in particular switched-capacitor circuits. Aftab and Styblinski in Ref.
16 showed how statistical analysis can be enhanced with the
symbolic approach. Analog testing and fault diagnosis using
symbolic analysis were studied by Manetti and Liberatore in
Ref. 16.
An overview of the symbolic approach can be found in Ref.
20. In Ref. 16, an extensive review of symbolic methods and
applications is presented.
BIBLIOGRAPHY
1. W. K. Chen, Applied Graph Theory, Amsterdam: North-Holland,
1976.
2. A. C. Davies, Matrix analysis of networks containing nullators
and norators, Electron. Lett., 21: 4849, 1966.
3. S. J. Mason, Feedback theoryFurther properties of signal flow
graphs, Proc. IRE, 3: 920926, 1956.
4. C. L. Coates, Flow graph solutions of linear algebraic equations,
IRE Trans. Circuit Theory, 6: 170187, 1959.
5. P. M. Lin, Symbolic Network Analysis, Amsterdam: Elsevier Science, 1991.
6. K. Singhal and J. Vlach, Generation of immitance functions in
symbolic form for lumped distributed active networks, IEEE
Trans. Circuit Theory, 21: 5767, 1974.
7. J. Starzyk and A. Konczykowska, Flowgraph analysis of large
electronic networks, IEEE Trans. Circuits Syst., 33: 302315,
1986.
8. M. Hassoun and P. M. Lin, A hierarchical network approach to
symbolic analysis of large-scale networks, IEEE Trans. Circuits
Syst. I, Fundum. Theory Appl., 42: 201211, 1995.
9. J. Starzyk and J. Zou, Direct symbolic analysis of large analog
networks, Proc. 39th Midwest Symp. Circuits and Systems, Ames,
IA, 1996, pp. 421424.
10. M. Pierzchala and B. Rodanski, Efficient generation of symbolic
network functions for large-scale circuits, Proc. 39th Midwest
Symp. Circuits Syst., Ames, IA, 1996, pp. 425428.
11. G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits, Norwell, MA: Kluwer, 1991.
12. H. N. Gabow, Two algorithms for generating weighted spanning
trees in order, SIAM J. Comput., 6: 139150, 1977.
13. Q. Yu and C. Sechen, Efficient approximation of symbolic network function using matroid intersection algorithms, Proc. ISCAS, Seattle, WA, 1995, pp. 20882091.
14. P. Wambacq et al., Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits,
IEEE J. Solid-State Circuits, 30: 327330, 1995.
15. Q. Yu and C. Sechen, A unified approach to the approximate symbolic analysis of large analog integrated circuits, IEEE Trans.
Circuits Syst. (I), 43: 656669, 1996.

231

16. F. Fernandez et al. (eds.), Symbolic Analysis Techniques. Applications to Analog Design Automation, Piscataway, NJ: IEEE
Press, 1997.
17. R. Sommer et al., Equation-based symbolic approximation by matrix reduction with quantitative error prediction, Alta FrequenzaRivista di Elettronica, Vol. 5: 2937, 1993.
18. M. Bon and A. Konczykowska, A topological analysis program for
switched-capacitor networks with symbolic capacitors and
switching functions, Proc. ECCTD, Warsaw, 1980, pp. 159164.
19. C. Borchers, R. Sommer, and E. Henning, On the symbolic calculation of nonlinear circuits, Proc. ISCAS, Atlanta, GA, 1996, pp.
719722.
20. G. Gielen, P. Wambacq, and W. Sansen, Symbolic analysis methods and applications for analog circuits: A tutorial overview, Proc.
IEEE, 82: 287304, 1994.
21. L. P. Huelsman, Personal computer symbolic analysis programs
for undergraduate engineering courses, Proc. ISCAS, Portland,
OR, 1989, pp. 798801.
22. A. Konczykowska, Methods and tools for characterisation, modelling and optimisation of electrical devices, Proc. World CongressManufacturing Technology Towards 2000, Cairns, Australia, 1997, pp. 4150.
23. A. Konczykowska and M. Bon, Automated design software for
switched-capacitor ICs with symbolic simulator SCYMBAL,
Proc. 25th Design Autom. Conf., Anaheim, 1988, pp. 363368.
24. R. Sommer, R. Kamitz, and E. Horneber, Qualitative reasoning
in the analog design expert system EASY, Proc. ECCTD, Copenhagen, 1991, pp. 387394.
25. G. Di Domenico et al., BRAINSA Symbolic Solver for Electronic
Circuits, Proc. SMACD Workshop, Bagneux, 1991.

AGNIESZKA KONCZYKOWSKA
National Center for
Telecommunications Studies
(CNET)

SYMBOLIC INSPIRED APPROACHES TO KNOWLEDGE REPRESENTATION. See KNOWLEDGE MANAGEMENT.

FILTER APPROXIMATION METHODS

449

FILTER APPROXIMATION METHODS

This article is concerned with obtaining the transfer function
of an electrical filter that meets certain specifications. These
specifications include discrimination properties, time delay, or
a combination of these. Depending on the complexity and severity of the requirements, one may either find solutions to
these problems in closed form, or one may have to resort to
iterative approximations to find solutions. Once the transfer
function is computed, one must then determine an implementation of the filter, which will be treated in other articles.
The transfer function of a filter is a real, rational fractional
function of the complex frequency variable s j usually
given in one of the two forms:

output/input = H(s) = N(s)/D(s)

n 0 + n 1 s + n 2 s2 + + n n sn
1 + d 1 s + d 2 s2 + + d d sd
n
(s zi )
= H0 di=1
j=1 (s p j )

(1)

where the numerator polynomial N(s) is of degree n and the

denominator D(s) is of degree d. If we express these polynomials in terms of their zeros, these zeros (zi) and poles (pj), if
complex, occur in complex conjugate pairs. The zeros and
poles are much more useful in describing the behavior of the
filter than the polynomial coefficients, and all the poles [the
zeros of D(s)] must be inside the left half of the s plane for stability.
This description is valid for analog filters i.e., those containing resistors, inductors, and capacitors (R, L, and C) or
active R and C components. For infinite-impulse-response
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

450

FILTER APPROXIMATION METHODS

(IIR) digital filters and microwave filters consisting of equal

length open- and short-circuited as well as cascaded transmission line segments, we can still use the preceding expressions,
if we replace the variable s by the expression
S = tanh

s
20

(2)

where 0 is half the sampling frequency in the digital case or

the (common) quarter-wave frequency of the transmission
line segments in the microwave case.
The significant filter performance parameters we are concerned with are the loss, defined as
a = 10 log10 |H( j)|2

(3)

and the delay

=

Im[H( j)]
d
d
arg[H( j)] =
tan1
d
d
Re[H( j)]

(4)

Occasionally, we need the impulse or step responses of the

filter; these can be computed as the inverse Laplace transforms of H(s) and H(s)/s, respectively.
In addition to the restriction on the locations of the poles,
the transfer function H(s) must also meet the following criteria to be realizable by an R, L, and C or a microwave network:
|H(s)|s= j 1

(5)

and the polynomial N(s) must be either pure even or pure odd
(i.e., its zeros must be either pure imaginary or occur in complex quadruplets); furthermore, its degree may not be greater
than that of D(s).
While the first condition is not necessary for digital and
active RC implementations, assuming that it is satisfied does
not restrict the generality at all, since we can always include
an amplifying stage anywhere in the structure and since the
function must necessarily be bounded on the imaginary axis;
hence we shall assume this bound to be unity.
For digital filters, the degree of N(s) is not restricted, but
again for simplicity we shall assume compliance, because otherwise difficulties arise. For IIR digital filters with numerators of degree greater than that of the denominators, please
see Ref. 1.
Finally, N(s) being pure even or pure odd is not strictly
necessary, since zeros may occur in the right half plane and
we can always pair them with zeros in the left half plane and
compensate for this by having poles at the same locations. In
any case, these types of zeros are found useful only in compensating for delay distortion and, as such, can and will be
treated separately. However, no zeros inside the left half
plane are allowed for passive RLC and microwave circuits,
without matching right-half-plane zeros.
As far as IIR digital and active RC circuits are concerned,
N(s) is not restricted to being pure even or odd. Nevertheless,
we shall assume that it is (except if the microwave filter contains unit elements), for the simple reason that it makes for
a unified treatment of all filter kinds and, furthermore, there
does not seem to be any advantage in assuming otherwise.

THE APPROXIMATION PROBLEM

Approximation problems in the design of filters take the following forms:
1. Requirements on the loss only. This is the most common
case and has usually two forms:
i. In the passband the loss should be low (near zero) or
of a specified shape.
ii. In the stopband the loss should be equal to or
greater than some specified amount (usually as a
function of frequency).
2. Requirements on the delay only. This covers the problem of delay equalization and the design of delay lines.
3. Requirements on both the loss and the delay. This is the
most complex case and is usually treated by breaking
it up into first dealing with the loss and subsequently
handling the delay, although methods exist to handle
them simultaneously.
4. Requirements on the impulse or step response. Occasionally we encounter this type of requirement placed
on the time-domain response of the filter. This may
even be combined with simultaneous requirements on
the loss. This is rare, but we shall mention some methods of dealing with cases of this type at the end of this
article.
CLOSED-FORM SOLUTIONS
The Approximation of Loss
To simplify the problem of loss approximation, we rewrite the
expression for the transfer function. If the function magnitude is bounded by 1, then we can write
|H(s)|2s= j = H(s)H(s)|s= j =

1
1 + ( j) ( j)

(6)

where the (s) function is called the characteristic function

and is of the form
(s) = F (s)/N(s)

(7)

Here N(s) is the numerator of H(s) and F(s) is a completely

arbitrary real polynomial of degree d [same as that of D(s)].
The only additional restriction is that F(s) and N(s) should be
relative prime (i.e., have no common roots). It is easy to see
that the zeros of N(s) should be in or near the stopband(s),
while those of F(s) should be in or near the passband. The
relationship between the three polynomials is concisely expressed by the celebrated Feldtkellers equation:
D(s)D(s) = F (s)F(s) + N(s)N(s)

(8)

Given an arbitrary F(s) and an even or odd N(s), one can easily find D(s) such that all of its roots are in the left half of the
s plane.
Butterworth Filters. Butterworth filters are one of the oldest
and simplest solutions to the filter problem. The characteristic function for lowpass filters can be written as
(s) = (s/p )n

(9)

FILTER APPROXIMATION METHODS

451

n = 1 to 6
1

Magnitude

0.8

0.6

n=1

2
0.4
3
4

5
0.2
6

0.25

0.5

0.75
1
1.25
Normalized frequency

1.5

100.1a p 1
100.1a s 1

and n

ln(L)
;
2ln(p /s )

 2 = 100.1a p 1
(10)

The resulting transfer function poles can be computed in

closed form, and so can the actual element values implementing this filter (although we shall not deal with that part of
the design). The poles can be computed as follows:

1 + (s) (s) = 1 + (1)  (s/p )

n 2

(s/p )

2n

= (1)

n+1

/ = e
2

2n

= 0 which yields

j (n+1+2k)

/ 2

Hence, assuming 1,

sk = p e j (n+1+2k)/2n


(n + 1 + 2k)
(n + 1 + 2k)
+ j sin
= p cos
2n
2n

for high-pass filters

for bandpass filters and
for band-reject filters

(stop) band width. A bit more general bandpass case could be

obtained using the characteristic function
(s) = k0 (s2 + 02 )n /sm

with 0 < m < 2n

(13)

but this does not yield closed-form solutions for the transfer
function poles and will be treated later under the numerical
approximation methods. As an example, Fig. 2 shows a sixthorder filter with 40% bandwidth and m 6 (the value we get
with the preceding transformation) as well as m 3. The
second case, which puts three transmission zeros at zero frequency and nine zeros at infinity, yields a much more symmetrical response.
Chebyshev Filters. Chebyshev filters have the low-pass
characteristic function
(s) = Tn (s/p ) =  cosh[n cosh

(s/p )]

(14)

where Tn is a polynomial that is varying between 1 in the

passband (s j, 0 p) and determines the passband
ripple ap as before:
ap = 10 log10 (1 +  2 )

(11)

and those inside the left half plane are the poles we need.
For other than lowpass filter types, we use the well-known
frequency transformation procedure by replacing the normalized frequency s/p by

p /s
(s2 + 02 )/s
s/(s2 + 02 )

2
Figure 1. Butterworth transfer function.

Here p is a normalization frequency, usually the passband

edge. This filter type will have a maximally flat passband and
a stopband loss that is monotonically increasing as we move
away from the passband. The magnitude of the first few functions for n 1 to 6 are shown in Fig. 1. The selection of the
parameters, including the degree n, for a specific set of requirements is nearly trivial. Assuming that a filter requires
not more than ap loss (in dB) up to the frequency p and as
loss from s to infinity, we compute

L=

1.75

(12)

In the latter two expressions 0 (AB)1/2 is the center frequency of the pass (stop) band and (B A) is the pass

The stopband is monotonic, and if we need a loss as at frequency s, then the necessary degree may be computed from

cosh
cosh

L1

(s /p )

where

cosh

(x) = ln(x +

x2 1)
(15)

and L is given by Eq. (10). Fig. 3 shows the computed response of a few low-pass filters with n 1 to 6 and about 1 dB
passband ripple. For other filter types, the transformations of
Eq. (12) are used again. In the bandpass case, the characteristic function will have nth order poles at both zero and infinite
frequencies; a more general case would distribute these unequally.

452

FILTER APPROXIMATION METHODS

40% bandwidth, n = 6 and m = 6,3

1

0.8

Magnitude

m=3

m=6

0.6

0.4

0.2

0.25

0.5

Figure 2. Butterworth bandpass function.

The resulting transfer function singularities can be found

explicitly again, and so can the element values needed to implement the filter. For the poles, we can write
cosh[n cosh

(s/p ) = cosh

sk /p = cosh{(1/n)[sinh

1
+


= ln

= sinh

1+

1
2

1.75

(1/) + j (1 + 2k)/2]}



1
(1 + 2k)
1 1
cosh
sinh
2n
n


1


(1 + 2k)
1 1
sinh
sinh
j sin
2n
n


= cos

(s/p )] = j/

( j/)

1.5

and consequently

and therefore

n cosh

0.75
1
1.25
Normalized frequency

(16)

Inverse Chebyshev Filters. Inverse Chebyshev filters are obtained simply by using the characteristic function


+ j (1 + 2k)/2

(1/) + j (1 + 2k)/2

(s) = k0 /Tn (s /s)

(17)

for lowpass filters. We note that this function will vary be-

n = 1 to 6
1

n=1

Magnitude

0.8

0.6
3
0.4

0.2

5
6

0
Figure 3. Chebyshev transfer function.

0.25

0.5

0.75
1
1.25
Normalized frequency

1.5

1.75

FILTER APPROXIMATION METHODS

453

n = 1 to 5
1

Magnitude

0.8

0.6
3
0.4
2
0.2
n=1

0.5

1.5
2
2.5
Normalized frequency

100.1a s 1

(18)

The element values of the RLC implementation can no longer

be expressed explicitly, especially since multiple implementations exist.
Elliptic (Cauer) Filters. If the filter loss requirements are
uniform in both the passband and stopband(s), the most efficient design is obtained by the use of the Jacobian elliptic
functions. The corresponding characteristic function for a lowpass is given by
( j ) =  cd(nuK1, k1 )

where = cd(uK, k)

(19)

and where cd(x, k) is one of the Jacobian elliptic functions (2)

of parameter k. K and K1 are the complete elliptic integrals
belonging to k and k1, respectively, while K and K1 are the
same and belong to the parameters k 1 k2 and k1
1 k12, respectively. These parameters are defined as follows:
k = (p /s ) and k21 =

10a p /10 1
=L
10a s /10 1

(20)

and, furthermore, the following condition must be satisfied:

K
nK 
= 1
K
K1

4
Figure 4. Inverse Chebyshev transfer function.

tween k0 and in the frequency range s , which is

therefore the stopband. The passband will be maximally flat.
Fig. 4 displays the magnitude of a few low-pass filters with
inverse Chebyshev characteristics. These were designed for a
stopband loss of about 20 dB and degrees 1 through 5. If we
need a passband loss not more than ap up to frequency p and
a stopband loss of at least as, the necessary degree can be
computed from exactly the same expression as in the Chebyshev case, except that k0 is given by
k0 =

3.5

(21)

which can be used to determine the necessary degree n of the

filter. The complete elliptic integrals may be easily computed

using the method of arithmetic-geometric mean (2). These expressions correspond to our usual normalization /p;
other normalizations yield slightly different expressions.
The function in Eq. (19) yields a normalized rational fraction of the form

(s) = 

n/2 s2 + 2

zj
j=1

z j = cd

where

1 + 2p j s2

(2 j 1)K 
n

,k

(22)
and p j = k z j

The poles and zeros are at inverse locations with respect to

the halfway point in the transition band. The preceding expression is for the even degree case; for the odd case, the upper limit on the product is only (n 1)/2 and there is an extra
s multiplier in front. The odd degree case is directly usable,
but in the even degree case the loss will be finite and nonzero
at both zero and infinite frequencies. If that is not acceptable,
a simple frequency transformation

s2

s2
1 2p1 s2

or

s2 s2 2z1

or a combination, where p1 and z1 are the lowest of the values, may be used to shift the highest pole to infinity or the
lowest zero to zero, respectively, but with an attendant increase in the transition bandwidth (3). Note also that the natural modes can again be calculated in closed form, but this is
usually ignored, since the computation of these poles will
need extensive numerical computation in any case and therefore direct root extraction methods are just as convenient.
The j values of Eq. (22), can be readily computed by using
the ascending Landen transformation (2), which converts the
elliptic functions into hyperbolic functions, or the descending
one, which converts the elliptic functions into circular ones.
A particularly detailed description of elliptic functions in the
design of filters is available in Ref. 4. Fig. 5 shows the magnitude of an elliptic low-pass transfer function of degree 7, with
10% transition bandwidth. These functions are not easy to

454

FILTER APPROXIMATION METHODS

n = 7, 10% transition bandwidth

1

Magnitude

0.8

0.6

0.4

0.2

0.25

0.5

0.75
1
1.25
Normalized frequency

Figure 5. Elliptic transfer function.

compute, and if one has no access to some filter design software (5), then many tables of Butterworth, Chebyshev, and
elliptic transfer functions (and element values) can be found,
the most extensive being that in Ref. 6, followed closely by
those in Refs. 7 and 8. Inverse Chebyshev functions are tabulated in Ref. 8.
Rather than using Eq. (21), we may calculate the necessary degree for a set of filter specifications by the (approximate, but very accurate) closed-form expressions

L
1 1 k1/2
L
1
1+
; 2 =
and
=
16
2
2 1 + k1/2
n f (1 ) f (2 ) where
f ()
= (1/ ) ln( + 2 5 + 15 9 + 150 13 )

(23)

Since 2, L, and consequently 1 are usually very small, and

therefore we hardly ever need more than the first term in the
expansion of either 1 or f(), these expressions can be rearranged easily in several ways to be able to compute any of
the four quantities ap, as, p /s k and n, if the other three
are specified.
Functions for other filter types may be easily generated by
the familiar frequency transformation method. Note, however, that in the bandpass case, this approximation usually
does not yield optimal performance. For that, the iterative
method described later is preferable.

1.5

1.75

zero frequency is 0 n/0, where 0 is the normalization frequency. Fig. 6 shows the magnitude of the Bessel transfer
function for degrees 1 through 6, and the corresponding delay
curves are shown in Fig. 7. These functions were all normalized to 0 1. Tables of Bessel polynomials can be found in
many texts (see Ref. 10, for instance).
These characteristics can be combined with an equalminima type stopband, using the technique of Temes and Gyi
(11) (see also Ref. 12) described in detail in Appendix A.
As shown in Fig. 6, the resulting filters have an increasing
loss in the passband; therefore it would be desirable to combine this delay with a flat passband of specified flatness. Consider the general low-pass transfer function H(s)
N(s)/D(s), where D(s) is given and we wish to select an even
N(s) such that the passband (i.e., the region around 0) is
flat. If D(s) is of the form
D(s) = d0 + d1 s + d2 s2 + d3 s3 + + dn sn

(25)

then we can generate the polynomial

G(s) = D(s)D(s) = g0 + g1 s2 + g2 s4 + + gn s2n

(26)

where the coefficients can be computed using

gj =

2j

(1)k dk d2 jk

(27)

k=0

The Approximation of Delay

Next we compute the square root of this function:

Bessel Filters (Maximally Flat Delay). The nth degree Bessel

polynomial is defined by the recursion formula

Bn (s) = (2n 1)Bn1 (s) + s2 Bn2 (s)

= b0 + b1 s + b2 s + + bn s
2

(24)

with starting points B0(s) 1 and B1(s) 1 s.

The transfer function H(s) b0 /Bn(s) can be shown to provide a delay function that is maximally flat at zero frequency
(i.e., the first n derivatives of the delay with respect to the
frequency are all zero; see Ref. 9). The value of the delay at

M(s) = (G(s))1/2 = m0 + m1 s2 + m2 s4 + + mi s2i + (28)

where the mi coefficients can be computed recursively as

m0 = ( g 0 )

1/2

1
and mi =
2

gi

i1

mk mik

(29)

k=1

Truncating this infinite series to a polynomial of degree less

than that of D(s) will yield the required numerator N(s). Fig.
8 shows both the delay and the loss characteristics of a sev-

FILTER APPROXIMATION METHODS

455

n = 1 to 6
1

0.8

Magnitude

n=1

0.6

0.4

0.2

0.5

1.5
2
2.5
Normalized frequency

3.5

Figure 6. Bessel (linear phase) transfer function.

enth-order Bessel (maximally flat delay) transfer function.

Curve a shows the loss when the numerator is a constant.
Curve b illustrates the case when we introduce a fourth-order
numerator to flatten the passband using the aforementioned
procedure. Finally, curve c is what we obtain by the use of
the TemesGyi procedure, when the stopband starts at the
normalized frequency of 0.5.
Rhodes (13) has provided another way of combining flat
delay and flat magnitude in a low-pass filter. His expression
for the overall transfer function for odd degrees is as follows:
H(s) =

Ev{Bn (s)[2Bn+1 (s) Bn (s)]}

Bn (s)[2Bn+1 (s) Bn (s)]

ceding equation, compared to the ninth-degree case obtained

by the method described previously, both having an eighthorder numerator. The Rhodes design has a somewhat steeper
stopband but cannot exchange passband flatness for stopband selectivity.
Maximally Flat Delay for Digital and Microwave Filters. One
cannot use the Bessel polynomials for the design of digital or
microwave filters because of the frequency transformation of
Eq. (2), which will negate the flat delay. However, Thiran (14)
has developed a set of polynomials for generating the equivalent behavior in digital filters (see also Ref. 15). He derived
the transfer function in terms of the variable z ej as

(30)

H0
k
k=0 bk z

where Bn(s) is the nth order Bessel polynomial and the overall
degree will be 2n 1 and Ev. . . designates the even part
of the polynomial inside the curly brackets. For the derivation
and the even degree case, refer to the literature. As a comparison, Fig. 9 shows a ninth-degree filter designed by the pre-

H(z) =
n

bk = (1)k

where

n

n!
2 + i
k!(n k)! i=0 2 + k + i

(31)

n = 1 to 6
1

Magnitude

0.8

0.6
6
5
4

0.4
3
2
0.2

n=1

4
6
Normalized frequency

10
Figure 7. Bessel (linear phase) transfer function.

456

FILTER APPROXIMATION METHODS

n=7
1

80
70

(a) Constant numerator

Delay

0.8
60

0.6
Delay

Loss

50
(c) Equal minima

40

0.4

30
20

0.2
(b) Fourth order flat

10
0
Figure 8. Bessel transfer function with various numerators.

0.5

and where the delay at zero frequency is 0 t0, being an

integer and t0 the sampling time. The disadvantage of this
procedure is that the delay can only be set to discrete values.
The value of H0 is selected to set the loss at zero frequency to
zero, yielding

H0 =

n

k=0

bk =

(2n)!
1
2n
n!
i=n+1 (2 + i)

(32)

An example of this transfer function is shown in Fig. 10,

which displays the loss and the delay of a ninth-order function with a delay of five samples. Note that this filter will
have a finite loss at half the sampling frequency due to the
constant numerator. We can, of course, introduce an arbitrary
numerator as long as it is a symmetric or antimetric polyno-

1
1.5
2
Normalized frequency

2.5

mial in z, without affecting the maximally flat delay property

of the filter, except that this adds another t0n/2 flat delay,
where n is the degree of the selected numerator. We may select this polynomial to provide either an equal-minima type
stopband using the TemesGyi procedure, or a flat passband
using the procedure outlined previously for the Bessel polynomial case. The way to do this is to apply the inverse bilinear
z transform first:
z=

1 st0 /2
1 + st0 /2

(33)

where t0 is again the sampling time, and use the resulting

numerator as the starting polynomial D(s) in Eq. (25) or in
the TemesGyi procedure. Once we have the proper numera-

N=9
30

1.25
Rhodes delay

25

Rhodes loss

.75
Delay

Loss in dB

20

15
.5
10

.25

0
Figure 9. Low-pass with both flat loss and flat
delay.

.5

1.5
2
2.5
Normalized frequency

3.5

FILTER APPROXIMATION METHODS

457

n = 9, t = 5
3

80
70

Delay

2
Loss

60

1
Delay

Loss

50
40

30
20

1
10
0

0.2

0.4
0.6
Normalized frequency

0.8

2
Figure 10. Maximally flat delay digital filter.

tor, we can return to the z domain using the standard bilinear

z transform. Fig. 11 shows the same ninth-order denominator,
combined with three different numerators. One (curve a) has
a numerator with all zeros at z 1 (the Nyquist rate), the
next (curve b) with only five zeros there and four zeros computed to make the passband flat, and finally the third (curve
c) with a numerator to provide an equal-minima type stopband from 0.15 in normalized frequency. Note that the delay
(also shown) is now 9.5 (5 9/2) times the sampling time.
This procedure applies equally well for the design of microwave filters with maximally flat delay, except that t0 here is
one-quarter of the inverse of the quarter-wave frequency.
Furthermore, this flat delay may be combined with an equalminima type stopband or a flat passband, exactly the same
way as in the digital filter case; the only difference is that the
delay will now be independent of the numerator. As opposed
to analog filters, in the digital or microwave case, one may

also obtain flat delay for high-pass filters, which in the microwave case are also bandpasses. The way to do this is to invert
the singularities of a low-pass filter by changing the signs of
the real parts of the poles and zeros in the z domain. For
instance, doing that to the basic filter displayed in Fig. 11, we
get the high-pass shown in Fig. 12.
Thiran has also formulated the problem for obtaining
equal-ripple type delay in digital low-pass filters (16), but the
equations presented have to be solved iteratively since no
closed-form solution is known.
Mainly as a curiosity, we must also mention that there is
a class of microwave filters with exactly linear phase. This is
true for a transfer function of the form (17):
H(s) =

N(s)
(1 + s)d

(34)

n = 9, t = 5
100

Delay

80

(a)
Constant
numerator

(b)
Fourth order flat

3
Delay

60
Loss

(c)
Equal
minima

40

20

0
0

0.2

0.4
0.6
Normalized frequency

0.8

Figure 11. Maximally-flat delay digital filter with

various numerators.

458

FILTER APPROXIMATION METHODS

N = 9, T = 5
100

80

4
Delay

60

40

20

Delay in s

Loss in dB

Loss

0
0

.2

.4
.6
Normalized frequency

Figure 12. Maximally flat delay digital high-pass.

where N(s) is an arbitrary even or odd polynomial of degree

not more than d and s is as in Eq. (2). The value of the delay
will be dt0 /4, where t0 is the inverse of the quarter-wave
frequency in Hz, as before. Again, N(s) may be selected to
provide either a flat passband or an equal-minima type stopband. If the circuit is selected to consist of d unit elements,
then N(s) [(1 s2)]d, which will yield H() 1 and the
circuit will consist of d unit elements, all of the same characteristic impedance, in cascade (which, of course, has constant
delay). Other numerators can be used to provide flatter passband or equal-minima stopband. Also available are high-pass
(actually bandpass) filters of various kinds. Fig. 13 shows the
loss of four versions of a seventh-order filter with a flat delay
of 1.75 s. The discrimination properties of these filters leave
a lot to be desired. One interesting feature of this group of
transfer functions is that converting them into digital form,

.8

using the bilinear z-transform method, they will become finite

impulse response (FIR) filters, which helps to explain their
constant delay property.
The Bessel polynomials as well as those developed by
Thiran may also be used for the approximation of delay lines
with maximally flat delay. This may be simply obtained by
using a transfer function of the form
H(s) =

Bn (s)
Bn (s)

or H(z) =

zn Bn (z1 )
Bn (z)

(35)

where Bn(s) is the nth degree Bessel polynomial and Bn(z) the
equivalent Thiran polynomial. The resulting delay at zero frequency will be twice that calculated previously, and the magnitude of H(s) and H(z) will be unity, of course, at real frequencies.

N=7
100

Loss in dB

80
Highpass
(bandpass)

60

Fourth order
flat highpass

40

Lowpass

Fourth order
flat lowpass

20

0
Figure 13. Constant delay microwave filter transfer functions.

.2

.4
.6
Normalized frequency

.8

FILTER APPROXIMATION METHODS

ITERATIVE SOLUTIONS
All of the results presented so far are closed-form solutions
(i.e., solutions that can be computed exactly in a finite number of steps). In many situations, we do not have closed-form
solutions and must rely on iterative optimization procedures.
We will find many different procedures useful in different circumstances. No general-purpose procedure has been found yet
that can be applied to all problems with guaranteed success.

the expression for z to obtain the (s) characteristic function.

For a real z0, it has a multiple zero inside the passband, and
if all zj values are also real, it has poles in the stopbands. The
range z 1 is off limits for the poles. We can select z0 in
such a manner that the function values at the ends of the
passband (0 and , respectively, in terms of z) are equal:

z0 =

Flat Passband Loss

The most common requirement in the passband is a flat loss,
and this may be approximated either in the maximally flat or
the equal-ripple sense. This can be combined with the following types of approximation in the stopband(s):
1. Monotonically increasing loss as we move away from
the passband. This combined with maximally flat passband is the familiar Butterworth characteristic. If we
combine it with equal-ripple type passband, we have
the equally familiar Chebyshev type of filter.
2. Equal-minima type stopband(s). This again can be combined with the maximally flat passband, which yields
the inverse Chebyshev type filter; while combining it
with the equal-ripple type passband leads to the elliptic
(or Cauer) filter type.

3. A more general stopband type is the piecewise-constant

loss specification. Again, this may be combined with either of the aforementioned passband characteristics,
and a very rugged and fast converging approximation
procedure is available for handling both cases (18).
To explain this procedure, we will use a change of variable
to place the passband in evidence:
z = (s +
2

A2 )/(s2

B2 )

(36)

where A is the lower edge and B is the upper edge of the

passband, assuming a bandpass filter for generality. (This
variable z should not be confused with the variable used in
the digital filter design procedure. Unfortunately, the literature uses the same letter for both.) Low- and high-pass filters
can be handled in an obvious manner; furthermore, in the
case of digital or microwave filters, A and B will be replaced
by A tan(A /20) and B tan(B /20), respectively.
From the preceding expression we can see that the variable z is pure imaginary in the passband and will vary between 0 and , while it will be real for both the lower and
the upper stopbands. In particular, it will vary from A /B
to 0 in the lower stopband and from to 1 in the upper
stopband.
Now we are ready to form a function, first for the maximally flat passband:

(z2 + z2 )d/2
(z) = 0 d/2 0
2
2
j=1 (z z j )

(37)

This is an even rational fractional function in z and hence it

is also an even rational one in terms of s when we substitute

d

2
j=1

d2

zj

(38)

Note that for low-pass or high-pass filters, z0 may be selected

to be zero or infinity, respectively, but need not. A finite z0
will then provide a maximally flat point inside the passband;
and the loss will be nonzero at zero or infinite frequencies
respectively, yielding nonequal terminations (matching filters). Returning to the general bandpass case, the passband
will be maximally flat and the stopband will have transmission zeros at the values specified by zj:
2j = (A2 z2j B2 )/(1 z2j )

(39)

Now it is very simple to modify the zj values and the multiplier 0 to obtain the required stopband behavior.
This procedure yields an even degree N(s); for the odd degree case we need to modify the (z) function slightly. We
have to replace one of the factors in the denominator by

All of these filter types have been treated previously.

459

(1 z2 )(z2 2 )

(40)

and modify the value of z0 accordingly:

z0 =

1
d

d
1
2
j=1

d2

zj

(41)

This will yield the same overall even degree d, but the numerator polynomial N(s) will be odd and of degree d 1. Odd
overall degree is also possible by the use of what is called
parametric design and will be considered under that heading
later.
Equal-Ripple Passband Loss
Let us now consider the equal-ripple type passband. We first
recognize that the variable z is pure imaginary in the passband; hence the function
(z j + z)/(z j z)

(42)

is of magnitude 1 (if zj is real) and its phase varies from 0 to

as varies from A to B. Consequently, the function:

e j =

d (z + z)

j
j=1

(z j z)

(43)

will also be of unity magnitude and will vary from 0 to d

in the passband. We can therefore form the function

1
cos = (e j + e j ) =
2

d

j=1 (z j

d
+ z)2 + j=1 (z j z)2
d
2
2
j=1 (z j z )

(44)

460

FILTER APPROXIMATION METHODS

This function is going to vary between 1 and 1 in the passband, and it is an even rational function of z (the odd terms in
the numerator cancel) and therefore will be an even rational
function of s after substitution. The proper characteristic
function therefore is
(z) =  cos

(45)

where is a constant, determining the passband loss ripple.

Again, the degrees d and n are equal and even; for odd degree
n, we must modify ej by replacing one of the factors by

(1 + z)(z + )

(46)

(1 z)(z )

It is clear that will still vary between 0 and d in the passband, and once we substitute z as per Eq. (36) above, the resulting () will still have an even numerator of degree d and
now an odd denominator of degree n d 1. For a microwave filter that contains u unit elements, we must further
include the factor

z

+z
zu z
u

u2

(47)

where zu is given by
2A + 1
2B + 1

z2u =

(48)

in order to have a factor (1 s2)u in N(s), which is necessary

for the implementation of unit elements. Note that the value
of zu is between and 1 [i.e., in the previously forbidden region and that for the purpose of the computation of the loss,
we can replace 1 s2 by (1 s)]. Since in the stopband(s)
the variable z is real, we introduce the new variable for the
purpose of computing the loss:
= ln z = ln[(2 A2 )/(2 B2 )]

(49)

and since the loss is given by

a = 10 log10 (1 + 2 ()) = 4.343 ln(1 + 2 ())

(50)

and

e =

d

i=1

coth

i
2

where j, therefore we obtain


() =  cosh =
2


d

d



+
coth i
tanh i
2
2
i=1
i=1

(51)

!
(52)

very good approximation [this approximation is not necessary; we can simply solve Eq. (53) for ]

a
= 8.686 ln(/2) + 8.686

= 8.686 ln(/2) + 8.686

i=1

a
= 8.686 ln  + 8.686 ln cosh

(53)

Next we realize that in the stopband is usually large, and

we can approximate cosh() by e /2, and consequently to a

 

ln coth  i
2 

(54)

The loss is therefore given as the sum of a number of identical

functions that are just shifted along the stopband () axis.
The resulting characteristic function will be of an even degree
for general bandpass filters. Odd overall degree is also available by the use of parametric design techniques and will be
considered later under that heading.
The zi values represent the variable (free) transmission
zero locations, although any number of them may be fixed by
the designer. Our job is to determine how many of these variable zeros we need and where to put them. We first plot the
stopband requirements as a function of the variable . The
first objective is reached by replacing these frequency-dependent stopband requirements by an averaged constant requirement, which can be satisfied by an elliptic type design. From
the closed-form solution of this problem we can get an estimate of the required number of zeros, from which we subtract
the number of fixed zeros and then distribute the additional
ones as uniformly as possible over the stopband(s).
Next we locate the loss minima between any two consecutive transmission zeros (including fixed zeros) and evaluate
the loss at all breakpoints (where the requirement changes)
and subtract the required loss values from all of these. This
yields a short list of frequencies and excess loss values. If
there is a minimum as well as a breakpoint(s) between two
zeros, we discard the pair with the larger excess loss value
until we have only one pair between the zeros. Next we consider the fixed poles. If there are minima on both sides of the
fixed pole, we discard the one with the higher excess loss.
Note that those zeros we explicitly put to zero or infinite frequencies (zi or 1, respectively) are fixed by definition, but
they are not counted here, since the region between them is
of no interest. This way, the number of items in this list of
excess loss minima is reduced to the number of movable zeros
(plus one in the bandpass case).
If the remaining excess loss values (all but one in the bandpass case) are all equal and positive (an error of 0.5 dB is
usually acceptable), we are done and the approximation converged. Otherwise, we average the excess loss values and
compute the deviation from this average and denote it by
ak. The actual iteration is performed by first computing the
derivative of the loss at each of these frequencies (ak /i),
with respect to the parameters of the variable zeros zi. Finally, we solve the approximate equations for the necessary
changes i in these parameters as follows:
a
i

and since we can usually neglect the 1 next to the characteristic function, we can have

i =
ak

k = 1, 2, . . .

(55)

Such a routine has been described by Smith and Temes in

their classic paper (18) and in a slightly modified form to handle piecewise linear requirements by Bell (19). Note that the
simplicity of the expression makes it easy to compute the derivatives that are necessary for the optimization. This procedure has been found to be fast and accurate, hardly ever need-

FILTER APPROXIMATION METHODS

ing more than 10 iterations to converge, and, of course, has

been further generalized to handle multiple zeros, the digital,
microwave (perhaps containing unit elements), and parametric filter cases and their combinations as well. Another extension, described in the literature (20), permits the program to
exchange excess loss for wider passband automatically.
Returning to the maximally flat passband case [Eq. (37)],
that expression is simple enough to be handled directly, although for uniformity, the new variable ln z is usually
introduced there also. For the details, we refer to the book by
Daniels (21).

461

which gives us the two (in fact, a double) real roots in the s
domain. The resulting characteristic function yields a filter
that is called even parametric. To find out how much this approximation is going to affect the equal-ripple property of the
transfer function, let us express the relative error in the passband, where z is pure imaginary (z jy):

( + y )
2

error =

a2 a2
1 2
2

+y

(a21 + y2 )(a22 + y2 )

a2 a2
+ 1 2 2 a21 a22 y2

(a21 + y2 )(a22 + y2 )

(59)

Parametric Bandpass Filters. As mentioned previously, bandpass filters designed by the methods outlined always turn out
to be of even degree. In some instances it would be desirable
to have an odd degree filter, which means a characteristic
function with an odd degree numerator (i.e., a root on the real
s axis). Also, for generating an LC structure with the absolute
minimum number of inductors, we often need a characteristic
function numerator with two real axis zeros. The explanation
of this fact will have to wait until the article on the LC implementation of bandpass filters.
In any case, in the equal-ripple type passband approximation procedure, both of these objectives can be achieved (22)
by the introduction of another factor

r z
+z

z
+z

or

(56)

<<1
Since its exact value is of minor importance, we usually select
1/2. Let us consider now the effect of this additional factor. First note that these factors have the difference terms in
their numerator, not in the denominator, as all the others.
Let us consider the second case first, where we must also have
an odd multiplicity of transmission zeros at both zero and infinite frequencies [i.e., we have the factor of Eq. (46) in the
definition of the characteristic function]. This characteristic
function will now have a factor (2 z2) in the denominator,
while the numerator can be written in the form

( z)2 (1 + z)( + z) (z j + z)2
j

+ ( + z) (1 z)( z)

(z j z)2

(57)

We can see that the second term will be negative between

z 1, while the first term is nonnegative there but has
a double zero at z inside this range. Consequently, the
function is negative at z but positive at z and z 1;
that is, it must have two zeros, a1 and a2 such that
< a1 < < a2 < 1
Furthermore, since the complete numerator will be an even
function of z, it must, in fact, contain the factors: (a12 z2)(a22
z2). At this stage, we can simplify the factors in the transfer
function by writing

a2 a2
1 2
2

z2


max error =

2 + a1 a2
(a1 + a2 )

2
1

(60)

Let us consider a very wide passband ( 0.25) filter with

0.5 and three transmission zeros at both zero and infinite
frequencies and no finite zeros. For this simple filter we calculate
a1 = 0.4754975 and a2 = 0.5225556
which gives

Assuming a passband ripple of 0.5 dB, this introduces an error that is less than 0.001 dB. This filter can be implemented
using only two inductors and four capacitors, instead of the
three inductors and three capacitors needed for the nonparametric case. For more complex filters and narrower passbands, the error will further decrease rapidly, because the
values of a1, a2 and get closer and closer.
To get the odd parametric case, we introduce the squareroot factor specified previously and note that one of the multiplicities of the transmission zeros at zero and infinity must
be odd, the other even. Again expanding the characteristic
function, we see that the denominator will contain the factor
2 z2, while the numerator can be written in the form

( z)( + z)n z (1 + z)n i
(z j + z)2
j

+ ( + z)( z)n z (1 z)n i

(a21 z2 )(a22 z2 )
=
2 z2

This function has a maximum at y2 a1a2 and therefore

max error = 0.002084

in Eq. (43), where is again in the forbidden zone:

(58)

(z j z)2

(61)

where one of ni and nz is odd, the other even. If nz is odd, then

the second term will be negative in the range z 1 and
zero at the boundaries, while the first term changes sign at
z . Consequently, the sum is positive at z and negative
at z 1; hence it must have a zero in between, say at a.
Furthermore, since the numerator will be an even function of
z, it must therefore have a factor (a2 z2). A similar result
can be observed if ni is odd. Now if we combine this numerator
factor with the irrational parts of the denominator, we get, if
nz is odd, the factor

(a2 z2 )
( z2 )( 2 z2 )
2

(62)

462

FILTER APPROXIMATION METHODS

and, if ni is odd, the factor

(a2 z2 )
( 2 z2 )(1 z2 )

(63)

Substituting Eq. (36), we get, in terms of the variable s, after

some rearrangement and saving for a multiplier,
A s2

s B2 s2
in the first case and
A  s2

B2 s2

(64)

similarly for the other case, yielding the real root we need in
the characteristic function. Again the approximation is very
accurate and gets better with increasing degree.
For the maximally flat case, the situation is much simpler;
we may just modify the function to read

(z) = 0

(z2 + z20 )d/21 (z2 a2 )

d/2 2
2
j=1 (z z j )

in the second case, where A and B are both positive and very
close and so are A and B. Now we can again simplify:
A s2 A

= s
B
B2 s2

preferably in factored form. This will provide us with substantially better control over numerical accuracy and a direct control over the question of stability. Here we are basically reduced to the two possibilities of the least pth, or the minimax
optimization procedures of classical optimization theory.
There are some other methods (the Pade method comes to
mind as an example), but none of them has been found to be
of general use.
The basic options we have here depend on our choice of
error function. The most often cited such error function we
must minimize is of the form

E = (1 )
w(i )(Hr (i ) H(i )) p

(65)

and get an even parametric case, where a is again in the forbidden region, and just introduce a linear factor in terms of s
for the odd parametric case.
The algorithm to locate the movable transmission zeros
can readily be modified to handle these parametric cases as
well.
Finally, for completeness we may mention that an even
parametric approximation is possible if the multiplicities of
the zeros at zero and infinite frequencies are both even, but
the resulting transfer function turns out to be useless.
Low-Q Approximations. All the standard approximating
functions (Butterworth, Chebyshev, or elliptic) have some of
their poles (those closest to the passband edges) too close to
the imaginary ( j) axis, which may cause difficulties in active RC implementations. This can be alleviated by replacing
the two or three poles closest to the imaginary axis by a multiple pole with multiplicity two or three, which will not be
quite so close to the axis. To maintain the nature of the approximation, the other parameters must, naturally, be readjusted also. This needs an iterative approach, which is of no
particular interest to us here except to mention that the resulting functions have been extensively tabulated in Refs.
2325.
Arbitrary Loss Shape
When we come to the question of completely arbitrary loss
shapes, we have fewer tools to simplify the problem. We must
go back to the original equation [Eq. (1)] and deal with that,

v(i )(r (i ) (i )) p

(66)

where Hr() is the required transfer function magnitude and

H() is the actual magnitude, r() is the required delay (to
make the approximation more general), () is the actual delay, w() and v() are the (user-specified) loss and delay
weights, respectively, and is a parameter allocating the error of the loss and the delay. The (even) parameter p is also a
user-selected parameter, controlling the approximation. Some
people prefer to work with loss, rather than transfer function
magnitude, but then the stopband causes problems since if
the actual loss is much higher than the required one, that
adds to the error, while in fact it is quite acceptable. Consequently, if the loss is greater than the required value, we usually set the corresponding w() weight to be zero. The problem with this choice is that it makes the error a nonanalytic
function, causing problems with the iteration methods one
uses.
The other, minimax, method can only handle one quantity
at a time (i.e., either the loss or the delay). Here we must
minimize the function
max w(i )|Hr (i ) H(i )|

(67)

or a similar one for the delay, over the whole frequency range.
See Appendix B for a brief description of several of the more
useful optimization strategies in use today for this problem.
Constant Delay Approximation
Consider first the problem of constant delay. The maximally
flat approximation has a closed-form solution, which was described previously. Equal-ripple approximation of a constant
delay is possible, using the following approximation technique.
There is a closed-form solution to the problem of interpolating a linear phase function at equidistant points (13). Assuming that the points are multiples of the step and the
phase is required to be proportional to , the interpolating
polynomials can be obtained by the recursion formula:

Pn+1 (s, ) = Pn (s, ) +

tan  


(s2 + (n)2 )
P (s, )
(2n + 1)(2n 1) n1
(68)

with initial conditions P0(s, ) 1 and P1(s, ) 1 (tan

/ )s. The value of is restricted to /2 by stability considerations. If one plots this type of approximation, it is clear

FILTER APPROXIMATION METHODS

that while the delay will not be equal ripple, it will definitely
have the correct number of extrema, and these are going to
be close to the interpolation points. Consequently, it is a relatively easy matter of locating these extrema and then using
an iterative procedure to make them all equal. Such a procedure has been implemented and takes very few (three to five)
iterations to converge. The resulting polynomial will be the
denominator D(s) of the transfer function, and we can still
select the numerator to shape the loss in the pass- or stopband. In particular, both the equal minima solution of TemesGyi as well as the flat passband solution, outlined for the
maximally flat case, are available. Fig. 14 shows a seventhdegree equal-ripple delay function over the frequency range
from 0 to 7.5, normalized to unity average passband delay.
This can be combined with a constant numerator, or a fourthdegree numerator yielding flat passband loss, obtained by the
procedure outlined previously. Finally, the third possibility is
a sixth-degree numerator yielding an equal-minima type stopband from normalized frequency 6.5 calculated using the
TemesGyi procedure and providing a minimum loss of about
48.9 dB, all shown in Fig. 15.
The polynomials of Eq. (68) can, of course, be used directly,
since the delay deviation from a constant, while not exactly
equal ripple, will be found satisfactory in most cases. Everything that we have said about equal-ripple delay functions
will work equally well with these polynomials. Additional
methods of simultaneous approximation of linear (or arbitrary) phase and flat magnitude may be found in Ref. 13.
Naturally, this procedure works for low-pass filters, but for
bandpasses, there is no closed-form interpolating polynomial
available, and due to the arbitrary intercept point of the linear phase line, we have another variable to be concerned
about. An approximate procedure for bandwidths of about
25% or less is to shift the low-pass poles and zeros by the
amount 0 parallel to the j axis, where 0 is the center of
the new bandpass filter. Clearly, all finite singularities of the
lowpass must be smaller than 20. The number of zeros of the
lowpass at infinity will be doubled and (if there is more than
one) are split up such that the bandpass has about three
times as many zeros at infinity as at zero. The resulting filter

463

will have the same delay as the low-pass and, in addition, will
be close to having an arithmetically symmetrical frequency
response (17). A direct iterative approximation method has
been described for equal-ripple delay bandpass design by Ulbrich and Piloty (see Ref. 26, which also contains tabulated
results for low-pass and bandpass filters).
Delay Lines. As explained previously in the discussion of
Bessel polynomials, these results may also be used to obtain
a delay line (i.e., a transfer function with H 1) by simply
using a numerator polynomial N(s) D(s) yielding twice
the delay.
Delay Equalization. Transfer functions of the form of Eq. (1)
will have a phase characteristics that will usually be far from
linear. This can be seen from the fact that minimum phase
transfer functions (those that have no zeros in the right half
of the s plane) have a unique relationship between loss and
phase (27). This can be expressed in the form
() =

a(x)
dx
x2 2

(69)

where () is the phase and a() is the loss in nepers (named

after Napier, the discoverer of the natural logarithm). That
is, a() lnH( j) and we take the principal value of the
integral at the pole x . For instance, if a() 0 for
0 and a() A elsewhere (an ideal low-pass filter that cannot be realized but may be approximated as closely as required), the corresponding minimum phase will be
() =

+ 0
A
ln

| 0 |

(70)

and, consequently, the delay is

() =

1
2A0
( 0 )2

(71)

1.005

Delay

0.995

0.99

0.985

0.98

0.975

3
4
5
Normalized frequency

Figure 14. Equal-ripple approximation of constant delay.

464

FILTER APPROXIMATION METHODS

100

Constant numerator
80

Loss (dB)

Equal
minima
60

40
Fourth order flat
20

0
Figure 15. Equal-ripple delay transfer function
with various numerators.

2.5

which is far from constant. Consequently, once the required

loss characteristics have been achieved, the minimum delay
is determined and our only choice left is to add additional
circuitry to approximate the required delay (if, in fact, the
delay must also meet certain criteria). When the need arises
for the equalization of a computed or measured delay curve,
we basically use the second half of Eq. (66) to define our error
function:
E=

v(i )(r (i ) (i )) p

(72)

where r is the required delay and the summation goes over

the frequency range of interest. We can usually select these
at our convenience, but if we are dealing with measured delay, the measurements usually also specify the frequencies.
The exponent p is going to control the nature of the approximation, and the weight function v() is also ours to choose.
This is a relatively simple procedure due to the relatively simple dependence of the delay curves on the quadratic coefficients, and the solution is routine (see, e.g., Ref. 5). Namely,
the transfer function of a delay equalizer (allpass network) is
most often written in the form
H(s) =

 1 a s + b s2
k
k
2
1
+
a
s
+
b
k
ks
k

(73)

where all coefficients are positive and sometimes (in the case
of a lowpass function) we may have a linear factor (1
a0s)/(1 a0s) as well. The magnitude of H is unity for all
frequencies, while the delay can be written as

() =


2Qk [1 + (/k )2 ]
2
+
1 + (/0 )2
[1 (/k )2 ]2 + Q2k (/k )2
k

(74)

where we have used the notation a0 1/0, ak Qk /k, and

bk 1/k2. We have plotted a few cases with various Qk values

7.5
10
12.5
Normalized frequency

15

17.5

20

in Fig. 16 to show their general behavior. The problem is to

select the number of sections k to be used and the parameters
Qk and k such that the delay of the equalizers added to the
delay to be equalized is flat. A simple example shows the
equalization of the delay of the seventh-order elliptic lowpass, with magnitude shown in Fig. 5. We have selected three
second-order sections to equalize the delay over 90% of the
passband, and the results are shown in Fig. 17. The curves
shown are the original delay [fairly close to the one we would
get from Eq. (71)], the delay of each of the three equalizer
sections, and finally their sum as the equalized delay. The
approximation was performed in the least squares sense, using Eq. (72) with p 2 and unity weighting.
For digital filters, the exact form of the equations is somewhat different, since the general allpass function is of the
form

H(z) =


0 + z1  2k + 1k z1 + z2
1 + 0 z1 k 1 + 1k z1 + 2k z2

(75)

If we designate the poles of a quadratic factor as p1,2 rej

and the zeros as z1,2 r1ej, where 0 r 1, then the delay
can be written as
=

r2 1
r2 1
+
2
1 + 2r cos( ) + r
1 + 2r cos( + ) + r2

(76)

for each of the second-order factors. For the linear factor, we

just have one of the terms with 0. While the specific equation is different from that of the analog system, the shapes of
these delay curves, shown in Fig. 18 for 90 and various
values of r, are quite similar, and so is the iterative procedure.
The minimax approximation to an arbitrary delay shape is
also possible, since it is easy to generate a starting approximation that has the requisite number of extrema by selecting
high enough values for the starting Qks. One approach has
been described by Deczky in Ref. 28.

FILTER APPROXIMATION METHODS

465

Q = 0.5, 0.75, 1.0, 1.25

9
8

Normalized delay

7
6
5
4
3
2
1
0

0.25

0.5

0.75

1.25

1.5

1.75

Normalized frequency

Figure 16. Delay of second-order delay sections.

APPROXIMATION OF FIR DIGITAL FILTERS

Depending on the parity of N we have the following precise

forms. For even N and symmetrical coefficients,

Formulation

FIR digital filters have to be treated differently than IIR filters. IIR filters have a rational transfer function and, as such,
can be obtained from analog filter functions, as we have done
previously. FIR filters, on the other hand, are represented by
a polynomial in z ejT and have no analog equivalent (except
the special case mentioned previously). The significant advantage of FIR filters over their IIR counterparts is that FIR filters may have exactly linear phase. This is easily observable
if the coefficients of the polynomial have even or odd symmetry:

H(z) =

ak zk

with aNk = ak

or aNk = ak

(77)

H() = e

jNT /2

aN/2 +

N/2


2ak1 cos T (k N/2)

(78a)

k=1

and for antimetrical coefficients

H() = e j(NT /2 /2)

N/2

2ak1 sin T (k N/2)

(78b)

2ak cos T (k N/2)

(78c)

k=1

while if N is odd, we have

H() = e jNT /2

k=0

(N1)/2

k=0

9
8
7

Delay

6
5
4
3
2
1
0

0.25

0.5
0.75
Normalized frequency

1.25

Figure 17. Delay equalization of low-pass using a

three-section equalizer.

466

FILTER APPROXIMATION METHODS

r = 0.4, 0.5, 0.6, 0.7

0.7

Delay

0.6

0.5
r = 0.4

0
Figure 18. Delay of digital second-order delay sections.

0.2

for symmetrical coefficients and

H() = e j(NT /2 /2)

(N1)/2

2ak sin T (k N/2)

Windowed Design. The ideal low-pass filter transfer function is of the form

sin(n) = sin() cos((n 1)) + cos() sin((n 1))

cos(n + /2) = 2 cos(/2) cos(n) cos(n /2)

k cosk

(81)

k=0

and where Q() is one of the four functions:

Case 1:
Case 2:
Case 3:
Case 4:

1
sin()
cos(/2)
sin(/2)

M
M
M
M

and has a corresponding impulse response

hd (n) =

sin n 
c

c n

with hd (0) =

(83)

h(n) = hd (n) for |n| (N 1)/2

= 0 elsewhere

(84)

(80)

where

k cos(k) =

(82)

= 0 for c <

which is, of course, of infinite length. We can, however, truncate it to a symmetrical set of finite length:

in the last three of the preceding equations, we see that all

four expressions can be represented in the general form
(where we have ignored the phase factor):
H() = Q()P()

H(s) = 1 for 0 c

(79)

sin(n + /2) = 2 sin(/2) cos(n) + sin(n /2)

k=0

(78d)

for antimetrical ones. Here T is the inverse of the sampling

frequency, which we can simply set to unity as normalization.
All of these have exactly linear phase and a delay of NT/2.
Ignoring the phase terms for the time being, we see that all
of these expressions are trigonometric series, and the last two
of these contain terms of the form sin(n 
) or cos(n 
).
Using the following trigonometric identities recursively,

0.8

method is not a true approximation technique; it is more a

trial-and-error procedure and will be treated only briefly here.

k=0

P() =

0.4
0.6
Normalized frequency

= N/2
= N/2 1
= (N 1)/2
= (N 3)/2

Approximation
There are basically two methods of FIR filter design in use at
the present time. One is the windowed design, and the other
is the equal-ripple approximation method. The windowed

which may be the coefficients of a (linear phase) FIR filter.

One can, of course, determine the corresponding frequency response, but that is not our direct concern here. Suffice it to
say that the resulting filter will have very limited stopband
suppression, and increasing N will not help here due to the
Gibbs phenomenon familiar from Fourier series theory. Many
people have come up with ideas for shaping these coefficients
in one way or another to alleviate this problem. This simply
means using the modified coefficients

h(n)
= h(n)w(n)

(85)

where w(n) is a window function and h(n) are the coefficients specified previously. We have seen more than 30 different window functions proposed (29) and will mention here
only a few. All equations are valid for odd N values; for even
N they must be modified slightly.

FILTER APPROXIMATION METHODS

The window function that does nothing [i.e., w(n) 1] is

called the rectangular window. The triangular (or Bartlett)
window is defined as
w(n) = 1

|2n|
N+1

where is an adjustable parameter. The w(n) coefficients are

unscaled; they should be scaled by dividing them by w(0). The
empirical relationship between the parameter and the stopband loss as is given by

(86)

= 0.0000769(as )2 + 0.0248as + 0.330 for as 60 dB

= 0.0000104(as )2 + 0.0328as + 0.079 for as > 60 dB

The Hamming window is

2n
N1

(87)

4n
2n
+ 0.08 cos
N1
N1

(88)

w(n) = 0.54 + 0.46 cos

The Blackmann window is
w(n) = 0.42 + 0.5 cos

Finally, the Hann (raised cosine) window is

w(n) = cos2

n
N+1

467

(95)

The Taylor window is a simplified version of this that attempts to hold a subset of the sidelobes constant and permits
the rest to decrease at 6 dB per octave. For the exact formulation of these and many other windows, please see the references.
For other than low-pass filters, one must appropriately
modify the h(n) function before applying the windowing. For
instance, for a bandpass filter with passband from A to B,
the ideal impulse response is

(89)

The last three are all examples of a large family of windows,

all in the form of a cosine series. Many more are described in
Ref. 29.
The Kaiser window is defined as


2n 2 
I0 1
N1
(90)
w(n) =
I0 ( )

The value of is related to the desired minimum stopband

loss through the following empirical relationship. If the required stopband loss in dB is as, then

hd (n) =

1
A
[sin(B n) sin(A n)] with hd (0) = B
n

(96)

Figures 19(a) through 19(h) illustrate some of these windows.

All the filters are 51 taps long low-pass filters with passband
up to 0.4 times the Nyquist rate and, when possible, requesting 50 dB stopband rejection. For the Gaussian window,
we selected a 3. We may conclude from these figures and
other studies that precise control of pass- and stopband properties is not possible with this method. Its major advantage
is that any filter length may be easily obtained without computational problems.

0.0
for as < 21 dB
Remez Algorithm (Equal-Ripple Design). Returning to Eqs.
0.5824(as 21)0.4 + 0.07886(as 21)
(80)
and (81) for the equal-ripple design, we have the un=
(91)
for 21 dB < as < 50 dB
known k coefficients of the trigonometric polynomial P() to
for as > 50 dB
0.1102(as 8.7)
determine, and the best procedure for this purpose is the Remez exchange algorithm. The formulation of the problem is
where I0(x) is the modified zeroth-order Bessel function and based on the error function
is a selectable parameter.
The Gaussian window is
E() = W ()[Hr () H()] = W ()[Hr () Q()P()]
(97)
2
= W ()Q()[Hr ()/Q() P()]
w(n) = exp[2(an/(N 1)) ]
(92)
where a is a selectable parameter.
For the Chebyshev (also called DolphChebyshev) and
Taylor windows, w(n) will also be a cosine series, where the
coefficients are calculated by evaluating the Chebyshev polynomial at N equidistant points along the unit circle and subsequently calculating its inverse discrete Fourier transform.
This attempts to make all sidelobes to be about equal and of
specified height. The equation that defines the weights is as
follows:
M

w(n)e j = TM [ cos + ( 1)]

where W is the usual weight function and P is the only unknown. Naturally, we must also select the case and therewith
the Q function, especially since some filter types can only be
implemented with some of the cases. For instance, lowpass
filters may not be implemented in a case where Q is a sine
function. Using the Remez algorithm, also described in Appendix B, the first step is to select a set of frequencies i, one
more than the number of free parameters in P(), and set the
value of E(k) in an alternating manner. Solving for the
trigonometric polynomial P, we obtain the expression

(93)

n=M

where M (N 1)/2, Tk(x) is the Chebyshev polynomial of

order k, and





2
2
= 1 + cos
1 + cos
(94)
2M + 1
2M + 1

P(i ) =

Hr (i )

= Ai Bi = Ci
Q(i )
W (i )Q(i )

(98)

at the selected frequencies, where the Ai and Bi values are

known. Including the unknown deviation , we have the right
number of equations for the right number of unknowns. In

468

FILTER APPROXIMATION METHODS

51 taps

90
80
70
60

Delay

50
40
30
20
10
0
10

0.2

Figure 19(a). Characteristics of a rectangular

window.

0.4
0.6
Normalized frequency

0.8

(a)

particular, these equations can be written in matrix form, using Eq. (81):

cos2 1
cos3 1 . . .
1 cos 1
1 cos
cos2 2
cos3 2 . . .

1 cos M+1 cos2 M+1 cos3 M+1 . . .

1 cos M+2 cos2 M+2 cos3 M+2 . . .
(99)

cosM 1
B1
0
A1

cosM 2
B2
1 A 2

M
M+1

cos M+1 (1)

BM+1
M
AM+1

AM+2
cosM M+2 (1)M+2BM+2

A similar matrix equation may be written for the k coefficients, if we replace the powers of cosine by the multiple angle
forms of the cosine function. This linear set of M 2 equations in M 2 unknowns is not solved directly, because that
would be time consuming. Instead, we first calculate , for
which we can find a closed-form expression:

M+2
q A
=
M+2k=0 k k
k
k=0 (1) qk Bk

where qk =

M+2


1
cos

cos i
k
i=0,
= k
(100)

Once this is computed, the remaining equations can be obtained by deleting the last row and the last column from the
preceding matrix equation and replacing the right side by the
column containing Ci Ai Bi. This forms an interpolation
51 taps

100

80

Loss

60

40

20

Figure 19(b). Properties of a Hann window.

0.2

0.4
0.6
Normalized frequency
(b)

0.8

FILTER APPROXIMATION METHODS

469

51 taps

100

80

Loss

60

40

20

0.2

0.4
0.6
Normalized frequency

0.8

(c)

Figure 19(c). Behavior of a Blackman window.

problem, which can be solved again explicitly by Lagranges

method in an effective manner (30):

P() =

M+1

lk ()Ck

k=0

M+1

i=0,
= k (cos

lk () = M=1

where

i=0,
= k (cos

cos i )
k cos i )

(101)

Next we evaluate the function E() on a dense set of frequencies to locate the true extrema i and replace the previous
frequencies by these new i values. Repeating the process
leads to the true minimax approximation in a very few steps.

Naturally, the procedure needs additional safeguards, especially concerning the treatment of extra ripples that may
occur and, of course, the convergence criteria and numerical
problems, if any. Nevertheless, a program has been available
in the public domain for some time now (31) and produces
excellent results. In this method there is no need to distinguish between low-pass, high-pass, or bandpass filters. Indeed, the procedure works for any number of pass- and stopbands. Also note that the requirements need not be flat; any
specified shape can be accommodated.
Fig. 20 shows a 51 tap long low-pass filter designed by this
method and requesting a passband up to 0.4 and a stopband
from 0.475 to 1.0, the Nyquist rate. The filter has less than 1
dB passband loss ripple, and the minimum stopband loss is

51 taps

100

80

Loss

60

40

20

0.2

0.4
0.6
Normalized frequency
(d)

0.8

1
Figure 19(d). Loss of a Hamming window.

470

FILTER APPROXIMATION METHODS

51 taps

100

80

Loss

60

40

20

0.2

about 51 dB. This design, of course, compares favorably with

any of the windowed designs demonstrated before.
Least Squares Design. If we go back to Eq. (66), consider the
loss only (since the phase is linear), and use the special case
p 2, we get
L

w(i )[Hr (i ) H(i )]2

i=1

(102)
w(i )[Hr (i ) Q(i )P(i )]

0.8

(e)

Figure 19(e). Loss shape of a Gaussian window.

E=

0.4
0.6
Normalized frequency

i=1

where H() is now given by Eqs. (80) and (81), we can see
that E is a quadratic function of all the unknown coefficients

k or k. The number of frequencies used in the summation

must be L M 1 (i.e., the number of available free parameters).
To clarify the formulation of the problem, let us introduce
the following vector-matrix notation. Let the vector (0,
1, . . . M)T be the unknown coefficient vector, F the M 1
by L matrix:

1 cos 1 cos2 1 . . . cosM 1

1 cos
cos2 2 . . . cosM 2

2
(103)

1 cos L cos2 L . . . cosM L

Hd is the requirement vector, Hd (Hd(1), Hd(2), . . .
Hd(L))T, and finally Q and V are L by L diagonal matrices,
51 taps

100

80

Loss

60

40

20

Figure 19(f). Behavior of a Kaiser window.

0.2

0.4
0.6
Normalized frequency
(f)

0.8

FILTER APPROXIMATION METHODS

471

51 taps

100

80

Loss

60

40

20

0.2

0.4
0.6
Normalized frequency

0.8

(g)

Figure 19(g). Properties of a Chebyshev window.

where the diagonal values are Q(i) and W(i), respectively.

With this notation, we can formulate an error vector of length
L as follows:
e = V (Hd QF )

(104)

and the total error is now given as E eTe.

If L M 1, then all matrices are square and the vector
e can be set to zero and the unknown vector computed as (the
weights are now immaterial)
= (QF )1 Hd

(105)

This is indeed a slight generalization of the method of frequency sampling and can be used for FIR filter design. Natu-

rally, the inverse matrix is not computed, but the equations

are solved by some other, numerically preferable, method.
If, however, L M 1 or even L M 1, then e has
many more elements than and consequently cannot be
made to disappear; we can only attempt to minimize its norm
(that is, eTe). This can be done by the use of the pseudoinverse of a rectangular matrix. We obtain this by premultiplying the error equation by (QF)T, obtaining
= (QF )T V Hd (QF )T e
(QF )T (QF )

(106)

We can now set the last error term to zero and solve this
equation, because the matrix on the left (QF)T(QF) is an M
1 by M 1 square matrix. We leave the details for the literature (32,33). We must be careful about using this algorithm,

51 taps

100

80

Loss

60

40

20

0.2

0.4
0.6
Normalized frequency
(h)

0.8

1
Figure 19(h). Characteristics of a Taylor window.

472

FILTER APPROXIMATION METHODS

51 taps (0.40.475)

90
80
70
60

Loss

50
40
30
20
10
0
10
Figure 20. Equal-ripple (Remez) FIR filter characteristics.

0.2

since the procedure can get numerically ill conditioned. Instead, we recommend the use of the methods in the LINPACK
program package (34) or the method of singular-value decomposition (33).
This method can also be applied to the case of nonlinear
phases, and it is one of the methods most often used in that
case.
Closed-Form Solutions. We may mention two special cases,
in which we can obtain closed-form expressions for the FIR
filter. Both use the Chebyshev polynomials Tn(x) we have already used (35). Since Tn(x) varies between 1 if x is in the
range 1 x 1, we can simply replace x by an expression
in terms of cos(). If we need a low-pass with an equal-ripple
passband, we select
x=

(1 + cos p ) 2 cos
1 cos p

(107)

(108)

The stopband will be monotonic, and to make the magnitude

of the transfer function at the Nyquist frequency zero we need
to select
p = 1/Tn [(3 cos p )/(1 + cos p )]

(109)

The other case is when we need an equal-ripple stopband; in

which case we use
x=

2 cos + 1 cos s
1 + cos s

0.8

if we wish H to be unity at 0. High-pass filters with

similar behavior are easily obtainable through a change of the
expression for x, but bandpass filters are more difficult since
we must make both H(0) and H() disappear.
In any case, we have very little control over the band that
is not equal ripple. Fig. 21 shows a pair of filters with 21 taps;
one has an equal ripple passband from 0 to 0.5, the other an
equal ripple stopband from 0.5 to 1.0. The ripple values in
both cases are extremely small.
A much more useful closed-form approximation (36,37) exists for maximally flat pass- and stopband lowpass filters. Using the case 1 formulation (symmetrical coefficients and N
even), we can find an H() such that it has 2L zeros at
and H() 1 has 2K zeros at 0, where M L K 1.
Ignoring the phase factor, we can then write this transfer
function in two equivalent forms:

K L1

1 cos n
1 + cos
dn
2
2
n=0
L K
n




1
1 + cos
1 cos
1
dn
2
2
n=0

H() =

and use the transfer function

H() = 1 p Tn (x)

0.4
0.6
Normalized frequency

(110)

and the transfer function will be given by

H() = s Tn (x) where s = 1/Tn [(3 cos s )/(1 + cos s )]
(111)

(112)

which is satisfied if (37)

dn =

(K 1 + n)!
(K 1)!n!

or d n =

(L 1 + n)!
(L 1)!n!

(113)

The design has only the powers K and L as free parameters,

and the way to satisfy specific requirements is also outlined
in Ref. 37. The parameters usually specified are the H()
0.5 point and the transition bandwidth, usually defined as the
distance between the 95% and the 5% transmission points.
Figure 22 shows an example, with K 11 and L 8, yielding
a (normalized) transition bandwidth of 0.24 and a half-power
point at 0.448. High-pass filters can easily be obtained
by using 1 H(), but there is no way to design bandpass
filters with similar characteristics. As pointed out by Kaiser,

FILTER APPROXIMATION METHODS

21 taps, passbands from 0 to 0.5 and 0.5 to 1

Transfer function magnitude

473

Equal-ripple passband

0.8

0.6

0.4

Equal-ripple stopband

0.2

0.2

0.4
0.6
Normalized frequency

0.8

Figure 21. FIR filters with equal ripple pass- or

stopband.

high-order filters designed by this method will have a number of coefficients at the end with very small values. Consequently, these filters are practical for medium complexity
(N 50) only.
Attempts have been made for developing algorithms for
the design of FIR filters with flat passband and equal-ripple
stopband or vice versa. Today, few of these methods are in
general use.
Additional algorithms have been developed for cascading
two or more functions to generate more selective filters and
their design, for which we refer the reader to the literature
(38).

ter, the first step is to expand the function divided by s into

partial fraction form:

TIME-DOMAIN APPROXIMATION

The step response can now be expressed as

 Aj
H(s) d+1
=
s
s pj
j=1

(114)

where Aj is the residue at the pole pj. Incidentally, while we

may make allowances for multiple poles, we have never encountered them in practical situations. The residues are, of
course, functions of the poles and zeros:
n
i=1 (p j zi )
A j = H0 d+1
(115)
k=1, = j (p j pk )

a(t) =

Returning to Eq. (1) for the overall transfer function and assuming that we are interested in the step response of the fil-

d+1


Aje p jt

(116)

j=1

K = 11, L = 8

Magnitude

0.8

0.6

0.4

0.2

0.2

0.4
0.6
Normalized frequency

0.8

Figure 22. Maximally flat FIR filter characteristics.

474

FILTER APPROXIMATION METHODS

Some of the poles will be complex, but they appear in complex

conjugate pairs, and the corresponding residues will also be
complex conjugates, yielding a real time function. A number
of papers have been published about approximating either the
step or the impulse response to have specified magnitude of
ringing and simultaneously the filter to have equal minima
type stopband with specified loss (3941). The approximation
was performed in the minimax sense, and extensive tabulated
results are available.
FIR filter design is basically a time-domain approach and
therefore need not be discussed. However, if the impulse response of IIR filters is specified, Pronys method may be used
to obtain the corresponding transfer function. This method is
based on the relationship


b + b1 z1 + + bM zM
N(z)
= 0
H(z) =
=
h(n)zn
D(z)
1 + a1 z1 + + aN zN
n=0
(117)

where the h(n) values are given and the ai and bi coefficients
are to be determined. If we truncate the right side to K
M N 1 terms and cross multiply, we can compare coefficients of zk and obtain the following set of linear equations
[denoting h(n) by hn for simplicity]:

b0
h0
b h
1 1

b2 h2

. .

. .

=
bM hM

0 h
M+1

. .

. .
0
hM+N

0
h0
h1

0
0
h0

...
...
...

hM1
hM

hM2
hM1

...
...

hM+N1

hM+N2

...

0
0
0
.
.

a
1

a2

hMN


hMN+1

a
.
N

.
hM
(118)

Ignoring the first M 1 equations for the moment, the rest

can be rewritten as

hM a1 + hM1a2 + hM2 a3 + + hMN+1aN = hM+1

hM+1a1 + hM a2 + hM1 a3 + + hMN+2aN = hM+2

APPENDIX A: TEMES-GYI PROCEDURE

To generate a low-pass transfer function with an equal-minima type stopband behavior with a given denominator D(s),
we shall start by writing the transfer function denominator
in factored form:

D(s) =

d


(s pk )

(A.1)

k=1

where the multiplier is immaterial and pk, if complex, appears

in complex conjugate pairs. Next we introduce a new variable
z:
z=

1 + (s/s )2

(A.2)

which will be pure imaginary in the stopband from s to infinity. If we compute the transformed values of the pk poles
as
zk =

1 + (pk /s )2

(A.3)

then we can observe that since the zk values, if complex, also

occur in complex conjugate pairs, hence for pure imaginary z
values the function
d

zk z
z +z
k=1 k

(A.4)

will have unit magnitude in the stopband and can therefore

be written as ej, that is,

1 j/2
1
(e
+ e j/2 ) =
2
2


d
Ev
k=1 (zk + z)
= d
(z2k z2 )
k=1

cos /2 =

d


z

k=1

d
z 
+
zk + z k=1
k

z

+z
zk z

(A.5)

is going to vary between zero and one in the stopband. Ev

designates the even part of the polynomial. The square of this
quantity is therefore

..
.
hM+N1a1 + hM+N2a2 + hM+N3a3 + + hM aN = hM+N
(119)
This set of N equations in the N unknown ai denominator
coefficients can be solved if the (square) matrix on the left is
nonsingular. Once this is done, we can go back to the first
M 1 equations and solve them for the numerator coefficients. If the matrix is singular, this indicates that the problem may be solved by a lower-degree H(z) function.
The problem with this method is that we have no control
over the values of h(n) beyond n M N 1 and, more
significantly, we have no idea if the resulting transfer function will turn out to be stable. The first of these can be somewhat alleviated by adding additional equations to those in Eq.
(119) and solve this (overdetermined) set of equations using
least squares techniques.

2
d
Ev k=1 (zk + z)
cos2 (/2) =
d
2
2
k=1 (zk z )

(A.6)

where the denominator corresponds to the polynomial

D(s) D(s), while the numerator is [N(s)]2, where N(s) is an
even polynomial. This is therefore the magnitude function
(save for a multiplier) we are looking for, and the required
transmission zeros are obtained by calculating the roots of the
polynomial

Ev

d


(zk + z)

k=1

and converting them back to s. The available minimum stopband loss can be computed simply by calculating the magnitude of N(s)/D(s) at s, assuming that the magnitude at s 0
is set to unity. Alternatively, we can evaluate the expression

FILTER APPROXIMATION METHODS

above for cos2( /2) at z 1 ( 0) and the minimum loss will

be

reduce the size of the polyhedron by a factor of two, starting

from the best point. The test for convergence is usually

amin = 10 log10 (1/ cos2 (/2)) at z = 1

This works fine if the degree d is odd. If it is even, the resulting loss will be finite at infinity, since the degree of N(s)
will be the same as that of D(s). This is acceptable for active
RC or digital implementations. For RLC realization, we could
apply a simple shift to the zeros and poles, as we have done
in the preceding elliptic case above, but that would also shift
s and, more significantly, all the zeros of D(s) as well. The
solution is to apply a reverse shift to these zeros and to s,
followed by the preceding computation, followed by the forward shift to cancel the reverse one. If this shifts the last zero
to infinity, we are done. If not, we modify the amount of reverse shift we used and repeat. This iterative procedure converges very fast, hardly ever needing more than two or three
steps. A somewhat different procedure is described in Ref. 12.

n+1
1 
( f (xi ) f ave )2
n + 1 i=1

The general optimization problem can be formulated as follows. The overall error function is a general, nonlinear function of the transfer function poles, zeros, and possibly a multiplier:
E = f (x1 , x2 , x3 , . . . xn ) = f (xx )

(B.1)

The variables xi are usually combined into a single vector x.

If we wish to reduce the problem to real variables, we may
use the quadratic coefficients in a factored form, instead of
the roots of these quadratics. We start from a set of initial
values x0 and wish to determine x such that E is minimized.
The method to be used is dependent on the exact form of the
error function f(x).
The Least pth Approximation
Consider first the least pth error definition of Eq. (66). The
currently favored methods can be classified according to
whether they need derivatives or not.
The Simplex Method. Nelder and Mead (42) introduced the
simplex method, which needs only function evaluations. It
starts by evaluating the function at the starting set of parameter values x0 and n additional points, which we get by changing the xi parameters by a fixed amount, one at a time (the
corner points of a polyhedron). Out of these n 1 points, we
select the one where f(x) is the largest and reflect this point
through the center of gravity of the remaining n points. At
this juncture, we again have n 1 points and function values
and we can repeat the procedure. Many refinements are possible, indeed, necessary. One is that if the function value at
the reflected point is better than at any other, we move further in the same direction, by a factor usually selected to be
about two. This is called expansion, and if it works, we accept
the new point; if not, we back off. If, on the other hand, the
new point has a value f(x), which is better than the worst
point but worse than all others, we contract the step (i.e.,
move a shorter distance in the indicated direction). Finally, if
the new point yields an evaluation that is still the worst, we

1/2
eps

(B.2)

where f ave is the average of all the function values and eps is
the specified tolerance. This simply means that the function
values are now so close as to make any distinction between
them meaningless.
This procedure is fast and cheap in terms of computational
expenses. Since the polyhedron is changing its shape and size
during the iteration, it is able to follow the terrain fairly well
and has been found to be effective in starting the optimization.
The Gradient Method. The gradient method needs the computation of the first set of partial derivatives:

f (x) =

APPENDIX B: OPTIMIZATION STRATEGIES

475

f f
f
,
,...
x1 x2
xn

T
(B.3)

either analytically or approximately (numerically). The superscript T indicates transposition. Since the direction f is
where the value of f would increase the fastest, we go in the
opposite direction and search for the minimum along
x = x 0 f

(B.4)

where is a scalar. There are again many ways to perform

this one-dimensional search that can be done with or without
calculating further derivatives. Some of the simplest ones are
the golden section and the Fibonacci searches. Here we compute the function values for two values of that are sure to
bracket the minimum and subdivide this range by either the
golden section or the Fibonacci series ratio. Once the new
function value is computed, we can do further subdivisions
and arrive at the location of the minimum in optimal time.
Another could be to calculate the function values for three
values of , fit a quadratic function to these points, and calculate its minimum. Repeating this procedure can locate the
minimum reasonably accurately.
Once the line search has located the minimum along the
variable , we recalculate the gradient and repeat the process.
It can readily be shown that if we locate the minimum along
this direction exactly, the new direction will be orthogonal to
the previous one, which may not help if we need to go along
a narrow valley. Refinements can come in the form of averaging the directions of several consecutive derivative calculations and many others.
Newton-Raphson Method. Newtons method goes one step
further along in expanding the function f(x) around x0 into a
Taylor series:
1
f (x)
= f (x0 ) + f T x + xT Hx
2

(B.5)

where H is the matrix of second derivatives (also called Hessian matrix):

Hij =

2 f
xi x j

(B.6)

476

FILTER APPROXIMATION METHODS

To find the point where f(x) is optimum (minimum), we must

find the value of x that will make all components of the vector f disappear:
f (x)
= f (x0 ) + H(x0 )x = 0
or
x = (x x0 ) = H 1 (x0 ) f (x0 )

(B.7)

This method only works if H is positive definite, but when we

are close to the optimum, it converges fast. The main problem
is the cost of evaluating (analytically or numerically) the Hessian matrix and inverting it. This method is hardly ever used
in its original form; it is useful mainly to introduce the next
method, the DavidonFletcherPowell method.
The DavidonFletcherPowell Method. This is one of a family of methods called the variable metric algorithms (43). The
idea for this method comes from the realization that the gradient method can be written in the form
x = x 0 f (xx 0 ) = x 0 G f (xx 0 )

(B.8)

where G is the unit matrix, while the NewtonRaphson

method has the same form, except that G is then proportional
to the inverse Hessian. Davidon had the idea that we can
start the approximation with G being the unit matrix but
then, as the iterations continue, build it up to approximate
the inverse Hessian numerically, without actually having to
calculate the Hessian and invert it. The reason for this being
a whole family of methods is that there is no unique way of
doing this, but many different ways instead. At any particular
iteration, we locate the minimum along the current direction
and determine the corresponding k1 and from that xk1 and
f(xk1), which give us
p k = x k+1 x k

and y k = f (xx k+1 ) f (xx k )

Gk+1 = Gk

pk pTk
(Gk yk )(Gk yk )T
+
yTk Gk yk
yTk pk

(B.9)

as one of the possible update expressions. (Note that if v and

w are two vectors, then vTw is a scalar, but vwT is a matrix.)
It can be shown that if f(x) is a true quadratic function
[i.e., the Taylor series expansion of Eq. (B.5) is exact], then
this Gk converges to the inverse Hessian in exactly n steps.
Also, if the original Hessian H is positive definite, the sequence of matrices Gk will also be positive definite.
Naturally, one equation an algorithm does not make; we
need convergence criteria, ways of handling special cases, numerical instability, and a host of other issues besides using
different expressions. For all of these as well as for finding
computer programs implementing the foregoing, we refer to
the extensive literature.
Thoroughly tested and highly efficient routines are available for these and other optimization techniques either commercially or in the public domain. All methods considered
previously were of the unconstrained variety (that is, there
were no limits placed on the possible values of the variables).
This is no restriction if we consider losses only, since dealing
with poles and zeros, putting all the poles back into the left

half of the s plane leaves the loss unchanged, and that is the
only restriction we need to satisfy. For delay requirements,
however, the poles may sometimes wander over to the righthalf plane, which is not permitted. We must then increase the
additional flat delay required to force these poles back into
the left half of the s plane. More complex constrained optimization techniques exist, but if we restrict our techniques to
optimizing the transfer function itself, these are usually not
necessary.
Minimax Approximation
All of the preceding methods are applicable if the error function is of the form of Eq. (66). For the minimax formulation
of Eq. (67), we have basically two options. One is based on the
fact that if the value of the exponent p in Eq. (66) tends to
very large values, the approximation in fact approaches the
minimax criteria. The other option is the application of the
Remez algorithm.
Remez Algorithm. The idea behind this algorithm is very
simple (44), and it is based on the alternation theorem: If
P() is a linear combination of M cosine functions,

P() =

M


k cos(k)

(B.10)

k=0

then a necessary and sufficient condition that P() be the

unique best weighted Chebyshev approximation to a continuous function Hr() is that the weighted error function
E() = W ()[P() Hr ()]

(B.11)

exhibit at least M 1 extremal frequencies in the range of

interest in .
We select M 2 frequency points k that is one more than
the number of free parameters and use the (weighted) approximating function to interpolate the required function Hr(k)
, where the sign alternates at consecutive frequencies.
Since we have M 2 frequencies, where M 1 is the number
of free parameters and M 2 parameters ( is also unknown),
this should be a well-defined problem. Next we find all the
extrema of this approximating function and replace the k
values by the locations of these extrema. Repeating the process will lead to the required minimax result. The problem is
the interpolation step, especially if the approximating function is highly nonlinear, when solving the interpolation problem is itself equivalent to an approximation procedure. In a
few special cases, we can obtain an appropriate interpolation
relatively easily; one is the procedure of approximating a constant delay, and the other is the design of FIR digital filters.

APENDIX C: SPECIAL FUNCTIONS

A number of classical polynomials have been tried to generate
characteristic functions, including Jacobi, Laguerre, Legendre, and various Chebyshev polynomials [other than the
Tn(x) we have used previously], but they have not been found
useful in practice. A few exceptions are as follows.

FILTER APPROXIMATION METHODS

477

N = 3, 4, 5, 6, 7

40
35

Equal ripple to 12 dB

30

Loss

25
20
15
10
5
0

0.5

1.5
2
2.5
Normalized frequency

3.5

4
Figure 23. Loss characteristics of Gaussian filters.

Gaussian Filter

and

In certain situations, one would like to have a filter characteristic that approximates the Gaussian shape: H()2
exp[(/0)2]. One can again do this in various ways; the simplest one approximating this shape in the maximally flat
sense is to use the characteristic function

(s) (s) = exp(s/0 )2 1 =


n=1

s 2n
0
n!

(C.1)

[a0 + a1 P1 (x)

(x + 1)[a0 + a1 P1 (x)

(C.4)

where we have two subcases:

Case 1: [(n 2)/2] is even:

2
a0 = a2 /5 = = a(n2)/2 /(n 1) =
n(n + 2)
a1 = a3 = = a(n4)/2 = 0
Case 2: [(n 2)/2] is odd:

(C.5)

2
a1 /3 = a3 /7 = = a(n2)/2/(n 1) =
n(n + 2)
a0 = a2 = = a(n4)/2 = 0
Reference 45 contains tables of these polynomials. Fig. 24
shows the fifth-order Butterworth and Papoulis filter characteristics. For comparison, we also included the fifth-order
Chebyshev function with 1 dB ripple, but scaled to the same
3 dB point as the others. The Chebyshev is, of course, the
fastest rising but it is not monotonic.
ButterworthThomson Filter

+ + a(n1)/2 P(n1)/2 (x)] dx

where the Pk(x) are the Legendre polynomials defined by

P1 (x) = x;

(C.2)
2

P0 (x) = 1;

2 2 1

+ + a(n1)/2 P(n1)/2 (x)] dx

Papoulis (46) has found the function that provides a loss that
rises the fastest among all the monotonically increasing
transfer functions with a constant numerator function. One
can derive the denominator polynomial of such a function as
follows (see Refs. 46 and 47). For n odd

() () =

() () =

Papoulis Filter

2 2 1

For n even, on the other hand, we have

Truncating this expansion to a finite number of terms will

yield a number of (equivalent) (s) functions depending on
how we allocate the zeros to (s) and (s). Equal ripple-type
approximation has also been tried, but the results are simply
tabulated natural modes for degrees from 3 to 10 and approximation errors of 0.05 dB up to either the 6 dB or 12 dB points.
Fig. 23 shows the loss characteristics of the first few maximally flat approximations and the seventh-order equal ripple
to 12 dB approximation. This last one has a much steeper rise
of the loss beyond the 12 dB point. Tabulated functions are
available (for instance, in Refs. 10 and 45).

2
a0 = a2 /5 = = a(n2)/2 /(n 1) =
n(n + 2)

and

2k + 1
k
xP (x)
P (x)
Pk+1 (x) =
k+1 k
k + 1 k1

(C.3)

Filter designers have found that the Butterworth characteristics are desirable from the loss point of view but have undesirable delay performance. The Bessel functions, on the other
hand, have the opposite behavior. It follows naturally that
someone would try to combine the two, yielding the ButterworthThomson filter. (In this context, Thomsons name is be-

N=5

10

Papoulis
8
Butterworth
Loss

2
Chebyshev
0
Figure 24. Comparison of polynomial low-pass
transfer functions.

0.25

0.5

0.75
1
Normalized frequency

1.25

1.5

2.5

2.5

N = 6, M = 0, 0.25, 0.5, 0.75, 1.0

60

50

Loss

40

30

20

10

0
Figure 25. Loss characteristics of Butterworth
Thomson filters.

0.5

1.5
2
Normalized frequency

n = 6, m = 0, 0.25, 0.5, 0.75, 1.0

1.2

Delay

0.8

0.6

0.4

0.2

0
Figure 26. Delay characteristics of Butterworth
Thomson filters.

0.5

478

1.5
2
Normalized frequency

FILTER APPROXIMATION METHODS

ing used instead of Bessel.) The idea is simply to take the

natural modes of the nth order Butterworth filter
B
zB
k = exp( jk )

k = 1, 2, . . . n

and the zeros of the (same degree) Bessel polynomial [Eq.

(21)]
zTk = rTk exp( jkT )

k = 1, 2, . . . n

The transitional ButterworthThomson filter will have natural modes given by

zk = rk exp( jk )

(C.6)

where

479

12. R. Unbehauen, Low-pass filters with predetermined phase or delay and Chebyshev stopband attenuation, IEEE Trans. Circuit
Theory, CT-15: 337341, 1968.
13. J. D. Rhodes, Theory of Electrical Filters, New York: Wiley, 1976.
14. J. P. Thiran, Recursive digital filters with maximally flat group
delay, IEEE Trans. Circuit Theory, CT-18: 659664, 1971.
15. A. Fettweis, A simple design of maximally flat delay digital filters, IEEE Trans. Audio Electroacoust., AU-20: 112114, 1972.
16. J. P. Thiran, Equal-ripple delay recursive digital filters, IEEE
Trans. Circuit Theory, CT-18: 664669, 1971.
17. G. Szentirmai, The design of arithmetically symmetrical bandpass filters, IEEE Trans. Circuit Theory, CT-10: 367375, 1963.
18. B. R. Smith and G. C. Temes, An iterative approximation procedure for automatic filter synthesis, IEEE Trans. Circuit Theory,
CT-12: 107112, 1965.
19. H. C. Bell, private communication.

(C.7)

20. H. C. Bell, Bandwidth adjustment in iterative approximation procedures, IEEE Trans. Circuits Syst., CAS-25: 951954, 1978.

Here m is a parameter between zero and one; m 0 yields

the pure Butterworth solution, while m 1 is the Bessel filter
(see Ref. 48). The roots of the Bessel polynomial rTk are usually
scaled first by dividing them by the factor

21. R. W. Daniels, Approximation Methods for Electronic Filter Design, New York: McGraw-Hill, 1974.

rk =

(rTk )m

and k =

kB

m(kB

kT )

2n 1
2 2n
e
to bring their magnitude close to unity. This quantity is an
approximation to the nth root of the constant term in the
polynomial and is based on Stirlings approximation of n!, but
it is very good even for low degrees. Also, this renormalization
will change the normalized delay at zero frequency from unity
to this value. Figures 25 and 26 show the loss and delay of
the sixth-order ButterworthThomson filters with m values
in the range 0.0 (0.25) 1.0.
BIBLIOGRAPHY
1. T. Saramaki, Design of optimum recursive digital filters with
zeros on the unit circle, IEEE Trans. Acoust. Speech Signal Process., ASSP-31: 450458, 1983.
2. M. Abramowitz and I. A. Stegun, Handbook of Mathematical
Functions, Washington, DC: National Bureau of Standards, 1964.
3. S. Darlington, Synthesis of reactance 4-poles which produce prescribed insertion loss characteristics, J. Math. Physics, 18: 257
353, 1939.
4. H. J. Orchard and A. N. Willson, Jr., Elliptic functions for filter
design, IEEE Trans. Circuits Syst. I, CAS-44: 273287, 1997.
5. G. Szentirmai, Computer-aided design methods in filter design,
in J. T. Taylor and Q. Huang (Eds.), CRC Handbook of Electrical
Filters, Boca Raton, FL: CRC Press, 1996.
6. R. Saal, Handbook of Filter Design, Berlin, Germany: AEG-Telefunken, 1979.
7. J. K. Skwirzynski, Design Theory and Data for Electrical Filters,
New York: Van Nostrand-Reinhold, 1965.
8. E. Christian and E. Eisenmann, Filter Design Tables and Graphs,
New York: Wiley, 1966.
9. L. Storch, Synthesis of constant-time-delay ladder networks using Bessel polynomials, Proc. IRE, 42: 16661675, 1954.
10. A. I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
11. G. C. Temes and M. Gyi, Design of filters with arbitrary passband
and Chebyshev stopband attenuation, 1967 IEEE Int. Conf. Rec.,
pp. 212.

22. H. Watanabe, Approximation theory for filter networks, IRE

Trans. Circuit Theory, CT-9: 341356, 1961.
23. A. Premoli, The MUCROMAF polynomials: An approach to the
maximally-flat approximation of RC-active filters with low sensitivity, IEEE Trans. Circuit Theory, CT-20: 7780, 1973.
24. A. Premoli, A new class of equal-ripple filtering functions with
low Q factors, IEEE Trans. Circuits Syst., CAS-21: 609613,
1974.
25. M. Biey and A. Premoli, Tables for Active Filter Design, Norwood,
MA: Artech House, 1985.
ber den Entwurf von Allpassen, Tief26. E. Ulbrich and R. Piloty, U
passen und Bandpassen mit einer in Tschebyscheffschen Sinne
approximiert konstanten Gruppenlaufzeit, AEU, 14: 451467,
1960.
27. H. W. Bode, Network Analysis and Feedback Amplifier Design,
New York: Van Nostrand-Reinhold, 1945.
28. A. G. Deczky, Equiripple and minimum (Chebyshev) approximation for recursive digital filters, IEEE Trans. Acoust. Speech Signal Process., ASSP-22: 98111, 1974.
29. D. F. Elliott (Ed.), Handbook of Digital Signal Processing, New
York: Academic Press, 1987.
30. F. B. Hildebrand, Introduction to Numerical Analysis, New York:
McGraw-Hill, 1956.
31. J. H. MacClellan, T. W. Parks, and L. R. Rabiner, A computer
program for designing optimum FIR linear phase digital filters,
IEEE Trans. Audio Electroacoust., AU-21: 506526, 1973.
32. J. E. Dennis, Jr. and R. B. Schnabel, Numerical Methods for Unconstrained Optimization and Nonlinear Equations, Philadelphia:
SIAM, 1996.
33. C. L. Lawson and R. J. Hanson, Solving Least Squares Problems,
Englewood Cliffs, NJ: Prentice-Hall, 1974.
34. J. J. Dongarra et al., LINPACK Users Guide, Philadelphia:
SIAM, 1979.
35. O. Herrmann, L. R. Rabiner, and D. S. K. Chan, Practical design
rules for optimum finite impulse response lowpass digital filters,
Bell Sys. Tech. J., 52: 769799, 1973.
36. O. Herrmann, On the approximation problem in nonrecursive
digital filter design, IEEE Trans. Circuit Theory, CT-18: 411
413, 1971.
37. J. F. Kaiser, Design subroutine (MXFLAT) for symmetric FIR
low-pass digital filters with maximally-flat pass and stop bands,
in Digital Signal Processing Committee, Programs for Digital Signal Processing, New York: IEEE Press, 1979, pp. 5.3-15.3-6.

480

FILTERING AND ESTIMATION, NONLINEAR

38. J. F. Kaiser and R. W. Hamming, Sharpening the response of a

symmetric nonrecursive filter by multiple use of the same filter,
IEEE Trans. Acoust. Speech Signal Process., ASSP-25: 415
422, 1977.
39. J. Jess, Uber Impulsfilter mit Tschebyscheffverhalten in Zeitund Frequenzbereich, AEU, 17: 391401, 1963.
40. J. Jess, On the design of pulse-forming networks, IEEE Trans.
Circuit Theory, CT-12: 393400, 1965.
41. K. L. Su, Time-Domain Synthesis of Linear Networks, Englewood
Cliffs, NJ: Prentice-Hall, 1971.
42. D. Kahaner, C. Moler, and S. Nash, Numerical Methods and Software, Englewood Cliffs, NJ: Prentice-Hall, 1989.
43. M. Avriel, Nonlinear Programming, Englewood Cliffs, NJ: Prentice-Hall, 1976.
44. E. Y. Remez, General computational methods of Chebyshev approximation, Atomic Energy Translation 4491, Kiev, USSR, 1957.
45. D. S. Humpherys, The Analysis, Design and Synthesis of Electrical
Filters, Englewood Cliffs, NJ: Prentice-Hall, 1970.
46. A. Papoulis, A new class of filters, Proc. IRE, 46: 649653, 1958.
47. M. Fukado, Optimum filters of even order with monotonic responses, IRE Trans. Circuit Theory, CT-6: 277281, 1959.
48. Y. Peless and T. Murakami, Analysis and synthesis of transitional Butterworth-Thomson filters and bandpass amplifiers,
RCA Rev., 18: 6094, 1957.

GEORGE SZENTIRMAI
DGS Associates Inc.

FILTER BANKS. See WAVELETS.

FILTERING. See IMAGE ENHANCEMENT.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

CIRCUIT OPTIMIZATION
The behavior of integrated circuits is influenced by the manner in which the circuit is built. For circuits that
are constrained to meet performance and time-to-market requirements, the use of automated techniques is
essential to manage the complexity. These parameters include the number of functional units in a behavioral
specification, the logic structure of the network, the layout topologies used, and many other factors. The behavior
of the circuit can be influenced by a number of such variable parameters, and a designer must carefully select
the correct parameters that meet the requirements with a reasonable overhead and in time to meet market
deadlines.
Optimization theory plays a large role in helping this process. There is a large body of literature on
optimizing linear functions, nonlinear functions, combinatorial functions, etc., that can be successfully applied
to these problems if appropriate models are used to fit the problem into any of these paradigms. It is important
to note that in addition to finding a model that fits into a known optimization problem form, it is imperative
that the model should be a good reflection of reality. This chapter assumes the presence of such models and
shows how they may be applied to circuit optimization problems.
A brief intuitive feel for optimization can be provided by the following example. The problem of optimization can be thought of as a multidimensional version of trying to find the lowest or highest point on a
topographical map. The possible solutions here are locations, specified as x and y coordinates, each of which
is associated with a particular height. In general, the map would be specified by a function and the number
of dimensions would be the number of parameters on which the function depends. Unconstrained optimization does not limit the search space at all, while constrained optimization limits the search to a specific area
(for example, finding the lowest point in the state of Colorado). Continuous optimization allows all possible
solutions, while discrete optimization permits only a few discrete points as solutions (for example, find the
highest point in Colorado that lies within the limits of a city with a population of over 10,000). Multicriterion
optimization attempts to find a balance of two objectives that should be optimized (for example, attempting
to find the highest point in the state of Colorado that has the least snowfall). The criteria, as is easily seen
from the example, can often be conflicting, and the problem has to be restated in a form that makes it more
unambiguous.
In this article, we will first provide a survey of optimization algorithms, followed by a set of examples that
illustrate the application of some of these algorithms on circuit optimization problems.

Optimization Algorithms
In this section, we survey a number of commonly used approaches for optimization. The vastness of this field
makes it infeasible to enumerate or describe all of the methods. While we will treat many prominent methods
in this chapter, several other methods, such as Newtons and modified Newton or quasi-Newton methods and
conjugate gradient methods, which are often useful in engineering optimization, are not covered here. For these
and more, the reader is referred to a standard text on optimization, such as Refs. 1 and 2.
1

CIRCUIT OPTIMIZATION

For the circuit designer, it is often not necessary or desirable to implement a complicated optimization
algorithm when an optimized public domain or commercially available piece of software is available for the
same purpose. However, understanding the underlying algorithms often helps a user to better utilize the
capabilities of the optimizer. Some prominent examples of such software include the public-domain tool LPSOL
(3) and the commercial tool CPLEX for linear programming and tools such as MINOS (4) and LANCELOT
(5) for nonlinear programming. Another valuable resource is Ref. 6, which provides a brief explanation and C
code for many common computational tasks, including optimization; related books in the same series address
numerical recipes in other programming languages.
Nonlinear Optimization Problems. The standard form of a constrained nonlinear optimization
problem is

representing the minimization of a function f of n variables under constraints specified by inequalities determined by functions g = [g1 gm ]T f and gi are, in general, nonlinear functions, so that the linear programming
problem is a special case of the above. The parameters x may, for example, represent circuit parameters, and
f (x) and gi (x) may correspond to circuit performance functions. In this equation, as in the rest of this paper, we
will denote a real vector space of k dimensions by Rk .
Note that inequalities can be handled under this paradigm by multiplying each side by 1, and
equalities by representing them as a pair of inequalities. The maximization of an objective function function
f (x) can be achieved by minimizing f (x).
The set F = {x | g(x) 0} that satisfies the constraints on the nonlinear optimization problem is known
as the feasible set, or the feasible region. If F is empty (nonempty), then the optimization is said to be
unconstrained (constrained).
Several mathematical programming techniques can be used to solve the optimization problem above;
some of these are outlined here. For further details, the reader is referred to a standard text on optimization,
such as Refs. 1 and 2. Another excellent source for optimization techniques and their applications to integrated
circuit (IC) design is a survey paper by Brayton, Hachtel, and Sangiovanni-Vincentelli (7).
The formulation above may not directly be applicable to real-life design problems, where often multiple
conflicting objectives must be optimized. In such a case, one frequently uses techniques that map on the problem
to the form in Eq. (1) (see section entitled Multicriterion Optimization and Pareto Criticality).
Basic Denitions. Apart from being able to evaluate a function, it is very important to determine
information about its variations. Such information is typically captured in the derivatives of the function, if the
function is smooth. In particular, the first and second derivatives play a large role in optimization. We define
two terms in this context with respect to a continuous function f (x), where x = [x1 x2 xn ]T .
Definition.
The gradient of a continuous and differentiable function f (x), denoted as f (x), is given by the 1 n
vector

CIRCUIT OPTIMIZATION

Fig. 1. Examples of convex and nonconvex sets.

Definition. The Hessian (sometimes also referred to as the Jacobian) of a continuous and twice differentiable
function, denoted as 2 f (x), is given by the n n matrix

In any discussion on optimization, it is virtually essential to understand the idea of a convex function and a
convex set, since these have special properties, and it is desirable to formulate problems as convex programming
problems, wherever it is possible to do so without an undue loss in modeling accuracy. (Unfortunately, it is not
always possible to do so)
Definition.
A set C in Rn is said to be a convex set if, for every x1 , x2 C, and every real number , 0 1, the
point x1 + (1 )x2 C.
This definition can be interpreted geometrically as stating that a set is convex if, given two points in the
set, every point on the line segment joining the two points is also a member of the set. Examples of convex and
nonconvex sets are shown in Fig. 1.
Two examples of convex sets are the following geometric bodies:
(1) An ellipsoid E(x,B ,r) centered at point x is given by the equation

If B is a scalar multiple of the unit matrix, then the ellipsoid is called a hypersphere.

CIRCUIT OPTIMIZATION

Fig. 2. The convex hull of five points.

(2) A (convex) polytope is defined as an intersection of half-spaces and is given by the equation

corresponding to a set of m inequalities aT i x bi , ai Rn .

Definition.
The convex hull of m points, x1 , . . ., xm Rn , denoted co {x1 , . . ., xm }, is defined as the set of points y Rn
such that

The convex hull is the smallest convex set that contains the m points. An example of the convex hull of
five points in the plane is shown by the shaded region in Fig. 2. If the set of points xi is of finite cardinality
(i.e., m is finite), then the convex hull is a polytope. Hence, a polytope is also often described as the convex hull
of its vertices.
Definition.
A function f defined on a convex set  is said to be a convex function if, for every x1 ,x2 , and every , 0
1,

f is said to be strictly convex if the inequality in Eq. (7) is strict for 0 < < 1.
Geometrically, a function is convex if the line joining two points on its graph is always above the graph.
Examples of convex and nonconvex functions on Rn are shown in Fig. 3.

CIRCUIT OPTIMIZATION

Fig. 3. Examples of functions that are convex, concave, or neither.

Definition.
A function g defined on a convex set  is said to be a concave function if the function f = g is convex.
The function g is strictly concave if g is strictly convex.
Definition.
The convex programming problem is stated as follows:

where f is a convex function and S is a convex set. This problem has the property that any local minimum of f
over S is a global minimum.
Definition.
A posynomial is a function h of a positive variable x Rn that has the form

where the exponents ij R and the coefficients j >0.

For example, the function 3.7x1.4 1 x3 2 + 1.8x 1 1 x2.3 3 is a posynomial in the variables x1 , x2 , x3 . Roughly
speaking, a posynomial is a function that is similar to a polynomial, except that the coefficients j must
be positive, and an exponent ij could be any real number and not necessarily a positive integer, unlike a
polynomial. A posynomial has the useful property that it can be mapped onto a convex function through an
elementary variable transformation, (xi ) = (ezi ) (8). Such functional forms are useful since in the case of an
optimization problem where the objective function and the constraints are posynomial, the problem can easily
be mapped onto a convex programming problem. A more inclusive function class with similar properties is the
set of generalized posynomials (9).
Definition.
A generalized posynomial function Gk (x), x Rn , where k 0 is called the order of the function, is defined
recursively as follows:
(1) A generalized posynomial of order 0, G0 , is simply the posynomial form defined earlier:

where the exponents ij R and the coefficients j R+ .

CIRCUIT OPTIMIZATION

(2) A generalized posynomial of order k is defined as

where the exponents ij R+ and the coefficients j R+ , and Gk 1,i (x) is a generalized posynomial of
order k1.
Two features of the definition are noteworthy, and we explicitly point them out. First, while the exponents
ij are unrestricted real numbers for G0 , they must necessarily be nonnegative for Gk , k > 0. Second, any
generalized posynomial of order k 1 is, by definition, also a generalized posynomial of order l k. Therefore,
in Eq. (12), Gk 1,i may be any generalized posynomial whose order is no greater than k1. As in the case of
regular posynomials, the mapping (xi ) = (ezi ) transforms a generalized posynomial of any order in the x space
to a convex function in the z space.
Constrained Optimization Methods. Most problems in integrated circuit design involve the minimization or maximization of a cost function subject to certain constraints. In this section, a few prominent
techniques for constrained optimization are presented. The reader is referred to Refs. 1,2, and 6 for details on
unconstrained optimization.
Linear Programming. Linear programming is a special case of nonlinear optimization, and is the convex
programming problem where the objective and constraints are all linear functions. The standard form of the
problem is stated as

Although the requirement on the nonnegativity of x may appear to be a limitation at first, this does not mean
that negative variables cannot be represented. For a variable xi that may be negative, we may simply use the
substitution xi = si1 si2 , where si1 , si2 0.
It can be shown that any solution to a linear program must necessarily occur at a vertex of the constraining
polytope. The most commonly used technique for the solution of linear programs, the simplex method (1), is
based on this principle. The computational complexity of this method can show an exponential behavior for
pathological cases, but for most practical problems, it has been observed to grow linearly with the number
of variables and sublinearly with the number of constraints. Algorithms with polynomial time worst-case
complexity do exist; these include Karmarkars method (10) and the Shor-Khachiyan ellipsoidal method (11).
The computational complexity of the latter, however, is often seen to be impractical from a practical standpoint.
Every linear program is associated with a dual linear program. Duality is a symmetric relationship, so
that the dual of the dual provides the primal. While it is generally true that any linear or nonlinear optimization
problem has a dual form, only in case of a linear program is it always true that the optimal value of the dual
is identical to the optimal value of the primal (original) problem. For a general nonlinear program, if we treat
the primal as the minimization problem and the dual as the maximization problem, then the optimal value of
the dual is less than or equal to that of the primal. The gap is referred to as the duality gap. For the primal

CIRCUIT OPTIMIZATION

form shown in Eq. (13), the dual is given by

If the values of x in Eq. (13) are restricted to the set of integers, the problem is referred to as an integer
linear programming problem. It is important to note that integer linear programming is a harder problem
than linear programming over a continuous space and that none of the existing algorithms for solving these
problems shows polynomial time behavior, either in theory or empirically in practice, for a general integer linear
program. However, for some special problem structures, such as shortest paths and network flows, polynomial
time solutions do exist.
Network Flows. Network flow problems are a specific instance of a linear program that have an
interpretation with respect to a graph construction. A network is a directed graph with two special vertices,
namely, a source s and a sink t, such that every other vertex in the graph lies on a directed path from s to t.
Each edges e = (i,j) in the network is associated with a maximum nonnegative capacity, uij . In the absence
of an edge, the capacity is considered to be zero. A flow through this network is a function that satisfies the
following requirements.

Capacity constraints. For each edge e = (i,j), xij uij , where uij is a constant.
Flow conservation. For each vertex i, i
/ s, t, the total inflow equals the total outflow, that is,

The value of a flow f is given by f = e = (s,i) xsi = e = (j,t) xjt , and an objective function that is often used
is to maximize f . Several problems can be formulated as maximum flow problems, and it is useful to obtain an
intuitive feel for the problem statement. We may think of the source as a water pump of unlimited capacity, the
sink as a reservoir of unlimited capacity, and the edges as pipes that have a limitation on how much water they
may let through in a unit time. The problem of maximizing the flow is then that of determining the maximum
volume of water per unit time that the entire network of pipes can let through.
A related problem is that of finding the minimum cut of a network. A cut is defined as a partition that
divides the vertex set into two parts, X and Y, such that s X, t Y, and X Y = 0. A minimum cut is one that
minimizes the sum of the capacities of edges from X to Y. Intuitively, it is easy to see that the volume of water
per unit time from the previous paragraph is limited by the bottleneck of the problem, which is the minimum
cut (this fact is also provable). This leads to the following result, called the max-flow min-cut theorem: The
value f of the maximum flow in a network is identical to the capacity of its minimum cut.

CIRCUIT OPTIMIZATION

Interestingly, the problem of maximizing the flow in network with n vertices can be represented by a
linear program as follows:

which is referred to a maximum flow problem. The special structure of this linear program can be exploited to
provide fast polynomial-time solutions to the various network flow problems. For details, the reader is referred
to Ref. 12.
A related problem is the minimum cost network flow, which can be stated as follows:

where cij and bi are constants and the xij s constitute the variables for this problem. Again, polynomial-time
algorithms for solving this problem exist. A practically efficient algorithm that is not guaranteed to converge
in polynomial time, but is empirically seen to, is an efficient adaptation of the simplex algorithm for linear
programming, called the network simplex algorithm (12).
An interesting property of the network flow problems is that if the edge capacities are all integers (and
so are the bi s in the case of minimum cost flow problems), then an optimum integer solution exists and can be
found in polynomial time. Therefore, for this specific structure, it is possible to solve the integer linear program
in polynomial time, though this is not possible for general problem statements.
Lagrange Multiplier Methods. The Lagrangian multiplier methods are closely related to the first-order
Kuhn-Tucker necessary conditions on optimality, which state that given an optimization problem of the form
in Eq. (1), if f and g are differentiable at x , then there is a vector Rm , ()i 0, such that

These correspond to m + 1 equations in m + 1 variables; the solution to these provides the solution to the
optimization problem. The variables are known as the Lagrange multipliers. Note that since gi (x ) 0, and
because of the nonnegativity constraint on the Lagrange multipliers , it follows from Eq. (19) that ()i = 0 for
inactive constraints (constraints with gi (x) < 0).

CIRCUIT OPTIMIZATION

Penalty Function Methods. Penalty function methods (13) convert the constrained optimization problem
in Eq. (1) into an equivalent unconstrained optimization problem, since such problems are easier to solve than
constrained problems, as

where P(x) : Rn R is known as a penalty function and c is a constant. The value of P(x) is zero within the
feasible region, and positive outside the region, with the value becoming larger as one moves farther from the
feasible region; one possible choice when the gi (x)s are continuous is given by

For large c, it is clear that the minimum point of Eq. (20) will be in a region where P is small. Thus, as c is
increased, it is expected that the corresponding solution point will approach the feasible region and minimize f .
As c , the solution of the penalty function method converges to a solution of the constrained optimization
problem.
In practice, if one were to begin with a high value of c, one may not have very good convergence properties.
The value of c is increased in each iteration until c is high and the solution converges.
Method of Feasible Directions. The method of feasible directions is an optimization algorithm that
improves the objective function without violating the constraints. Given a point x, a direction d is feasible if
there is a step size > 0 such that x + d F 0 , where F is the feasible region. More informally,
this means that one can take a step of size up to along the direction d without leaving the feasible region.
The method of feasible direction attempts to choose a value of in a feasible direction d such that the objective
function f is minimized along the direction, and is such that x + d is feasible.
One common technique that uses the method of feasible directions is as follows. A feasible direction at x
is found by solving the following linear program:

where the second set of constraints are chosen for all gi b, where b serves to incorporate the effects of
near-active constraints to avoid the phenomenon of jamming (also known as zigzagging) (1). The value of b
is brought closer to 0 as the optimization progresses. One common method that is used as a normalization
requirement is to set dT d = 1; others are given in Ref. 14. This constraint is nonlinear and nonconvex and is
not added to the linear program as an additional constraint; rather, it is exercised by normalizing the direction
d after the linear program has been solved. An appropriate step size in this direction is then chosen by solving
a one-dimensional optimization problem.
Feasible direction methods are popular in finding engineering solutions because the value of x at each
iteration is feasible, the algorithm can be stopped at any time without waiting for the algorithm to converge,
and the best solution found so far can be used.

10

CIRCUIT OPTIMIZATION

Multicriterion Optimization and Pareto Criticality

Most integrated circuit design problems involve tradeoffs between multiple objectives. In cases where one
objective can be singled out as the most important one, and a reasonable constraint set can be defined in
terms of the other objectives, the optimization problem can be stated using the formulation in Eq. (1). This is
convenient since techniques for the solution of a problem in this form have been extensively studied and a wide
variety of optimization algorithms are available.
Let f be a vector of design objectives that is a function of the design variables x, where

It is extremely unlikely in a real application that all of the f i s will be optimal at the same point, and hence
one must trade off the values of the f i s in a search for the best design point.
In this context, we note that at a point x, we are interested in taking a step in a direction d, d,  = 1,
so that

A Pareto critical point is defined as a point x where no such small step of size less than exists in any direction.
If a point is Pareto critical for any step size from the point x, then x is a Pareto point. The notion of a Pareto
critical point is, therefore, similar to that of a local minimum, and that of a Pareto point is similar to a global
minimum. In computational optimization, one is concerned with the problem of finding a local minimum since,
except in special cases, it is the best that one can be guaranteed of finding without an exhaustive search. If the
set of all Pareto critical points is Pc , and the set of Pareto points is P, then clearly P Pc . In general, there
could be an infinite number of Pareto points, but the best circuit design must necessarily occur at a Pareto
point x P.
In Fig. 4, the level curves of two objective functions are plotted in R2 f 1 is nonlinear and has a minimum

at x f 2 is linear and decreases as both x1 and x2 decrease. The Pareto critical set, Pc , is given by the dashed
curve. At a few of the points, the unit normal to the level lines of f 1 and f 2 , that is, the negative gradients of f 1
and f 2 , is shown. From the figure, it can be seen that if the unit normals at point x are not equal and opposite,
then the unit normals will have a common downhill direction allowing a simultaneous decrease in f 1 and f 2 ,
and hence, x would not be a Pareto critical point. Therefore, a Pareto critical point is one where the gradients
of f 1 and f 2 are opposite in direction, that is, f 1 = f 2 , where is some scale factor.
In higher dimensions, a Pareto critical point is characterized by the existence of a set of weights, wi > 0
1 i m, such that

Some of the common methods that are used for multicriterion optimization are discussed in the following
sections.
Weighted-sum optimization. The multiple objectives, f 1 (x), . . ., f m (x) are combined as

where wi > 0 i = 1, . . ., m, and the function F(x) is minimized.

CIRCUIT OPTIMIZATION

11

c
Fig. 4. Exact conflict at a Pareto critical point (
1981
IEEE) (7).

At any local minimum point of F(x), the relation in Eq. (26) is seen to be valid, and hence, x Pc . In
general, P = Pc , but it can be shown that when each f i is a convex function, then P = Pc ; if so, it can also be
shown that all Pareto points can be obtained by optimizing the function F in Eq. (27). However, for nonconvex
functions, there are points x P that cannot be obtained by the weighted sum optimization since Eq. (26) is
only a necessary condition for the minimum of F. A characterization of the Pareto points that can be obtained
by this technique is provided in Ref. 7.
In practice, the wi s must be chosen to reflect the magnitudes of the f i s. For example, if one of the objectives
is a voltage quantity the typical value of which is a few volts, and another is a capacitor value that is typically
a few picofarads, the weight corresponding to the capacitor value would be roughly 1012 times that for the
voltage, in order to ensure that each objective has a reasonable contribution to the objective function value.
The designer may further weigh the relative importance of each objective in choosing the wi s. This objective
may be combined with additional constraints to give a formulation of the type in Eq. (1).
Minmax optimization. The following objective function is used for Eq. (1):

where the weights wi > 0 are chosen as in the case of weighted sums optimization.
The above can equivalently be written as the following constrained optimization problem:

12

CIRCUIT OPTIMIZATION

Minimizing the objective function described by Eq. (28) with different sets of wi values can be used to obtain
all Pareto points (7).
Since this method can, unlike the weighted-sum optimization method, be used to find all Pareto critical
points, it would seem to be a more natural setting for obtaining Pareto points than the weighted-sum minimization. However, when the f i s are convex, the weighted-sum approach is preferred since it is an unconstrained
minimization and is computationally easier than a constrained optimization. It must be noted that when the
f i s are not all convex, the minmax objective function is nonconvex, and finding all local minima is a nontrivial
process for any method.

Discrete Optimization
Simulated Annealing. The simulated annealing algorithm (15) is an approach that is very suitable for
combinatorial optimization problems in which the number of possible solutions is very large, and most iterative
improvement algorithms are liable to be stuck in a local minimum that is not globally optimal. In this section,
we treat the simulated annealing algorithm as a procedure for combinatorial optimization. While extensions
for continuous nonlinear optimization do exist, they are typically used to a lesser degree.
The basic operation during simulated annealing is a move, which is an alteration in the current solution,
most often a minor perturbation. Like a greedy iterative algorithm, simulated annealing accepts a move to the
perturbed solution if it resulted in a lower cost; unlike a greedy approach, however, simulated annealing may
sometimes also accept a move if it has a larger cost than the current solution. This last property permits the
algorithm to perform hill-climbing that helps it to exit from local minima in a quest for the global minimum.
The metaphor that is used here is the process of annealing a metal, where at high temperatures, the atoms
may move freely and randomly in the metal. As the metal cools, the motion of the atoms becomes increasingly
restricted and localized and hence less random. As the metal cools sufficiently slowly, the totality of these
peregrinations lead to a state in which the atoms have been permitted to explore their freedoms and settle into
the minimum energy state with the lowest cost.
In a similar manner, the simulated annealing approach performs a set of iterations in an outer loop that
changes a parameter that is referred to as the temperature. Within this outer loop lies an inner loop in which
a number of moves are made at any given temperature, and the temperature is gradually reduced from a high
value to a low value according to a specified cooling schedule, which dictates how the temperature is changed
from one iteration of this outer loop to the next. For high values of the temperature, almost all moves are
accepted, regardless of whether they increase or decrease the cost of the solution. As the temperature becomes
lower, cost-increasing moves are rejected with larger probabilities. The probability of acceptance is determined
by the Metropolis function, defined as

where Cost is the increase in cost due to the move. At any given temperature, if Cost 0, the move is
accepted; if not, it is accepted with a probability of M (Cost, T), which clearly has the desired behavior. It is
worth noting that 0 < M(Cost, T) < 1.
In practice, the acceptance of the move is determined by generating a random number under a uniform
distribution; note that the probability that a uniformly distributed random variable is less than p, 0 p 1 is
given by p. Therefore, if the number is less than M(Cost, T), then the move is accepted.
The behavior of simulated annealing can be modeled using a Markov chain, where the next state after
a move is dependent only on the current state and not on the history of how that state was attained. Using
such models, it has been shown that simulated annealing will asymptotically find the optimal solution to

CIRCUIT OPTIMIZATION

13

a combinatorial problem. While such a proof is of limited comfort since an engineer can seldom wait until
time reaches infinity, it is definitely true that the procedure, while slower than most other methods, has been
successful in finding better solutions than several of its competing deterministic approaches for many problems.
An interesting feature of simulated annealing is that it is independent of the initial solution since at a high
temperature, almost all moves are accepted, and consequently the initial configuration is soon lost.
Genetic Algorithms. Genetic algorithms (16) are another set of nondeterministic algorithms that
mimic the process of evolution to search for an optimal solution. Genetic algorithms begin with an arbitrary
initial set of solutions, of varying costs, referred to as the population. Each individual in the population is
characterized by a set of symbols, referred to as genes, and the set of genes that identify an individual are
called chromosomes. In each iteration, or a generation, a segment of the population is altered through a set
of random transformations, referred to as crossover, mutation, and inversion. New candidates are created by
applying these transformations to one or more members of the population, with a fitness function being used
to calibrate their ability to survive. In any generation, the fitness function for all members of the population is
computed, and only the fittest survive.
Like simulated annealing, genetic algorithms also operate by permitting solutions that are worse than
the best, with the difference that they maintain a number of solutions in the population instead of only one,
and the manner in which moves are made is different. The likelihood that a solution would survive is dictated
by the fitness of other competing solutions that are created in each generation.
The individual operations may be briefly described as follows. A crossover operation takes the genes of
two parents and generates an offspring by combining the genes of each parent. A mutation operation, on the
other hand, operates only on a single individual, and produces spontaneous random changes in an individual
by altering a subset of these genes. Finally, an inversion operation takes a single chromosome and alters a
randomly chosen segment of the chromosome by flipping it. Note that the inversion operation does not alter
the set of genes associated with that individual solution but merely modifies the order. The significance of the
crossover operation is similar to birth, which allows the chromosomes of two parents to be selectively combined.
On the other hand, since crossover operations within a restricted population could result in inbreeding, the
mutation operation plays the vital role of introducing new external sets of genes that are not to be found
in the current population. Alternatively, mutation may reintroduce sets of genes that were rejected as being
incompatible with some other genes, but that could provide good solutions when combined with others. The
role of inversion is simply to permit the genes within a given solution to be permuted to help enlarge the space
of possible solutions.

Application to Circuit Optimization Problems

Transistor sizing.
Problem Description. Circuit delays in integrated circuits often have to be reduced to obtain faster
response times. A typical complementary metal oxide semiconductor (CMOS) digital integrated circuit consists
of multiple stages of combinational logic blocks that lie between latches that are clocked by system clock
signals. For such a circuit, delay reduction must ensure that valid signals are produced at each output latch
of a combinational block, before any transition in the signal clocking the latch. In other words, the worst-case
input-output delay of each combinational stage must be restricted to be below a certain specification.
Given the circuit topology, the delay of a combinational circuit can be controlled by varying the sizes of
transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the
channel lengths of MOS transistors in a digital circuit are generally uniform. In coarse terms, the circuit delay
can usually be reduced by increasing the sizes of certain transistors in the circuit. Hence, making the circuit
faster usually entails the penalty of increased circuit area. The area-delay tradeoff involved here is, in essence,
the problem of transistor-size optimization.

14

CIRCUIT OPTIMIZATION

Fig. 5. An RC transistor model.

Three formal statements of the problem were proposed in Ref. 17:

where c is a constant. Of all of these, the first form is perhaps the most useful practical form, since a designers
objective is typically to meet a timing constraint dictated by a system clock.
Delay Modeling. We examine the delay modeling procedure used in the program TILOS (Timed Logic
Synthesizer) at the transistor, gate, and circuit levels. Most existing transistor-sizing algorithms use minor
variations on this theme.
A MOS transistor is modeled as a voltage-controlled switch with an on-resistance, Ron , between drain and
source, and three grounded capacitances, Cd , Cs , and Cg , at the drain, source, and gate terminals, respectively,
as shown in Fig. 5. The behaviors of the resistance and capacitances associated with a MOS transistor of
channel width x are modeled as

Other more accurate models that have good analytic properties are discussed in Ref. 9.
At the gate level, delays are calculated in the following manner. For each transistor in a pull-up or pulldown network of a complex CMOS gate, the largest resistive path from the transistor to the gate output is
computed, as well as the largest resistive path from the transistor to a supply rail. Thus, for each transistor,
the network is transformed into an RC line, and its Elmore time constant (18,19) is computed and is taken to be
the gate delay. While finding the Elmore delay, the capacitances that lie between the switching transistor and
the supply rail are assumed to be at the voltage level of the supply rail at the time of the switching transition
and do not contribute to the Elmore delay.
Each Ri is inversely proportional to the corresponding transistor size xi , and each Ci is some constant (for
wire capacitance) plus a term proportional to the width of each transistor the gate, drain, or source of which is
connected to node i. Thus, the delay can be written as a sum of terms formed by a product of resistance terms
of the type A/x1 + A/x2 and capacitance terms of the type Bx2 + Cx3 + D, which yields a posynomial function
of x1 , x2 , and x3 .
At the circuit level, the PERT technique (20) is used to find the circuit delay. A gate is said to be ready
for processing when the signal arrival time information is available for all of its inputs. Initially, since signal
arrival times are known only at the primary inputs, only those gates that are fed solely by primary inputs are

CIRCUIT OPTIMIZATION

15

ready for processing. These are placed in a queue and are scheduled for processing. In the iterative process,
the gate at the head of the queue is scheduled for processing. Each processing step consists of

Finding the latest arriving input to the gate, which triggers the output transitionthis involves finding
the maximum of all worst-case arrival times of inputs to the gate
Adding the delay of the gate to the latest arriving input time, to obtain the worst-case transition time at
the output
Checking all of the gate that the current gate fans out to, to find out whether it is ready for processingif
so, the gate is added to the tail of the queue

The iterations end when the queue is empty. The critical path, defined as the path between an input and
an output with the maximum delay, can be found by successively tracing back, beginning from the primary
output with the latest transition time, and walking back along the latest arriving fan-in of the current gate,
until a primary input is reached.
In the case of CMOS circuits, the rise and fall delay transitions are calculated separately. For inverting
CMOS gates, the latest arriving input rise (fall) transition triggers off a fall (rise) transition at the output. This
can easily be incorporated into the PERT method previously described, by maintaining two numbers, tr and
tf , for each gate, corresponding to the worst-case rise (high transition) and fall (low transition) delays from a
primary input. To obtain the value of tf at an output, the largest value of tr at an input node is added to the
worst-case fall transition time of the gate; the computation of tr is analogous. For noninverting gates, tr and tf
are obtained by adding the rise (fall) transition time to the worst-case input rise (fall) transition time. Since
each gate delay is a posynomial, and the circuit delay found by the PERT technique is a sum of gate delays,
the circuit delay is also a posynomial function of the transistor sizes.
The Area Model. The exact area of a circuit cannot easily be represented as a function of transistor
sizes. This is unfortunate, since a closed functional form facilitates the application of optimization techniques.
As an approximation, the following formula is used by many transistor sizing algorithms, to estimate the active
circuit area:

where xi is the size of the ith transistor and n is the number of transistors in the circuit. In other words, the
area is approximated as the sum of the sizes of transistors in the circuit, which, from the definition equation
(10), is clearly a posynomial function of the xi s.
The Sensitivity-based TILOS Algorithm. The algorithm that was implemented in TILOS (17,21) was
the first used to recognize the fact that the area and delay can be represented as posynomial functions of the
transistor sizes. The algorithm is heuristic and proceeds as follows.
An initial solution is assumed in which all transistors are at the minimum allowable size. In each iteration,
the critical path for the circuit is first determined. Let N be the primary output node on the critical path. The
algorithm then walks backward along the critical path, starting from N. Whenever an output node of a gate,
Gatei , is visited, TILOS examines the largest resistive path between V DD (ground) and the output node if
Gatei s tr (tf ) causes the timing failure at N. This path contains a set of transistors connected between output
and a supply node, including the transistor on the critical path. We classify the transistors as

The critical transistor, that is, the transistor with a gate terminal on the critical path
The supporting transistors, that is, transistors along the largest resistive path from the critical transistor
to the power supply (V DD or ground)
The blocking transistors, that is, transistors along the highest resistance path from the critical transistor
to the logic gate output

16

CIRCUIT OPTIMIZATION

TILOS finds the sensitivity, which is the reduction in circuit delay per increment of transistor size, for
each critical, blocking, and supporting transistor. Since the effect of changing a transistor size on the path
delay is very localized, as it affects only the present gate, its fan-ins, and its fan-outs under the delay model
discussed here, the sensitivities can be calculated very efficiently. The size of the transistor with the greatest
sensitivity is increased by multiplying it by a constant, BUMPSIZE, a user-settable parameter that defaults
to 1.5. The process above is repeated until all constraints are met, implying that a solution is found, or the
minimum delay state has been passed, and any increase in transistor sizes would make it slower instead of
faster, in which case TILOS cannot find a solution.
Since each iteration changes exactly one transistor size, the timing analysis method can employ incremental simulation techniques to update delay information from the previous iteration. This substantially reduces
the amount of time spent in critical path detection.
Note that increasing the size of a transistor with negative sensitivity only means that the delay along the
current critical path can be reduced by changing the size of this transistor, and does not necessarily mean that
the circuit delay can be reduced; the circuit delay is the maximum of all path delays in the circuit, and a change
in the size of this transistor could increase the delay along some other path, making a new path critical. This
is the rationale behind increasing the size of the most sensitive transistor by only a small factor.
Transistor Sizing Using the Method of Feasible Directions. Shyu et al. (22) proposed a two-stage
optimization approach to solve the transistor sizing problem. The delay estimation algorithm is identical to
that used in TILOS. The algorithm can be summarized in the following pseudocode:

In the first stage, the TILOS heuristic is used to generate an initial solution. The heuristic finds a solution
that satisfies the constraints, and only the sized-up transistors are used as design parameters. Although TILOS
is not guaranteed to find an optimal solution, it can serve as an initial guess solution for an iterative technique.
In the second stage of the optimization process, the problem is converted into a mathematical optimization
problem, and is solved by a method of feasible directions (MFD) algorithm described earlier, using the feasible
solution generated in the first stage as an initial guess.
To reduce the computation, a sequence of problems with a smaller number of design parameters is solved.
At first, the transistors on the worst-delay paths (usually more than one) are selected as design parameters.
If, with the selected transistors, the optimizer fails to meet the delay constraints and some new paths become
the worst-delay paths, the algorithm augments the design parameters with the transistors on those paths and
restarts the process. However, while this procedure reduces the run time of the algorithm, one faces the risk of
finding a suboptimal solution since only a subset of the design parameters is used in each step.

CIRCUIT OPTIMIZATION

17

The MFD optimization method proceeds by finding a search direction d, a vector in the n-dimensional
space of the design parameters, based on the gradients of the cost function and some of the constraint functions.
Once the search direction has been computed, a step along this direction is taken, so that the decrease in the
cost and constraint functions is large enough. The computation stops when the length of this step is sufficiently
small.
Since this algorithm has the feature that once the feasible region (the set of transistor sizes for which all
delay constraints are satisfied) is entered, all subsequent improvements will remain feasible, and the algorithm
can be terminated at any time with a feasible solution.
For convergence, the MFD requires that the objective and constraint functions be continuously differentiable. However, since the circuit delay is defined as the maximum of all path delays, the delay constraint
functions are usually not differentiable. To cope with the nondifferentiability of the constraint functions, a
modification of the MFD is used that employs the concept of the generalized gradient (23). The idea is to use a
convex combination of the gradients of the active or nearly active constraints near a discontinuity. For details
of the scheme, the reader is referred to Ref. 22.
Lagrangian Multiplier Approaches. As can be seen from the approaches studied so far, the problem of
transistor sizing can be formulated as a constrained nonlinear programming problem. Hence, the method of
Lagrangian multipliers, described earlier, is applicable. Early approaches that used Lagrangian multipliers
(24,25) rely on the user to provide critical path information, which may be impractical since critical paths are
liable to change as sizing progresses. An alternative solution to transistor-size optimization using Lagrangian
multipliers was presented by Marple. This technique uses a different area model and employs the idea of
introducing intermediate variables to reduce the number of delay constraints from an exponential number to
a number that is linear in the circuit size.
This technique begins with a prespecified layout and performs the optimization using an area model for
that layout. While such an approach has the disadvantage that it may not result in the minimal area over all
layouts, it still maintains the feature that the area and delay constraints are posynomials. Apart from the delay
constraints, there also exist some area constraints, modeled by constraint graphs that are commonly used in
layout compaction (26). These constraints maintain the minimum spacing between objects in the final layout,
as specified by design rules.
The delay of the circuit is modeled by a delay graph D(V,E), where V is the set of nodes (gates) in D, and
E is the set of arcs (connections among gates) in D. This is the same graph on which the PERT analysis is to
be carried out. Let mi represent the worst-case delay at the output of gate i from the primary inputs. Then for
each gate, the delay constraint is expressed as

where gate i fan-in (gate j) and dj is the delay of gate j. Thus, the number of delay constraints is reduced
from a number that could, in the worst case, be exponential in | V |, to one that is linear in | E |, using | V |
additional variables. These techniques are implemented in Refs. 27 and 28.
A more recent work (29) uses the idea of Lagrangian relaxation to solve the problem. The essential idea
is to minimize, using the notation of the section entitled Lagrange Multiplier Methods, the function f (x) +
T g(x) for a fixed value for the Lagrange multiplier vector . After this is done, the value of the is updated,
and the procedure is continued until convergence. The results using this approach were found to be extremely
fast.
Two-step Optimization. Since the number of variables in the transistor-sizing problem, which equals
the number of transistors in a combinational segment, is typically too large for most optimization algorithms
to handle efficiently, many algorithms choose a simpler route by performing the optimization in two steps.
Examples of algorithms that use this idea to solve the transistor-sizing problem are iCOACH (30) and MOSIZ
(31).

18

CIRCUIT OPTIMIZATION

In the first step in MOSIZ, each gate is mapped onto an equivalent macromodeling primitive, such as
an inverter. The transistor-sizing problem on this simplified circuit is then solved. Note that the number of
variables is substantially reduced when each gate is replaced by a simple primitive with fewer transistors. The
delay of each equivalent inverter, with the transistor sizes obtained above, is taken as the timing budget for
the gate represented by that inverter, and the gate is optimized under the timing budget.
iCOACH uses macromodels for timing analysis of the circuit and has the capability of handling dynamic
circuits. The optimizer employs a heuristic to estimate an improvement factor for each gate, which is related
to the sensitivity of the gate. The improvement factor depends on the fan-in count, fan-out count, and the
worst-case resistive path to the relevant supply rail. The improvement factor is then used to allocate a timing
budget to each gate. In the second step, for each gate, a smaller transistor-sizing problem is solved, in which the
areadelay product of the gate is minimized, subject to its delay being within its timing budget. The number
of variables for each such problem equals the number of transistors within the gate, which is typically a small
number. The optimization method used here is Rosenbrocks rotating coordinate scheme (32).
The two steps are repeated iteratively until the solution converges. While this technique has the obvious
advantage of reducing the number of design parameters to be optimized, it suffers from the disadvantage that
the solution may be nonoptimal. This stems from the simplifications introduced by the timing budget allocation;
the timing budget allocated to each gate may not be the same as the delay of the gate for the optimal solution.
A more recent approach (33) performs a set of provably optimal iterations between the delay budgeting
phase and the gate optimization phase. The method proceeds through two phases that are iteratively repeated:
first, fixing the set of transistor sizes and finding a set of delay budgets, under a maximum delay perturbation,
that would minimize the circuit area, and then finding the optimal sizes for each gate corresponding to those
budgets. The method is found to be very fast in practice.
The Convex Programming-based Approach. The algorithm in iCONTRAST (34) solves the underlying
optimization problem exactly. The objective of the algorithm is to solve the transistor-sizing problem in Eq. (28),
where both the area and the delay are posynomial functions of the vector x of transistor sizes. The procedure
described below may easily be extended to solve the formulations in Eqs. (29) and (30) as well; however, these
formulations are not as useful to the designer. The variable transformation (xi ) = (ezi ) maps the problem in Eq.
(28) to

The delay of a circuit is defined to be the maximum of the delays of all paths in the circuit. Hence, it can be
formulated as the maximum of posynomial functions of x. This is mapped by the above transformation onto a
function D(z) that is a maximum of convex functions; a maximum of convex functions is also a convex function.
The area function is also a posynomial in x, and is transformed into a convex function by the same mapping.
Therefore, the optimization problem defined in Eq. (28) is mapped to a convex programming problem, that is, a
problem of minimizing a convex function over a convex constraint set. Due to the unimodal property of convex
functions over convex sets, any local minimum of Eq. (28) is also a global minimum. A convex programming
method (35) is then used to find the unique global minimum of the optimization problem.
Concluding Remarks. The list of algorithms presented above are among the most prominent used for
transistor sizing. For further details and a more complete survey, the reader is referred to Ref. 19. For a related
problem, the gate-sizing problem for selecting optimal gate sizes from a standard cell library, the reader is
referred to Refs. 36,37,38.
The reader must be cautioned here that the actual optimization problem in transistor sizing is not exactly
a posynomial programming problem. The use of Elmore delay models (which are accurate within about 20%) to

CIRCUIT OPTIMIZATION

19

approximate the circuit delay, and the use of approximate area models allows the problem to be formulated as
a convex program, and hence although one may solve this optimization problem exactly, one still must endure
the inaccuracies of the modeling functions. In practice, in most cases, this is not a serious problem.
Design Centering. The design-centering problem is described in this section, and this discussion
provides some insight into the formulation of the problem as a linear program and as a convex program.
Problem Description. While manufacturing a circuit, it is inevitable that process variations will cause
design parameters, such as component values, to waver from their nominal values. As a result, the manufactured circuit may no longer meet some behavioral specifications, such as requirements on the delay, gain, and
bandwidth, that it has been designed to satisfy. The procedure of design centering attempts to select the nominal values of design parameters so as to ensure that the behavior of the circuit remains within specifications,
with the greatest probability. In other words, the aim of design centering is to ensure that the manufacturing
yield is maximized.
The values of n design parameters may be ordered as an n-tuple that represents a point in Rn . A point
is feasible if the corresponding values for the design parameters satisfy the behavioral specifications on the
circuit. The feasible region (or the region of acceptability), Rf Rn , is defined as the set of all design points for
which the circuit satisfies all behavioral specifications.
The random variations in the values of the design parameters are modeled by a probability density
function, (z) : Rn [0,1], with a mean corresponding to the nominal value of the design parameters. The
yield of the circuit Y as a function of the mean x is given by

The design center is the point x at which the yield, Y(x), is maximized. There have traditionally been
two approaches to solving this problem: one based on geometrical methods and another based on statistical
sampling. In addition, several methods that hybridize these approaches also exist.
A common assumption made by geometrical design centering algorithms is that Rf is a convex bounded
body. Geometrical algorithms recognize that the evaluation of the integral in Eq. (39) is computationally
difficult and generally proceed as follows: the feasible region in the space of design parameters, that is, the
region where the behavioral specifications are satisfied, is approximated by a known geometrical body, such as
a polytope or an ellipsoid. The center of this body is then approximated and is taken to be the design center.
The Simplicial Approximation Method. The simplicial approximation method (39) is a method for approximating a feasible region by a polytope and finding its center. This method proceeds in the following
steps:
(1) Determine a set of m n + 1 points on the boundary of Rf .
(2) Find the convex hull (see the section entitled Basic Definitions) of these points and use this polyhedron
as the initial approximation to Rf . In the two-dimensional example in Fig. 6(a), the points 1, 2, and 3 are
chosen in step (a), and their convex hull is the triangle with vertices 1, 2, and 3. Set k = 0.
(3) Inscribe the largest n-dimensional hypersphere in this approximating polyhedron and take its center as
the first estimate of the design center. This process involves the solution of a linear program. In Fig. 6(a),
this is the hypersphere C0 .
(4) Find the midpoint of the largest face of the polyhedron, that is, the face in which the largest (n1)dimensional hypersphere can be inscribed. In Fig. 6(a), the largest face is 23, the face in which the largest
one-dimensional hypersphere can be inscribed.

20

CIRCUIT OPTIMIZATION

c
Fig. 6. The simplicial approximation method (
1977
IEEE) (39).

(5) Find a new boundary point on Rf by searching along the outward normal of the largest face found in step
(d) extending from the midpoint of this face. This is carried out by performing a line search. In Fig. 6(a),
point 4 is thus identified.
(6) Inflate the polyhedron by forming the convex hull of all previous points, plus the new point generated in
step (e). This corresponds to the quadrilateral vertices 1, 2, 3, and 4 in Fig. 6(a).
(7) Find the center of the largest hypersphere inscribed in the new polyhedron found in step (f). This involves
the solution of a linear program. Set k = k + 1, and go to step (d). In Fig. 6(a), this is the circle C1 .
Further iterations are shown in Fig. 6(b). The process is terminated when the sequence of radii of the
inscribed hypersphere converges.
The procedure of inscribing the largest hypersphere in the polytope proceeds as follows. Given a polytope
specified by Eq. (5), if the ai s are chosen to be unit vectors, then the distance of a point x from each hyperplane
of the polytope is given by r = aT i x bi .
The center x and radius r of the largest hypersphere that can be inscribed within the polytope P are then
given by the solution of the following linear program:

Since the number of unknowns of this linear program is typically less than the number of constraints, it is
more desirable to solve its dual (1). A similar technique can be used to inscribe the largest hypersphere in a
face of the polytope; for details, see Ref. 39. For a generalization of the simplicial approximation method for
the inscription of maximal norm bodies to handle joint probability density functions with (nearly) convex level
contours, see Ref. 40.
If the above design-centering procedure is applied to a rectangular feasible region, the best possible
results may not be obtained by inscribing a hypersphere. For elongated feasible regions, it is more appropriate to
determine the design center by inscribing an ellipsoid rather than a hypersphere. The simplicial approximation
handles this problem by scaling the axes so that the lower and upper bounds for each parameter differ by the
same magnitude, and it is shown in Ref. 39 that one may inscribe the largest ellipsoid by inscribing the largest
hypersphere in a transformed polytope. This procedure succeeds in factoring in reasonably the fact that feasible

CIRCUIT OPTIMIZATION

21

c
Fig. 7. The ellipsoidal method (
1991
IEEE) (41).

regions may be elongated; however, it considers only a limited set of ellipsoids that have their axes aligned
with the coordinate axis, as candidates for inscription within the polytope.
The Ellipsoidal Method. This method, proposed in Ref. 41, is based on principles similar to those used by
the Shor-Khachiyan ellipsoidal algorithm for linear programming (11). This algorithm attempts to approximate
the feasible region by an ellipsoid, and takes the center of the approximating ellipsoid as the design center.
It proceeds by generating a sequence of ellipsoids, each smaller than the last, until the procedure converges.
Like other methods, this procedure assumes that an initial feasible point is provided by the designer. The steps
involved in the procedure are as follows (see also Fig. 7):
(1) Begin with an ellipsoid E0 that is large enough to contain the desired solution. Set j = 0.
(2) From the center of the current ellipsoid, choose a search direction, and perform a binary search to identify a
boundary point along that direction. One convenient set of search directions are the parameter directions,
searching along the ith, i = 1, 2, . . ., n in a cycle, and repeating the cycle, provided the current ellipsoid
center is feasible. If not, a linear search is conducted along a line from the current center to the given
feasible point.
(3) A supporting hyperplance (1) at the boundary point can be used to generate a smaller ellipsoid, Ej+1 , that is
guaranteed to contain the feasible region Rf , if Rf is convex. The equation of Ej+1 is provided by an update
procedure described in Ref. 41.
(4) Increment j, and go to step (a) unless the convergence criterion is met. The convergence criterion is triggered
when the volume is reduced by less a given factor, . Upon convergence, the center of the ellipsoid is taken
to be the design center.

Convexity-based Approaches. In the technique presented in Ref. 42, the feasible region, Rf Rn , is

first approximated by a polytope described by Eq. (5). The algorithm begins with an initial feasible point, z0
Rf . An n-dimensional box, namely, {z Rn | zmin zi zmax }, containing Rf is chosen as the initial polytope P0 .
In each iteration, n orthogonal search directions, d1 , d2 . . . dn are chosen (possible search directions include

22

CIRCUIT OPTIMIZATION

c
Fig. 8. Polytope approximation for the convexity-based methods (
1994
IEEE) (42).

the n coordinate directions). A binary search is conducted from z0 to identify a boundary point zbi of Rf , for
each direction di . If zbi is relatively deep in the interior of P, then the tangent plane to Rf at zbi is added to
the set of constraining hyperplanes in Eq. (5). A similar procedure is carried out along the direction di . Once
all of the hyperplanes have been generated, the approximate center of the new polytope is calculated, using a
method described in Ref. 42. Then z0 is reset to be this center, and the above process is repeated.
Therefore, unlike the simplicial approximation method that tries to expand the polytope outwards, this
method starts with a large polytope and attempts to add constraints to shrink it inwards. The result of polytope
approximation on an ellipsoidal feasible region is illustrated in Fig. 8.
When the probability density functions that represent variations in the design parameters are Gaussian
in nature, the design-centering problem can be posed as a convex programming problem. The joint Gaussian
probability density function of n independent random variables z = (z1 , . . ., zn ) with mean x = (x1 , . . ., xn ) and
variance = (1 . . ., n ) is given by

This is easily seen to be a log-concave function of x and z, that is, the logarithm of the function x (z) is
concave in x and z. Also, note that arbitrary covariance matrices can be handled, since a symmetric matrix
may be converted into a diagonal form by a simple linear (orthogonal) transformation. The design centering

CIRCUIT OPTIMIZATION

23

c
Fig. 9. Two different retimings for the same circuit (
1998
IEEE) (60).

problem is now formulated as

where P is the polytope approximation to the feasible region Rf . It is a known fact that the integral of a logconcave function over a convex region is also a log-concave function. Thus, the yield function Y(x) is log-concave,
and the above problem reduces to a problem of maximizing a log-concave function over a convex set. Hence,
this can be transformed into a convex programming problem. A convex programming algorithm (35) is then
applied to solve the optimization problem.
Concluding Remarks. The list of algorithms above is by no means exhaustive but provides a general
flavor for how optimization methods are used in geometrical design centering. The reader is referred to Refs. 43,
44,45,46 for further information about statistical design. In conclusion, it is appropriate to list a few drawbacks
associated with geometrical methods: first, it is not always true that the feasible region will be convex; second,
although some methods such as the simplicial approximation assume the center of the ellipsoid to be the design
center, this is not accurate, as the precise design center can change depending on the probability distributions
of the variables; and third, geometric methods suffer from the so-called curse of dimensionality, whereby the
computational complexity of these algorithms increases greatly with the number of variables.

Retiming.
Introduction. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates
to allow the circuit to be operated under a faster clock. The chief idea is that while the FFs are relocated
internally, the circuit must remain unchanged from an input-output perspective. Specifically, every path must
have an identical latency (number of FF stages) in the original and in the retimed circuit. An example of a
simple circuit under two different retimings is shown in Fig. 9.
The technique was first proposed by Leiserson, Rose, and Saxe (47,48), where the algorithmic basis
of retiming circuits with edge-triggered FFs was described without specifically focusing on implementational
aspects. Several papers have been published since then, such as Refs. 49,50,51,52,53,54,55,56, primarily dealing
with algorithmic issues and extending the LeisersonRoseSaxe method to handle variations of the original
LeisersonRoseSaxe problem.

24

CIRCUIT OPTIMIZATION

Notation. A sequential circuit can be represented by a directed graph G(V, E), where each vertex v
corresponds to a gate, and a directed edge euv represents a connection from the output of gate u to the input of
gate v, through zero or more registers. Each edge has a weight w(euv ), which is the number of registers between
the output of gate u and the input of gate v. Each vertex has a constant delay d(v). A special vertex, the host
vertex, is introduced in the graph, with edges from the host vertex to all primary inputs of the circuit and edges
from all primary outputs to the host vertex.
A retiming is a labeling of the vertices r : V Z, where Z is the set of integers. The weight of an edge euv
after retiming, denoted by wr (euv ) is given by

The retiming label r(v) for a vertex v represents the number of registers moved from its output towards its
inputs. One may define the weight of any path p originating at vertex u and terminating at vertex v (represented
as u v), w(p), as the sum of the weights on the edges on p, and its delay d(p) as the sum of the weights of
the vertices on p. A path with w(p) = 0 corresponds to a purely combinational path with no registers on it;
therefore, the clock period can be calculated as

Another important concept used in the LeisersonRoseSaxe approach is that of the W and D matrices
that are defined as follows:

The matrices are defined for all pairs of vertices (u, v) such that there exists a path p : u v that does not
include the host vertex. W(u, v) denotes the minimum latency, in clock cycles, for the data flowing from u to v
and D(u, v) gives the maximum delay from u to v for the minimum latency.
The retiming problem as posed by Leiserson, Rose, and Saxe can be framed in the following two ways:
(1) The minimum period retiming problem, in which FFs are relocated to obtain a circuit with the minimum
clock period, without any consideration to the area penalty due to an increase in the number of registers.
Retiming for a specified clock period is a special case of this problem.
(2) The constrained minimum area retiming problem, in which FFs are relocated to achieve a given target clock
period with the minimum register count. Constrained minimum area retiming is a much harder problem
than minimum period retiming. Unconstrained minimum area retiming (i.e., retiming for minimum area
without any regard for the final clock period) is a special case of minimum area retiming and can be solved
efficiently because the time-consuming step of generating the period constraints (to be defined later) is not
required.

CIRCUIT OPTIMIZATION

25

Minimum period retiming. The minimum period retiming problem can be stated as follows:

Note that this is not a linear program, since the second set of constraints depends on P. However, it can be
solved efficiently by a binary search on the value of P. For a given value of P, there is no objective function, and
the task is simply to find a feasible solution that satisfies all of the constraints, which are easily verified to be
linear in the r variables.
The search could proceed as follows: starting with an initial interval, [Pmin , Pmax ], test to see whether the
constraints are satisfiable for Pmid = Pmin + Pmax /2. If so, reduce the search interval to [Pmin , Pmid ]; otherwise,
reduce it to [Pmid , Pmax ]. The search is completed when the interval is sufficiently small. The binary search
approach is supported by the (provable) observation that if no such solution exists for a given value of P, then
no solution exists for any smaller value of P.
Therefore, at each step of the binary search, we must find a feasible point that satisfies a set of linear
constraints. While this may be solved as a linear program, we can observe that each constraint has a very
specific form: it says that the difference between two variables should be no larger than a constant. Such a
system is referred to as a system of difference constraints (57) and can be solved using graph traversal methods.
Specifically, for each constraint of the type

one may build a constraint graph with one vertex for each r variable, with an edge from vertex v to vertex u
with a weight of c. The solution to this system then corresponds to the shortest path in the graph from the
host node, whose r variable is used as a reference and set to 0. For a general set of edge weights cuv which
may be larger or smaller than 0, the Bellman-Ford algorithm (57) may be applied to this graph to find the
shortest paths. Note that there may be many feasible solutions to the set of inequalities, and the Bellman-Ford
algorithm only identifies one of these.
Minimum area retiming. For minimum period retiming or for a retiming for any period, there are, in
general, a number of solutions that correspond to different ways of using up the slacks in the constraint graph.
The minimum area retiming problem for a target period P finds the solution that has the smallest number of
FFs. It can be formulated as the following linear program:

where FI(v) and FO(v) represent the fan-in and fan-out sets of the gate v.
The significance of the objective function and the constraints is as follows (the reader is referred to Ref.
48 for details).

26

CIRCUIT OPTIMIZATION
The objective function represents the number of registers added to the retimed circuit in relation to the
original circuit.
The first constraint ensures that the weight euv of each edge (i.e., the number of registers between the
output of gate u and the input of gate v) after retiming is nonnegative. We will refer to these constraints as
circuit constraints.
The second constraint ensures that after retiming, each path whose delay is larger than the clock period
has at least one register on it. These constraints, being dependent on the clock period, are often referred to
as period constraints.

It is easily verified, using the relations in Eqs. (13), (14), and (17), that the dual of this problem is an
instance of a minimum-cost network flow problem.
Concluding Remarks. Some recent algorithms have presented fast and practical solutions to the retiming problem for large circuits. These include Refs. 58,59,60,61 and proceed primarily by pruning the number of
constraints in the problem using insights available from a deeper study of the problem. Other approaches (62,63)
provide a framework for incorporating long-path and short-path constraints together in a single formulation.
Placement. During the layout of a circuit, it is common for the preliminary layout of each module, such
as a gate, to be designed independently. Subsequently, depending on the load to be driven, the module may be
altered through sizing or other synthesis transformations. The placement problem involves the determination
of locations for a set of modules that have a fixed size. The modules may be joined by a set of nets, each of which
is connected to two or more modules. This connection point for a module is at a location that is fixed relative
to a reference point on the module, such as the bottom left corner. The objective of the placement problem may
be to minimize the packing area and to optimize the wire length or congestion or delay in the circuit.
While many algorithms for placement have been proposed (see, for example Refs. 64,65, and 26 for a
survey), in this section, we will concentrate on two algorithms that use simulated annealing and genetic
algorithms, respectively. The placement problem is amenable to being tackled using these approaches since
it is inherently a combinatorial problem that has a very large search space, which is practically difficult to
optimize over.
Placement by Simulated Annealing. One of the most successful placement algorithms for placement,
which is often used as a benchmark against which to compare other placers, is based on the application of simulated annealing. The TimberWolf algorithm (66) is directed towards standard cell-based applications, where
cells are arranged in rows so that all cells in a row have the same height but possibly different widths (26).
The skeleton of the algorithm progressing according to the simulated annealing procedure described
earlier. At each temperature, a fixed number of moves is made. A move may consist of one of three actions:
(i) moving a single cell to a new location in the same row or a different row, (ii) swapping two cells, and (iii)
mirroring a cell while leaving its height and location unchanged. The first two types make up a majority of the
moves, a relatively smaller number of the last type of move are introduced, and the ratio of the first type of
move to the second is a parameter that is found to provide the best performance at values significantly larger
than 1 (typically 3 to 8). The distance that a cell can move is bounded by a temperature-limited range limiter,
which reduces this distance logarithmically with the temperature.
The cost function is a weighted sum of three components:
(1) The wire length cost, estimated as the sum, over all nets, of the semiperimeter of the bounding box of each
net (with the option of weighting horizontal and vertical spans differently)
(2) A term that penalizes overlaps between cells, taken as the sum of the squares of overlaps between between
all pairs of cells
(3) A term that penalizes nonuniformity of row lengths, taken as a sum, over all rows, of the absolute value of
the difference between an expected row length and the actual row length

CIRCUIT OPTIMIZATION

27

The cooling schedule for annealing is taken by multiplying the temperature T i at the ith outer loop
iteration by a factor (T i ) to obtain the temperature for the (i + 1)th iteration. The value of is typically set
to a lower value (such as 0.8) for the upper and lower ranges of the temperature schedule and a higher value
(such as 0.95) for the middle range.
Genetic Algorithms for Placement. The work in Ref. 67 presents an excellent example of the application of a genetic algorithm on the standard cell placement problem. The general framework is the same as described earlier. The genes correspond to ordered triples that define the cell identities and their x and y locations.
The crossover operation combines the genes of two parents to obtain an offspring chromosome. For a layout
with n cells, the process of crossover can be performed by choosing the first k < n cells from one chromosome, for
some random value of k, and appending the remaining n k to the end of the string that identifies the offspring
cell. Note that the ordering of the genes in the chromosome is important since two parents with the same
genes but differently ordered chromosomes could lead to a different offspring even for the same value of k.
The mutation operation is a unary operation, and exchanges the locations of two cells. This corresponds to
altering the genes in the chromosome so that their (x,y) locations are swapped. Finally, the inversion operation
does not alter the placement correspond to a chromosome, but simply inverts the order of genes in a substring
of the chromosome. Note that this permits a larger variation in the possible offspring that may be produced as
a result of future crossover operations.
The fitness function is calculated as the inverse of the sum of the semiperimeters of all nets, with the
horizontal and vertical directions being weighted differently. In each generation a set of crossover, mutation,
and inversion operations are performed according to a specified rate. The crossover and mutation operations
could potentially result in cell overlaps and are followed by a step that realigns the cells to remove these
overlaps in the offspring. Following this step, the fitness function is evaluated for each offspring. Finally, a
selection method is applied to cull the set of offspring to maintain the fittest of these in the population using
either a deterministic or a random criterion, so as to maintain a constant population. The procedure continues
for a certain number of generations, after which the fittest solution is selected.

Conclusion
The potential for applying optimization methods to circuit optimization is vast and has been shown to provide efficient optimal solutions. A good solution combines accurate models with an efficient optimizer, and
compromising too much on either can lead to unusable solution. This article has presented a survey of such
optimization algorithms and examples of their application to circuit optimization problems. Prominent conferences in this area, such as the ACM/IEEE Design Automation Conference and the IEEE/ACM International
Conference on Computer-Aided Design and journals such as the IEEE Transactions on Computer-Aided Design, the IEEE Transactions on VLSI Systems, and the ACM Transactions on Design Automation of Electronic
Systems publish the most recent advances in this area and are good references for further reading.

Acknowledgments
This effort was supported in part by the Semiconductor Research Corporation under Contract No. 99-TJ-692
and by the National Science Foundation under Grant No. CCR-9800992.

BIBLIOGRAPHY
1. D. G. Luenberger Linear and Nonlinear Programming, 2nd ed., Reading, MA: Addison-Wesley, 1984.
2. P. E. Gill W. Murray M. H. Wright Numerical Linear Algebra and Optimization, Reading, MA: Addison-Wesley, 1991,
Vol. 1.

28

CIRCUIT OPTIMIZATION

3. M. Berkelaar LP SOLVE Users Manual, 1992.

4. B. A. Murtagh M. A. Saunders, MINOS 5.4 Users Guide, Tech. Rep. SOL 83-20R, Stanford University, Stanford, CA,
1995.
5. A. R. Conn N. I. M. Gould P. L. Toint LANCELOT: A Fortran Package for Large-Scale Nonlinear Optimization, Heidelberg: Springer, 1992.
6. W. H. Press S. A. Teukolsky W. T. Vetterling B. P. Flannery Numerical Recipes in C: The Art of Scientific Computing,
2nd ed., New York: Cambridge University Press, 1992.
7. R. K. Brayton G. D. Hachtel A. L. Sangiovanni-Vincentelli A survey of optimization techniques for integrated-circuit
design, Proc. IEEE, 69: 13341362, 1981.
8. J. Ecker Geometric programming: methods, computations and applications, SIAM Rev., 22: 338362, 1980.
9. M. Ketkar K. Kasamsetty S. S. Sapatnekar Convex delay models for transistor sizing, in Proc. ACM/IEEE Design
Automation Conf., 2000.
10. N. Karmarkar A new polynomial-time algorithm for linear programming, Combinatorica, 4: 373395, 1984.
11. A. Schrijver Theory of Linear and Integer Programming, New York: Wiley, 1986.
12. M. S. Bazaraa J. J. Javis H. Sherali Linear Programming and Network Flows, New York: Wiley, 1977.
13. A. V. Fiacco G. P. McCormick Nonlinear Programming: Sequential Unconstrained Minimization Techniques, New York:
Wiley, 1968.
14. G. Zoutendijk Methods of Feasible Directions: A Study in Linear and Nonlinear Programming, Amsterdam, The Netherlands: Elsevier, 1960.
15. S. Kirkpatrick C. Gelatt, Jr., M. Vecchi Optimization by simulated annealing, Science,220: 671680,
1983.
16. D. E. Goldberg Genetic Algorithms in Search, Optimization, and Machine Learning, Reading, MA: Addison-Wesley,
1989.
17. J. Fishburn A. Dunlop TILOS: A posynomial programming approach to transistor sizing, inProc. IEEE Int. Conf.
Comput.-Aided Design, 1985, pp. 326328.
18. J. Rubinstein P. Penfield M. A. Horowitz Signal delay in RC tree networks, IEEE Trans. Comput.-Aided Design,CAD-2:
202211, 1983.
19. S. S. Sapatnekar S. M. Kang Design Automation for Timing-Driven Layout Synthesis, Norwell, MA: Kluwer Academic,
1993.
20. T. Kirkpatrick N. Clark PERT as an aid to logic design, IBM J. Res. Devel.,10: 135141, 1966.
21. D. Hill D. Shugard J. Fishburn K. Keutzer Algorithms and Techniques for VLSI Layout Synthesis, Norwell, MA: Kluwer
Academic, 1989.
22. J. Shyu J. P. Fishburn A. E. Dunlop A. L. Sangiovanni-Vincentelli Optimization-based transistor sizing, IEEE J.
Solid-State Circuits,23: 400409, 1988.
23. F. H. Clarke Optimization and Nonsmooth Analysis, New York: Wiley-Interscience, 1983.
24. M. A. Cirit Transistor sizing in CMOS circuits, inProc. 24th ACM/IEEE Design Automation Conf., June 1987, pp.
121124.
25. K. S. Hedlund AESOP: A tool for automated transistor sizing, in Proc.24th ACM/IEEE Design Automation Conf., June
1987, pp. 114120.
26. N. Sherwani Algorithms for VLSI Physical Design Automation, Norwell, MA: Kluwer Academic, 1995.
27. D. Marple A. E. Gamal Area-delay optimization of programmable logic arrays, inProc. Adv. Res. VLSI, Apr. 1986, pp.
171194.
28. D. Marple A. E. Gamal Optimal selection of transistor sizes in digital VLSI circuits, inProc. Adv. Res. VLSI, 1987, pp.
151172.
29. C.-P. Chen C. C. N. Chu D. F. Wong Fast and exact simultaneous gate and wire sizing using lagrangian relaxation,
inProc. IEEE/ACM Int. Conf. Comput.-Aided Design, 1999, pp. 617624.
30. H. Y. Chen S. M. Kang iCOACH: A circuit optimization aid for CMOS high-performance circuits, Integration, VLSI
J.,10: 185212, 1991.
31. Z. Dai K. Asada MOSIZ: A two-step transistor sizing algorithm based on optimal timing assignment method for
multi-stage complex gates, inProc. 1989 Custom Integrated Circuits Conf., May 1989, pp. 17.3.117.3.4.
32. H. H. Rosenbrock An automatic method for finding the greatest or least value of a function, Comput. J.,3: 175184,
1960.

CIRCUIT OPTIMIZATION

29

33. V. Sundararajan S. S. Sapatnekar K. K. Parhi MINFLOTRANSIT: Min-cost flow based transistor sizing tool, inProc.
ACM/IEEE Design Automation Conf., 2000.
34. S. S. Sapatnekar V. B. Rao P. M. Vaidya S. M. Kang An exact solution to the transistor sizing problem for CMOS circuits
using convex optimization, IEEE Trans. Comput.-Aided Des.12: 16211634, 1993.
35. P. M. Vaidya A new algorithm for minimizing convex functions over convex sets, Proc. IEEE Found. Comput. Sci., 1989
(Oct.): 332337.
36. W. Chuang S. S. Sapatnekar I. N. Hajj Delay and area optimization for discrete gate sizes under double-sided timing
constraints, inProc. IEEE Custom Integrated Circuits Conf., 1993, pp. 9.4.19.4.4.
37. P. K. Chan Algorithms for library-specific sizing of combinational logic, inProc. ACM/IEEE Design Automation Conf.,
1990, pp. 353356.
38. S. Lin M. Marek-Sadowska E. S. Kuh Delay and area optimization in standard-cell design, inProc. ACM/IEEE Design
Automation Conf., 1990, pp. 349352.
39. S. W. Director G. D. Hachtel The simplicial approximation approach to design centering, IEEE Trans. Circuits
Syst.,CAS-24: 363372, 1977.
40. R. K. Brayton S. W. Director G. D. Hachtel Yield maximization and worst-case design with arbitrary statistical distributions, IEEE Trans. Circuits Syst.,27: 756764, 1980.
41. H. L. Abdel-Malek A.-K. S. O. Hassan The ellipsoidal technique for design centering and region approximation, IEEE
Trans. Comput.-Aided Des.,10: 10061014, 1991.
42. S. S. Sapatnekar P. M. Vaidya S. M. Kang Convexity-based algorithms for design centering, inProc. IEEE/ACM Int.
Conf. Comput.-Aided Design, 1993, pp. 206209.
43. S. W. Director P. Feldmann K. Krishna Statistical integrated circuit design, IEEE J. Solid-State Circuits,28: 193202,
1993.
44. M. D. Meehan J. Purviance Yield and Reliability in Microwave Circuit and System Design, Boston, MA: Artech House,
1993.
45. S. W. Director W. Maly A. J. Strojwas VLSI Design for Manufacturing: Yield Enhancement, Boston, MA: Kluwer
Academic, 1990.
46. R. Spence R. S. Soin Tolerance Design of Integrated Circuits, Reading, MA: Addison-Wesley, 1988.
47. C. Leiserson F. Rose J. B. Saxe Optimizing synchronous circuitry by retiming, inProc. of the 3rd Caltech Conf. on VLSI,
1983, pp. 87116.
48. C. E. Leiserson J. B. Saxe Retiming synchronous circuitry, Algorithmica,6: 535, 1991.
49. N. Shenoy R. K. Brayton A. Sangiovanni-Vincentelli Retiming of circuits with single phase transparent latches, inProc.
IEEE Int. Conf. Comput. Design, 1991, pp. 8689.
50. A. Ishii C. E. Leiserson M. C. Papaefthymiou Optimizing two-phase, level-clocked circuitry, inAdv. Res. VLSI Parallel
Systems: Proc. 1992 Brown/MIT Conf., 1992, pp. 246264.
51. H.-G. Martin Retiming by combination of relocation and clock delay adjustment, inEur. Design Automation Conf., 1993,
pp. 384389.
52. T. Soyata E. G. Friedman J. H. Mulligan, Jr., Integration of clock skew and register delays into a retiming algorithm,
inProc. IEEE Int. Symp. Circuits Syst., 1993, pp. 14831486.
53. A. T. Ishii Retiming gated-clocks and precharged circuit structures, inProc. IEEE/ACM Int. Conf. Comput.-Aided
Design, 1993, pp. 300307.
54. B. Lockyear C. Ebeling Optimal retiming of level-clocked circuits using symmetric clock schedules, IEEE Trans.
Comput.-Aided Des., 10971109, 1994.
55. T. Soyata E. G. Friedman Retiming with non-zero clock skew, variable register and interconnect delay, inProc.
IEEE/ACM Int. Conf. Comput.-Aided Design, 1994, pp. 234241.
56. K. N. Lalgudi M. Papaefthymiou DeLaY: An efficient tool for retiming with realistic delay modeling, inProc. ACM/IEEE
Design Automation Conf., 1995, pp. 304309.
57. T. H. Cormen C. E. Leiserson R. L. Rivest Introduction to Algorithms, New York: McGraw-Hill, 1990.
58. N. Shenoy R. Rudell Efficient implementation of retiming, inProc. IEEE/ACM Int. Conf. Comput.-Aided Design, 1994,
pp. 226233.
59. R. B. Deokar S. S. Sapatnekar A fresh look at retiming via clock skew optimization, inProc. ACM/IEEE Design
Automation Conf., 1995, pp. 310315.
60. N. Maheshwari S. S. Sapatnekar Efficient retiming of large circuits, IEEE Trans. VLSI Syst.6: 7483, 1998.

30

CIRCUIT OPTIMIZATION

61. N. Maheshwari S. S. Sapatnekar Optimizing large multiphase level-clocked circuits, IEEE Trans. Comput.-Aided
Des.,18: 12491264, 1999.
62. M. Papaefthymiou Asymptotically efficient retiming under setup and hold constraints, inProc. IEEE/ACM Int. Conf.
Comput.-Aided Design, 1998, pp. 288295.
63. V. Sundararajan S. S. Sapatnekar K. K. Parhi Marsh: Minimum area retiming with setup and hold constraints, inProc.
IEEE/ACM Int. Conf. Comput.-Aided Design, 1999, pp. 26.
64. M. Sarrafzadeh C. K. Wong An Introduction to VLSI Physical Design, New York: McGraw-Hill, 1996.
65. S. M. Sait H. Youssef VLSI Physical Design Automation: Theory and Practice, New York: IEEE, 1995.
66. C. Sechen A. L. Sangiovanni-Vincentelli TimberWolf3.2: A new standard cell placement and global routing package,
inProc. ACM/IEEE Design Automation Conf., 1986, pp. 432439.
67. K. Shahookar P. Mazumder A genetic approach to standard cell placement using meta-genetic parameter optimizations,
IEEE Trans. Comput.-Aided Des.,9: 500511, 1990.

SACHIN S. SAPATNEKAR
University of Minnesota

254

SIGNAL AMPLIFIERS

SIGNAL AMPLIFIERS
OPEN-LOOP AMPLIFIERS
Amplification is needed whenever a signal (coming from a
transducer, an antenna, etc.) is too small to be efficiently processed. A signal amplifier is primarily intended to operate on
very small input signals with the aim of increasing the signal
energy. For instance, a voltage amplifier works with input
signals in the range of millivolts or even microvolts, and has
to provide a power gain. This last property distinguishes a
voltage amplifier from a transformer. A transformer, in fact,
can provide an output voltage greater than the input (primary) voltage, but the output power never exceeds the power
supplied by the signal source. The smallest signal which can
be detected and amplified is limited by the noise performance
of the amplifier. In fact, noise masks the signal so that recovery may not be possible. Linearity is another fundamental reJ. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

SIGNAL AMPLIFIERS

Ii

the circuit ground. Depending on the signal type to be amplified and on the desired type of output, amplifiers can be classified into four categories:

Io

Vi

Vo

1. Voltage amplifiers, with an open-circuit voltage gain

Avo Vo /Vi
2. Current amplifiers, with a short-circuit current gain
Aio Io /Ii
3. Transresistance amplifiers, with an open-circuit transresistance gain Rto Vo /Ii
4. Transconductance amplifiers, with a short-circuit transconductance gain Gto Io /Vi

(a)

Ii

Vi

Io

Vo

(b)
Figure 1. (a) Amplifier symbol; (b) amplifier with a common terminal (ground).

quirement for a signal amplifier, in order to ensure that the

signal information is not changed and no new information is
introduced. An amplifier providing an output signal linearly
related to the input is characterized by the relationship
xo = Axi

(1)

where xi and xo are the input and the output signals, respectively, which can be either voltage or currents, and A is a
constant representing the magnitude of the amplification,
usually termed the amplifier gain.
In general, an amplifier is a two-port network, which can
be represented by the circuit symbol in Fig. 1(a), showing the
input and output ports as well as the signal flow direction.
The amplifier model considered is unilateral since the signal
flow is unidirectional. This usually leads to a good approximation of real-life amplifiers which, however, also exhibit an undesired reverse transmission. Figure 1(b) illustrates a usual
situation where a common terminal between the input and
the output port exists and is used as a reference point called

ro

Vi

ri

AvoVi

In Fig. 2 circuit models for the four types of amplifier are

illustrated, also accounting for finite input and output resistances. These models are independent of the complexity of the
amplifier, which can be made up of a single stage or of several
stages. Referring to a voltage amplifier connected at the input
to a signal voltage source (Vs with a series resistance Rs) and
connected at the output to a load resistance, RL, the overall
voltage gain is
Av =

Vo

(c)

(2)

FEEDBACK AMPLIFIERS
Although open-loop amplifiers have their own specific range
of applications (e.g., RF amplifiers are always open-loop circuits), an important class of amplifier is constituted by feedback stabilized amplifiers.
Negative feedback is widely used in the design of amplifiers, since it allows the gain to be stabilized with respect to

Io
ri Ai0Ii

ro

(b)
ro

ri

ri
RL
Avo
r i + Rs
RL + r o

It is apparent that in order to preserve the gain, the input

resistance ri should be much greater than the source resistance Rs and the output resistance ro should be much smaller
than the load resistance RL. For the other three types of amplifier a similar result is obtained, which can be summarized
with the concept of mismatched amplifiers. In this case only
one kind of variable (voltage or current) has to be processed
and the other is reduced to its minimum possible value.

Ii

(a)
Ii

255

RtoVi

Ii
Vo

Vi

ri Gt0Vi

(d)

ro
Figure 2. Circuit models for (a) voltage
amplifier; (b) current amplifier; (c) transresistance amplifier; and (d) transconductance amplifier.

256

SIGNAL AMPLIFIERS

active device parameter spreads, power supply variations,

and temperature changes. Feedback allows the input and output resistances of the circuit to be modified in any desired
fashion. It improves the linearity of the amplifier, thus reducing the distortion produced in the output signal. Finally, it
can lead to an increase in the bandwidth of the amplifier.
However, all these features are paid for in terms of a proportional reduction in the gain. Moreover, negative feedback can
cause the tendency of oscillation to occur in the circuit, and
hence frequency compensation is usually mandatory (13).
The analysis of an ideal feedback system like that shown
in Fig. 3 is straightforward, and leads to the transfer function
GF =

xo
A
=
xs
1 + fA

(3)

Unfortunately, for real cases where the blocks, A and f, are

made up of active and passive components, the analysis is not
so simple. Several techniques for the analysis of real feedback
amplifiers have been reported in Refs. 17 and are critically
discussed in Ref. 8 and Ref. 9. Each technique has its own
benefits and drawbacks, but from a design point of view, two
of them are the most interesting and powerful. The first was
proposed in 1974 by Rosenstark (10), and was recently rediscovered and formalized using signal flow graphs (2); the second was proposed in 1990 by Choma and is based on signal
flow analysis (11).
Rosenstark Method
The Rosenstark method is based on calculation of the return
ratio, T, the asymptotic term, G, and the direct transmission
term, G0. All these quantities, which are functions of the input
source resistance, RS, and output load resistance, RL, must be
calculated with respect to one and only one controlled source
within the feedback amplifier. The exact transfer function between the input and output of the feedback amplifier (10) is
thus given by
GF (RS , RL ) =

G (RS , RL )T (RS , RL ) + G0 (RS , RL )

1 + T (RS , RL )

(4)

More specifically, to evaluate the three terms, we have to relate a controlled source quantity, xo, to the controlling quantity, xc, by the parameter P (i.e., xo Pxc) and to follow the
steps below:
1. Switch off the critical controlled source setting P 0
and, to achieve the direct transmission term, G0, compute the transfer function between the input and output.

xs +

xi

xo

2. Set the input source to zero. This means a short-circuit

voltage source or an open-current source. Replace the
critical controlled source by an independent one of
value P. The return ratio, T, coincides with the resulting controlling quantity with the opposite sign,
xc.
3. Set the critical parameter to infinity (i.e., P ). Since
the controlled source is still finite, this is equivalent to
having xc 0 with the related consequence. The Asymptotic term, G, is the transfer function between the input and the output under these conditions.
Comparing Eq. (4) with Eq. (3), it is apparent that with a
negligible direct transmission term, G0, the return ratio, T,
and the asymptotic gain, G are equal to the product between
the amplifier gain, A, and the feedback factor, f, and to the
inverse of the feedback factor, f, respectively (i.e., T fA and
G 1/f) (14). It is worth noting that the term G represents the ideal transfer function of the feedback network. Indeed, for well-designed feedback amplifiers which have a low
G0 and a high T, the transfer function of the feedback circuit
is well approximated by G.
Choma Method
The Choma method starts from the same assumptions made
in the Rosenstark method. After choosing a controlled source
P inside the feedback, we again have to calculate the return
ratio, T, and the direct transmission term, G0, as described in
points 1 and 2 of the previous subsection. But now, instead of
the asymptotic term, G, we have to evaluate the null return
ratio, TR. Thus the desired exact transfer function between
the input and output of the feedback amplifier (11) is given
by
GF (RS , RL ) = G0 (RS , RL )

1 + TR (RS , RL )
1 + T (RS , RL )

(5)

More specifically, the null return ratio, TR, can be evaluated

by replacing the critical controlled source with an independent one of value P, as done in the point 2 of the previous
subsection, but without nullifying the input source. It will coincide with the resulting controlling quantity with the opposite sign, xc, assuming the output voltage to be equal to zero.
The ratio between the return ratio and the null return ratio, T(RS, RL)/TR(RS, RL), quantifies the degree to which the
local feedback approaches global feedback (11) (when it is
the feedback is global), and hence gives interesting information regarding the kind of feedback. Of course, both methods
presented give the same results, and combining Eq. (3) with
Eq. (4) the degree to which the local feedback approaches
global feedback versus the asymptotic gain is given by
G (R , R )
T (RS , RL )
= 0 S L
TR (RS , RL )
G (RS , RL )

(6)

Input and Output Resistances

xf

Figure 3. Block scheme of a feedback system.

The driving point input impedance and driving point output

impedance of a feedback amplifier can be simply evaluated by
using the Blackman theorem (12). The same relationships are
obtained using signal flow analysis (11). The input and output

SIGNAL AMPLIFIERS

resistance are given by

Ri = Riol

1 + T (0, RL )
1 + T (, RL )

(7)

Ro = Rool

1 + T (RS , 0)
1 + T (RS , )

(8)

where Riol, and Rool, are the corresponding driving point input
and output resistances with the critical parameter P equal to
zero, and T(0, RL), T(, RL), T(RS, 0), and T(RS, ) are the
return ratios under the conditions specified for the source resistance, RS, and load resistance, RL.
FEEDBACK AMPLIFIER CONFIGURATIONS (13)
It follows from the previous discussion that the characteristics of the four amplifier types can be improved with the use
of negative feedback. For each amplifier we have to sample
the output signal by a suitable network and transmit a portion of this signal back to the input.
There are four basic types of single-loop feedback amplifiers analyzed below: (1) series-shunt, (2) shunt-series, (3)
shunt-shunt, and (4) series-series. The four typical amplifiers
are only implemented with bipolar transistors. However,

257

since bipolar transistors are modeled with the equivalent-

circuit, the results can be extended to the MOS transistor
quite simply by setting r to infinity.
Series-Shunt Feedback Amplifier
Figure 4(a) depicts the ac schematic diagram (a circuit diagram divorced of biasing details) of a series-shunt feedback
amplifier. A portion of the output voltage, vo, sampled by the
feedback network RE, RF, is compared with the input voltage
vS. The small signal model of the amplifier in Fig. 4(a) is
shown in Fig. 4(b).
A practical consideration regarding application of the Rosenstark approach is the choice of the critical controlled
source. Although the approach is general, evaluation of the
terms becomes simpler if one node of the controlled source
is at ground potential. This, in other words, means that for
multitransistor amplifiers we have to choose a controlled
source associated to a common emitter transistor. Thus we
choose the transconductance gm2, as the controlled source P
and follow the steps below:
1. Set P 0 (gm2 0). This, unless there is a load effect
on the collector of T1 due to r2, means switching off
transistor T2 and, hence, the ac schematic diagram is

vo
T2
RL
T1
RC1
+
vs

Ro

Rs

Ri
RF
RE

(a)
iC1
+

vo

Rs
r 1 v 1

vs

RC1
gm1v 1

r 2

v 2

ro2

RL

gm2 v 2

Ri
Ro
RF
RE

(b)

Figure 4. (a) Ac schematic of seriesshunt feedback amplifier; (b) small signal

equivalent circuit of the series-shunt feedback amplifier in (a), obtained by replacing each transistor with its small-signal
model.

258

SIGNAL AMPLIFIERS

and neglecting the resistance ro1, we get

RC1 r 2

RL
ic1
gm1 r 1
=
i
RL + RF gm1 r 1 + 1

T1
Rs
+
vs

RF

vo

(RF + RL )RE
r + RS
(RF + RL )RE + 1
gm1 r 1 + 1

RL
RL + RF

(14)

Se

Hence, the return ratio, T, with respect to the critical

parameter gm2 is

RL

Ri

T = gm2

Ro

Figure 5. Ac schematic for the evaluation of the direct transmission

term for the circuit in Fig. 4(a). On having nullified the transconductance of T2 in Fig. 4(a), the circuit becomes a simple emitter follower.

the one in Fig. 5, which is a voltage follower whose

transfer function, assuming the transistor output resistance, ro1, to be much greater than RC1r2, is given by
ve
(gm1 r 1 + 1)[RE (RL + RF )]
=
1
vS
( gm1 r 1 + 1)[RE (RL + RF )] + r 1 + RS

(9)
T1


vo 
v S g

m2 =0

RL
RL
ve

RL + RF v S
RL + RF

Rool = RF +

r 1 + RS
R RF
gm1 r 1 + 1 E

(11)

RL
i
RL + RF

(13)

v 2

RF

RE

RL

(a)

Rs
r 1

ro1

v 1

(12)

2. Set vs to zero and replace the original controlled current

generator, gm2v2, with an independent current source,
i, of value P. Again, transistor T2 can be considered to
be switched off while transistor T1 is in a common base
configuration [Fig. 6(a)]. Then, by introducing a Norton
equivalent generator at the input, as shown in Fig. 6(b),
where the current i is given by
i =

RC1 r 2

RS

(10)

It is apparent that this contribution is always lower

than one. Since closed-loop resistances are evaluated
with P 0, we can compute the corresponding driving
point input and output resistances, Riol, and Rool, given
by
Riol = r 1 + ( gm1 r 1 + 1)[RE (RL + RF )]

(15)

RL
(R r ) g
RL + RF C1 2 m2

3. Now evaluate the closed loop asymptotic gain, G, by

setting the parameter gm2 infinitely large. By inspection
of Fig. 4(b), to be the current of generator gm2v2 finite,
the voltage v2 must be zero and this holds only if the
current generator ic1 is zero which, in turn, means v1
0. Therefore, vb1 vS (where b1 is the base of T1), and
all the input voltage is found across the resistance RE

where ve is the voltage on the emitter of T1. Thus, including the term RL /(RL RF), which takes into account
the voltage partition at the output of the voltage buffer,
we get the gain, G0, under the special condition of zero
feedback

G0 =

v 2
i
= (RC1 r 2 )gm2 c1
i
i

v 2

RC1 r 2

gm1v 1

(RF + RL) RE

i'

(b)
Figure 6. (a) Ac schematic for the evaluation of the return ratio for
the circuit in Fig. 4(a). On nullifying the input signal and replacing
the controlled generator of T2 with an independent current source i,
T1 becomes a common-base transistor. (b) Small-signal circuit of (a).

SIGNAL AMPLIFIERS

Thus, the null return ratio is given by

RF
vo

TR =
vel

259

RE

gm2 v 2
R + RF
= gm2 E
(RC1 r 2 )
i
RE

(22)

RL

It is apparent that the relationship displayed in Eq. (6) is verified.

Figure 7. Equivalent circuit for the evaluation of the asymptotic
gain for the circuit in Fig. 4(a). The transconductance of T2 in Fig.
4(a) has been made infinitely large.

(i.e., the typical virtual short-circuit condition). According to Fig. 7, which follows from these considerations,

G =


vo 
v S g

=1+
m2

RF
RE

(16)

The final closed-loop gain is obtained by substituting G0, T,

and G, into Eq. (14). In order to calculate the input and output resistance, according to Eqs. (7) and (8), since the relationship of the return ratio in Eq. (15) is independent of the
source resistance, it is necessary to introduce the exact expression of Eq. (14) into Eq. (15), before evaluating the terms
T(0, RL) and T(, RL). The four return ratios needed are

RL
T (0, RL ) =
(R r ) g
RL + RF C1 2 m2
T (, RL ) = T (RS , 0) = 0

Shunt-Series Feedback Amplifier

While the series-shunt feedback circuit functions as a voltage
amplifier, the shunt-series configuration, whose ac schematic
diagram is depicted in Fig. 9(a), is best suited as a current
amplifier. In the subject circuit, the current through the emitter of transistor T2, which is approximately equal to the output signal current, io, is sampled by the feedback network
formed on the resistance, RE and RF. The sampled current is
fed back as a current to a current-driven input port. Thus
the resulting driving point output resistance is large, and the
driving point input resistance is small. These characteristics
allow for a closed-loop current gain, Gi(RS, RL) io /is, which
is relatively independent of the source and load resistances
and insensitive to transistor parameters.

T1

(17a)

RS
+

(17b)

T (RS , ) = (RC1 r 2 ) gm2

Ri = Riol 1 +
Ro =

RL
(R r ) g
RL + RF C1 2 m2

(17c)

RE

(18)
(a)

(19)
iz1

To follow the Choma method, one must replace point 3 with

the following step, in order to evaluate the null return ratio
TR.
First substitute the original controlled current generator,
gm2v2, with an independent current source, i. By inspection of
Figure 4(b), to have an output voltage equal to zero means
that the critical current, i, is forced to flow through the resistance RF. Hence, the equivalent circuits in Fig. 8 can be used.
Under the assumption that the voltage on the emitter of transistor T1 follows the input source voltage (i.e., ve vS), the
voltage on the collector of T1 and the critical current i, are,
respectively,
v 2 =

+
vs

RS
r 1 v 1

RC1

r 2 v 2

gm1v 1
Ri
i

ve
RF
RE

(b)

R r
gm1 r 1 RC1 r 2
v C1 2 vS
1 + gm1 r 1 RE RF S
RE RF

(20)

vS
RF

(21)

i=

Rool
1 + (RC1 r 2 ) gm2

RF

vs

And, hence, the input and output resistances are



RC1 r 2

Figure 8. (a) Ac schematic for the evaluation of the null return ratio
for the circuit in Fig. 4(a). The controlled generator of T2 is replaced
by an independent current source i. (b) Small-signal circuit of Fig.
8(a).

260

SIGNAL AMPLIFIERS

T2

io

T1

RL

RC1
Ro
RS

is

RF
Ri
RE

(a)

is

RS

r 1

v 1

ro1

r 2

RC1

io

v 2

ro2

gm1v 1

gm2v 2

RL
Ro

Ri
RF

RE

(b)
Figure 9. (a) Ac schematic of shunt-series feedback amplifier; (b) small-signal equivalent circuit
of the shunt-series-shunt feedback amplifier in (a), obtained by replacing each transistor with its
small-signal model.

To analyze the circuit in Fig. 9(a), consider its small signal

model shown in Fig. 9(b), and assume the transconductance
gm1 as the critical parameter P.
1. Set P 0 (gm1 0), which means switch off transistor
T1; then, taking into account the input resistance of T1
which still exists, the circuit has the ac schematic diagram depicted in Fig. 10(a), and the small signal model
shown in Fig. 10(b) where the resistance RS and the current is are given by
RS = (RF + RS r 1 )RE
is =

RS r 1
is
RF + RS r 1

(23)
(24)

The circuit in Fig. 10 represents a common base configuration; from it one obtains

RS
RS r 1
io 
gm2 r 2
Go = 
=
R
+
r
iS g =0
g
r
+
1
R
2
m2 2
F + RS r 1
RS + C1
m1
gm2 r 2 + 1
RS r 1

(25)
RF + RS r 1

which is always lower than one. The corresponding input and output resistance, Riol, and Rool, are given by
Riol =

r 2 + RC1
R
gm2 r 2 + 1 S

Rool = ro2 + (1 + gm2 ro2 )[RS (RC1 + r 2 )]

(26)
(27)

2. Set is to zero and replace the original controlled current

generator, gm1v1, with an independent current source,
i. Now, as shown from the equivalent ac circuit shown
in Fig. 11, transistor T2 works as a voltage follower,
and the voltage v1 is a portion of the emitter voltage of
T2. Therefore, since ro2 is usually much higher than RL
and RE, and assuming RC1 to be lower than the equivalent resistance at the base terminal of T2, the loop gain
is

RS r 1
gm1 RC1
r 2
R
r
S 1 + RF
gm2 r 2 + 1 +
RE (RF + RS r 1 )
RS r 1

g R
(28)
RS r 1 + RF m1 C1

T=

gm2 r 2

SIGNAL AMPLIFIERS

ses, one can model the circuit with the one shown in
Fig. 12, and by inspection we find that the current entering into the emitter of transistor T2 is equal to

io
T2

RL

RC1

ie2 =

1+

RF

Rs r 1

iS

(29)

Therefore, combining Eqs. (25), (28), and (30) the exact

expression of the closed-loop gain of a shunt-series feedback amplifier can be found quite simply. For common
values, the loop gain is much greater than one and the
closed-loop gain is equal to the asymptotic one.
Finally, the resulting input and output resistances
are given by Eqs. (7) and (8), where the return ratios
are

io

RC1
v 2

(a)

r 2

RF
RE

Hence, neglecting the resistance ro2, one obtains



R 
io 
gm2 r 2
R
G = 
=
1 + F 1 + F (30)
is g
1 + gm2 r 2
RE
RE

is
RE

261

ro2

RL

gm1v 2

T (0, RL ) = 0
R'S

T (, RL ) =

i's

T (RS , 0) =
(b)
Figure 10. (a) Ac schematic for the evaluation of the direct transmission term for the circuit in Fig. 9(a). On having nullified the input
signal and the transconductance of T1, the circuit acquires a commonbase configuration. (b) Small-signal equivalent circuit of the circuit in
(a). The current generator iS and resistor RS represent the Norton
equivalent seen by the emitter of T2.

3. Now evaluate the closed-loop asymptotic gain, G. By

inspection of Fig. 9(b), setting the parameter gm1 infinitely large leads to v1, equal to zero which, in turn,
means that all the input current, is, enters the feedback
resistance, RF. Moreover, since a finite value for the current gm1v1 determines a v1 other than zero, the term
gm1v1 itself must be equal to zero. Under these hypothe-

T2

T (RS , ) =

(31)

r 1
g R
r 1 + RF m1 C1

(32)

RS r 1
g R
RS r 1 + RF m1 C1

(33)

RS r 1
g
RS r 1 + RF m1
{RC1 [r 2 + RE (RF + RS r 1 )]}

Shunt-Shunt Feedback Amplifier

The ac schematic diagram of the third type of the single-loop
feedback amplifier, the shunt-shunt triple, is drawn in Fig.
13(a). A cascade interconnection of three transistors, T1, T2,
and T3, forms the open loop, while the feedback subcircuit is
a single resistance, RF. This resistance samples the output
voltage, vo, and feeds it back as current to the input port.
Therefore, both the driving point input and output resistance
are very small. Accordingly, the circuit operates best as a
transresistance amplifier, in that its closed-loop transresis-

io

RC1

RL

v 2
r 2

i = gm1 v 1
RC1

RS

ro2

RL

gm1 v 2
ie2

RF

RE

(34)

r 1

v 1

RF

RE

is

Figure 11. Ac schematic for the evaluation of the return ratio for
the circuit in Fig. 9. On replacing the controlled generator of T1 with
an independent current source i, T1 becomes an emitter follower.

Figure 12. Equivalent circuit for the evaluation of the asymptotic

gain for the circuit in Fig. 9. The transconductance of T1 has been
made infinitely large.

262

SIGNAL AMPLIFIERS

vo

RF
T1

T2

T3

Ro
RS

is

Ri

RC1

RC2

RL

(a)

RF

is

r 1 v 1

RS

RC1

r 2

vo

v 2

gm1v 1

r 3 v 3

RC2

gm3v 3
RL

gm2v 2

Ri
Ro

(b)

Figure 13. (a) Ac schematic of shunt-shunt feedback amplifier; (b) small-signal equivalent circuit of the shunt-shunt feedback amplifier, obtained by replacing each transistor in (a) with its
small-signal model.

tance, RM(RS, RL) vo /is, is nominally invariant with source

resistance, load resistance, and transistor parameters.
Considering the equivalent small signal model of the
shunt-shunt circuit shown in Fig. 13(b), we can arbitrarily
choose the transconductance gm1 as the parameter P (other
choices do not lead to any substantial differences). Setting
gm1 0, the feedforward transresistance and the corresponding input and output resistances are


vo 
Rfo = 
is g

=
m1 =0

RS r 1
R
RS r 1 + RF + RL L

(35)

Riol = (RF + RL )r 1

(36)

Rool = RF + RS r 1

(37)

Series-Series Feedback Amplifier

Figure 14 reports the ac schematic diagram of the series-series feedback amplifier. Three transistors, T1, T2, and T3, are
embedded in the open-loop amplifier. Although it is possible
to achieve series-series feedback via emitter or source degeneration of a single-stage amplifier, the series-series triple offers substantially more loop gain and thus a better desensitization of the forward gain with respect to both transistor
parameters and source and load termination. Of course, these
benefits are paid for in terms of frequency response.
One can conveniently choose the transconductance gm2 as
the parameter P. Hence, assuming ideal behavior for the
transistor working as a current or voltage follower, the fundamental relationships are given by

The return ratio is

G0 =
RL
T = gm1 (RC1 r 2 ) gm2 (RC2 r 3 ) gm3
R r
RL + RF + RS r 1 S 1
(38)
and the asymptotic transresistance is

Rf =


vo 
i s g

m1

= RF

(39)

Hence, substituting Rfo, T and Rf into Eq. (4), we get the

closed-loop transresistance Rcl.
Finally, the input and output resistance can be simply obtained by properly evaluating the particular return ratio by
using Eq. (38).


io 
v S g

m2 =0

1
RF

(40)



RC2 + r 3
Riol = r 1 + ( gm1 r 1 + 1) RE1  RF + RE2 
gm3 r 3 + 1
(41)

Rool = ro3 + ( gm3 ro3 + 1) (r 3 + RC2 )RE2 




 RS + r 3

(42)
RF + RE2 
gm3 r 3 + 1
T = RC1 gm2

G =


io 
vS  g

RC2
RF

m2

(43)

1
RF
1
+
+
RE1
RE2
RE1 RE2


(44)

SIGNAL AMPLIFIERS

T1

RS

T2

T3

263

is

+
vs

Ro

RC1

Ri

RC2

Ri

RF
RE1

RE2
Figure 14. Ac schematic of series-series feedback amplifier.

Since the loop gain generally has a very high value, the
closed-loop transconductance is almost equal to the asymptotic one, G. Moreover, the particular return ratios needed
to calculate the input and output resistance, assuming ro1 to
be a very high resistance, are
T (0, RL ) = T (RS , 0) = RC1 gm2

gC2
RF

T (, RL ) 0

(45)
(46)

TS (RS , ) (RC1 r 2 ) gm2

plied. Moreover, it is equal to the maximum bandwidth

achieved with a unitary feedback factor, f 1 (i.e., with the
amplifier in a unity gain feedback configuration).
Two-Pole Amplifier
Real amplifiers have transfer functions with more than one
pole and instability problems arise. Consider now an amplifier with a two-pole transfer function

A(s) =

RC2
RE2
RC2 + r 3 + RE2 RF RE2 + RF
(47)

s
1+
p1

A
0

1+

s
p2

(51)

Its closed-loop transfer function is

STABILITY

GF (s) =

In order show the increase in bandwidth of a feedback amplifier, consider an amplifier having the following single-pole
transfer function

A(s) =

A0

s
1+
p1

(48)

GF (s) =

GF0
GF0

s
s
1+
1+
(1 + f A0 )p1
T0 p1

(49)

where GF0 is the dc closed-loop gain equal to

GF0 =

A0
G
1 + f A0

(50)

Hence, the resulting pole is shifted to a higher frequency by

a factor equal to the dc gain of the return ratio, T0. It is worth
noting that, when a feedback amplifier can be modeled with
the scheme in Fig. 3, the gain-bandwidth product of the openloop amplifier is equal to that of the closed-loop amplifier.
Thus the gain-bandwidth product is an invariant amplifier
parameter which is independent of the degree of feedback ap-

(52)

where o is the pole frequency and is the damping factor,

0 =

Assuming a pure resistive feedback network, the closed-loop

transfer function is

GF0

s2
1+2
s+ 2
0
0

p1 p2 (1 + f A0 )

p1 + p2
1

20
2 T0

r p r p 
1

p2

p1

(53)

(54)

Normalizing the closed-loop transfer function to 0, the frequency and step responses for different values of are those
plotted in Fig. 15(a) and Fig. 15(b), respectively. The behavior
is overdamped, critically damped, or underdamped if the
value is greater than, equal to, or lower than 1, respectively.
The underdamped condition (i.e., with two complex poles) is
critical since overshoot occurs in both the frequency and the
time domain and, to keep the peak in both the frequency and
step responses below the desired value, the parameter must
be properly set.
According to Eq. (54), to avoid overshoot one needs an amplifier, A, with widely spaced poles. More specifically, in order
to avoid an excess of underdamping, open-loop amplifiers are
designed with a dominant-pole behavior and a second pole at
a frequency higher than the gain-bandwidth product, GBW, of
the return ratio transfer function (i.e., p2 T0 p1). Thus it is

264

SIGNAL AMPLIFIERS

frequency T. For a two-pole system it is

10

 = 180 arctg

= 0.1
= 0.3

= 0.7

K tan

=1

0.1

10

(a)
2

0 = p1 KT0 (1 + T0 ) GBW K

1 1 + KT0
K
=

2
2
KT0

1 + s +

(59)

s2
K

(60)

where the complex frequency s is the complex frequency s

normalized to GBW. This is a useful representation of a closedloop amplifier, since it is simple and depends on K (or the
phase margin) and GBW, which are two fundamental parameters in amplifier design. The frequency and step responses for
different values of K are those plotted in Fig. 16(a) and Fig.
16(b), respectively. The overshoot in the frequency domain of
the transfer function in Eq. (60) occurs at a frequency cp
given by

= 0.7
=1

GF0

GF (s ) =

= 0.3
= 0.5

(58)

and hence the closed-loop transfer function is

= 0.1

0.5

(57)

Hence, for a required phase margin one obtains the value of

the separation factor needed during the compensation design
step. Of course, there is the well-known rule that the phase
margin must be greater than 45 to avoid excessive underdamped behavior. Moreover, the underdamped natural frequency and the damping factor can be represented as

1
/ 0

1.5

(56)

Since for a dominant-pole amplifier the gainbandwidth product, GBW, is about equal to the transition frequency, T, and
arctg (1 /T) 0, from Eqs. (55) and (56) one obtains

= 0.5

0.1

arctg T = arctg 1 + arctg 2

1
2
T
T

10

15

20

0t

cp = GBW

(b)

Figure 15. (a) Frequency-response module for a two-pole feedback

amplifier in the traditional representation. Overshoot arises for
lower than 1/ 2. The overshoot is around the pole frequency 0. (b)
Step response for a two-pole feedback amplifier in the traditional representation.

K=

p2
p2
=
GBW
T0 p1

(55)

A well-known parameter which gives the degree of stability

of a feedback system is the phase margin, , defined as 180
plus the phase of the return ratio evaluated at the transition

K2
2

(61)

It is apparent that for values of K greater than 2 peaking is

avoided in the frequency domain. In order to optimize the
closed-loop amplifier time response (15), useful information
for the designer is the time, tpcl, at which the first peak occurs
and its overshoot, D, given by
tp =

useful to define the separation factor, K, between the second

pole and the gain-bandwidth product of the return ratio T
(observe that the return ratio transfer function has the same
pole as the amplifier transfer function) (14)

GBW 4K K 2

D = e

K
4K

(62)
(63)

For example, having the minimum settling time at 0.1%, Eq.

(63) gives a K equal to 2.75 (i.e., a phase margin of 70); then
from Eq. (62) the amplifier gain-bandwidth product needed to
achieve the required settling time can be found.
Three-Pole Amplifier
For amplifiers with more than two poles, more accurate relationships have to be used during compensation. Of course, a

SIGNAL AMPLIFIERS

265

Hence, remembering that tan(a b) tan(a) tan(b)/1

tan(a) tan(b) and tan(a 90) 1/tan(a), one obtains

10

K = 0.04

2
GBW

K=1
K = 1.96

tan()

K=4

0.1
0.1

1

1
3

1
1

=0
GBW
2 3

(66)

By solving Eq. (66) the required gain-bandwidth product for

a fixed phase margin is obtained:



 
1
2 3
tan() 1
1
4
1+ 1+
=
+
GBW
2
2
3
tan2 () (2 + 2 )2

K = 0.36

tan()

1

1
3

(67)

It is worth noting that compensation of a three-stage amplifier can be performed like that of a two-pole amplifier, where
the equivalent time constant of the second pole is equal to the
sum of the second and third pole time constants of the threepole amplifier.
10

/ GBW

POLE SPLITTING COMPENSATION

(a)

Generally, the return ratio of amplifiers used in negative

feedback is not characterized by a dominant-pole frequency
response. Therefore, compensation is needed to achieve the
required phase margin. Compensation can be simply performed by increasing the capacitance at the node which determines the lower pole. However, except in the case of a onestage amplifier, such as a cascade amplifier, a more efficient
approach based on pole splitting compensation can be used.

2
K = 0.04
1.5
K = 0.36

K = 1.96
K=1

Open-Loop Amplifier

K=4

0.5

10
GBWt

15

20

(b)

The return ratio of a two-stage feedback amplifier such as the

series-shunt and the shunt-series feedback amplifiers in Fig.
4(a) and Fig. 9(a), can be evaluated with the simplified
scheme plotted in Fig. 17, which is composed of two equivalent transconductances and two equivalent resistances with
the associated parasitic capacitances. More specifically, Ci is
the equivalent capacitance at the interstage node, the capacitance Co is the equivalent one at the output node, and Cr is
the equivalent capacitance across the two stages (CC is the
capacitor used to achieve compensation). Moreover, for the se-

Figure 16. (a) Frequency-response module for a two-pole feedback

amplifier in the proposed representation. Overshoot arises for values
of K lower than 2. (b) Step response for a two-pole feedback amplifier
in the proposed representation. Rise time and settling time increase
for values of K greater than 2.

CC

Cr

dominant-pole behavior is mandatory to achieve stability.

Consider an amplifier with three separate poles:

A(s) =

s
1+
p1



A0

s
1+
p2



s
1+
p3

(64)

If 1 is the dominant pole, the phase margin is equal to

arctg

+ arctg 3 90
GBW
GBW

(65)

vo

Reqi
Gmeq1vo

Ci

Reqo

v'

Co

Gmeq2v'

Figure 17. Small-signal equivalent circuit for the evaluation of the

generalized loop gain frequency behavior of two-stage amplifiers. The
two stages are represented by Gmeq1, Reqi and by Gmeq2, Reqo. Since we
assume the amplifier in unity-gain configuration, the output voltage
vo drives the input stage.

266

SIGNAL AMPLIFIERS

ries-shunt amplifier Gmeq2 is equal to gm2 and Gmeq1; Reqi and

Reqo are about equal to 1/RF, RC1 //r2, and RLT //RF, respectively.
For the shunt-series amplifier Gmeq2 is equal to gm1 and Gmeq1,
Reqi and Reqo are about equal to 1/(RS //r1 RF), RS //r1 and
RC1, respectively.
Referring to Fig. 17, the return ratio, T(s), can be written
in the form

T (s) = T0
1+

1
p1

1
+

s
zr

1
p2

s+

s2
p1 p2

(68)

crease in the internal feedback capacitance, Cr, moves the

dominant pole and the second pole to lower and higher frequencies, respectively. Thus, in order to improve the separation of the two poles it is efficient to increase Cr since its contribution is magnified by the gain factor (1 Gmeq2Reqo).
Actually, this is the technique followed to perform compensation (i.e., to obtain a phase margin greater than 45 or K
1), which allows the amplifier to be connected in a closed loop
without an excess of underdamped behavior. In this case one
adds to the internal feedback capacitance Cr a compensation
capacitance, Cc and, since the Miller effect becomes the dominant capacitive contribution, Eqs. (73) can be further simplified:

where
T0 = Gmeq1 Reqi Gmeq2 Reqo

(69)

The dashed branch containing the capacitor CC, which will be

addressed later, is the pole splitting compensation element.
The frequency, zr, of the right half-plane zero due to the forward path through the feedback capacitance, Cr, to the output
is given by
zr =

Gmeq2
Cr

(70)

and the lower pole frequency, p1, and the higher pole frequency, p2, derive implicitly from
1
1
+
= Reqo (Co + Cr ) + Reqi [Ci + (1 + Gmeq2 Reqo )Cr ] (71)
p1
p2
and


C 
1
= Reqi ReqoCo Ci + 1 + i Cr
p1 p2
Co

(72)

Pole Splitting Analysis

Under the assumption that the amplifier has a dominant-pole
behavior (fundamental to use the amplifier in feedback), one
can neglect the term 1/p2 in Eq. (71) with respect to the term
1/p1. Consequently, the following pole expressions are obtained:

p1

1
Reqo (Co + Cr ) + Reqi [Ci + (1 + Gmeq2 Reqo )Cr ]
1
Reqi [Ci + (1 + Gmeq2 Reqo )Cr ]

(73a)

Reqo (Co + Cr ) + Reqi [Ci + (1 + Gmeq2 Reqo )Cr ]



C 
Reqi ReqoCo Ci + 1 + i Cr
Co
Ci + (1 + Gmeq2 Reqo )Cr

(73b)

C 
ReqoCo Ci + 1 + i Cr
Co

p2

It is worth noting that the above approximations hold since,

in practical cases, the Miller effect represented by the term (1
Gmeq2Reqo)Cr leads to an input dominant pole. From Eqs. (73)
the pole splitting due to Miller effect it is apparent. An in-

P1c
p2c

1
Roeqi Gmeq2 ReqoCp
Gmeq2

(74a)
(74b)

Co + Ci

where the capacitance Cp, which is the sum of Cr and Cc, has
been assumed to be greater than Ci or Co. After compensation
the value of the second pole given by Eq. (74b) finds an intuitive justification. At the frequency at which it occurs, the capacitance Cp can be considered short-circuited, and Eq. (74b)
can be simply obtained by inspection of the circuit in Fig. 17.
From Eqs. (69) and (74a), the gain-bandwidth product is
GBW =

Bmeq1
Cp

(75)

Sometimes the large transconductance, Gmeq2, allows the zero

which is now given by Eq. (70) substituting Cp for Cr to be
neglected. Otherwise, the right half-plane zero determines a
negative contribution on the phase margin, and it must be
compensated as discussed in the next subsection to achieve
the required phase margin.
Considering the return ratio of a two-stage amplifier compensated by using the Miller effect, where the zero has also
been compensated, it is apparent that the bandwidth performance of the amplifier is only set by the frequency of second
pole given in Eq. (74b), and the separation factor, K, is
K=

Gmeq2

Cp
Gmeq1 Co + Ci

(76)

Hence, one has to choose the compensation capacitance, Cc, to

provide the value of K (always greater than 1) which gives
the required frequency- or time-domain behavior.
The compensation technique is extensively used in the design of two-stage amplifiers. Moreover, for off-the-shelf bipolar amplifiers including a voltage buffer output stage, compensation is still achieved by means of the Miller effect by
using Eq. (67). It is worth noting that when using three-stage
gain amplifiers such as the shunt-shunt feedback amplifier in
Fig. 13, the series-series feedback amplifier in Fig. 14, or
CMOS power amplifiers, low-voltage signal amplifiers, and so
forth, nested Miller, employing two or more compensation capacitors, is mandatory (16,17).
Zero Compensation Techniques
Various techniques for compensation of the right half-plane
zero have been proposed for two-stage MOS opamps. They are

SIGNAL AMPLIFIERS

based on the concept of breaking the forward path through

the compensation capacitor by using active or passive components. The original of these was first applied in an NMOS
opamp (18) and then in a CMOS opamp (19). It breaks the
forward path by introducing a voltage buffer in the compensation branch. Then a compensation technique was proposed
which uses a nulling resistor in series with the compensation
capacitor (20). Another solution works like the former but
uses a current buffer to break the forward path (21). Finally,
both current and voltage buffers can be used for compensation
of the right half-plane zero (22).
The most popular compensation technique is that based on
the nulling resistor, since it can be implemented using only a
MOS transistor biased in the triode region (which approximates a linear resistor) and does not reduce the input or output dynamic range of the original amplifier. It is achieved by
introducing the resistance Rc in series with the compensation
capacitor, as shown in Fig. 18(a). Neglecting the capacitance
Cr (usually much lower than CC), the zero is now at a frequency of

zr =

and is moved to infinite frequency by setting Rc equal to

1/Gmeq2. Thus from Eqs. (55), (74), and (75) assuming Cp
Cc, one gets
GBW

Figure 18(b) shows the compensation branch with a voltage buffer. Use of an ideal voltage buffer (i.e., with zero output resistance) to compensate the right half-plane zero gives
the same second pole as Eq. (74b) without the dependence on
the interstage capacitance, Ci and, hence, about the same
GBW. On the other hand, the finite output resistance of a real
voltage buffer leads to a left half-plane zero, which can be
efficiently exploited to perform a pole-zero compensation and
to increase the amplifier gain-bandwidth (24). Following this
last compensation strategy the second pole is given by
p2 =

Gmeq1

(78)

K(Co + Ci )

Hence the gain-bandwidth product is inversely proportional

to the sum of the output and interstage capacitance.
The resistance Rc can also be set to compensate the second
pole giving a new second pole 1/(RcCc), as proposed in (23),
but this approach has a worse GBW than the other optimized
compensation strategies described below.

Gmeq2 CC Cb

(79)

Ci + Cb

Co

where Cb is the feedforward capacitance of the voltage buffer.

After solving Cc by substituting Eq. (79) into Eq. (55), the
gain-bandwidth product is

GBW

(77)

1
Rc Cc
Gmeq2

267

Cb
+
2

sG G

meq1

meq1

Gmeq2

(80)

K(Ci + Cb )Co

The resulting GBW has a higher value than that given by Eq.
(78), and, apart from the small contribution of Cb, is inversely
dependent on the geometric mean of Ci Cb and Co.
Compensation based on a current buffer, as shown in Fig.
18(c), is very efficient both for the gain-bandwidth (25,26) and
the PSRR performance (21,27,28). Moreover, unlike the voltage buffer, it does not have the drawback of reducing the amplifier output swing.
Considering an ideal current buffer in the compensation
branch, the second pole is given by

p2 =

Gmeq2

Co
Ci 1 +
CC

(81)

which leads to the gain-bandwidth product

Cb

GBW

Gmeq1
2Gmeq2

B
RC

Av = 1

CC

CC

(b)

(a)

Ai = 1

B
CC

sG

Gmeq1
KCi +

(82)
meq1

Gmeq2

KCiCo

Since usually Cb Ci Co and Gmeq1 Gmeq2, the first term of

the denominator of Eq. (82) is negligible and, hence, the performance obtainable with an ideal current buffer is slightly
better than that obtained using an optimized design based on
a voltage buffer. However, compensation with a real current
buffer (i.e., with finite input resistance) is not as straightforward as other compensation approaches. As shown in Ref. 29,
in order to achieve compensation, one needs to guarantee that
the input resistance of the current buffer, Rb, must be equal
to or lower than half 1/Gmeq1. Moreover, the condition

(c)
Figure 18. (a) Compensation network with nulling resistor. The
technique allows one to modify the zero zr according to Eq. (77). (b)
Compensation network with voltage buffer that breaks the feedforward path. (c) Compensation network with current buffer: another
way to break the feedforward path.

Rb =

1
2Gmeq1

(83)

allows compensation based on a current buffer to be optimized. Under the condition of Eq. (83) one obtains the follow-

268

SIGNAL AMPLIFIERS

ing gain-bandwidth product:

GBW

given by

sGG

meq1

Gmeq1 2K 1
C +
2Gmeq2 2 + K i

meq1

2K 1

Gmeq2

2+K


1
2

HD2 f l =
CoCi
(84)

Thus, GBW is at least 20% higher than that obtained with an

ideal current buffer (29). On the other hand, for the same
gain-bandwidth product this kind of compensation needs
more area and/or power than that based on a voltage buffer.

HD3 f l =

1
1 a2
1 a2 1
Xs =
Xo
2 a1 (1 + T0 )2
2 a21 1 + T0
1 a3
4 a1

2 f a22
2 f a22
1
1 a3
a3 (1 + T0 ) 2
a3 (1 + T0 ) 2
Xs =
Xo
(1 + T0 )3
4 a31
1 + T0
(89b)

The third harmonic distortion can be further minimized by

canceling its numerator, according to the following relation:
f
a
= 32
1 + T0
2a2

DISTORTION IN CLOSED-LOOP AMPLIFIERS

To characterize the effects of nonlinearity in circuits and systems used as linear blocks, harmonic distortion terms are often used. More specifically, consider the open-loop amplifier
to be nonlinear with its transfer function, A(xi), well represented by the first three terms of a power series
xo = A(xi ) a1 xi + a2 x2i + a3 x3i

(85)

Assuming that the incremental input voltage is a pure sinusoidal tone xi Xi cos(1t), one obtains the following output:
xo = b0 + b1 cos(1t) + b2 cos(21t) + b3 cos(31t)

(86)

a2 2
X
2 i

b1 = a1 Xi +
a
b2 = 2 Xi2
2
a3 3
X
b3 =
4 i

3
a X3
4 3 i

(90a)

which with high return ratios, T0, simplifies to

a1 =

2a22
a3

(90b)

Moreover, according to Eq. (89b) for amplifiers where the

term a3 is negligible, the third harmonic is still determined
by the term a2.
Nonlinear Feedback
Considering a feedback amplifier where the feedback path is
also nonlinear and is represented by the following relation:

where terms bi up to the third order are

b0 =

(89a)

(87a)

xf = F (xo ) = f 1 xo + f 2 x2o + f 3 x3o +

(87b)

it is demonstrated in (32) that, assuming the return ratio,

To, to be much greater than 1, the second and third harmonic
distortion coefficients are respectively given by

(87c)
(87d)

HD2 f =

and hence the second and third harmonic distortion factors

are given by

HD2o =

1 a2
|b2 |
1 a2

X =
Xo
|b1 |
2 a1 i
2 a21

(88a)

HD3o =

1 a3 2
|b3 |
1 a3 2

X =
X
|b1 |
4 a1 i
4 a31 o

(88b)

in which the gain compression, which arises in term b1 and is

due to term a3 (30), has been neglected. In order to allow a
simple comparison with the closed-loop case, the harmonic
factors refer to the output voltage magnitude.
Linear Feedback
If we close the amplifier in a loop with a linear feedback, f
(which means a return ratio T0 fa1), the harmonic distortion
terms given by Eq. (88) must be reduced by the factors (1
T0)2 and (1 T0)3, respectively. This implies a reduction, approximately equal to the return ratio T0, in the harmonic distortion terms referring to the output signal magnitude.
As reported in Ref. 31, a more accurate analysis shows that
the harmonic distortion terms for a closed-loop amplifier are

HD3 f =

1
2
1
4



1
a f 2N
To a1 2N

(91)


Xo

1
2
(a 2a22N ) ( f 3N 2 f 2N
)
To a21 3N

1
a2N f 2N Xo2
4
To a1

(92a)

(92b)

where a2N and a3N represent the amplifier terms normalized

to the amplifier gain a1, and f 2N and f 3N represent the feedback
terms normalized to the feedback gain f 1. It is apparent that
feedback does not reduce the nonlinearity of the feedback network. Thus one cannot obtain an amplifier having a nonlinearity lower than that of the feedback network, and even small
nonlinearity terms of feedback networks cannot be neglected,
but must be taken into account during harmonic distortion
evaluation. It is also worth noting that for negative feedback,
distortion due to the feedback network has an opposite sign
to that due to the amplifier. A more compact and clear representation of the harmonic distortion in a nonlinear amplifier
with nonlinear feedback is

HD2f = HD2 f l + HD2fn

(93a)

HD3f = HD3l + HD3fn + 4HD2 f l HD2fn

(93b)

SIGNAL DETECTION THEORY

where HD2fn, and HD3fn, are the harmonic distortion terms of

the feedback amplifier assuming nonlinear feedback but a linear amplifier, which are given by

HD2fn

HD3fn

1 f 2 a21
1 f 2 a1
Xo
=
X =
2 (1 + T0 )2 S
2 (1 + T0 )
1
=
4

f 3 a31

2 f 22 a41

1
(1 + T0 ) 2
Xs =
(1 + T0 )3
4

(94a)

f 3 a1

2 f 22 a21

(1 + T0 ) 2
X0
1 + T0
(94b)

Hence, the second and third harmonic distortion terms can be

compactly represented by Eqs. (93), which are only a simple
function of the second and third harmonic distortion of the
whole feedback network evaluated in two particular cases:
1. A nonlinear amplifier with a linearized feedback network.
2. A linearized amplifier with a nonlinear feedback
network.
BIBLIOGRAPHY
1. M. Ghausi, Electronic Devices and Circuits: Discrete and Integrated, Philadelphia: Saunders, 1985.
2. J. Millman and A. Grabel, Microelectronics, 2nd ed., Singapore:
McGraw-Hill, 1987.
3. A. Sedra and K. Smith, Microelectronic Circuits, 3rd ed., Philadelphia: Saunders, 1991.
4. S. Ben-Yaakov, A unified approach to teaching feedback in electronic circuits courses, IEEE Trans. Educ., 34: 310316, 1991.
5. P. Gray and R. Meyer, Analysis and Design of Analog Integrated
Circuits, 3rd ed., New York: Wiley, 1993.
6. K. Laker and W. Sansen, Design of Analog Integrated Circuits
and Systems, New York: McGraw-Hill, 1994.
7. A. Arbel, Negative feedback revisited, Analog Integ. Circuits Signal Process., 10 (3): 157178, 1996.
8. P. Hurst, A comparison of two approaches to feedback circuit
analysis, IEEE Trans. Educ., 35: 253261, 1992.
9. G. Palumbo and J. Choma Jr., An overview of analog feedback,
Part I: Basic theory, Analog Integ. Circuits Signal Process., in
press.

269

18. Y. Tsividis and P. Gray, An integrated NMOS operational amplifier with internal compensation, IEEE J. Solid-State Circuits, SC11: 748754, 1976.
19. G. Smaradoiu et al., CMOS pulse-code-modulation voice codec,
IEEE J. Solid-State Circuits, SC-13: 504510, 1978.
20. D. Senderowicz, P. Gray, and D. Hodges, High-performance
NMOS operational amplifier, IEEE J. Solid-State Circuits, SC13: 760766, 1978.
21. B. Ahuja, An improved frequency compensation technique for
CMOS operational amplifiers, IEEE J. Solid-State Circuits, SC18: 629633, 1983.
22. C. Makris and C. Toumazou, Current-mode active compensation
techniques, Electron. Lett., 26: 17921794, 1990.
23. W. Black, Jr., D. Allstot, and R. Reed, A high performance low
power CMOS channel filter, IEEE J. Solid-State Circuits, SC-15:
929938, 1980.
24. G. Palmisano and G. Palumbo, An optimized compensation strategy for two-stage CMOS Op Amps, IEEE Trans. Circuits Syst.,
42: 178182, 1995.
25. R. Castello, CMOS Buffer Amplifier, in J. Huijsing, R. van der
Plassche, and W. Sansen (eds.), Analog Circuit Design, Norwell,
MA: Kluwer, 1993, pp. 113138.
26. R. Reay and G. Kovacs, An unconditionally stable two-stage
CMOS amplifier, IEEE J. Solid-State Circuits, 30: 591594, 1995.
27. D. Ribner and M. Copeland, Design techniques for cascoded
CMOS op amps with improved PSRR and common-mode input
range, IEEE J. Solid-State Circuits, SC-19: 919925, 1984.
28. M. Steyaert and W. Sansen, Power supply rejection ratio in operational transconductance amplifier, IEEE J. Solid-State Circuits,
37: 10771084, 1990.
29. G. Palmisano and G. Palumbo, Two-stage CMOS OPAMPS based
on current buffer, IEEE Trans. Circuits Syst. I, 44: 257262, 1997.
30. R. Meyer and A. Wong, Blocking and desensitization in RF amplifier, IEEE J. Solid-State Circuits, 30: 944946, 1995.
31. D. Pederson and K. Mayaram, Analog Integrated Circuits for Communication: Principle, Simulation and Design, Norwell, MA:
Kluwer, 1991.
32. G. Palumbo and S. Pennisi, Harmonic distortion in nonlinear amplifier with nonlinear feedback, in print, Int. J. Circuit Theory
Appl., 26: 293299, 1998.

GAETANO PALUMBO
SALVATORE PENNISI
University of Catania

10. S. Rosenstark, A simplified method of feedback amplifier analysis, IEEE Trans. Educ., E-17: 192198, 1974.
11. J. Choma, Jr., Signal flow analysis of feedback networks, IEEE
Trans. Circ. Syst., 37: 455463, 1990.
12. R. Blackman, Effect of feedback on impedance, Bell Syst. Tech.
J., 22: 269277, 1943.
13. G. Palumbo and J. Choma, Jr., An overview of analog feedback,
Part II: Amplifier configurations in generic device technologies,
in print Analog Integ. Circuits Signal Process.
14. G. Palmisano and G. Palumbo, A novel representation for twopole feedback amplifiers, IEEE Trans. Educ., 41: 216218, 1998.
15. H. Yang and D. Allstot, Considerations for fast settling operational amplifiers, IEEE Trans. Circuits Syst., 37: 326334, 1990.
16. E. Cherry, A new result in negative feedback theory, and its application to audio power amplifiers, Int. J. Circuit Theory, 6: 265
288, 1978.
17. R. Eschauzier and J. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers, Norwell, MA:
Kluwer, 1995.

SIGNAL COMPRESSION. See LOGARITHMIC AMPLIFIERS.

SIGNAL DELAY. See INTEGRATED CIRCUIT SIGNAL DELAY.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

NONLINEAR SYSTEM REPRESENTATION

It has been said that whereas linearity is a specification of a field of activity, nonlinearity is a nonspecification
and its field is unbounded. In nature, nonlinearity is the rule rather than the exception, while linearity is a
simplification adopted for analysis. Most practical systems used for control are essentially nonlinear, and in
many applications, particular in the area of chaos, it is the nonlinear rather than the linear characteristics
that are most used. Signals found in the physical world are also far from conforming to linear models. Indeed,
the complex structure of dynamic systems makes it almost impossible to use linear models to represent them
accurately. Nonlinear models are designed to provide a better mathematical way to characterize the inherent
nonlinearity in real dynamic systems, although we may not be able to take all their physical properties into
account. In this article, we will focus on other nonlinear techniques than modeling, which may provide readers
with useful perspectives.
For most real-world practical applications, there are advantages to using nonlinear models to characterize
the nonlinear relationships. Mathematical models may be expressed in the form of difference or differential
equations. Depending on the given engineering problem and the circumstances, one mathematical model may
be better suited than another. Figure 1 shows a typical system for processing and evaluating a system model.
In general, nonlinear representations can be classified into three types: (1) system inputoutput representation, (2) state-space representation, and (3) model-free representation. The first type considers the
inputoutput behavior of a system without considering any internal variations. The second type focuses on
both internal and external performance of the system, and the last type focuses on the representation of
nonlinear systems that cannot be handled by the other two approaches.
Although the selection of the type of model is often quite subjective, it is usually the result of a compromise
between the model selection and familiarity with the model itself. In this regard, a number of nonlinear
techniques will be briefed in this article.

InputOutput System Representation

Nonlinear system representation means the characterization of nonlinear systems using nonlinear mathematical models. In fact, nonlinear models may be considered as a tool for explaining the nonlinear behavior patterns
in terms of a set of easily understood elements. Figure 2 shows the inputoutput representation approach for
describing a given nonlinear system

where y(t) refers to the system output, u(t) refers to the system input, the independent variable t is time, and
the f denotes a mathematical relationship describing the nonlinear behavior: the system yields the output y(t)
when the system has a input u(t).
1

NONLINEAR SYSTEM REPRESENTATION

Fig. 1.

Fig. 2.

Model for investigating systems.

Model of nonlinear inputoutput system.

Generally, the nonlinear mapping f is very complicated, and there is no single technique suitable for the
analysis of all nonlinear behaviors. In order to appreciate the complexity associated with nonlinear systems, it
is best first to review the relative simplicity associated with linear systems. The main reason is that dynamic
system analysis relies heavily on linear models, due to their comprehensiveness and the availability of welldeveloped linear system theories.
A system (1) is called a linear system if it satisfies

We note two important features. One is that the sum of inputs results in the sum of the responses to the
individual inputs, and the other is that a multiple of an input results in the same multiple of the corresponding
output. An electric circuit containing a capacitor and a resistor is a common example used for explication. In
this article we will mainly focus on the theoretical aspect.
A dynamic system is called anticipatory or noncausal if its outputs depend on the past, present, and
future values of its inputs. A system is called nonanticipatory or causal if its outputs depend only on the past
and present values of its inputs. We say that a system is time-invariant if its properties are invariant to a shift
of time.
First let us consider the following linear system, which can be described as single-input, single-output,
time-invariant, and causal (1):

where h(t) is called the impulse response of the system. Without loss of generality, this system can be assumed
to satisfy the following assumptions: (1) h(t) is a real-valued function defined for t (, ) and piecewise
continuous except possibly at t = 0; (2) the input signal is a real-valued function defined for t (, )
and piecewise continuous. These conditions imply that the output signal is a continuous, real-valued function
defined for t (, ). In practical engineering, however, it is often assumed that h(t) is a real-valued function
defined for t (0, ), corresponding to causality. Considering only input signals that are zero prior to t = 0,
which allows the upper limit in Eq. (3) to be replaced by t, a change of the integration variable shows that Eq.

NONLINEAR SYSTEM REPRESENTATION

(3) can be rewritten as

In this form the one-sidedness assumption on h(t) implies that the upper limit can be lowered to t, while a
one-sided assumption on u(t) enables the lower limit to be raised to 0. The representation (3) is usually favored
for time-invariant systems.
If the assumption that the system is time-invariant is dropped, the following inputoutput representation
applies. We replace h(t) with a real-valued function h(t, s) defined for t (, ), s (, ), with h(t, s) =
0 if s > t, that is,

It is straightforward to confirm that this represents a linear system in a general sense. In fact, the assumption
on h(t, s) implies causality; only the delay-invariance property has been dropped. Typically h(t, s) is allowed to
contain impulses for s = t, but otherwise is piecewise continuous for t s 0. The range of integration in Eq.
(5) can be narrowed as discussed before.
Comparison of Eqs. (4) and (5) highlights the fact that time-invariant linear systems are, in fact, special
cases of time-varying linear systems. Thus, the impulse function h(t, s) in (5) is called time-invariant if there
exists an impulse response h (t) such that

An easy way to check for time invariance of h(t, s) is to check the condition h(0, s t) = h(t, s). If this is satisfied,
then setting h (t) = h(0, t) verifies Eq. (6).

Nonlinear Differential Algebraic Representation

The specification of the modeling problem for a linear system is simplified by the fact that it is easy to
parametrize the response via a defined coordinate system. This fact enables us to reduce the problem of
constructing a standard model from an inputoutput relation to a linear-algebra expression. In the nonlinear
case, there is no such global coordinate system. Usually we have to be cautious in defining what we mean by
the problem data. We cannot simply assume the system response to be as simple as an infinite sequence of
functions or an impulse function.
The first step in constructing a nonlinear model is the development of a differential representation for
describing the system inputoutput behavior. Clearly, there are a number of ways in writing differential
equations that describe the behavior of different dynamic systems. No single one of them is preferable in all
circumstances. In general, the result required and the familiarity of the investigator with a particular method
determine the form of the differential equations.
One particularly convenient method of characterizing the behavior of a nonlinear system is by (2)

NONLINEAR SYSTEM REPRESENTATION

Fig. 3.

A nonlinear system model in differential representation.

where u(t) is the system input, y(t) is the system output, and f () is an arbitrary nonlinear function. Figure
3 shows the corresponding inputoutput relationship. There are several reasons for the importance of this
differential algebraic form of the system equations. Apart from the notational simplicity, one can deal with
all systems by means of a compact notation instead of having to write a system of simultaneous differential
equations. Also, this representation is the one that most modern literature in the theory of differential equations
makes use of.
It is natural to represent the output in terms of the input as a series expansion

where the real-valued function of n variables hi (t1 ,t2 ,. . .,tn ), i = 0, 1, 2, . . ., is equal to zero if any ti < 0, that is to
say, the system is causal. Obviously the system is not linear, and it is a time-invariant system if hi (t1 ,t2 ,. . .,tn ) =
h i (t1 t2 tn ). Formally the expansion (8) is a generalization of the linear-variation-of-constants formula
(5). Clearly, this type of modeling problem for nonlinear systems may be expressed as follows: given a sequence
of inputoutput pairs, find a canonical model (8) whose inputoutput behavior generates the series of impulse
functions hi , i = 0, 1, 2, . . ..
The modeling process is rather straightforward if there are no further hypotheses on the analytic behavior
of f in Eq. (7) and there is a suitable definition of the canonical model. In general the problem is unsolvable,
but the following theorem (3) provides conditions under which the expansion (8) exists and is unique.
Theorem 1. If the nonlinear relationship f in Eq. (7) is an analytic vector field and Eq. (7) has a solution on
[0, T] with y(0) = h0 (0), then the inputoutput behavior of Eq. (7) has a unique representation expressed by
Eq. (8) on [0, T] (3).
Now it is quite clear that the condition of analyticity of the defining vector field is essential. The reason is
clear: analyticity forces a certain type of rigidity upon the system, namely, the system behavior is determined
by its response in an arbitrarily small open set. Fortunately, it is a property possessed by all systems defined
by sets of algebraic equations.

Volterra Representation
In this section, we introduce a special type of nonlinear series, Volterra series, which exhibit many important
features for nonlinear system modeling, control, and signal processing. Put in simple words, a Volterra series
contains symmetrical parameters, Volterra kernels, of order n, which are nth-order impulse responses, to

NONLINEAR SYSTEM REPRESENTATION

represent nonlinear dynamics. In most cases, we have to estimate the Volterra kernels. This is usually a
computationally rather complex procedure and is best performed offline.
Based on a real-valued function of n variables hn (t1 , t2 , . . ., tn ) defined for ti (, ), i = 1, 2, . . ., n, and
such that hn (t1 ,t2 ,. . .,tn ) = 0 if any ti < 0, we consider the following system response:

Equation (9) is a nonlinear model of degree n, in which application of the input au(t), where a is a scalar, yields
the output an y(t). The impulse function hn (t1 , t2 ,. . .,tn ) is called the model kernel.
If the input signal is one-sided, then all the upper limits can be replaced by t. A change of each variable
of integration shows that Eq. (9) can be rewritten in the following form:

In most science and engineering applications the above model is usually obtained from physical systems that are
structured in terms of interconnections of linear subsystems and simple nonlinearity, especially time-invariant
linear subsystems and nonlinearities that can be represented in terms of multipliers. Simply by tracing the
input signal through the system structure, it is easy to derive the system kernels from the subsystem kernels
for the interconnection-structured systems. The model (10) can also arise with a state-equation description of
a nonlinear system, which will be discussed in detail later on.
A model described by a finite sum of terms like those in Eq. (10),

is called an Nth-order Volterra model (4). It is worth noting that, as special cases, static nonlinear models
described by a polynomial or power series in the input,

or

are included in this Volterra model simply taking hn (t1 , t2 ,. . ., ti ) = ai (t1 )(t2 ) (ti ).

NONLINEAR SYSTEM REPRESENTATION

As a Volterra series is an infinite series, convergence conditions must be considered. Usually these
conditions include a bound on the time interval and a bound for u(t) on this interval, but the determination of
the bound is often difficult.
With reference to the derivation of the Volterra representation for a nonlinear model, it is reasonable to
consider the output y(t) of a nonlinear model at a particular time t as depending on all values of the input at
times prior to t, which implies that y(t) depends on u(t i) for all i 0. In other words, the present output
depends on all past input values. This viewpoint leads to the following idea. If u(t i) for all i 0 can be
described by a set of quantities u1 (t), u2 (t),. . ., then the output y(t) can be represented as a nonlinear function
of these quantities,

Suppose that t is fixed, and the input u(t i) is an element of the Hilbert space L2 (0, ) of square-integrable
functions, that is,

Also, suppose that w1 (t), w2 (t),. . . is an orthonormal basis for this space:

The value of the inputs at any time of the past is in the form

where

Equation (17) yields a characterization of the past of u(t) in terms of u1 (t), u2 (t),. . ., regardless of t. Expand the
function f (u1 (t), u2 (t),. . .) into a power series, so that the output at any time t is

NONLINEAR SYSTEM REPRESENTATION

Substituting Eq. (18) into Eq. (19), we obtain

In view of the definition of the kernel, this is the kind of representation that has been discussed.
The generalization of the Laplace transform to functions of variables is of importance for nonlinear system
modeling 5. This representation is very handy for characterizing model properties and for describing the model
inputoutput response. Given a time-invariant linear model, the transfer function of the model is the Laplace
transform of h(t),

For one-sided input signals, by using the convolution property of the Laplace transform, the inputoutput
response can be expressed as

or

where Y(s) and U(s) are the transforms of y(t) and u(t), respectively. If a model transfer function is given and the
input signal of interest has a simple transform U(s), then the utility of this representation for computing the
corresponding output signal is quite clear. Moreover, many system properties can be expressed rather simply
as properties of H(s). Consider that an nth-order nonlinear model with one-sided inputs is represented by

Because of the properties of the multivariable Laplace transform, there is no direct way of updating in a
form similar to Eq. (23). An indirect approach is therefore employed, writing Eq. (24) as the following pair of

NONLINEAR SYSTEM REPRESENTATION

equations:

Then, Eq. (25) can be written as a relationship between Laplace transforms in the form

Now let us look at the Laplace transform representation of Volterra models. It basically involves the collection of submodel transfer functions in Eq. (25). Obviously, response calculations are performed by summing
the responses of the submodels as calculated individually by association of variables:

This summation requires consideration of the convergence properties of an infinite series of time functions.
Usually convergence is crucially dependent on properties of the input signals, for example, bounds on their
amplitude. Using the growing exponential signals as inputs of Volterra models, it is easy to determine the
transfer function of the model.
The nonlinear Volterra models discussed above can be developed for discrete-time cases. There are differences, of course, but these mostly are differences in technical details or interpretation of the results. The
situation is similar to the linear case, where the continuous- and discrete-time theories look much the same.
Consider the following discrete-time system representation:

The input signal u(t) and the output signal y(t) are real sequences that are assumed to be zero for t < 0. The
kernel h(i0 , i1 , . . ., il ) is real, and assumed to be zero for any i0 , i1 , . . ., il < 0. It is straightforward to verify that
a system described by Eq. (29) is nth-order, time-invariant, and causal. It is noted that the upper limits on the
summations can be lowered to t.
Since, for any t, y(t) is given by a finite summation, problems like continuity and integrability in the
continuous-time case do not arise with regard to the representation in Eq. (29). Notice that direct transmission
terms are explicitly displayed in Eq. (29), and there is no need to consider impulsive kernels. The familiar sumover-permutations argument shows that the kernel in Eq. (29) can be replaced by the symmetric kernel hsym (i0 ,
i1 , . . ., in ) = 1/n! () h(i(1) , i(2) , . . ., i(n) ) without loss of generality. From the symmetric kernel representation,

NONLINEAR SYSTEM REPRESENTATION

a triangular-type kernel can be defined as htri (i0 , i1 , . . ., il ) = hsym (i0 , i1 , . . ., il )(i1 i2 , i2 i3 , . . ., il 1 il ) (6),
where the special multivariable step function takes the form

It is easy to verify that when n = 2, this setup yields consistent results in going from the symmetric kernel to
the triangular kernel and vice versa. The higher-degree cases are less easy but still straightforward.
The regular kernel representation is another special form of the system kernel. With the triangular kernel
representation

a simple change of variables argument gives

where

Also it is noticed that the upper limits of the summation in Eqs. (31) and (32) can be replaced by finite quantities.
Although only time-invariant systems are usually considered, a general representation of the form

is also very important. It is natural to follow the continuous-time case and call a kernel h(t, i0 , i1 , . . ., il )
time-invariant if h(0, i0 t, i1 t, . . ., il t) = h(t, i0 , i1 , . . ., il ). If this relationship holds, then setting g(i0 , i1 ,

10

NONLINEAR SYSTEM REPRESENTATION

. . ., il ) = h(0, i0 , i1 , . . ., il ) yields the representation

which is equivalent to Eq. (34). Actually the above equation can be described as

which is in the same form as Eq. (29).

With these basic representations, the description of Volterra models is simply a matter of finite sums of
the terms in Eq. (29). In circuit theory, signal processing, and communication applications, the following two
truncated Volterra models are usually utilized:
Quadratic Model.

Cubic Model.

Of course the convergence issue is important for Volterra models, but the basic approach to convergence
in the continuous-time case carries over directly (4).
In the frequency domain, the z-transform representation is used for Volterra systems in just the same
way that the Laplace transform is used in the continuous-time case (7). A transfer function for a nth-order
discrete-time system [Eq. (29)] is defined as the z-transform of a kernel for the system. That is,

NONLINEAR SYSTEM REPRESENTATION

11

Unfortunately, it seems to be impossible to represent the inputoutput relationship in Eq. (29) directly in terms
of U(z), Y(z), and H(z1 , z2 , . . ., zl ). The usual alternative is to rewrite Eq. (29) as a pair of equations

Then the first equation has the form

while the second equation is an association of variables that involves contour integrations of the following
form:

As far as the regular transfer function is concerned, the formulas in Eqs. (40) and (41) do not directly apply.
However, by suitably restricting the class of input signals, a much more explicit formula can be obtained.
By establishing a basic expression for the z-transform of the inputoutput relation (32), the regular transfer
function is cast in the following form:

where each Hi1 i2 ...il 1 (zl ) is defined according to

State-Space Representation
A state-space representation is usually used for describing physical systems. If the state of a system is known,
then any output or quantity of interest with respect to certain performance indices can be achieved. To deter-

12

NONLINEAR SYSTEM REPRESENTATION

mine the state of a system as a function of time, we need a set of equations to relate the inputs state of the
system. One approach for obtaining that set of equations is to consider each state variable as an output, to
be determined via an nth-order differential or difference equation. Using the state-space approach, we will be
able to write n first-order differential or difference equations for the n state variables of the system. In general
they will be coupled equations, that is, they will have to be solved simultaneously. For nonlinear systems,
these first-order equations will be nonlinear ones. One advantage of the state-space representation is that once
the first-order equations are solved, complete knowledge of the system behavior is obtained. All outputs are
algebraic functions of the state variables. No further solution of a differential or difference equation is needed.
The inputoutput behavior of a nonlinear system can be characterized by first-order differential or difference equations

or

where x n are the internal states of the system, u m are the inputs, y q are the outputs and f : n+m
n , g : n q . While the inputs and outputs of a system are generally the tangible physical data, it is the
state variables that assume the dominant role in this formulation. It is possible that quantities that are not of
interest will lead to an unnecessarily complicated problem.
A major difficulty in dealing with nonlinear equations is that the existence and the uniqueness of solutions,
even in a local sense, cannot be taken for granted. As a matter of fact, there does not exist any general
methodology to determine the nonlinear relations f and g. Instead, various simplified nonlinear models are
widely used in practical engineering applications. The so-called bilinear model is among these. We will discuss
the bilinear representation in detail later.
Now let us look at the discrete-time nonlinear model (47). It is assumed that the initial state is x(0) = 0,
and that f (0, 0) = 0 and g(0, 0) = 0. Then the functions f (x, u) and g(x, u) can be represented using a Taylor
series about x = u = 0 of order sufficient to permit calculating the polynomial inputoutput representation to
the degree desired:

where x(i) = x x x (i factors) and F ij , Gij are the standard Kronecker products. Just as in the continuoustime case, the crucial requirement is that the kernels through order N corresponding to Eq. (48) should be
identical to the kernels through order N corresponding to Eq. (47).

NONLINEAR SYSTEM REPRESENTATION

13

Bilinear Representation
In the class of nonlinear dynamic systems, bilinear models are probably the simplest ones. They take the form
(8)

or

where F, N i , and C are n n real matrices and G, D are n m real matrices. Bilinear models are widely
used in control systems, signal processing, and communications, because they can be parametrized by matrix
operations and lead to linear models of familiar type.
The solution of Eq. (49) for x(t) in terms of a series expansion is given by (9)

where Nx(t)u(t) = (m i = 1 N i ui )x(t). The first term xl (t) in Eq. (51) is the solution, for the state vector x(t), of the
linear system described by the equation x (t) = Fx(t) + Gu(t). The second term xb (t) is due to the bilinear term
(m i = 1 N i ui )x(t) appearing in Eq. (49).
The term xl (t) may be approximated via orthogonal series as follows:

14

NONLINEAR SYSTEM REPRESENTATION

where f r (t) = [f 0 (t), f 1 (t), . . ., f r 1 (t)]T is the orthogonal basis vector and

where e is a constant r 1 vector, whose form depends on the particular orthogonal series; Pr is the r r
operational matrix of integration; and U is the m r coefficient matrix of the input u(t), defined by

An approximation of Eq. (54) is obtained by keeping the first k power-series terms of eFt and eF(t t1 ) appearing
in xl (t).
Similarly to xl (t) in Eq. (54), the second term xb (t) can be expressed by the following equations:

where

Then Eq. (51) can be replaced by an orthogonal expression in the form

This makes the study of controllability and observability of bilinear models much easier via orthogonal functions.

Narma Representation
In this section, the nonlinear autoregressive moving-average (NARMA) model is discussed. Detailed nonlinear
system modeling using this model can found in Refs. (10) and (11).

NONLINEAR SYSTEM REPRESENTATION

15

Now let us consider the following discrete-time system:

where y(t) Y, the output set of dimension q; x(t + 1), x(t) X, the state set of dimension n; u(t) U, the input
set of dimension m; t Z, the set of integers; f : Z X U X is the one-step-ahead state transition function;
and g : Z X U Y is the output function. Assuming that the system is at the zero equilibrium point at
time t = 1, the zero-state response for an input sequence of length t is given by

where ht : U t Y. The function ht is a different function for every t = 1, 2, . . ., because the domain of definition
U t is different. Assume that the response functions ht are continuously differentiable functions, and let the
vector ut (t) = [u(t), u(t 1), . . ., u(1)]T ; then

Let yt k (t) = [y(t), y(t 1),. . ., y(t + k 1)]T and ut k (t) = [u(t + k 1), u(t + k 2),. . ., u(t)]T . Then Eq. (63) can
be rewritten as

where yk (t) Y k , ut k U k , ut 1 U t 1 . The function H t k : U k U t Y k can be defined for any k = 1, 2, . . ., t =

1, 2, . . ., when the response function ht is known for t = 1, 2, . . .. The function H t k is continuously differentiable,
since it is the Cartesian product of k response functions of continuously differentiable. For simplicity, we let z
= ut+1 k U k , x = ut U t . The assumptions on the function H t k are the following:
Assumption 1. max[rank dH t k (z,x)/dx]=n for any z = uk t+1 U k , x = ut U t and any t, k =1, 2, . . ..
Assumption 2. rank dH t k (0,0)/dx = n for some t and some k.
We can prove the following theorem.
Theorem 2. For any nonlinear system satisfying Assumptions 1 and 2, there exists a number l and a continuous function  : yl ul y such that the recursive inputoutput representation given as

has the same inputoutput behavior as the original system in a restricted operating region and around the
zero equilibrium point.

16

NONLINEAR SYSTEM REPRESENTATION

Recall the autoregressive moving-average (ARMA) model in the linear case,

The model (65) is called the NARMA model (10) by extension. The NARMA model can be further extended to
a nonlinear stochastic system. Let the estimate y (t) denote the prediction of y(t) that is in the form

The prediction error vector e(t) can be calculated as e(t) = y(t) y (t); it is a vector random variable and shows
how much the actual output at time t differs from the predicted one. Then the stochastic NARMA model can
be expressed as (12)

Fuzzy-Logic Nonlinear Representation

The real physical world is very complex, so that problems may always arise from many uncertain factors. The
uncertainty in all engineering problems motivates us to establish appropriate methods or models to express
the uncertainty. Fuzzy logic is a mathematical approach developed by Zadeh (13) to tackle this issue. Because
of their outstanding ability to relate fuzzy sets with humanistic variables, fuzzy-logic nonlinear models have
recently been widely used in the areas of control, signal processing, and communication applications. They
have demonstrated their versatility in representing complex nonlinear physical systems using linguistic rules
of the IFTHEN form. For example, Fig. 4 shows the nonlinear relation between the probability of a machine
fault and the vibration magnitude. The mapping shown in Fig. 4 can be best described by fuzzy logic.
A fuzzy-logic model consists of an identification algorithm that adjusts the parameters. The model is designed from certain IFTHEN rules using fuzzy-logic principles. In general, there are two strategies for combining
numerical and linguistic information using adaptive fuzzy models. In the first, one uses linguistic information
to construct an initial fuzzy-logic model. The parameters of that model are then adjusted in accordance with
numerical information. The final fuzzy-logic model can then be obtained by combining numerical and linguistic
information. In the second strategy, two separate fuzzy-logic models are initially constructed from numerical
information and linguistic information. These models are then averaged to obtain the final fuzzy-logic model.
The most popular fuzzy logic models may be classified into three types: the pure fuzzy-logic model, Takagi
and Sugenos fuzzy model, and fuzzy-logic models with fuzzifier and defuzzifier (14,15).
Pure Fuzzy-Logic Model. Basically, this first type consists of a fuzzy rule base and a fuzzy inference
engine. The rule base is a collection of fuzzy IFTHEN rules, and the inference engine is based on fuzzy-logic
principles. The IFTHEN rules are to determine a mapping from fuzzy sets in the input universe to fuzzy sets

NONLINEAR SYSTEM REPRESENTATION

Fig. 4.

17

A fuzzy nonlinear relation mapping from an input space to an output space.

in the output. They are of the following form:

where F l i and Gl are fuzzy sets, and u = [u1 , u2 , . . ., un ]T U and y V are input and output linguistic
variables, respectively. The major advantage of fuzzy logic is its remarkable ability to incorporate common
sense, as reflected in decisions, into numerical information. Each fuzzy IFTHEN rule of Eq. (69) defines a fuzzy
set F l 1 F l 2 F l n Gl in the product space U V.
The most commonly used fuzzy-logic principle is the so-called supstar composition. Let A be the input to
the pure fuzzy-logic model. Then the output determined by each fuzzy IFTHEN rule of Eq. (69) is a fuzzy set A
(R(l) ) in V whose membership function is

where is an operator such as minimization or multiplication, and A is the membership function of the fuzzy
set A. The output of the pure fuzzy-logic system is a fuzzy set A (R(1) , R(2) ,. . .,R(M) ) in V that combines the M
fuzzy sets in accordance with Eq. (70):

18

NONLINEAR SYSTEM REPRESENTATION

where the operator
is maximization, that is, u
y = u + y uy. The model becomes a fuzzy dynamic model
if there is feedback in the fuzzy-logic model.
Takagi and Sugenos Fuzzy Model. The pure fuzzy-logic model constitutes the essential part of
all fuzzy-logic models. By itself, however, it has the disadvantage that its inputs and outputs are fuzzy sets,
whereas in most physical systems the inputs and outputs of a system are real-valued variables. In order to
overcome this shortcoming, Takagi and Sugeno designed another fuzzy-logic model of which inputs and outputs
are real-valued variables.
In this model (16), the following fuzzy IFTHEN rules are proposed:

where F l i are fuzzy sets, cl i are real-valued parameters, yl is the model output due to the rule Ll , and l = 1, 2,
. . ., M. That is, they considered rules of which the IF part is fuzzy, but the THEN part is crisp. Also, the output
is a linear combination of input variables. For a real-valued input vector u = [u1 , u2 , . . ., un ]T , the output y(u)
is a weighted average of the yl s:

where the weight wl represents the overall truth value of the premise of the rule Ll for input and can be
determined by

where Fil is the member function of the fuzzy set F i l . The major advantage of this model lies in the fact that it
provides a compact system equation (73). Hence, parameter estimation and order determination methods can
be developed to estimate the parameters cl i and the order M. A shortcoming of this model is, however, that the
THEN part is not fuzzy, so that it cannot incorporate fuzzy rules from common sense and human decisions.
Fuzzy-Logic Models with Fuzzier and Defuzzier. Models of this type (17) add a fuzzifier to the
input and a defuzzifier to the output of the pure fuzzy-logic model. The fuzzifier maps crisp points in U to
fuzzy sets in U, while the defuzzifier maps fuzzy sets in V to crisp points in V. The fuzzy rule base and fuzzy
inference engine are the same as those described in the pure fuzzy-logic model.
Evidently the fuzzy-logic model with fuzzifier and defuzzifier has certain advantages over other nonlinear
modeling techniques. First, it is suitable for engineering systems in that its input and outputs are real-valued
variables. Second, it is capable of incorporating fuzzy IFTHEN rules from common sense and human decisions.
Third, there is much freedom in the selection of fuzzifier, fuzzy inference engine, and defuzzifier, in order to
obtain the most appropriate fuzzy-logic model for a given problem. Finally, we are able to design different
identification algorithms for this fuzzy-logic model, so as to integrate given numerical and human information.
The fuzzifier that performs the mapping from a crisp point into a fuzzy set A in U can be a singleton or
a nonsingleton fuzzifier. Singleton fuzzifiers have mainly been used, but nonsingleton fuzzifiers can be useful
when the inputs are noise-corrupted.
There are at least three possible choices for the defuzzifer that performs a mapping from fuzzy sets in V
into a crisp point y V:

NONLINEAR SYSTEM REPRESENTATION

Fig. 5.

19

A typical fuzzy control system.

(1) The maximum defuzzifier, defined as

where B is a fuzzy set with support y.

(2) The center average defuzzifier, defined as

where yl is the center of the fuzzy set Gl , that is, the point in V at which Gl (y) achieves its maximum value.
(3) The modified center average defuzzifier, which is given as

where l is a parameter characterizing the shape of Gl (y) such that the narrower the shape of Gl (y), the
smaller is l . For example, if G (y) = exp[(y yl )/l ]2 , then l is such a parameter.

Fuzzy Control Summarized. For nonlinear system modeling, fuzzy logic can be viewed as a versatile
tool to perform nonlinear mapping. But in such an inputoutput nonlinear system model, the input signals
should be representative and sufficiently rich. In most cases, the fuzzy nonlinear model is based on inputs such
as the rate of change of error, and the fuzzy model may be in continuous time or discrete time.
Figure 5 shows a typical fuzzy control system, in which input values are normalized and fuzzified, the
fuzzy-model rule base is the control rule base used to produce a fuzzy region, and a defuzzification process is
used to find the expected output value. A typical fuzzy learning control-system design is that proposed in 1993
by Harris et al. (18). Wang and Vachtsevanos (19) detailed an indirect fuzzy-control approach in 1992. In their
early research, a separate fuzzy model was developed. A well-designed procedure was then used to calculate
the control signal. More detailed discussion of control of nonlinear systems using fuzzy logic can be found in
Refs. 18,19,20.

20

NONLINEAR SYSTEM REPRESENTATION

Fig. 6.

A neuron with p inputs and a nonlinear activation function .

Nonlinear Representation Using Neural Networks

Conventional model-based theoretical methods have dominated nonlinear-representation research over the
last few decades. These methods depend on a mathematical characterization of the monitored system. The
main disadvantage of such approaches is that they are very sensitive to the selection of model type, modeling
errors, parameter variations, and measurement noise. The success of model-based representation approaches
is heavily dependent upon the quality of the models as well. For most practical nonlinear physical systems, it
is often very difficult, if not impossible, to describe them by sufficiently simplified analytical models. In view
of these, there is great interest in developing a robust and less model-dependent methodology for representing
a complex nonlinear dynamic system. To avoid the difficulties experienced in the classical nonlinear system
modeling, neural-network-based nonlinear system modeling methods appeared to be an appealing alternative.
The rationale behind this approach lies in the fact that a multilayer neural network (Fig. 6) with an appropriate
nonlinear activation function can approximate any nonlinear relationship.
In using neural networks for nonlinear system modeling, their nonlinear functional approximation capability can be enhanced by using higher-order architectures. In Refs. (32) and (33) strong theoretical arguments
were introduced for the functional-approximation capability of the random-vector version of functional-link
nets (RVFL). (See Fig. 7.) The distinctive aspects of this network are that the parameters of the hidden layer,
such as the weights and the thresholds, are selected randomly and independently in advance. The parameters
of the output layer are learned using simple quadratic optimization, whereas under conventional approaches
all parameters need to be learned using complicated nonquadratic optimization.
Two

types of RVFL have been proved to be universal approximators. One [Fig. 7(a)] can be formulated as
f n (x) = n k = 1 ak g(wk x + bk , where n = (n, a1 , a2 , . . . an , b1 , b2 , . . ., bn , w1 , w2 , . . ., wn ) is the whole parameter
vector of the net, f (x) C(Id ), and wk x is the inner product of the vectors wk and x. The random part of n is
denoted as n = (b1 , b2 , . . ., bn , w1 , w2 , . . ., wn ). Each n is selected
 in a specified probabilistic space.

uniformly
The second type of RVFL [Fig. 7(b)] is formulated as f n (x) = n k = 1 ak d i = 1 g(wki xi + bki , where x = (x1 , x2 ,
xd ), wk = (wk1 , wk2 , wkd ), and bk = (bk1 , bk2 , bkd ). The parameters wk , bk are selected uniformly in a
specified probabilistic space, and ak are learned from the information of f (x). The parameter ak represents a
dth-order weight from the kth group in the hidden layer to the output unit. This is an interesting structure
in that it is also a partially connected higher-order neural network. Apart from the network architecture, the
self-learning ability is another appealing property, enabling the neural network to extract the system features
through a learning process. This provides great flexibility and convenience for modeling nonlinear systems.
Many types of neural networks have been developed for tackling different problems, but two types have
received the most attention in recent years (22,23): (1) multilayer feedforward neural networks and (2) recurrent

NONLINEAR SYSTEM REPRESENTATION

21

Fig. 7. (a) The structure of the an RVFL network with weights ak , 1 k n, that are first-order and adjustable. The
weights and the thresholds of the hidden units are distributed uniformly in the selection spaces and determined in advance.
(b) The structure of the RVFL of the second type. This network is an extremely sparsely connected higher-order network.
The weights ak , 1 k n, are dth-order and adjustable. The weights and the thresholds of the hidden units are distributed
uniformly in the selection spaces and determined in advance.

networks. Multilayer feedforward networks have proved extremely successful in pattern recognition problems,
and recurrent networks for dynamical system modeling and time-series forecasting.
A multilayer network is a network of neurons organized in the form of layers. Figure 8 shows a typical
form of a multilayer network, in which an input layer of source nodes projects onto the hidden layer composed
of hidden neurons. The output of the hidden neurons then projects onto an output layer. In general, one
hidden layer is adequate to handle most engineering problems. The nonlinear activation function of the hidden

22

NONLINEAR SYSTEM REPRESENTATION

Fig. 8.

A simple multilayer feedforward neural network.

neurons, which is generally sigmoidal, is chosen to intervene between the external input and the network
output.
For hidden neurons to be useful in modeling nonlinear systems, they must be sufficiently numerous.
Though there has been much research on determining the optimal number of hidden neurons, there is no
straightforward rule for doing so. When the number of hidden neurons reaches a certain threshold, the overall
performance will not be significantly affected by small further increases. In this respect, the design criterion
is rather loose.
The source nodes of the network supply corresponding elements of the activation pattern (input vector),
which constitute the input signals applied to the neurons in the hidden layer. The set of output signals of the
neurons in the output layer of the network constitutes the overall response of the network to the activation
pattern supplied by the source nodes at the input layer.
A neural network is said to be fully connected when every node in each layer of the network is connected to every other node in the adjacent forward layer. We say that the network is partially connected if
some of the links are missing. Evidently, fully connected networks are relatively complex, but they are usually capable of much better functional approximation. A form of partially connected multilayer network of
particular interest is the locally connected network. In practice, the specialized structure built into the design
of a connected network reflects prior information about the characteristics of the activation pattern being
classified.
As multilayer feedforward neural networks have become generally recognized as a suitable architecture
for representing unknown nonlinearities in dynamic systems, numerous algorithms for training the networks
on the basis of observable inputoutput information have been developed by many researchers. In this article, a training algorithm for neural networks called the cumulant-based weight-decoupled extended Kalman
filter (CWDEKF) is described (24). Third-order cumulants are employed to define output errors for the network training. By this means, Gaussian disturbances or non-Gaussian noises with symmetric probability
density function among the output signals can be rejected in the cumulant domain. Thus we can obtain clean
neural network output information for nonlinear mapping implementation. The weight-decoupled extended
Kalman filter training algorithm is applied because it provides faster convergence (learning rate) then other
training algorithms. This feature is very important for neural-network-based analysis of nonlinear dynamic
systems.
To ease the mathematical burden, we first present a summary of the notation used in the network learning
algorithm.

NONLINEAR SYSTEM REPRESENTATION

23

Notation.

The index i refers to different layers in the network, where 1 i M, and M is the total number of layers
(including the hidden and output layers) in the network.
The index j refers to different neurons in the ith layer, where 1 j ni , and ni is the neuron number of the
ith layer.
The index s refers to different neurons in the (i 1)th layer, where 1 s ni 1 + 1.
The index v refers to different neurons in the output layer, where 1 v nM .
The iteration index k refers to the kth training pattern (example) presented to the network.
The symbol wi js (k) denotes the synaptic weight connecting the output of neurons in the (i 1)th layer to
the input of neuron j in the ith layer at iteration k.
The learning-rate parameter of the weight wi js (k) at iteration k with respect to the vth output error is
denoted by i jsv (k).
The symbol ev (k) refers to the error signal between the target output and the actual output at the output
of neuron v in the output layer at iteration k.
The symbol hi jsv (k) denotes the derivative of the output error ev (k) at iteration k with respect to the weight
wi js (k 1) at iteration k 1.
The symbol pi js (k) denotes the variance of the estimated weight wi js (k) at iteration k.
The symbol av (k) refers to the central adjustment parameters for the output of neuron v in the output
layer at iteration k.
Suppose the network output is corrupted by a Gaussian noise {nv (k)} at iteration k. Then the symbol rv
(k) denotes the variance of {nv (k)}.
The symbol y(k) refers to the target output of the network, N(w(k 1), u(k)) refers to the actual output of
the network, its weight matrix is w(k 1) at iteration k1, and the network input at iteration k is u(k).
The training mechanism can be described by the following:

24

NONLINEAR SYSTEM REPRESENTATION

where Cum3 [] denotes the third-order cumulant operation

with

where pp is the sample number.

A number of network initialization procedures have been developed for general feedforward networks
(25,26). These algorithms are based on linear-algebraic methods to determine the optimal initial weights. With
the optimal initial weights, the initial network error is much smaller, thus speeding up the overall training
procedure (25,26). In this article, a conventional randomized-weight initialization procedure is presented:
(1) Weights are initialized as random numbers with normal distribution, typically in the range of 0.1.
(2) We initialize the matrices Pi (k):{pi js (k)} and R(k):{rv (k)} as Pi (0) = 100.0I and R(0) = I, where I refers to
the unit matrix.
Thereafter, the CWDEKF algorithm can be applied to train the neural network on which the nonlinear
representation is based.
A recurrent neural network differs from a multilayer feedforward neural network in that it has at least
one feedback loop, which represents the dynamical characteristics of the network. For example, a recurrent
network may consist of a single layer of neurons with each neuron feeding its output signals back to the inputs
of all the other neurons. In this structure, there are no self-feedback loops in the network. Self-feedback refers
to a situation where the output of a neuron is fed back to its own input. The feedback connections originate from
the hidden neurons as well as the output neurons. The presence of feedback loops has a profound influence on
the learning capability of the network and on its dynamical performance. Moreover, the feedback loops involve
the use of special branches composed of unit-delay elements, which result in nonlinear dynamical behavior by

NONLINEAR SYSTEM REPRESENTATION

25

virtue of the nonlinear nature of the neurons. Nonlinear dynamics plays a key role in the storage function of a
recurrent network.
The Hopfield network is a typical recurrent network that is well known for its capability of storing information in a dynamically stable configuration. It was Hopfields paper (27) in 1982, elaborating the remarkable
physical capacity for storing information in a dynamically stable network, that sparked off the research on
neural networks on the eighties. One of the most fascinating findings of his paper is the realization of the
associative memory properties. This has now become immensely useful for pattern recognition.
Physically, the Hopfield network operates in an unsupervised fashion. Thus, it may be used as a contentaddressable memory or as a computer for solving optimization problems of a combinatorial kind. The classical
traveling-salesman problem is a typical example. Koch applied Hopfield networks to the problem of vision.
There has been other work on depth computation and on reconstructing and smoothing images.
In tackling a combinatorial optimization problem we are facing a discrete system that has an extremely
large but finite number of possible solutions. The task is to find one of the optimal solutions through minimizing
a cost function, which provides a measure of system performance. The Hopfield network requires time to
converge to an equilibrium condition. The time required depends on the problem size and the possible stability
problem. Hence it is never used online unless special-purpose hardware is available for its implementation.
The operational procedure for the Hopfield network may be summarized as follows:
(1) Storage (Learning) Let 1 , 2 ,. . .,p denote a known set of N-dimensional memories. Construct the network
by using the outer-product rule to compute the synaptic weights of the network as

where wji is the synaptic weight from neuron i to neuron j. The elements of the vector equal 1. Once
they are determined, the synaptic weights are kept fixed.
(2) Initialization Let X denote an unknown N-dimensional input vector presented to the network. The algorithm is initialized by setting

where sj (0) is the state of neuron j at time n = 0, and xj is the jth element of the vector X.
(3) Iteration until Convergence Update the elements of the state vector sj (n) asynchronously (i.e., randomly
and one at a time) according to the rule

Repeat until the state vector s remains unchanged.

(4) Outputting Let sf denote the fixed point (stable state) computed at the end of step 3. The resulting output
vector y of the network is

26

NONLINEAR SYSTEM REPRESENTATION

It is clear that a neural network is a massively parallel-distributed network that has a natural capacity
for storing experimental knowledge and making it available for use.
The primary characteristics of knowledge representation are twofold: (1) what information is actually
made explicit, and (2) how the information is physically encoded. In real-world applications of intelligent
machines, neural networks represent a special and versatile class of modeling techniques that are significantly different from conventional mathematical models. Neural networks also offer a convenient and reliable
approach for the modeling of highly nonlinear multiinput multioutput systems.

Model-Free Representation
The traditional qualitative modeling techniques discussed above focus on means for abstracting the value
spaces of variables that are used to represent system inputoutput relationships as well as system states and
for simplifying the constraints that hold among the values of those variables. It is obvious that no general
nonlinear representations exist for modeling an arbitrary nonlinear system. The approximation accuracy of
a nonlinear model depends on what physical system is modeled and what type of model is used. In some
cases, where all possible nonlinear models are found to be unsuitable, model-free representations for nonlinear
systems will be a better alternative. Rather than a model-based methodology, a flexible model-free technique
based on signal processing provides a set of enhanced, sensitive, and definitive characterizations of nonlinear
systems. Higher-order statistics have been found to be useful in such analyses (28).
Given an arbitrary real, stationary random signal {y(t)} at the discrete times t = 0, 1, 2,. . ., its secondorder moment (SOM) M y 2 (m) and third-order moment (TOM) M y 3 (m, n) provide a measure of how the sequence
is correlated with itself at different time points:

where m is the time lag; m, n = 0, 1, 2,. . .; and E[] denotes statistical expectation.
Third-Order Cumulant in Time Domain
For the random signal {y(t)}, its third-order cumulant (TOC) Cy 3 (m, n) is given by

Note that the SOM M y 2 (m) in Eq. (90) is a symmetric function about m = 0, that is, M y 2 (m) = M y 2 (m).
Hence, M y 2 (m) is a zero-phase function, which means that all phase information about y(t) is lost in M y 2 (m).
With regard to the TOC Cy 3 (m, n), important symmetry conditions follow from the properties of SOM and

NONLINEAR SYSTEM REPRESENTATION

27

TOM and Eq. (92):

Thus Cy 3 (m, n) is a phase-bearing function, and knowing the TOC in any of the six sectors delimited by Eq.
(93) would enable us to find it everywhere.
If {y(t)} is corrupted by an independent Gaussian measurement noise {v(t)}, then the SOM, TOM, and
TOC of the noisy random sequence {x(t) = y(t)+v(t)} are found to be

which means that the TOC is blind to any kind of a Gaussian process, whereas the SOM and TOM are not.
The TOC, on the other hand, can be used to deal with quadratic phase-coupling phenomena. Suppose

where y1 (t) is the phase-decoupled component and y2 (t) the phase-coupled component. Then only the second
component appears in the TOC of y(t), that is,

where f stands for a nonlinear relationship between the TOC and the phase-coupled component. The fact that
only phase-coupled components contribute to the TOC of a random process is what makes the TOC a useful
tool for detecting quadratic phase coupling and discriminating phase-coupling components from those that are
not.
Bispectrum in the Frequency Domain. According to its definition, the bispectrum Cy 3 (f 1 , f 2 ) of the
random signal {y(t)} is defined as its two-dimensional Fourier transform:

where |f 1 |, < , |f 2 | < , |f 1 + f 2 | < . In general, Cy 3 (f 1 , f 2 ) is complex, that is, it has magnitude and phase:

28

NONLINEAR SYSTEM REPRESENTATION

It is clear from Eqs. (99) and (100) that the bispectrum is periodic with period 2, and preserves both the
magnitude and phase information associated with the random sequence {y(t)}. Thus, it provides one easy way
to extract useful information directly, in contrast with complicated nonlinear models.
In view of the filtering nature of the TOC in Eq. (96), one can obtain that

Bearing Eq. (98) in mind, the bispectrum of y(t) can be easily obtained as

where g stands for a nonlinear relationship between the bispectrum and the phase-coupled component.
The above discussion has shown that the TOC and bispectrum statistical measures provide an enhanced
system characterization capability over conventional second-order measures. As a result, model-free TOC- and
bispectrum-based analysis techniques are particularly suitable for extracting internal chararacteristics of a
nonlinear system.

Features of Nonlinear Representations

Identiability. Identifiability is a concept that is central in system identification problems. Loosely
speaking, the problem is whether the system modeling procedure will yield a unique value of the parameter
and whether the resulting model is faithful to the true system. The issue involves whether the measured data
set is informative enough to distinguish between different models as well as properties of the model structure
itself: If the data are informative enough to distinguish between unequal models, then the question is whether
different values of parameters can give equal models. Depending on the availability of system information, the
corresponding models can be distinguished as: (1) gray-box models, whose structures are known on physical
grounds but that have certain of parameters to be estimated from observed data; and (2) black-box models,
whose structures as well as parameters are totally unavailable. In the following, we define different kinds of
identifiability corresponding to different models.
Definition 1. A gray-box model (y(t), u(t), ), where the observed inputoutput pair {y(t), u(t)} is given, is
internally identifiable at parameter vector if (y(t), u(t), ) = (y(t), u(t), ),  , leads to = , where
comprises the true parameters of the model, and their estimates. A gray-box model (y(t), u(t), ) is globally
internally identifiable if it is internally identifiable at almost all  . Moreover, the gray model (y(t), u(t),
) is blindly internally identifiable if its input u(t) is unknown.
Definition 2. A black-box model (y(t), u(t)), where the observed inputoutput pair {y(t), u(t)} is given, is
externally identifiable if there exists a determined model structure and parameters such that (y(t), u(t))
= (y(t), u(t), ),  . A black-box model (y(t), u(t)) is globally externally identifiable if it is externally
identifiable at almost all u u , y y .
A nonlinear differential algebraic representation (7) and a state-space representation (46) are globally
internally identifiable if and only if one can obtain differential equations in the form

NONLINEAR SYSTEM REPRESENTATION

29

where i=1, 2, ,. . ., n, by differentiating, adding, scaling and multiplying the equations (7) and (46). Then the
identification algorithm gives the parameter estimate (29)

As a special case of Eq. (46), a bilinear model (49) is internally identifiable if the above condition (103) is
satisfied.
For the Volterra representation, it should be pointed out, there is no general identifiability principle.
However, if we consider the finite-support Volterra model (34) excited by a zero-mean Gaussian signal, then
the model is globally internally identifiable if and only if the power spectral process of the input signal is
nonzero at at least t distinct frequencies (30). Moreover, if we consider the finite-support second-order Volterra
model (37) excited by an unknown arbitrary zero-mean independent and identically distributed (i.i.d.) random
signal, then the model is of blind internal identifiability if and only if the following equation has a unique
solution (24):

and

where

30

NONLINEAR SYSTEM REPRESENTATION

and

where Cy 3 (m,n) is the TOC of the output signal y(t) defined in Eq. (92), and iu , i=2, 3, 4, 6, is the ith-order
autocorrelation of the input u(t). Clearly, one must estimate the (q + 1)2 TOCs Cy 3 (m,n) for 0 m,n q, and

then invert the equations to solve for the unknown quantities h(i,j).
This inversion involves solving (q + 1)2
2
simultaneous cubic equations with (q + 1) unknowns. The parameter-coupled terms in Eq. (105) are of high
complexity, and conventional model-based estimation theories cannot directly applied. However, the following
theorem provides a possible way to estimate the model parameters based on neural networks:

NONLINEAR SYSTEM REPRESENTATION

31

Let (m,n) Mp and H ij Hq , where H ij =[h(0,0) h(0,1) h(0,q) h(q,0) h(q,1) h(q,q)] be
open. Let g be continuous on M H. Consider the equation (105).
Theorem 3. Let DHij g(H ij , (m, n)) be nonsingular for H ij , H and (m, n) M. Given the class of neural
networks, N, that map p q to q , there exist 1 ,2 > 0 and a neural network NN N such that, given >
0,

where = {(Cy 3 (m,n), (m,n)) : |Cy 3 (m,n) g(H ij ,(m, n))|< 1 ,|(m,n) (m, n)| < 2 }.
As far as the identifiability of NARMA models is concerned, Eqs. (103) and (104) are also suitable, because
a NARMA model is a special type of nonlinear differential algebraic representation and can be characterized
by a state-space representation. On the other hand, relying on the approximation capabilities of multilayer
neural networks, the functions  in Eq. (65) can be approximated by a neural network with appropriate input
and output dimensions. This can be stated as the following theorem (31).
Theorem 4. For generic , the inputoutput behavior of the NARMA model (65) is externally identifiable
with arbitrary precision by a multilayer feedforward neural-network-based inputoutput model of the form

where NN() is a multilayer feedforward neural network with 2l inputs and one output characterizing the
monitored nonlinear system. Here l is the order of the model.
An important problem faced herein is the choice of the most suitable network topology to perform the
identification and modeling of unknown nonlinear dynamic systems efficiently. It mainly lies in the choice
of the optimal number of neurons for each of the networks employed, which plays a crucial role in network
performance. Considering the external identifiability of fuzzy-logic models, the following theorem shows that
the fuzzy-logic models with fuzzifier and defuzzifier are capable of uniformly approximating any nonlinear
function over U to any degree of accuracy if U is compact (32).
Theorem 5. For any given real continuous function g on a compact set U n and arbitrary > 0, there
exists a fuzzy-logic model f such that

This theorem provides a justification for applying the fuzzy-logic representations to almost any nonlinear modeling problem. It also provides an explanation for the practical success of the fuzzy logic models in
engineering applications.
Some nonlinear systems are very difficult, if not impossible, to describe with analytical equations. Hence,
there is a great need to develop a robust and less model-dependent methodology for the representation of a complex nonlinear dynamic system. To avoid the difficulties of the classical nonlinear-system modeling approach,

32

NONLINEAR SYSTEM REPRESENTATION

neural-network-based modeling methods for nonlinear systems have been proposed recently. The main motivation is that any nonlinear relationship can be approximated by a neural network given suitable weighting
factors and architecture. Another important property of such networks is their self-learning ability: a neural
network can extract the system features from previous training data through learning, whilst requiring little
or no a priori knowledge about the system. This provides great flexibility for modeling general nonlinear physical systems and guarantees robust external identifiability of neural-network-based system representations. A
multilayer network trained with the CWDEKF algorithm may be viewed as a practical vehicle for performing
general nonlinear inputoutput mapping, due to the following universal approximation theorem (23,33).
Theorem 6. Let () be a nonconstant, bounded, and monotone-increasing continuous function. Let Ip denote
the p-dimensional unit hypercube [0,1]p . The space of continuous functions on Ip is denoted by C(Ip ). Then,
given any function f C(Ip ) and > 0, there exist an integer M and sets of real constants j , i , and wij , where
i=1, 2, . . ., M and j=1, 2, . . ., p, such that we may define

as an approximate realization of the function f (); that is, |F(x1 , x2 , . . ., xp ) f (x1 , x2 , . . ., xp )| < for all (x1 , x2 ,
. . ., xp ) Ip .
This theorem is directly applicable to multilayer networks. We first note that the logistic function used
as the nonlinearity in a neuron node for the construction of a multilayer network is indeed a nonconstant,
bounded, and monotone-increasing function. It therefore satisfies the conditions imposed on the function ().
Next, we note that the above equation represents the output of a multilayer network described as follows: (1)
the network has p point nodes and a single hidden layer consisting of M neurons; the inputs are denoted by
(x1 , x2 , . . ., xp ); (2) hidden neuron i has synaptic weights (wi1 , W i2 ,. . ., wip ) and threshold i ; and (3) the network
output is a linear combination of the outputs of the hidden neurons, with (1 , 2 , . . . M ) as coefficients.
The universal approximation theorem 6 is an existence theorem in the sense that it provides the mathematical justification for the approximation of an arbitrary continuous function as opposed to exact representation.
Controllability. Controllability is one of the most important properties of systems modeled by statespace representations. A state-space model in Eq. (46) is said to be controllable if an available input u(t)
is sufficient to bring the model from any initial state x(0) to any desired final state x(t). The importance of
controllability in the formulation of the control problems for linear systems is evident. A linear time-invariant
system x (t) = Ax(t) + Bu(t) is completely controllable if and only if the matrix E = [B AB An 1 B] has rank
n, where x(t) n , u(t) m .
In spite of many attempts to characterize controllability for nonlinear systems, similar generic results to
those available for linear systems do not exist for nonlinear systems. Hence, the choice of controller models for
nonlinear systems is a formidable problem, and successful control has to depend on several strong assumptions
regarding the inputoutput behavior of the systems. For example, we consider the specified (affine) nonlinear
model of the form

where x(t) = [x1 ,x2 , . . ., xn ]T is the local coordinate on a smooth n-dimensional manifold M, the control u(t) is a
scalar piecewise smooth function, and f (x, t), g(x, t) are the local coordinate representations of smooth vector

NONLINEAR SYSTEM REPRESENTATION

33

fields globally defined on M. The model (110) is locally controllable at an equilibrium point xe of f () if [B, AB,
. . ., An 1 B] has full rank, where B = g(xe ) and A = f (xe )/x (36).
On the other hand, the variable structure of bilinear systems allows them to be more controllable than
linear systems, just as it frequently provides for a more accurate model. Let us consider the bilinear system
given by Eq. (49). It is assumed that the class of admissible inputs u(t) is the class of all piecewise continuous
vector time functions with [0, ) and range U, where U is a compact connected set containing the origin in
m . The reachable zone from an initial state x0 , R(x0 ) n , is the set of all states to which the system can be
transferred in finite time, starting at x0 . Similarly, the incident zone to a terminal state xf , I(xf ) n , is the set
of all initial states from which xf is reachable in finite time.
For each fixed x U, the bilinear system is a constant-parameter linear system with system matrix F +
m i = 1 N i ui . The term m i = 1 N i ui in the system matrix permits manipulation of the eigenvalues of the fixedcontrol system. With an appropriate controller it is often possible to shift these eigenvalues from the left half
of the complex plane to the right half. The controllability analysis presented here can be summarized by the
following sufficient conditions (5):
Theorem 7. The bilinear system (49) is completely controllable if: (1) there exist input values u+ and u such
that the real parts of the eigenvalues of the system matrix are positive and negative, respectively, and such
that equilibrium states xe (u+ ) and xe (u ) are contained in a connected component of the equilibrium set, and
(2) for each x in the equilibrium set with an equilibrium input ue (x) U such that f (x, ue (x)) = 0, there exists a
v Rm such that g lies in no invariant subspace of dimensional at most n 1 of the matrix E, where

As one might expect, the conditions given by the above theorem are not as simple as the popular conditions
for complete controllability of linear systems. For phase-variable systems, x1 = x, x2 = a , . . ., xn = x(n 1) , condition
(2) is always satisfied if G is a nonzero matrix. Condition (2) is satisfied if all the eigenvalues of the system
matrix F + m i = 1 N i ui can be shifted across the imaginary axis of the complex plane without passing through
zero, as u ranges continuously over a subset of U.
Observability. A nonlinear state-space model is said to be observable if, given any two states x1 , x2 ,
there exists an input sequence of finite length, ul = [u(0), u(1),. . ., u(l)]T , such that yl (x1 , ul ) = yl (x2 , ul ), where
yl is the output sequence. The ability to effectively estimate the state of a model or to identify it based on
inputoutput observations is determined by the observability properties of the model.
Observability has been extensively studied in the context of linear systems and is now part of the standard
control literature. An nth-order single-input and single-output time-invariant linear system is described by
the set of equations

34

NONLINEAR SYSTEM REPRESENTATION

where x(t) n , u(t) , y(t) , A is an n n matrix, and B, C are n-dimensional vectors. A basic result in
linear control theory states that the above system will be observable if and only if the n n matrix M = [C CA
CAn 1 ]T is of rank n. M is called the observability matrix.
If the system (112) is observable and [CB CAB CAd 2 B]T = 0, but CAd 1 B = 0, then we have y(t +
d) = CAd x(t) + CAd 1 Bu(t). This implies that the input at any instant t can affect the output only d instants
later, where d denotes the delay in the propagation of the signals through the system and is called the relative
degree of the system.
Observability of a linear system is a system-theoretic property and remains unchanged even when inputs
are present, provided they are known. For an observable linear system of order n, any input sequence of length
n will distinguish any state from any other state. If two states are not distinguishable by this randomly chosen
input, they cannot be distinguished by any other input sequence. In that case, the inputoutput behavior of
the system can be realized by an observable system of lower dimension, where each state in the new system
represents an equivalence class that corresponds to a set of states that could not be distinguished in the old
one.
Whereas a single definition is found to be adequate for linear time-invariant systems, the concept of
observability is considerably more involved for nonlinear systems. A desirable situation would be if any input
sequence of length l sufficed to determine the state uniquely, for some integer l. This form of observability
will be referred to as strong observability. It readily follows that any observable linear system is strongly
observable with l = n, n being the order of the system. A less restrictive form of observability is the notion of
generic observability. A system of the form (46) is said to be generically observable if there exists an integer l
such that almost any input sequence of length greater or equal to l will uniquely determine the state.
Now let us look at the observability of nonlinear systems using Eq. (46). This problem arises when the
laws governing the system are known but the states of the system are not accessible or only partly accessible.
By definition, complete knowledge of the states will enable accurate prediction of the systems behavior. Thus
the observation problem in this case actually reduces to the estimation of the state based on input and output
observations over a time interval [t0 , t0 + l], or in other words establishing an observer. Sufficient conditions for
strong local observability of a system (46) around the origin can be derived from the observability properties of
its linearization at the origin:

where A = f x |0,0 , B = f u |0,0 , C = gx |0 are the systems Jacobian matrices. This is summarized by the following
theorem (33).
Theorem 8. Let  be nonlinear system (45), and l its linearization around the equilibrium as given in Eq.
(113). If l is observable, then  is locally strongly observable.
A bilinear model (49) or (50) is called observable if there are no indistinguishable states in the model.
Theorem 9 gives a necessary and sufficient condition for observability of bilinear models (8).
Theorem 9. The bilinear model described in Eq. (49) or (50) is observable if and only if rank Qn = n, where
Qn = [q1 , q2 , . . ., qn ]T , q1 = C, qi = [qi 1 F qi 1 N i ]T , i = 2, 3, . . ., n.

NONLINEAR SYSTEM REPRESENTATION

35

Example
This example shows how a neural network together with a nonlinear model approach is used for short-term
electric load forecasting (34). This neural-network model utilizes the full dynamic range of the neural network
and is a nonlinear model for nonstationary time series. The model is used to provide hourly load forecasts one
day ahead. Off-line simulation has been done on the Hong Kong Island electric load profile provided by the
Statistics and Planning Division of Hong Kong Electric Company Limited.
The electric load forecast models can be summarized in the following two equations: for a static model
(feedforward neural network),

and for a dynamical model (recurrent neural network),

where xt is the load consumption, w

t+l is the weather forecast, wt is the weather information, and et is a noise
residual at time t. The nonlinear function h is nonlinearly approximated by ANN. From the above models, the
load forecast x t+l is estimated mainly from the currently available load profile.
In general, a linear time series {xt } can be written in the form of an ARMA model as

where B is the backward shift operator, and the autoregressive operator (B) of order p is given by

The moving-average operator (B) of order q is defined by

where the white noise et with finite variance 2 is zero-mean, i.i.d., and independent of past xt . Equation (114)
can be rewritten in the form

If the roots of the equation

lie outside the unit circle, the time series {xt } is stationary; otherwise {xt } is nonstationary. For linear nonstationary time series {xt }, the ARMA model for stationary time series can still be used, but the above ARMA

36

NONLINEAR SYSTEM REPRESENTATION

model (115) has to be reformulated as

or

where d xt = (1 Bd )xt = xt xt d and i = i + i+d . The model 116a is the so-called ARIMA model. A
natural generalization of the linear ARIMA model to the nonlinear case would be the nonlinear autoregressive
integrated moving average (NARIMA) model, which is given by

or

where h is an unknown smooth function and, as in Eq. (114), it is assumed that the white noise et with variance
2 is zero-mean, i.i.d, and independent of past xt . The minimum-mean-squared-error optimal predictor of xt
given xt 1 , . . ., xt r is the conditional expectation

This predictor has mean squared error 2 . In this work, a nonlinear autoregressive integrated (NARI) model,
the special case of the NARIMA, is considered and is defined by

or

We focus on a multilayer feedforward neural network (FNN) and how it may be used to forecast the
hourly load consumption of the coming day. In many time-series predictions, the time-series model is based on
nonlinear autoregressive (NAR) models of the form

NONLINEAR SYSTEM REPRESENTATION

37

The neural STLF model can be considered as a modified NAR model given by

and the unknown smooth function h is nonlinearly approximated by a FNN. Hence, the neural optimal predictor
is given by

where 0 l 24 and the function is a smooth bounded monotonic function, tanh(0.5x). The vector wt of m
components contains the available weather information at time t. The parameters W 0 ij , W 0 ik , and W 1 i are the
neural-network weights.
To obtain an accurate load forecast, we should identify the most appropriate model in accordance with
the nature of load consumption. In this example, the modified NARI model in Eq. (118b) is proposed for
STLF. Several important weather factors are also included, because weather variation is one of the crucial
disturbances to electric load demand. Consequently, the modified NARI model for STLF is given by

and the neural optimal predictor is then formulated by

where 0 l 24. The weather information vector wt contains four components, namely, temperature, relative
humidity, level of rainfall, and level of sunshine.
The architecture of our proposed neural network model is illustrated in Fig. 9(b). The structure of the
modified NAR model for STLF is depicted in Fig. 9(a). This type of NARI neural-network model is called a
weather compensation neural network because the weather-dependent component will be only determined
from the weather information and load consumption of the previous day.
The characteristics of electric load consumption gradually change because of many uncontrollable factors. Our weather compensation neural network (NARI model), without keeping track of the change of load
characteristic, will degrade in forecasting performance over the years. An adaptive tracking scheme is therefore proposed so that the weather compensation neural network will be retrained every day. This scheme can
efficiently update the neural network to adapt to the changing conditions of the environment. Different sizes
of window of the trained set have been studied. The size of the window determines the memory of past knowledge. Too small a window may produce catastrophic loss of information that severely degrades the forecasting
performance and robustness. Three different sizes10 days, 20 days, and 136 daysare examined. Updating
is omitted when the standard deviation of the forecast error is less than 990 MW. The results are depicted in
Fig. 10, and they show that the neural network provides the most robust forecasting when the window size of
136 days is used. Figure 11 displays a comparison of the actual load and the load forecast for seven consecutive
working days using our proposed NARI neural network and adaptive tracking scheme. Figures 12 and 13

38

NONLINEAR SYSTEM REPRESENTATION

Fig. 9. (a) The architecture of modified NAR model for neural short-term load forecasting. (b) The architecture of the
weather compensation neural network (modified NARI model).

display a comparison of the actual load and the load forecast for the worst cases using the NAR and the NARI
neural network, respectively.

NONLINEAR SYSTEM REPRESENTATION

Fig. 10.

39

Comparison of percentage error for different sizes of moving window using the neural-network NARI model.

Fig. 11. Comparison of actual load and load forecast using neural network NARI model (136-day window) for seven
consecutive working days.

Concluding Remarks
Nonlinear system representations are classified by a simple dichotomy: a system is represented either linearly
or nonlinearly. The number and variety of nonlinear representations is almost limitless, and one does not
find the complete and elegant theory that exists for linear representations. It would be expecting too much if
one hoped to find a universal analytical technique applicable to any nonlinear system representation with an
arbitrary input signal.
In this article, we have discussed several nonlinear representations and their important features such
as identifiability, controllability, and observability. These representations are widely used in signal processing,

40

NONLINEAR SYSTEM REPRESENTATION

Fig. 12.

Comparison of the actual load and the load forecast using the neural-network NAR model (worst case).

Fig. 13. Comparison of the actual load and the load forecast using the neural network NARI model with 136-day window
(worst case).

circuit systems, control systems, and communication systems. A comparison of these representations is given
in Table 1. It can be seen that, with different types of input signal, different nonlinear representations should
be selected. When internal identifiability is important, Volterra, state-space, and bilinear representations are
the better choices, due to the linear parameter relationship of the Volterra system and the compact description
of the state-space and bilinear systems. For external identifiability, fuzzy logic and neural-network-based
representations often appear to be useful for characterizing nonlinear systems in a black-box approach.

NONLINEAR SYSTEM REPRESENTATION

41

On the other hand, a state-space representation can be used to guarantee high controllability and observability, since the corresponding theories in the linear domain can be extended to the nonlinear world. For
system inversion, no one representation is the best, due to the complexity of the problem; but suboptimal
alternatives may be obtained with Volterra, state-space, or bilinear representations.

Acknowledgment
The authors would like to thank the Hong Kong Electric Company Limited for providing the electric load data
and weather information for this part of work.

BIBLIOGRAPHY
1. D. E. Thompson Design Analysis: Mathematical Modeling of Nonlinear Systems, New York: Cambridge Univ. Press,
1999.
2. M. Vidyasagar Nonlinear Systems Analysis, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1993.
3. A. J. Fossard D. Normand-Cyrot Nonlinear Systems, Modeling and Estimation, London: Chapman & Hall, 1995.

42
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.

NONLINEAR SYSTEM REPRESENTATION

M. Schetzen The Volterra and Wiener Theories of Nonlinear Systems, New York: Wiley, 1980.
J. L. Casti Nonlinear System Theory, Orlando, FL: Academic Press, 1985.
P. G. Drazin Nonlinear Systems, New York: Cambridge Univ. Press, 1992.
J. S. Bendat A. G. Piersol Engineering Applications of Correlation and Spectral Analysis, New York: Wiley, 1993.
R. R. Mohler Bilinear Control Processes, New York: Academic Press, 1973.
P. N. Paraskevopoulos A. S. Tsirikos K. G. Arvanitis A new orthogonal series approach to state space analysis of bilinear
systems, IEEE Trans. Automat. Control, 39: 793797, 1994.
S. Chen S. A. Billings Representation of nonlinear systems: the NARMA model, Int. J. Control, 49(3): 10131032, 1989.
I. J. Leontaritis S. A. Billings Inputoutput parametric models for non-linear systems, part I: deterministic non-linear
systems, Int. J. Control, 41(2): 303328, 1985.
E. D. Sontag Realization theory of discrete-time nonlinear systems: Part Ithe bounded case, IEEE Trans. Circuits
Syst. 26: 342356, 1979.
L. Zadeh Fuzzy sets, Inf. Control, 8: 338353.
C. C. Lee Fuzzy logic in control systems: fuzzy logic controller, part I, IEEE Trans. Syst. Man Cybern., SMC-20: 404418,
1990.
C. C. Lee Fuzzy logic in control systems: fuzzy logic controller, part II, IEEE Trans. Syst. Man Cybern., SMC-20:
419435, 1990.
T. Takagi M. Sugeno Fuzzy identification of systems and its applications to modeling and control, IEEE Trans. Syst.
Man Cybern., 15: 116132, 1985.
E. H. Mamdani Applications of fuzzy algorithms for simple dynamic plant, Proc. IEE, 121(12): 15851588, 1974.
C. J. Harris C. G. Moore M. Brown Intelligent Control: Some Aspects of Fuzzy Logic and Neural Networks, London and
Singapore: World Scientific Press, 1993.
B. H. Wang G. Vachtsevanos Learning fuzzy logic control: an indirect control approach, Proc. IEEE Int. Conf. on Fuzzy
Systems, San Diego, CA, 1992, pp. 297304.
T. J. Ross Fuzzy Logic with Engineering Applications, New York: McGraw-Hill, 1995, Chapter 13.
J. Y. Li T. W. S. Chow Functional approximation of higher-order neural networks, J. Intell. Syst., 6(34): 239260, 1996.
J. J. Hopfield Learning algorithm and probability distributions in feed-forward and feed-back networks, Proc. Nat.
Acad. Sci. U.S.A., 84, 84298433, 1987.
K. Hornik M. Stinchcombe H. White Multilayer feedforward networks are universal Approximators, Neural Netw., 2:
359366, 1989.
H.-Z. Tan T. W. S. Chow Blind identification of quadratic nonlinear models using neural networks with higher-order
cumulants, IEEE Trans. Ind. Electron., 47: 687696 2000.
J. Y. F. Yam T. W. S. Chow A weight initialization method for improving training speed in feedforward neural network,
Neurocomputing, 30(14): 219232, 1999.
J. Y. F. Yam T. W. S. Chow C. T. Leung A new method in determining initial weights of feedforward neural networks for
training enhancement, Neurocomputing, 16(1): 2332, 1997.
J. J. Hopfield Neural networks and physical systems with emergent collective properties, Proc. Nat. Acad. Sci. U.S.A.,
79: 25542558, 1982.
C. L. Nikias A. P. Petropuop Higher-Order Spectra Analysis: A Non-linear Signal Processing Framework, Englewood
Cliffs, NJ: Prentice-Hall, 1993.
L. Ljung System Identification: Theory for the User, 2nd ed., Upper Saddle River, NJ: Prentice-Hall, 1999.
G. A. Glentis P. Koukoulas N. Kalouptsidis Efficient algorithm for Volterra system identification, IEEE Trans. Signal
Process., 47: 30423057, 1999.
A. U. Levin K. S. Narendra Recursive identification using feedforward neural networks, Int. J. Control, 61(3): 533547,
1995.
L. X. Wang J. M. Mendel Fuzzy basis function, universal approximation, and orthogonal least squares learning, IEEE
Trans. Neural Netw., 3: 807814, 1992.
H.-Z. Tan Y. Fang T. W. S. Chow Wiener models identification based on the higher-order cumulants and orthogonal
wavelet neural networks, Int. J. Knowledge Based Intell. Eng. Syst., 3(2): 102107, 1999.
T. W. S. Chow C. T Leung A non-linear autoregressive intergrated neural network model for short-term load forecasting,
IEE Proc. Gener. Transm. Distrib., 143(5): 500506, 1996.

NONLINEAR SYSTEM REPRESENTATION

43

READING LIST
G. Anger Inverse Problems in Differential Equations, New York: Plenum, 1990.
B. Igelnik Y.-H. Pao Stochastic choice of basis functions in adaptive function approximation and the functional-link net,
IEEE Trans. Neural Netw., 6: 13201329, 1995.
W. J. Rough An extended linearization approach to nonlinear system inversion, IEEE Trans. Automat. Control, AC-31(8):
725733, 1986.
S. N. Singh A modified algorithm for invertibility in nonlinear systems, IEEE Trans. Automat. Control, 26: 595598, 1981.

TOMMY W. S. CHOW
City University of Hong Kong
HONG-ZHOU TAN
University of Manitoba
YONG FANG
Shanghai University

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

STABILITY OF NONLINEAR SYSTEMS

Stability of Nonlinear Systems
A nonlinear system refers to a set of nolinear equations (algebraic, difference, differential, integral, functional,
or abstract operator equations or a combination of some of these) used to describe a physical device or process
that otherwise cannot be well defined by a set of linear equations of any kind. Dynamical system is used as a
synonym for a mathematical or physical system when the describing equations represent evolution of a solution
with time and, sometimes, with control inputs and/or other varying parameters.
The theory of nonlinear dynamical systems, or nonlinear control systems if control inputs are involved,
has been greatly aanced since the nineteenth century. Today, nonlinear control systems are used to describe
a great variety of scientific and engineering phenomena ranging from the social, life, and physical sciences to
engineering and technology. This theory has been applied to a broad spectrum of problems in physics, chemistry,
mathematics, biology, medicine, economics, and various engineering disciplines.
Stability theory plays a central role in system engineering, especially in the field of control systems and
automation, with regard to both dynamics and control.
Stability of a dynamical system, with or without control and disturbance inputs, is a fundamental requirement for its practical value, particularly in real-world applications. Roughly speaking, stability means
that the system outputs and its internal signals are bounded within admissible limits (the so-called boundedinput bounded-output stability), or, sometimes more strictly, the system outputs tend to an equilibrium state of
interest (the so-called asymptotic stability). Conceptually, there are different kinds of stabilities, among which
three basic notions are the main concerns in nonlinear dynamics and control systems: the stability of a system
with respect to its equilibria, the orbital stability of a system output trajectory, and the structural stability of
a system itself.
The basic concept of stability emerged from the study of an equilibrium state of a mechanical system,
dating back to as early as 1644 when E. Torricelli studied the equilibrium of a rigid body under the natural
force of gravity. The classical stability theorem of G. Lagrange, formulated in 1788, is perhaps the best known
result about stability of conservative mechanical systems. It states that if the potential energy of a conservative
system, currently at the position of an isolated equilibrium and perhaps subject to some simple constraints,
has a minimum, then this equilibrium position of the system is stable (1). The evolution of the fundamental
concepts of system and trajectory stabilities then went through a long history, with many fruitful advances and
developments, until the celebrated Ph.D. Thesis of A. M. Lyapunov, The General Problem of Motion Stability,
summarized it all in 1892 (2). This monograph is so fundamental that its ideas and techniques are virtually
leading all basic research and applications regarding stabilities of dynamical systems today. In fact, not only
dynamical behavior analysis in modern physics but also controller design in engineering systems depend upon
the principles of Lyapunovs stability theory. This article is devoted to a brief description of the basic stability
theory, criteria, and methodologies of Lyapunov, as well as a few related important stability concepts, for
nonlinear dynamical systems.
1

STABILITY OF NONLINEAR SYSTEMS

Nonlinear System Preliminaries

Nonlinear Control Systems. A continuous-time nonlinear control system is generally described by a
differential equation of the form

where x = x(t) is the state of the system belonging to a (usually bounded) region
x Rn , u is the control
input vector belonging to another (usually bounded) region
u Rm (usually, m n ), and f is a Lipschitz or
continuously differentiable nonlinear function, so that the system has a unique solution for each admissible
control input and suitable initial condition x(t0 ) = x0
x . To indicate the time evolution and the dependence
on the initial state x0 , the trajectory (or orbit) of a system state, x(t), is sometimes denoted as t (x0 ) .
In the control system (1), the initial time used is t0 0, unless otherwise indicated. The entire space
Rn , to which the system states belong, is called the state space. Associated with the control system (1), there
usually is an observation or measurement equation

where y = y(t) Rl is the output of the system, 1 l n, and g is a continuous or smooth nonlinear function.
When both n, l > 1, the system is called a multi-input multi-output (MIMO) system, whereas if n = l = 1, it is
called a single-input single-output (SISO) system. The MISO and SIMO systems are similarly defined.
In a discrete-time setting, a nonlinear control system is described by a difference equation of the form

where all notation is similarly defined.

Most of the time in this article, only the control system in Eq. (1), or the first equation of Eq. (3), is
discussed. In this case, the system state x is also considered the system output for simplicity.
A special case of the system in Eq. (1), with or without control, is said to be autonomous if the time variable
t does not appear separately (independently) from the state vector in the system function f . For example, with
a state-feedback control u(t) = h(x(t)), this is often the situation. In this case, the system is usually written as

Otherwise, as Eq. (1) stands, the system is said to be nonautonomous. The same terminology may be
applied in the same way to discrete-time systems, although they may have different characteristics.
An equilibrium, or fixed point, of system (4), if it exists, is a solution x of Eq. (4) that satisfies the algebraic
equation

It then follows from Eqs. (4) and (5) that x = 0, which means that an equilibrium of a system must be a
constant state. For the discrete-time case, an equilibrium of system

STABILITY OF NONLINEAR SYSTEMS

is a solution, if it exists, of equation

An equilibrium is stable, if all the nearby trajectories of the system states, starting from various initial
states, approach it; it is unstable, if nearby trajectories move away from it. The concept of system stability with
respect to an equilibrium will be precisely introduced in section 3, entitled Lyapunov, Orbital, and Structural
Stabilities.
A control system is deterministic, if there is a unique consequence to every change of the system parameters or initial states. It is random or stochastic, if there is more than one possible consequence for a change
in its parameters or initial states according to some probability distribution (3). This article only deals with
deterministic systems.
Hyperbolic Equilibria and Their Manifolds. Consider the autonomous system in Eq. (4). The Jacobian of this system is defined by

Clearly, this is a matrix-valued function of time. If the Jacobian is evaluated at a constant state, say x or
x0 , then it becomes a constant matrix determined by f and x or x0 .
An equilibrium, x , of system in Eq. (4) is said to be hyperbolic, if all eigenvalues of the system Jacobian,
evaluated at this equilibrium, have nonzero real parts.
For a p-periodic solution of the system in Eq. (4), x (t), with a fundamental period p > 0, let J(x (t )) be its
Jacobian evaluated at x (t) . Then this Jacobian is also p-periodic:

In this case, there always exist a p-periodic nonsingular matrix M(t) and a constant matrix Q such that
the fundamental solution matrix associated with the Jacobian J(x (t)) is given by (4)

Here, the fundamental matrix (t) consists of, as its columns, n linearly independent solution vectors of the
linear equation x = J(x(t)) x, with x(t0 ) = x0 .
In the preceding discussion, the eigenvalues of the constant matrix epQ are called the Floquet multipliers of
the Jacobian. The p-periodic solution x (t) is called a hyperbolic periodic orbit of the system if all its corresponding
Floquet multipliers have nonzero real parts.
Next, let D be a neighborhood of an equilibrium, x , of the autonomous system in Eq. (4). A local stable
and local unstable manifold of x is defined by

and

STABILITY OF NONLINEAR SYSTEMS

Fig. 1.

Stable and unstable manifolds.

respectively. Furthermore, a stable and unstable manifold of x is defined by

and

respectively, where denotes the empty set. For example, the autonomous system

has a hyperbolic equilibrium (x , y ) = (0, 0) . The local stable and unstable manifolds of this equilibrium are
illustrated by Fig. 1(a), which is enlarged, and the corresponding stable and unstable manifolds are visualized
by Fig. 1(b).
A hyperbolic equilibrium only has stable and/or unstable manifolds because its associated Jacobian
only has stable and/or unstable eigenvalues. The dynamics of an autonomous system in a neighborhood of
a hyperbolic equilibrium is quite simple: it has either stable (convergent) or unstable (divergent) properties.
Therefore, complex dynamical behaviors such as chaos are usually not associated with isolated hyperbolic
equilibria or isolated hyperbolic periodic orbits (5 6,7) (also see Theorem 16); they generally are confined
within the so-called center manifold W c (x ), where dim(W s ) + dim(W c ) + dim(W u ) = n .
Open-Loop and Closed-Loop Systems. Let S be an MIMO system, which can be linear or nonlinear,
continuous-time or discrete-time, deterministic or stochastic, or any well-defined input-output map. Let U and
Y be the sets (sometimes, spaces) of the admissible input and corresponding output signals, respectively, both
defined on the time domain D = [a, b], a < b (for control systems, usually a = t0 = 0 and b = ).
This simple relation is described by an open-loop map

and its block diagram is shown in Fig. 2. Actually, every control system described by a differential or difference
equation can be viewed as a map in this form. But, in such a situation, the map S can only be defined implicitly
via the equation and initial conditions.
In the control system in Eq. (1), or (3), if the control inputs are functions of the state vectors, u = h(x;
t), then the control system can be implemented via a closed-loop configuration. A typical closed-loop system is

STABILITY OF NONLINEAR SYSTEMS

Fig. 2.

The block diagram of an open-loop system.

Fig. 3.

A typical closed-loop control system.

shown in Fig. 3, where usually S1 is the plant (described by f ) and S2 is the controller (described by h ); yet
they can be reversed.
Norms of Functions and Operators. This article only deals with finite-dimensional systems. For an
n-dimensional vector-valued function of the form x(t) = [x1 (t) xn (t)]T , let  and p denote its Euclidean
norm and Lp -norm, defined respectively by the length

and by

Here, a few remarks are in order:

(1) ess sup means essential supremum (i.e., the supremum except perhaps over a set of measure zero). For a
piecewise continuous function f (t), they are actually the same:

(2) The main difference between the sup and the max is that max |f (t)| is attainable but sup |f (t)| may not
be. For example, max0t< |sin(t)| = 1 but sup0t< |1 e t | = 1 .
(3) A difference between the Euclidean norm and the Lp -norms is that the former is a function of time but the
latter are all constants.

STABILITY OF NONLINEAR SYSTEMS

(4) For a finite-dimensional vector x(t), with n < , all the Lp -norms are equivalent in the sense that for any
p, q [1, ], there exist two positive constants and such that

For the input-output map in Eq. (13), the so-called operator norm of the map S is defined to be the
maximum gain from all possible inputs over the domain of the map to their corresponding outputs. More
precisely, the operator norm of the map S in Eq. (13) is defined by

where yi = S(ui ) Y, i = 1, 2, and 

sets (or spaces) U and Y, respectively.

and 

are the norms of the functions defined on the input-output

Lyapunov, Orbital, and Structural Stabilities

Three different types of stabilities, namely, the Lyapunov stability of a system with respect to its equilibria, the
orbital stability of a system output trajectory, and the structural stability of a system itself, are of fundamental
importance in the studies of nonlinear dynamics and control systems.
Roughly speaking, the Lyapunov stability of a system with respect to its equilibrium of interest is about the
behavior of the system outputs toward the equilibrium statewandering nearby and around the equilibrium
(stability in the sense of Lyapunov) or gradually approaching it (asymptotic stability); the orbital stability of
a system output is the resistance of the trajectory to small perturbations; the structural stability of a system
is the resistance of the system structure against small perturbations (1,8 9 10 11 12 13 14 15 16,17). These
three basic types of stabilities are introduced in this section for dynamical systems without explicitly involving
control inputs.
Consider the general nonautonomous system

where the control input u(t) = h(x(t),t), if it exists [see the system in Eq. (1)], has been combined into the
system function f for simplicity of discussion. Without loss of generality, assume that the origin x = 0 is the
system equilibrium of interest. Lyapunov stability theory concerns various stabilities of the system orbits with
respect to this equilibrium. When another equilibrium is discussed, the new equilibrium is first shifted to zero
by a change of variables, and then the transformed system is studied in the same way.
Stability in the Sense of Lyapunov. System in Eq. (15) is said to be stable in the sense of Lyapunov
with respect to the equilibrium x = 0, if for any  > 0 and any initial time t0 0, there is a constant, = (,
t0 ) > 0, such that

This stability is illustrated by Fig. 4.

STABILITY OF NONLINEAR SYSTEMS

Fig. 4.

Geometric meaning of stability in the sense of Lyapunov.

It should be emphasized that the constant generally depends on both  and t0 . It is particularly important
to point out that, unlike autonomous systems, one cannot simply fix the initial time t0 = 0 for a nonautonomous
system in a general discussion of its stability. For example, consider the following linear time-varying system
with a discontinuous coefficient:

It has an explicit solution

which is stable in the sense of Lyapunov about the equilibrium x = 0 over the entire time domain [ 0,
) if and only if t0 1 . This shows that the initial time t0 does play an important role in the stability of a
nonautonomous system.
The previously defined stability, in the sense of Lyapunov, is said to be uniform with respect to the initial
time, if the existing constant = () is indeed independent of t0 over the entire time interval [ 0, ). According
to this discussion, uniform stability is defined only for nonautonomous systems since it is not needed for
autonomous systems (for which it is always uniform with respect to the initial time).
Asymptotic and Exponential Stabilities. System in Eq. (15) is said to be asymptotically stable about
its equilibrium x = 0, if it is stable in the sense of Lyapunov and, furthermore, there exists a constant, =
(t0 ) > 0, such that

This stability is visualized by Fig. 5.

The asymptotic stability is said to be uniform, if the existing constant is independent of t0 over [ 0,
), and is said to be global, if the convergence, x 0, is independent of the initial state x(t0 ) over the entire
spatial domain on which the system is defined (e.g., when = ). If, furthermore,

STABILITY OF NONLINEAR SYSTEMS

Fig. 5.

Geometric meaning of the asymptotic stability.

Fig. 6.

Geometric meaning of the exponential stability.

for two positive constants c and , then the equilibrium is said to be exponentially stable. The exponential
stability is visualized by Fig. 6.
Clearly, exponential stability implies asymptotic stability, and asymptotic stability implies the stability in
the sense of Lyapunov, but the reverse need not be true. For illustration, if a system has output trajectory x1 (t)
= x0 sin (t), then it is stable in the sense of Lyapunov about 0, but it is not asymptotically stable. A system with
output trajectory x2 (t) = x0 (1 + t t0 ) 1 is asymptotically stable (so it is also stable in the sense of Lyapunov),
but it is not exponentially stable about 0. A system with output x3 (t) = x0 e t is exponentially stable (hence, it
is both asymptotically stable and stable in the sense of Lyapunov).
Orbital Stability. The orbital stability differs from the Lyapunov stabilities in that it is concerned with
the stability of a system output (or state) trajectory under small external perturbations.
Let t (x0 ) be a p-periodic solution, p > 0, of the autonomous system

and let represent the closed orbit of t (x0 ) in the state space, namely,

If, for any  > 0, there exists a constant = () > 0 such that for any x0 satisfying

STABILITY OF NONLINEAR SYSTEMS

Fig. 7.

Fig. 8.

Geometric meaning of the orbital stability.

Trajectories of three systems for comparison.

the solution of the system, t (x0 ), satisfies

then this p-periodic solution trajectory, t (x0 ), is said to be orbitally stable.

Orbital stability is visualized by Fig. 7. For a simple example, a stable periodic solution, particularly a
stable equilibrium of a system is orbitally stable. This is because all nearby trajectories approach it, and, as
such, it becomes a nearby orbit after a small perturbation and so will move back to its original position (or
stay nearby). On the contrary, unstable and semistable (saddle-type of) periodic orbits are orbitally unstable.
Orbital stability for nonperiodic solutions may also be defined.
Structural Stability. Two systems are said to be topologically orbitally equivalent, if there exists a
homeomorphism (i.e., a continuous map whose inverse exists and is also continuous) that transforms the
family of trajectories of the first system to that of the second while preserving their motion directions. Roughly,
this means that the geometrical pictures of the orbit families of the two systems are similar (no one has extra
knots, sharp corners, bifurcating branches, etc.). For instance,
systems x = x and x = 2x are topologically
orbitally equivalent, but they are not so between x = x and x = x . These three system trajectories are shown
in Fig. 8.
Return to the autonomous system in Eq. (19). If the dynamics of the system in the state space changes
radically, for example by the appearance of a new equilibrium or a new periodic orbit, due to small external
perturbations, then the system is considered to be structurally unstable.
To be more precise, consider the following set of functions:

10

STABILITY OF NONLINEAR SYSTEMS

If, for any g S, there exists an  > 0 such that the orbits of the two systems

are topologically orbitally equivalent, then the autonomous system in Eq. (19), namely, the first (unperturbed)
system above, is said to be structurally stable.
For example, x = x is structurally stable, but x = x2 is not, in a neighborhood of the origin. This is because,
2
when the second system isslightly perturbed,
to become say x = x + , where  > 0, then the resulting system

has two equilibria, x 1 = and x 2 = , which has more numbers of equilibria than the original system
that possesses only one, x = 0 .

Various Stability Theorems

Consider the general nonautonomous system

where f: D [0, ) Rn is continuously differentiable in a neighborhood of the origin, D Rn , with a given

initial state x0 D . Again, without loss of generality, assume that x = 0 is a system equilibrium of interest.
Lyapunov Stability Theorems. First, for the autonomous system in Eq. (19), an important special
case of Eq. (20), with a continuously differentiable f: D Rn , the following criterion of stability, called the first
(or indirect) method of Lyapunov, is very convenient to use.
Theorem 1 (First Method of Lyapunov, for Continuous-Time Autonomous Systems). In system
Eq. (19), let J = [f /x]x = x = 0 be the system Jacobian evaluated at the zero equilibrium. If all the eigenvalues
of J have negative real parts, then the system is asymptotically stable about x = 0 .
First, note that this and the following Lyapunov theorems also apply to linear systems because linear
systems are merely a special case of nonlinear systems. When f(x) = A x, the linear time-invariant system x =
A x has the only equilibrium x = 0 . If A has all eigenvalues with negative real parts, Theorem 1 implies that
the system is asymptotically stable about its equilibrium since the system Jacobian is simply J = A . This is
consistent with the familiar linear stability results.
Note also that the region of asymptotic stability given by Theorem 1 is local, which can be quite large
for some nonlinear systems but may be very small for some others. However, there is no general criterion for
determining the boundaries of such local stability regions when this and the following Lyapunov methods are
applied.
Moreover, it is important to note that this theorem cannot be applied to a general nonautonomous system,
since for general nonautonomous systems this theorem is neither necessary nor sufficient (18). A simple
counterexample is the following linear time-varying system (11,19):

This system has eigenvalues 1,2 = 0.25 j 0.25 7, both having negative real parts and being independent of the time variable t . If Theorem 1 is used to judge this system, the conclusion would be that the system

STABILITY OF NONLINEAR SYSTEMS

11

is asymptotically stable about its equilibrium 0. However, the solution of this system is

which is unstable, for any initial conditions with a bounded and nonzero value of x1 (t0 ), no matter how small
this initial value is. This example shows that by using the Lyapunov first method alone to determine the
stability of a general time-varying system, the conclusion can be wrong.
This type of counterexamples can be easily found (13). On the one hand, this demonstrates the necessity
of other general criteria for asymptotic stability of nonautonomous systems. On the other hand, however, a
word of caution is that these types of counterexamples do not completely rule out the possibility of applying
the first method of Lyapunov to some special nonautonomous systems in case studies. The reason is that there
is no theorem saying that the Lyapunov first method cannot be applied to all nonautonomous systems. Due
to the complexity of nonlinear dynamical systems, they often have to be studied class by class, or even case
by case. It has been widely experienced that the first method of Lyapunov does work for some, perhaps not
too many, specific nonautonomous systems in case studies (e.g., in the study of some chaotic systems (5); see
also Theorem 18). The point is that one has to be very careful when this method is applied to a particular
nonautonomous system; the stability conclusion must be verified by some other means at the same time.
Here, it is emphasized that a rigorous approach for asymptotic stability analysis of general nonautonomous
systems is provided by the second method of Lyapunov, for which the following set of class- functions are useful:

Theorem 2 (Second Method of Lyapunov, for Continuous-Time Nonautonomous Systems).

The system (20) is globally (over the entire domain D ), uniformly (with respect to the initial time over the
entire time interval [ t0 , )), and asymptotically stable about its zero equilibrium, if there exist a scalar-valued
function, V(x, t), defined on D [t0 , ], and three functions (), (), () , such that
(1)
(2)
(3)
(4)

V(0, t) = 0 for all t t0 ;

V(x, t) > 0 for all x = 0 in D and all t t0 ;
(x) V(x, t) (x) for all t t0 ;

V(x,
t) (x) < 0 for all t t0 .

In Theorem 2, the function V is called a Lyapunov function. The method of constructing a Lyapunov
function for stability determination is called the second (or direct) method of Lyapunov.
The geometric meaning of a Lyapunov function used for determining the system stability about the zero
equilibrium may be illustrated by Fig. 9. In this figure, assuming that a Lyapunov function V (x) has been
found, which has a bowl-shape as shown based on conditions i and ii. Then, condition iv is

where [ v/x ] is the gradient of V along the trajectory x . It is known, from calculus, that if the inner product of
this gradient and the tangent vector x is constantly negative, as guaranteed by the condition in Eq. (21), then
the angle between these two vectors is larger than 90 , so that the surface of V(x) is monotonically decreasing

12

STABILITY OF NONLINEAR SYSTEMS

Fig. 9.

Geometric meaning of the Lyapunov function.

to zero (this is visualized in Fig. 9). Consequently, the system trajectory x, the projection on the domain as
shown in Fig. 9, converges to zero as time evolves.
As an example, consider the following nonautonomous system:

where A is a stable constant matrix and g is a nonlinear function satisfying g (0, t) = 0 and g(x, t) c x
for a constant c > 0 for all t [t0 , ) . Since A is stable, the following Lyapunov equation

has a unique positive definite and symmetric matrix solution P . Using the Lyapunov function V (x, t) = xT P
x, it can be easily verified that

where max (P) is the largest eigenvalue of P . Therefore, if the constant c < 1/(2max (P)) and if the class-
functions

are used, then conditions iii and iv of Theorem 2 are satisfied. As a result, the system given here is globally,
uniformly, and asymptotically stable about its zero equilibrium. This example shows that the linear part of a
weakly nonlinear nonautonomous system can indeed dominate the stability.
Note that in Theorem 2, the uniform stability is guaranteed by the class- functions , , stated in
conditions iii and iv, which are necessary since the solution of a nonautonomous system may sensitively depend
on the initial time, as seen from the numerical example discussed earlier in the section entitled stability in
the sense of Lyapunov. For autonomous systems, these class- functions (hence, condition iii) are not needed.
In this case, Theorem 2 reduces to the following simple form.

STABILITY OF NONLINEAR SYSTEMS

13

Theorem 3 (Second Method of Lyapunov, for Continuous-Time Autonomous Systems). The

autonomous system (19) is globally (over the entire domain D ) and asymptotically stable about its zero
equilibrium, if there exists a scalar-valued function, V(x), defined on D, such that
(1)
(2)
(3)

V(0) = 0;
V (x) > 0 for all x = 0 in D ;
(x) < 0 for all x = 0 in D .
V
Note that if condition iv in Theorem 3 is replaced by

(x) 0 for all x D ;

(1) V
then the resulting stability is only in the sense of Lyapunov but may not be asymptotic. For example,
consider a simple model of an undamped pendulum of length  described by

where y = is the angular variable defined on < < , with the vertical axis as its reference, and g is the
gravity constant.
Since the system Jacobian at the zero equilibrium has a pair of purely imaginary eigenvalues

1,2 = g/, Theorem 1 is not conclusive. However, if one uses the Lyapunov function

= 0 over the entire domain. Thus, the conclusion is that the undamped
then it can be easily verified that V
pendulum is stable in the sense of Lyapunov but not asymptotically, consistent with the physics of the undamped
pendulum.
Theorem 4 (Krasovskii Theorem, for Continuous-Time Autonomous Systems). For the autonomous system in Eq. (19), let J x = [f/x] be its Jacobian evaluated at x(t) . A sufficient condition for the
system to be asymptotically stable about its zero equilibrium is that there exist two real positive definite and
symmetric constant matrices, P and Q, such that the matrix

is seminegative definite for all x = 0 in a neighborhood D of the origin. For this case, a Lyapunov function is
given by

Furthermore, if D = Rn and V(x) as x , then this asymptotic stability is also global.
Similar stability criteria can be established for discrete-time systems. Two main results are summarized
as follows.

14

STABILITY OF NONLINEAR SYSTEMS

Theorem 5 (First Method of Lyapunov, for Discrete-Time Autonomous Systems). Let x = 0

be an equilibrium of the discrete-time autonomous system

where f: D Rn is continuously differentiable in a neighborhood of the origin, D Rn , and let J = [f /xk]xk = x = 0

be the Jacobian of the system evaluated at this equilibrium. If all the eigenvalues of J are strictly less than
one in absolute value, then the system is asymptotically stable about its zero equilibrium.
Theorem 6 (Second Method of Lyapunov, for Discrete-Time Nonautonomous Systems). Let
x = 0 be an equilibrium of the nonautonomous system

where fk : D Rn is continuously differentiable in a neighborhood of the origin, D Rn . Then the system in

Eq. (22) is globally (over the entire domain D ) and asymptotically stable about its zero equilibrium, if there
exists a scalar-valued function, V(xk , k), defined on D and continuous in xk , such that
(1)
(2)
(3)
(4)

V(0, k) = 0 for all k k0 ;

V (xk ) > 0 for all xk = 0 in D and for all k k0 ;
V(xk , k): = V(xk , k) V(xk 1 , k 1) < 0 for all xk = 0 in D and all k k0 + 1;
0 < W(xk ) < V(xk , k) for all k k0 + 1, where W () is a positive continuous function defined on D,
satisfying W(0) = 0 and lim W() = monotonically.

As a special case for discrete-time autonomous systems, Theorem 6 reduces to the following simple form.
Theorem 7 (Second Method of Lyapunov, for Discrete Time Autonomous Systems). Let x
= 0 be an equilibrium for the autonomous systems in Eq. (22). Then the system is globally (over the entire
domain D ) and asymptotically stable about this zero equilibrium if there exists a scalar-valued function V(xk ),
defined on D and continuous in xk , such that
(1)
(2)
(3)
(4)

V(0) = 0 ;
V(xk ) > 0 for all xk = 0 in D;
 V(xk ): = V(xk ) V(xk 1 ) < 0 for all xk = 0 in * ;
V(x) as x .

To this end, it is important to emphasize that all the Lyapunov theorems stated earlier offer only sufficient
conditions for asymptotic stability. On the other hand, usually more than one Lyapunov function may be
constructed for the same system. For a given system, one choice of a Lyapunov function may yield a less
conservative result (e.g., with a larger stability region) than other choices. However, no conclusion regarding
stability may be drawn if, for technical reasons, a satisfactory Lyapunov function cannot be found. Nevertheless,
there is a necessary condition in theory about the existence of a Lyapunov function (7).
Theorem 8 (Massera Inverse Theorem). Suppose that the autonomous system in Eq. (19) is asymptotically stable about its equilibrium x and f is continuously differentiable with respect to x for all t [t0 , )
. Then a Lyapunov function exists for this system.
Some Instability Theorems. Once again, consider a general autonomous system,

STABILITY OF NONLINEAR SYSTEMS

15

with an equilibrium x = 0 . To disprove the stability, the following instability theorems may be used.
Theorem 9 (A Linear Instability Theorem). For system in Eq. (24), let J = [f /x]x = x = 0 be the system
Jacobian evaluated at x = 0. If at least one of the eigenvalues of J has a positive real part, then x = 0 is
unstable.
For discrete-time systems, there is a similar result: A discrete-time autonomous system

is unstable about its equilibrium x = 0 if at least one of the eigenvalues of the system Jacobian is larger than
1 in absolute value.
The following two negative theorems can be easily extended to nonautonomous systems in an obvious
way.
Theorem 10 (A General Instability Theorem). For system in Eq. (24), let V (x) be a positive and
continuously differentiable function defined on a neighborhood D of the origin, satisfying V(0) = 0 . Assume
that in any subset, containing the origin, of D, there is an x such that V (x) > 0. If, moreover,

then the system is unstable about the equilibrium x = 0 .

One example is the system

which has equilibrium

( x , y ) = (0, 0) . The system Jacobian at the equilibrium has a pair of imaginary
eigenvalues, 1,2 = 1, so Theorem 1 is not conclusive. On the contrary, the Lyapunov function

= (x2 + y2 )(x2 + y4 ) > 0 for all ( x, y) = (0, 0) . Therefore, the conclusion is that this system is unstable
leads to V
about its zero equilibrium.
Theorem 11 (Chetaev Instability Theorem). For system in Eq. (24), let V (x) be a positive and
continuously differentiable function defined on D, and let
be a subset, containing the origin, of D, (i.e., 0  D

). If

(1) V(x) > 0 and V(x)

> 0 for all x = 0 in D ,
(2) V(x) = 0 for all x on the boundary of
,
then the system is unstable about the equilibrium x = 0 .
This instability theorem is illustrated by Fig. 10, which graphically shows that if the theorem conditions
are satisfied, then there is a gap within any neighborhood of the origin, so that a system trajectory can escape
from the neighborhood of the origin along a path in this gap (1).
As an example, consider the system

16

STABILITY OF NONLINEAR SYSTEMS

Fig. 10.

Fig. 11.

Illustration of the Chetaev theorem.

The defining region of a Lyapunov function.

with the Lyapunov function

which is positive inside the region defined by

Let D be the right-half plane and
be the shaded area shown in Fig. 11. Clearly, V = 0 on the boundary
= 2x3 > 0 for all ( x, y) D . According to the Chetaev theorem, this system is unstable
of
and V > 0 and V
about its zero equilibrium.
LaSalle Invariance Principle. Consider again the autonomous system in Eq. (24) with an equilibrium
x = 0 . Let V (x) be a Lyapunov function defined on a neighborhood D of the origin. Let also t (x0 ) be a bounded
solution orbit of the system, with the initial state x0 and all its limit states being confined in D . Moreover, let

and M E be the largest invariant subset of E in the sense that if the initial state x0 M then the entire orbit
t (x0 ) M for all t t0 .
Theorem 12 (LaSalle Invariance Principle). Under the preceding assumptions, for any initial state
x0 D, the solution orbit satisfies

STABILITY OF NONLINEAR SYSTEMS

17

This invariance principle is consistent with the Lyapunov theorems when they are applicable to a problem
= 0 over a subset of the domain of V, a Lyapunov theorem is not easy to apply directly,
(6,12). Sometimes when V
but the LaSalle invariance principle may be convenient to use. For instance, consider the system

The Lyapunov function V = x2 + y2 yields

which is negative for x2 < 3 but is zero for x = 0 and x2 = 3, regardless of variable y . Thus, Lyapunov theorems
do not seem to be applicable,
at least not
directly. However, observe that the set E defined earlier has only three

straight lines: x = 3, x = 0, and x = 3, and that all trajectories which intersect the line x = 0 will remain
on the line only if y = 0 . This means that the largest invariant subset M containing the points with x = 0 is
the only point (0, 0). It then follows from the LaSalle invariance principle that
starting from any initial state
located in a neighborhood of the origin bounded within the two stripes x = 3, say located inside the disk

the solution orbit will always be attracted to the point (0, 0). This means that the system is (locally) asymptotically stable about its zero equilibrium.
Comparison Principle and Vector Lyapunov Functions. For large-scale and interconnected nonlinear (control) systems, or systems described by differential inequalities rather than differential equations,
the preceding stability criteria may not be directly applicable. In many such cases, the comparison principle
and vector Lyapunov function methods turn out to be advantageous (20 21,22).
To introduce the comparison principle, consider the general nonautonomous system

where f (0, t) = 0 is continuous on a neighborhood D of the origin, t0 t < .

In this case, since f is only continuous (but not necessarily satisfying the Lipschitz condition), this differential equation may have more than one solution (23). Let xmax (t) and xmin (t) be its maximum and minimum
solutions, respectively, in the sense that

where x (t) is any solution of the equation, and xmin (t0 ) = x(t0 ) = xmax (t0 ) = x0 .
Theorem 13 (The Comparison Principle). Let y(t) be a solution of the following differential inequality:

18

STABILITY OF NONLINEAR SYSTEMS

If xmax (t) is the maximum solution of the system in Eq. (26), then

The next theorem is established based on this comparison principle.

A vector-valued function, g (x, t) = [g1 (x, t)gn (x, t)]T is said to be quasi-monotonic, if

Theorem 14 (Vector Lyapunov Function Theorem). Let v (x, t) be a vector Lyapunov function
associated with the nonautonomous system in Eq. (26), with v(x, t) = [V 1 (x, t) V n (x, t)]T in which each V i is
a continuous Lyapunov function for the system, i = 1, , n, satisfying v (x, t) > 0 for x = 0 . Assume that

for a continuous and quasi-monotonic function g defined on D . Then

(1) if the system

is stable in the sense of Lyapunov (or asymptotically stable) about its zero equilibrium y = 0, then so is
the nonautonomous system in Eq. (26);
(2) if, moreover, v(x, t) is monotonically descreasing with respect to t and the preceding stability (or asymptotic
stability) is uniform, then so is the nonautonomous system (26);
(3) if, furthermore, v(x, t) cx for two positive constants c and , and the preceding stability (or asymptotic
stability) is exponential, then so is the nonautonomous system (26).
A simple and frequently used comparison function is

where A is a stable M matrix (Metzler matrix). Here, A = [aij ] is an M matrix if

Theorem 14 (Vector Lyapunov Function Theorem).

Theorem 15 (Orbital Stability Theorem). Let x (t) be a p-periodic solution of an autonomous system.
Suppose that the system has Floquet multipliers i , with 1 = 0 and |i | < 1 for i = 2,, n . Then this periodic
solution x (t) is orbitally stable. Note that Floquet multipliers are defined preceding Eq. (9).
Theorem 16 (Peixoto Structural Stability Theorem). Consider a two-dimensional autonomous system. Suppose that f is twice differentiable on a compact and connected subset D bounded by a simple closed
curve, , with an outward normal vector, n . Assume that fn = 0 on . Then the system is structural stable
on D if and only if

STABILITY OF NONLINEAR SYSTEMS

19

(1) all equilibria are hyperbolic;

(2) all periodic orbits are hyperbolic;
(3) if x and y are hyperbolic saddles (probably, x = y), then W s (x) W u (y) = .

Linear Stability of Nonlinear Systems

The first method of Lyapunov provides a linear stability analysis for nonlinear autonomous systems. In this
section, the following general nonautonomous system is considered:

which is assumed to have an equilibrium x = 0 .

Linear Stability of Nonautonomous Systems. For the system in Eq. (27), Taylor-expanding the

function f about x = 0 gives

where J(t) = [f/x]x = 0 is the Jacobian and g(x, t) is the residual of the expansion, which is assumed to satisfy

in a neighborhood of zero, where a > 0 is a constant. It is known, from the theory of elementary ordinary
differential equations (16), that the solution of Eq. (28) is given by

where (t, ) is the fundamental matrix of the system associated with matrix J(t) .
Theorem 17 (A General Linear Stability Theorem). For the nonlinear nonautonomous system in
Eq. (28), if there are two positive constants, c and , such that

and if

uniformly with respect to t [t0 , ), then there are two positive constants, and , such that

for all x0  and all t [t0 , ) .

This result implies that under the theorem conditions, the system is locally, uniformly, and exponentially
stable about its equilibrium x = 0 .

20

STABILITY OF NONLINEAR SYSTEMS

In particular, if the system matrix J(t) = J is a stable constant matrix, then the following simple criterion
is convenient to use.
Theorem 18 (A Special Linear Stability Theorem). Suppose that in system (28), the matrix J(t) =
J is a stable constant matrix (all its eigenvalues have a negative real part), and g(0, t) = 0 . Let P be a positive
definite and symmetric matrix solution of the Lyapunov equation

where Q is a positive definite and symmetric constant matrix. If

for a constant a < 12 max (P) uniformly on [ t0 , ), where max (P) is the maximum eigenvalue of P, then system
in Eq. (28) is globally, uniformly, and asymptotically stable about its equilibrium x = 0 .
This actually is the example used previously for illustration of Theorem 2.
Linear Stability of Nonlinear Systems with Periodic Linearity. Consider a nonlinear nonautonomous system of the form

where g(0, t) = 0 and J(t) is a p-periodic matrix ( p > 0 ):

Theorem 19 (Floquet Theorem). For system in Eq. (30), assume that g(x, t) and g(x, t)/x are both
continuous in a bounded region D containing the origin. Assume, moreover, that

uniformly on [ t0 , ). If the system Floquet multipliers satisfy

then system in Eq. (30) is globally, uniformly, and asymptotically stable about its equilibrium x = 0 .

Total Stability: Stability Underpersistent Disturbances

Consider a nonautonomous system of the form

where f is continuously differentiable, with f(0, t) = 0, and h is a persistent perturbation in the sense that for
any  > 0, there are two positive constants, 1 and 2 , such that if h(x, t) < 1 for all t [t0 , ) and if  x (t0 )
< 2 then  x (t) <  .

STABILITY OF NONLINEAR SYSTEMS

21

The equilibrium x = 0 of the unperturbed system [system in Eq. (32) with h = 0 therein] is said to be
totally stable, if the persistently perturbed system in Eq. (32) remains to be stable in the sense of Lyapunov.
As the next theorem states, all uniformly and asymptotically stable systems with persistent perturbations
are totally stable, namely, a stable orbit starting from a neighborhood of another orbit will stay nearby (7,9).
Theorem 20 (Malkin Theorem). If the unperturbed system in Eq. (32) (i.e., with h = 0 therein)
is uniformly and asymptotically stable about its equilibrium x = 0, then it is totally stable, namely, the
persistently perturbed system in Eq. (32) remains to be stable in the sense of Lyapunov.
Next, consider an autonomous system with persistent perturbations:

Theorem 21 (Perturbed Orbital Stability Theorem). If t (x0 ) is an orbitally stable solution of the
unperturbed autonomous system in Eq. (33) (with h = 0 therein), then it is totally stable, that is, the perturbed
system remains to be orbitally stable under persistent perturbations.

Absolute Stability and Frequency Domain Criteria

Consider a feedback system in the Lure form:

where A, B, C are constant matrices, in which A is nonsingular but B and C are not necessarily square (yet,
probably, B = C = I ), and h is a vector-valued nonlinear function. By taking the Laplace transform with zero
initial conditions and denoting the transform by x = L{x}, the state vector is obtained as

so that the output is given by

with the system transfer matrix

This can be implemented via the block diagram shown in Fig. 12, where, for notational convenience, both timeand frequency-domain symbols are mixed.
The Lure system shown in Fig. 12 is a closed-loop configuration, where the block in the feedback loop is
usually considered as a controller. Thus, this system is sometimes written in the following equivalent form:

22

STABILITY OF NONLINEAR SYSTEMS

Fig. 12.

Configuration of the Lure system.

SISO Lure Systems. First, single-input single-output Lure systems are discussed, where u = h(y)
and y = cT x are both scalar-valued functions:

Assume that h(0) = 0, so that x = 0 is an equilibrium of the system.

The sector condition. The Lure system in Eq. (39) is said to satisfy the local (global) sector condition
on the nonlinear function h(), if there exist two constants, < , such that
(1) local sector condition:

(2) global sector condition:

Here, [, ] is called the sector for the nonlinear function h() . Moreover, the system in Eq. (39) is said to be
absolutely stable within the sector [ , ] if the system is globally asymptotically stable about its equilibrium
x = 0 for any nonlinear function h() satisfying the global sector condition. These local and global sector
conditions are visualized by Fig. 13(a, b), respectively.
Theorem 22 (Popov Criterion). Suppose that the SISO Lure system in Eq. (39) satisfies the following
conditions:
(1) A is stable and { A, b } is controllable;
(2) the system satisfies the global sector condition with = 0 therein;
(3) for any  > 0, there is a constant > 0 such that

STABILITY OF NONLINEAR SYSTEMS

Fig. 13.

Fig. 14.

23

Local and global sector conditions.

Geometric meaning of the Popov criterion.

where G(s) is the transfer function defined by Eq. (37), and Re{} denotes the real part of a complex number
(or function). Then, the system is globally asymptotically stable about its equilibrium x = 0 within the
sector.
The Popov criterion has the following geometric meaning: Separate the complex function G(s) into its real
and imaginary parts, namely,

and so rewrite condition iii as

Then any graphical situation of the Popov criterion shown in Fig. 14 implies the global asymptotic stability
of the system about its zero equilibrium.
The Popov criterion has a natural connection to the linear Nyquist criterion (11,15,16,24). A more direct
generalization of the Nyquist criterion to nonlinear systems is the following.
Theorem 23 (Circle Criterion). Suppose that the SISO Lure system in Eq. (39) satisfies the following
conditions:
(1) A has no purely imaginary eigenvalues and has eigenvalues with positive real parts;
(2) the system satisfies the global sector condition;
(3) one of the following situation holds:
0 < < : the Nyquist plot of G(j) encircles the disk D(1/, 1/) counterclockwise times but does not
enter it;
0 = < : the Nyquist plot of G(j) stays within the open half-plane Re{s} > 1/ ;

24

STABILITY OF NONLINEAR SYSTEMS

Fig. 15. The disk D(1/, 1/) .

< 0 < : the Nyquist plot of G(j) stays within the open disk D(1/, 1/) ;
< < 0 : the Nyquist plot of G(j) encircles the disk D(1/, 1/) counterclockwise times but does not
enter it.
Then, the system is globally asymptotically stable about its equilibrium x = 0 .
Here, the disk D( 1/, 1/), for the case of 0 < < , is shown in Fig. 15.
MIMO Lure Systems. Consider a multi-input multi-output Lure system, as shown in Fig. 12, namely,

with G(s) as defined in Eq. (37). If this system satisfies the following Popov inequality:

for a constant 0 independent of t, then it is said to be hyperstable.

The linear part of this MIMO system is described by the transfer matrix G(s), which is said to be positive
real if
(1) there are no poles of G(s) located inside the open half-plane Re{s} > 0 ;
(2) poles of G(s) on the imaginary axis are simple, and the residues form a semi-positive definite matrix;
(3) the matrix [ G(j) + GT (j) ] is a semi-positive definite matrix for all real values of that are not poles of
G(s) .

Theorem 24 (Hyperstability Theorem). The MIMO Lure system in Eq. (43) is hyperstable if and
only if its transfer matrix G(s) is positive real.
Describing Function Method. Return to the SISO Lure system in Eq. (39) and consider its periodic
output y(t) . Assume that the nonlinear function h() therein is a time-invariant odd function and satisfies the
property that for y(t) = sin(t), with real constants and = 0, only the first-order harmonic of h(y) in its
Fourier series expansion is significant. Under this setup, the specially defined function

is called the describing function of the nonlinearity h(), or of the system (15,24,25).

STABILITY OF NONLINEAR SYSTEMS

25

Fig. 16. Graphical describing function analysis.

Theorem 25 (First-Order Harmonic Balance Approximation). Under the preceding conditions, if

furthermore the first-order harmonic balance equations

have solutions and = 0, then

is the first-order approximation of a possible periodic orbit of the output of system in Eq. (39). However, if these
harmonic balance equations have no solution, then likely the system will not have any periodic output.
When solving the equation Gr (j)  () = 1 graphically, one can sketch two curves in the complex plane:
Gr (j ) and 1/ () by increasing gradually and , respectively, to find their crossing points:
(1) If the two curves are (almost) tangent, as illustrated by Fig. 16(a), then a conclusion drawn from the
describing function method will not be satisfactory in general.
(2) If the two curves are (almost) transversal, as illustrated by Fig. 16(b), then a conclusion drawn from the
describing function analysis will generally be reliable.

Theorem 26 (Graphical Stability Criterion for a Periodic Orbit). Each intersection point of the two
curves, Gr (j) and 1/(), in Fig. 16 corresponds to a periodic orbit, y1 (t), of the output of system (39). If the
points, near the intersection and on one side of the curve 1/() where is increasing, are not encircled by
the curve Gr (j ), then the corresponding periodic output is stable; otherwise, it is unstable.

Bibo Stability
A relatively simple, and also relatively weak notion of stability is discussed in this section. This is the boundedinput bounded-output (BIBO) stability, which refers to the property of a system that any bounded input to the
system produces a bounded output through the system (11,26,27).
Return to the input-output map in Eq. (13) and its configuration Fig. 2.
Denition 1. The system S is said to be BIBO stable from the input set U to the output set Y, if for each
admissible input u U and the corresponding output y Y, there exist two nonnegative constants, bi and bo ,

26

STABILITY OF NONLINEAR SYSTEMS

such that

Note that since all norms are equivalent for a finite-dimensional vector, it is generally insignificant to
distinguish under what kind of norms for the input and output signals the BIBO stability is defined and
achieved. Moreover, it is important to note that in this definition, even if bi is small and bo is large, the system
is still considered to be BIBO stable. Therefore, this stability may not be very practical for some systems in
certain applications.
Small Gain Theorem. A convenient criterion for verifying the BIBO stability of a closed-loop control
system is the small gain theorem (11,26,27), which applies to almost all kinds of systems (linear and nonlinear,
continuous-time and discrete-time, deterministic and stochastic, time-delayed, of any dimensions), as long as
the mathematical setup is appropriately formulated to meet the theorem conditions. The main disadvantage
of this criterion is its over-conservativity.
Return to the typical closed-loop system shown in Fig. 3, where the inputs, outputs, and internal signals
are related via the following equations:

It is important to note that the individual BIBO stability of S1 and S2 is not sufficient for the BIBO
stability of the connected closed-loop system. For instance, in the discrete-time setting of Fig. 3, suppose that
S1 1 and S2 1, with u1 (k) 1 for all k = 0, 1, . Then S1 and S2 are BIBO stable individually, but it can
be easily verified that y1 (k) = k as the discrete-time variable k evolves. Therefore, a stronger condition
describing the interaction of S1 and S2 is necessary.
Theorem 27 (Small Gain Theorem). If there exist four constants, L1 , L2 , M 1 , M 2 , with L1 L2 < 1,
such that

then

where the norms  are defined over the spaces that the signals belong. Consequently, Eqs. (48) and (24)
together imply that if the system inputs ( u1 and u2 ) are bounded then the corresponding outputs [ S1 (e1 ) and
S2 (e2 ) ] are bounded.
Note that the four constants, L1 , L2 , M 1 , M 2 , can be somewhat arbitrary (e.g., either L1 or L2 can be large)
provided that L1 L2 < 1, which is the key condition for the theorem to hold [and is used to obtain ( 1 L1 L2 ) 1
in the bounds in Eq. (49)].
In the special case where the input-output spaces, U and Y, are both the L2 -space, a similar criterion
based on the system passivity property can be obtained (11,27). In this case, an inner product between any two
vectors in the space is defined by

STABILITY OF NONLINEAR SYSTEMS

27

Theorem 28 (Passivity Stability Theorem). If there exist four constants, L1 , L2 , M 1 , M 2 , with L1 +

L2 > 0, such that

then the closed-loop system in Eq. (47) is BIBO stable.

As mentioned earlier, the main disadvantage of this criterion is its over-conservativity in providing the
sufficient conditions for the BIBO stability. One resolution is to transform the system into the Lure structure,
and then apply the circle or Popov criterion under the sector condition (if it can be satisfied), which can usually
lead to less-conservative stability conditions.
Contraction Mapping Theorem. The small gain theorem by nature is a kind of contraction mapping
theorem. The contraction mapping theorem can be used to determine the BIBO stability property of a system
described by a map in various forms, provided that the system (or the map) is appropriately formulated. The
following is a typical (global) contraction mapping theorem.
Theorem 29 (Contraction Mapping Theorem). If the operator norm of the input-output map S,
defined by Eq. (14) on Rn , satisfies |S| < 1, then the system equation

has a unique solution for any constant vector c Rn . This solution satisfies

In the discrete-time setting, the solution of the equation

satisfies

Concluding Remarks
This article has offered a brief introduction and description of the basic theory and methodology of the Lyapunov
stability, orbital stability, structural stability, and input-output stability for nonlinear dynamical systems. More
subtle details for stability analysis of general dynamical systems can be found in, for example, Refs. 1,6,8 9 10
12 12,13,15,16,23,24, and 27 28,29. When control is explicitly involved, stability and stabilization issues are
studied in Refs. 11,14,26,30,31, and 35 to name just a few.
Several important classes of nonlinear (control) systems have been left out in the preceding discussion
of various stability issues: some general functional systems such as systems with time delays (32), measure
ordinary differential equations such as systems with impulses (33,34), and some weakly nonlinear systems like
piecewise linear and switching (non)linear systems. Moreover, discussion on more advanced nonlinear systems
such as singular nonlinear systems (perhaps with time delays), infinite-dimensional (non)linear systems,
spatiotemporal systems described by nonlinear partial differential equations, and nonlinear stochastic (control)
systems are all beyond the scope of this elementary expository article.

28

STABILITY OF NONLINEAR SYSTEMS

BIBLIOGRAPHY
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.

D. R. Merkin, Introduction to the Theory of Stability, New York: Springer-Verlag, 1997.

A. M. Lyapunov, The General Problem of Stability of Motion, 100 Anniversary, London: Taylor & Francis, 1992.
G. Chen, G. Chen, S. H. Hsu, Linear Stochastic Control Systems, Boca Raton, FL: CRC Press, 1995.
F. Brauer, J. A. Nohel, The Qualitative Theory of Ordinary Differential Equations: An Introduction, New York: Dover,
1989.
G. Chen, X. Dong, From Chaos to Order: Methodologies, Perspectives and Applications, Singapore: World Scientific,
1998.
P. Glendinning, Stability, Instability and Chaos, New York: Cambridge Univ. Press, 1994.
F. C. Hoppensteadt, Analysis and Simulation of Chaotic Systems, New York: Springer-Verlag, 1993.
N. P. Bhatia, G. P. Szego, Stability Theory of Dynamical Systems, Berlin: Springer-Verlag, 1970.
W. Hahn, Stability of Motion, Berlin: Springer-Verlag, 1967.
D. W. Jordan, P. Smith, Nonlinear Ordinary Differential Equations, 2nd ed., New York: Oxford Univ. Press, 1987.
H. K. Khalil, Nonlinear Systems, 2nd ed., Upper Saddle River, NJ: Prentice-Hall, 1996.
J. P. LaSalle, The Stability of Dynamical Systems, Philadelphia: SIAM, 1976.
S. Lefschetz, Differential Equations: Geometric Theory, 2nd ed., New York: Dover, 1977.
N. Minorsky, Theory of Nonlinear Control Systems, New York: McGraw-Hill, 1969.
R. R. Mohler, Nonlinear Systems: Vol. 1, Dynamics and Control, Englewood Cliffs, NJ: Prentice-Hall, 1991.
P. C. Parks, V. Hahn, Stability Theory, New York: Prentice-Hall, 1981.
M. Vidyasagar, Nonlinear Systems Analysis, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1993.
M. Y. Wu, A note on stability of linear time-varying systems, IEEE Trans. Autom. Control, AC-19: 162, 1974.
F. Verhulst, Nonlinear Differential Equations and Dynamical Systems, 2nd ed., Berlin: Springer-Verlag, 1996.
V. Lakshmikantham, V. M. Matrosov, S. Sivasundaram, Vector Lyapunov Functions and Stability Analysis of Nonlinear
Systems, Boston: Kluwer, 1991.
A. N. Michel, R. K. Miller, Qualitative Analysis of Large Scale Dynamical Systems, New York: Academic Press, 1977.
D. D. Siljack, Large Scale Dynamic Systems: Stability and Structure, Amsterdam: North-Holland, 1978.
R. Grimshaw, Nonlinear Ordinary Differential Equations, Boca Raton, FL: CRC Press, 1993.
K. S. Narendra, J. H. Taylor, Frequency Domain Criteria for Absolute Stability, New York: Academic Press, 1973.
D. P. Atherton, Nonlinear Control Engineering, New York: Van Nostrand Reinhold, 1982.
R. J.P. de Figueiredo, G. Chen, Nonlinear Feedback Control Systems: An Operator Theory Approach, San Diego: Academic
Press, 1993.
C. A. Desoer, M. Vidyasagar, Feedback Systems: Input-Output Properties, New York: Academic Press, 1975.
L. Cesari, Asymptotic Behavior and Stability Problems in Ordinary Differential Equations, New York: Springer-Verlag,
1971.

S. Yu. Pilyugin, Introduction to Structurally Stable Systems of Differential Equations, Boston: Birkhaser,
1992.
H. Nijmeijer, A. J. van der Schaft, Nonlinear Dynamical Control Systems, New York: Springer-Verlag, 1990.
E. D. Sontag, Mathematical Control Theory: Deterministic Finite Dimensional Systems, 2nd ed., New York: SpringerVerlag, 1998.
J. Hale, Theory of Functional Differential Equations, New York: Springer-Verlag, 1977.
D. D. Bainov, and P. S. Simeonov, Systems with Impulse Effect: Stability, Theory and Applications, Chichester: Ellis
Horwood, 1989.
A. M. Samoilenko, N. A. Perestyuk, Impulsive Differential Equations, Singapore: World Scientific, 1995.
S. Sastry, Nonlinear Systems: Analysis, Stability, and Control, New York: Springer, 1999.

GUANRONG CHEN
University of Houston

VOLTERRA SERIES

359

VOLTERRA SERIES
Functional expansions are used in every branch of nonlinear
system theory: identification and modelling, realization, stability, optimal control, stochastic differential equations and
filtering, etc. Almost all the expansions used are of the Volterra type or, in the stochastic case, of the Wiener type. There
exist a great number of publications on these expansions. Let
us here mention only the early works by Wiener (1), Barrett
(2), and George (3) and the two books by Rugh (4) and Schetzen (5).
After recalling the definition of the Volterra series expansion and some of its convergence issues, we will study various
methods in order to derive the Volterra kernels and the response to typical inputs. The analysis is then applied to the
study of weakly nonlinear circuits in order to derive distortion
rates or intermodulation products.
FUNCTIONAL REPRESENTATION OF NONLINEAR SYSTEMS
Volterra Functional Series
For simplicity of presentation, we shall consider time-invariant systems. If a system is linear and time-invariant, then
the output y(t) can be expressed as the convolution of the input u(t) with the system unit impulse response h(t):


y(t) =

h( )u(t ) d

(1)

The system unit impulse response h(t) completely characterizes the linear time-invariant system since, once known, the
response to any input can be determined from Eq. (1). A system is said to be causal if the output at any given time does
not depend on future values of the input. That is, for any
time t1,


y(t1 ) =

h( )u(t1 ) d = 0

This will be so if and only if

h( ) = 0 for < 0
The extension of Eq. (1) to nonlinear time-invariant systems
with memory is the Volterra series

y(t) = h0 +

n=1

...

hn (1 , 2 , . . ., n )u(t 1 )u(t 2 )

u(t n ) d1 d2 dn

(2)

This functional form was first studied by Volterra. Much of

his work in this area is summarized in his book (6). The functions hn(1, 2, . . ., n) are called the Volterra kernels of the
system. A nonlinear system which can be represented by a
Volterra series is completely characterized by its Volterra
kernels. Also, with an argument similar to that of linear systems, it can be shown that the nonlinear system is causal if
hn (1 , 2 , . . ., n ) = 0 for j < 0,

j = 1, . . ., n

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

360

VOLTERRA SERIES

It is well known that without loss of generality, the kernels

can be assumed to be symmetric. In fact, any kernel hn(1, 2,
. . ., n) can be replaced by a symmetric one by setting

hsym
n (1 , 2 , . . ., n ) =

1
n!


( i , i ,..., i )S
n
1
2

hn (i , i , . . ., i n )
1

y(t) =

On the Convergence of Volterra Series

The Volterra series is a nonlinear power series with memory
(7). The nonlinearity can be seen by changing the input by a
gain factor c so that the new input is cu(t). By using Eq. (2),
the new output is

y(t) = h0 +

n=1

cn

hn (1 , 2 , . . ., n )u(t 1 )u(t 2 )

u(t n ) d1 d2 dn
which is a power series in the amplitude factor c. It is a series
with memory since the integrals are convolutions. As a consequence of its power series character, there are some limitations associated with the application of the Volterra series to
nonlinear problems. One major limitation is the convergence
of this series.
In order to illustrate this let us consider the system of Fig.
1, where the system L is a linear system with the unit impulse response h(t)


z(t) =

h( )u(t ) d

(3)

and the system N is a nonlinear no-memory system with the

input-output relation
y(t) = N[z(t)] =

z(t)
1 + z2 (t)

The Taylor series expansion of this expression is

y(t) =

(1)n [z(t)]2n+1

n=0

u(t)
L

z(t)

y(t) = T[u(t)]
N

T
Figure 1. An example of a nonlinear system.

2n+1
h( )u(t ) d

in which the Volterra kernels are

h2n+1 (1 , . . ., 2n+1 ) = (1)n h(1 )h(2 ) . . . h(2n+1 )

h2n (1 , . . ., 2n ) = 0,

is called the nth-order transfer function. Since hn(1, . . ., n)

is symmetric, so is Hn(s1, . . ., sn).



(1)n

and

hn (1 , . . ., n )es 1 1

es n n d1 d2 dn


n=0

where S is the set of all permutations of 1 . . ., n.

The multiple Laplace transform L[.] of the nth-order Volterra kernel n 0 (one-sided in each variable)

Hn (s1 , . . ., sn ) =

which converges only for z2(t) 1. The Volterra series representation of the overall system T is now easily derived by substituting Eq. (3) for Eq. (4) to obtain

(4)

n0

Since the Taylor series converges only for z2(t) 1, the above
Volterra series will diverge at those times for which z(t) 1.
The Volterra series, thus, is valid only for the class of inputs
u(t) for which the amplitude of z(t) is less than one.
Now let N be replaced by the following nonlinear, no-memory system
y(t) = Esign[z(t)]
Clearly, the system T cannot be represented by a Volterra
series. It is, therefore, evident that generally, many types of
nonlinear systems, such as those that include saturating elements, cannot be characterized by a Volterra series that converges for all inputs.
Proofs are presented in Volterra (6), Brillant (8), and
Blackman (9) which show that under certain conditions, a
functional y(t) T[x(t)] can be approximated to any desired
degree of accuracy by a finite series of the form of Eq. (2).
Such a functional is called continuous. In particular, it is easy
to show that the functional relation between the solution (output) and the forcing function (input) of a nonlinear differential equation with constant coefficients which satisfies the
Lipschitz condition is continuous. If T[x(t)] can exactly be represented by a converging infinite series of the form of Eq. (2),
it is called analytic or weak. Conditions for convergence are
discussed by Volterra and Brillant. Brillant also notes that
two special types of systems, for which the functional relation
between input and output is analytic, are a linear system and
a nonlinear no-memory system with a power series relation
between input and output. He then shows that various combinations such as cascading, adding, or multiplying such systems results in an analytic system.
In practice, most of the analog circuits used in communication systems, such as modulators, mixers, amplifiers, harmonic oscillators, etc., are of a weak nature and, therefore,
analyzed and designed in the frequency domain. For such
weakly nonlinear circuits (having, say, distortion components
of 20 dB or more below the fundamental one), the Volterra
series technique can be readily used in the frequency domain
to obtain results both quantitatively and qualitatively.
Given an input-output map described by a nonlinear control system x f(x, u) and a nonlinear output y h(x), Lesiak
and Krener (10) present a simple means for obtaining a series
representation of the output y(t) in terms of the input u(t).
When the control enters linearly, x f(x) ug(x), the method
yields the existence of a Volterra series representation. The
uniqueness of Volterra series representations is also dis-

VOLTERRA SERIES

cussed in (10). This work generalizes Brocketts technique

(11), the work of Gilbert (12) and the method described by
Bruni, Di Pillo, and Koch (13) for bilinear systems where explicit formulas for the calculation of the kernel functions were
given. Later Boyd and Chua (14) show that any time-invariant continuous nonlinear operator can be approximated by a
Volterra series.

then

F (s1 , . . ., sn ) =

Before going on, let us recall some properties of the multiple

Laplace transform (4). In the following list of results, onesidedness is assumed, and the capital letter notation is used
for transforms.

1 i

Restricting our attention to one-sided input signals, and using

the convolution property of the Laplace transform, the inputoutput relation for a stationary linear system

1. The Laplace transform operation is linear

y(t) =

L[ f (1 , . . ., n ) + g(1 , . . ., n )]
= F (s1 , . . ., sn ) + G(s1 , . . ., sn ), R

f (1 , . . ., n ) = h(1 , . . ., k )g(k+1 , . . ., n )
then
F (s1 , . . ., sn ) = H(s1 , . . ., sk )G(sk+1, . . ., sn )
3. If f(1, . . ., n) can be written as a convolution of the
form
f (1 , . . ., n ) =

h( )g(1 , . . ., n ) d

h( )u(t ) d
0

can be written in the form

Y (s) = H(s)U (s)

(5)

Therefore, if a system transfer function H(s) is known, and

the input signal of interest has a simple Laplace transform
U(s), then the utility of this representation for computing the
corresponding output signal is clear. Let us now consider a
homogeneous system of degree n with one-sided input signals
represented by

y(t) =

hn (1 , 2 , . . ., n )u(t1 1 )u(t2 2 )

u(tn n ) d1 d2 dn

t

t
=

hn (1 , 2 , . . ., n )u(t 1 )u(t 2 )
0

then

h( )u(t ) d =

2. If f(1, . . ., n) can be written as a product of two factors

of the form

n +i
1
(2i)n n i

+
1

H(s1 w1 , . . ., sn wn )

G(w1 , . . ., wn ) dw1 dwn

Properties of the Multiple Laplace Transform

361

(6)

u(t n ) d1 d2 dn
F (s1 , . . ., sn ) = H(s1 + + sn )G(s1 , . . ., sn )

4. If f(1, . . ., n) can be written as an n-fold convolution

of the form

f (1 , . . ., n ) =

Inspection of the above list of properties of the multivariable

Laplace transform yields no direct way to write this in a form
similar to Eq. (5). Therefore, an indirect approach is adopted
by writing Eq. (6) as a pair of equations

h(1 1 , . . ., n n )g(1 , . . ., n )
d1 . . . dn

yn (t1 , . . ., tn ) =

t1
0

tn

hn (1 , 2 , . . ., n )u(t 1 )u(t 2 )

u(t n ) d1 d2 dn

(7)

y(t) = yn (t1 , . . ., tn )|t 1 ==t n =t = yn (t, . . ., t)

then
F (s1 , . . ., sn ) = H(s1 , . . ., sn )G(s1 , . . ., sn )
5. If c1, . . ., cn are nonnegative constants, then
L[ f (1 c1 , . . ., n cn )] = F (s1 , . . ., sn )es 1 c 1 s n c n
6. If f(1, . . ., n) is given by the product
f (1 , . . ., n ) = h(1 , . . ., n )g(1 , . . ., n )

Now, Eq. (7) yields

Yn (s1 , . . ., sn ) = Hn (s1 , . . ., sn )U (s1 ) U (sn )

(8)

where Hm(s1, . . ., sn) L[h(t1, . . ., tn)] is a (multivariable)

transfer function of the homogeneous system. Therefore,
given Hn(s1, . . ., sn) and U(s), it is easy to compute Yn(s1,
. . ., sn). However, the inverse Laplace transform must be
computed before y(t) can be found, and often this is not easy.

362

VOLTERRA SERIES

H3(s)

H2(s)

H1(s)

where m under the summation sign indicates that the sum

k
includes all the distinct vectors (m1, . . ., mk) such that i1
mi n. Note that if m1 m2 mk 1, then the
amplitude associated with the exponential component
e(sk sk )t is simply k!Hk(s1, . . ., sk). This suggests a recursive
procedure for determining all the nonlinear transfer functions
from the behavior of a system.
Let us apply the method to the simple nonlinear circuit
(16) of Fig. 3 consisting of a capacitor, a linear resistor, and a
nonlinear resistor in parallel with the current source i(t).
The nonlinear differential equation relating the current excitation i(t) and the voltage v(t) across the capacitor is given
by
1

Figure 2. Association of three linear systems.

Example: The overall transfer function of the system shown

in Fig. 2 is
H(s1 , s2 , s3 ) = H1 (s1 + s2 + s3 )H2 (s1 + s2 )H3 (s1 )

v + k1 v + k2 v2 = i

RECURSIVE COMPUTATION OF THE KERNELS

Several methods have been developed in the literature for determining the kernels or the associated transfer functions
based on the classical symbolic method of Brillant (8), George
(3), Bedrosian and Rice (15), Bussgang, Ehrman and Graham
(16), Chua and Ng (17), and Flake (18). Among them, the
method of exponential inputs is particularly used. After recalling this method, we describe a differential geometry approach (10) and an algebraic approach based on generating
power series (19) when the system is described by a set of
differential equations. We shall see that the algebraic approach has the advantage of being easily implementable on a
computer by using algebraic computing software.

Let i(t) est. Equating the coefficients of est on both sides of

Eq. (12) after the substitution of (11) for v(t) we get
H1 (s) =

In order to determine H2(s1, s2), let us take i(t) es1t es2t and
identify the coefficient of the term 2!e(s1s2)t after the substitution of Eq. (11) for v(t) in both sides of Eq. (12). We obtain
H2(s1, s2) in term of H1(s) as follows
H2 (s1 , s2 ) = k2 H1 (s1 )H1 (s2 )H1 (s1 + s2 )

Let us consider the Volterra series expansion of a nonlinear

system of the form

y(t) =

t1

tn

n=1 0

hn (1 , 2 , . . ., n )u(t 1 )u(t 2 )

(9)

Let the input u(t) be a sum of exponentials

u(t) = es 1 t + es 2 t + + es k t
where s1, s2, . . ., sk are rationally independent. This means
that there are no rational numbers 1, 2, . . ., k such that
the sum 1s1 2s2 ksk is rational. Then Eq. (9) becomes

k
k




s k ++s k t
n

y(t) =

Hn sk , . . ., sk n e 1
(10)
k 1 =1

i(t) = es 1 t + es 2 t + es 3 t
It follows

u(t n ) d1 d2 dn

n=1

1
s + k1

Similarly, the third-order transfer function is obtained by injecting a sum of three exponentials inputs

Exponential Input Method

(12)

k n =1

2
[H (s , s )H (s ) + H2 (s2 , s3 )H1 (s1 )
3 2 1 2 1 3
+ H2 (s1 , s3 )H1 (s2 )]h1 (s1 + s2 + s3 )

H3 (s1 , s2 , s3 ) =

Repeating this process indefinitely gives higher order nonlinear transfer functions in terms of lower-order nonlinear
transfer functions.
Differential Geometry Approach
Consider a control system of the general form (10)
x = f (x, u),

x(0) = x0

y = h(x)

where the input takes values in Rl, the state x is an element

of Rm, and the output y takes values in Rn. The vector field f

If each si occurs in (sk1, . . ., skn) mi times, then there are

n!
m1 !m2 ! . . . mk !
identical terms in the expression between brackets. Thus, Eq.
(10) can be written in the form
y(t) =



n=1 m



s ++s k t
n!
n
Hn sk , . . ., sk n e k 1
(11)
1
m1 !m2 ! . . . mk !

+
i(t)

v(t)

Figure 3. A simple nonlinear circuit.

VOLTERRA SERIES

and the output function h are assumed to possess a sufficient

degree of smoothness. The input function u belongs to L1([0,
T], Rl), the space of absolutely integrable functions on [0, T],
or belongs to L([0, T], Rl), the space of bounded and measurable functions on [0, T]. In either case, the output is a member of the space of continuous functions C0([0, T], Rn). Therefore, it is natural to associate with the input-output map

Given
h0 (t) = h(0 (t, 0, x0 ))
and

w1 (t, , x) =

 : L1 ([0, T], Rl ) or L ([0, T], Rl ) C0 ([0, T], Rn )

h(0 (t, , x))

g(x)
x

Definition: has a Volterra series representation if there

exists a set of kernels h0, h1, h2, . . . such that

Eq. (13) can be reduced to

1. h0 is defined on [0, T], and hi, i 1, 2, . . ., is defined

on (t, 1, . . ., i)0 i 1 t T

2. Each hi, i 0, 1, 2, . . . is continuous on its domain of

definition
3. There exists a 0 such that whenever u



t
1

i1
(u)(t) = h0 (t) +

hi (t, 1 , . . ., i )u(1 )
i=1

363

 

h u t, 0, x0 = h0 (t) +


x= u ( ,0,x 0 )




u(1 )w1 t, 1 , u 1 , 0, x0 d1 (14)

Replacing h(.) by w1(t, 1, .) and applying Eq. (13) yields

w1 (t1 , u (1 , 0, x0 ))

= h1 (t, 1 ) +

u(2 )w2 (t, 1 , 2 , u (2 , 0, x0 )) d2

u(i ) di d1

where
h1 (t, 1 ) = w1 (t, 1 , 0 (1 , 0, x0 ))

The series converges in norm topology on C0([0, T], Rn) for all
u .
and
Theorem: Let f, g be analytic vector fields and h an analytic function. If x f(x), and x(0) x0 has a solution on [0,
T], then has a Volterra series representation, and it is
unique.

w2 (t, 1 , 2 , x) =
Hence, Eq. (14) becomes

The proof of this theorem is given by Lesiak and Krener in

(10). Let us sketch the idea. For simplicity of notation, the
input and output are taken to be scalar valued. Let 0(t, , x)
denote the solution of the differential equation

h(u (t, 0, x0 )) = h0 (t) +

t

0

0 ( , , x) = x
Given u, let u(t, , x) be the solution of the differential equation

h(u (t, 0, x0 )) = h0 (t) +

w2 (t, 1 , 2 , 0 (2 , 0, x0 ))

k
t


i=1

1
0

i1

hi (t, 1 , 2 , . . ., i )

u(1 ) u(i ) di d1

t



1
k
+

wk+1 (t, 1 , . . ., k+1 ),

0

0 (2 , 0, x0 ))u(1 )u(2 ) u(k+1 ) dk+1

u ( , , x) = x



h(0 (t, , x))
d
h(( )) = u( )
g(x)
d
x
x= u ( ,0,x 0 )

After k repetitions of this process, we obtain the output representation

satisfying

Direct calculations yield

h1 (t1 )u(1 ) d1

u(1 )u(2 ) d2 d1

d
u (t, , x) = f (u (t, , x)) + u(t)g(u (t, , x))
dt

For a fixed t, the curve () 0(t, , u(, 0, x0)) satisfies

(0) 0(t, 0, x0) and (t) u(t, 0, x0). Further, for any smooth
function h, the fundamental theorem of calculus yields

t
 

 

d
h(( )) d
(13)
h u t, 0, x0 = h 0 t, 0, x0 +
d
0

d
(t, , x) = f (0 (t, , x))
dt 0
such that

w1 (t, 1 , 0 (t, 1 , x))

g(x)
x

with
hi (t, 1 , 2 , . . ., i ) = wi (t, 1 , . . ., i , 0 (1 , 0, x0 ))
and
wi (t, 1 , . . ., i , x) =

wi1 (t, 1 , . . ., i1 , 0 (i1 , i , x))

g(x)
x

Continuing indefinitely, we generate the Volterra series representation in Eq. (13).

364

VOLTERRA SERIES

Algebraic Approach
Fliess algebraic framework (19) summarized below allows deriving an explicit expression of the Volterra kernel by using
an algebraic computing software.
Let us recall some definitions and results from this algebraic approach (20). Let u1(t), u2(t), . . ., um(t) be some
piecewise continuous inputs and Z z0, z1, . . ., zm be a
finite set called alphabet. We denote by Z* the set of words
generated by Z. The algebraic approach introduced by Fliess
may be sketched as follows. Let us consider the letter z0 as an
operator which codes the integration with respect to time and
the letter zi, i 1, . . ., m, as an operator which codes the
integration with respect to time after multiplying by the input ui(t). In this way, any word w Z* gives rise to an iterated integral, denoted by Itw, which can be defined recursively as follows:

I {} = 1

t

d I {v}
if w = z0 v

0
t
,
I {w} =
t

ui ( ) d I {v} if w = z1 v

(16)] in terms of the vector fields and the output function defining the system,

y(t) = w0 (t)+

t



x(t)
= f (x(t)) +

i=1 ui (t)gi (x(t)),

w0 (t)

w1 (t, 1 )

(16)

y(t) = h(x0 ) +

Lf

0 j 0 , j 1 ,..., j =0
L f L f h(x0 )It {z j z j
0
1
j
j
2
1

(17)


0 , 1 ,..., n 0

0 j 0 , j 1 ,, j =0

Lf

(18)

L f 0 Lg Lf 1 Lg Lf n h(x0 )

Lf

L f L f h(x0 )
j

t
0

d j d j

which can also be written



Llf h(x0 )

l0

tl
l!

or using a formal notation,

y(t) = etL f h(x0 )
This formula is nothing else than the classical formula given
by Grobner (21).
For the computation of the first-order kernel, let us consider the terms of Eq. (17) which contain only one contribution of the input u. Therefore,

t
0

This algebraic setting allows us to generalize the Heaviside

calculus for linear system to the nonlinear domain. This will
clearly appear in the next section devoted to the efficient computation of the Volterra series.

In order to show this, let us use the fundamental formula [Eq.

(17)]. The zero order kernel is the free response of the system.
Indeed, from Eq. (17) we have

y(t) =

L f L f h(x0 )z j z j z j

1 ) 1 1
1 !0 !

= e 1 L f Lg e( 2 1 )L f Lg e(t n )L f h(x0 )
(20)

z j nu }

with the series converging uniformly for a small t and small

ui(), 0 t; i 1, . . ., m. This functional expansion is
called the Fliess fundamental formula or Fliess expansion of
the solution. To this expansion, it can also be associated (20)
with an absoluting converging power series for small t and
small ui(), 0 t; i 1, . . ., m, called the Fliess generating power series or Fliess series denoted by g of the following
form

t
= etL f h(x0 )
!

(t n ) n ... 0

d j

Lf h(x0 )

(t
0
1
0 , 1 0 L f Lg L f h(x0 )

0 j 0 ,..., j =0

(19)

..
.

w0 (t) = h(x0 ) +

may be written (20)

n !... 0 !

x(0) = x0

wn (t, n , . . ., 1 )u(n )

= e 1 L f Lg e(t 1 )L f h(x0 )

(15)

y(t) = h(x(t))

g = h(x0 ) +

where the kernels are analytic functions of the form

wn (t, n , n1 , . . ., 1 )

Using the previous formalism and an iterative scheme, the

solution y(t) of the nonlinear control system

m

u(1 ) dn d1

n=1 0

v Z

w1 (t, 1 )u(1 ) d1
=

0 , 10

L f 0 Lg L f 1 h(x0 )

t
0

d0 d0 d1 d0 d0
  
  
1 times

0 times

But the iterated integral inside can be proved to be equal to

Links Between Volterra and Fliess Series
The following result (19) gives the expression of the Volterra
kernels of the response of the nonlinear control system [Eq.

t
0

(t 1 ) 1 1 0
1 !0 !

u(1 ) d1

VOLTERRA SERIES

So, the first order kernel may be written as

w1 (t, 1 ) =

0 , 1 0

is very heavy in general. Let us consider, for instance, the

Duffing equation,

L f 0 Lg L f 1 h(x0 )

(t 1 ) 1 1 0

y + ay + by + cy3 = u(t)

1 !0 !

= e 1 L f Lg e(t 1 )L f h(x0 )

or


x1 = x2
x2 = ax2 bx1 cx31 + u(t)

For the computation of the second order kernel, let us regroup

the terms of Eq. (17) which contain exactly two contributions
of the input u; therefore,

t

0

2
0

w2 (t, 1 , 2 )u(1 )u(2 ) d1 d2



y = x1
Here,

t

L f 0 Lg L f 1 Lg L f 2 h(x0 )

0 , 1 , 2 0

L f = x2

d0 d0 d1 d0 d0 d1 d0 d0
  
  
  
2 times

1 times

The iterated integral inside this expression can be proved to

be equal to

(t 2 ) (2

1 ) 1 1 0

2 !1 !0 !

w2 (t, 1 , 2 ) =

u(1 )u(2 ) d1 d2

0 , 1 , 2 0

=e

2 L f

Lg e

( 1 2 )L f

Lg e

(t 1 )L f

Efficient Computation of Volterra Kernels

L f 0 Lg L f 1 Lg L f 2 h(x0 )

x2

In the following, we will show, through a simple example, how

to obtain the algebraic expression of the terms of the Volterra
series and how to derive the expression of the Volterra
kernels.

Thus, the second-order kernel may be written as

(ax2 + bx1 + c1 x31 )

x1
x2

and

0 times

Lg =

t

365

(t 2 ) 2 (2 1 ) 1 1 0
2 !1 !0 !

Let us consider the system (4),

y(t)
+ (2 + u(t))y(t) = 0,

h(x0 )

t 0,

y(0) = 0,

y(0)

=1

After two integrations, we obtain

The higher-order kernels are obtained in the same way.
Using the Campbell-Baker-Hausdorff formula (21)

t

0


i i
ad Lg
e L f Lg e L f h(x0 ) =
i! L f
i=1

u( )y( ) d d t = 0

where gi contains all the terms of the solution g having exactly i occurrences in the variable z1,

g0 = (1 + 2 z20 )1 z0
g1 = (1 + 2 z20 )1 z0 z1 g0 = (1 + 2 z20 )1 z0 z1 (1 + 2 z20 )1 z0

(22)

These kernel expressions lead to techniques which can, for

example, be used in singular optimal control problems (22).
This will be sketched in a next section.
However, efficient computation remains an open problem
for the moment. Indeed, the computation of the operator
L f 0 Lg Lf 1 Lg Lf n h(x0 )

g = g0 + g1 + g2 + + gi +

(21)


1i 2j i
adL Lg adLj Lg etL f h(x0 )
f
i!
j!
f
i, j=1

..
.

In order to solve this equation, let us use the following iterative scheme

(t 1 )L f

w2(t,n ,n1 , . . ., 1 ) = e 1 L f Lg e(2 1 )L f Lg e(t 2 )L f h(x0 )

=

(1 + 2 z20 )g + z0 z1 g z0 = 0

w0 (t) = etL f h(x0 )

Lg e
h(x0 )
w1 (t, 1 ) = e

i

1 i
adL Lg etL f h(x0 )
=
f
i!
i=1

t

y( ) d d +

The associated algebraic equation for g is

the expressions for the kernels Eq. (20) may be written

1 L f

y(t) + 2

(23)

g2 = (1 + 2 z20 )1 z0 z1 g1
(1 + 2 z20 )1 z0 z1 (1 + 2 z20 )1 z0 z1 (1 + 2 z20 )1 z0
..
.
Each gi, i 0, 1, 2, . . . is a (rational) generating power series
of analytic causal functionals yi, i 0, 1, 2, . . . which represents the ith order term of the Volterra associated with the
solution y(t). Let us now compute yi(t), i0.

366

VOLTERRA SERIES

First,

Therefore,
g0 =

1
1
(1 + jz0 )1 +
(1 jz0 )1
2 j
2 j

y1 (t) =

and
y0 (t) = w0 (t) =

1
0

w1 (t, )u( ) d

with w1(t, ) 1/2 sin [(t )] sin t

The higher-order kernel can be computed in the same way
after decomposing into partial fractions each rational power
series. A recent implementation of this algorithm can be
found in (24).

1 jt
1 jt
1
e
e
+
= sin(wt)
2 j
2 j

The power series

g1 = (1 + 2 z20 )1 z0 z1 (1 + 2 z20 )1 z0

COMPUTATION OF THE RESPONSE TO TYPICAL INPUTS

after decomposing into partial fractions the term on the righthand side and on the left-hand side of z1,


1
1
(1 + jz0 )1
(1 jz0 )1 z1
2 j
2 j


1
1
(1 + jz0 )1 +
(1 jz0 )1

2 j
2 j

or

g1 =

1
[(1 + jz0 )1 z1 (1 + jz0 )1
42
(1 + jz0 )1 z1 (1 jz0 )1
(1 jz0 )1 z1 (1 + jz0 )1
+ (1 jz0 )1 z1 (1 jz0 )1 ]

In order to obtain the equivalent expression in the time domain, we need the following result (23).
The rational power series can be written as
(1 a0 z0 ) p 0 z1 (1 a1 z0 ) p 1 z1 . . . z1 (1 al z0 ) p l

(24)

where a0, a1, . . ., al C, p0, p1, . . ., pl N, in the symbolic

representation of

t

0

f a 0 (t l ) . . . f a l 1 (2 1 ) f a l (1 )u(l )
l 1

(25)

. . . u(1 )dl . . . d1

The next objective is to show how the Volterra series can be

used to determine the output of a system subject to various
deterministic excitations (steps, slopes, harmonics, etc.). In
the linear case, Laplace and Fourier transforms are systematic and powerful tools of operational calculus. A direct generalization of these techniques to the nonlinear domain leads
to multidimensional Laplace and Fourier transforms, but the
computation based on these transforms is often tedious, even
for low-order Volterra kernels, and seems difficult to implement on a computer. An alternative method, presented here,
based on noncommutative variables and on the properties of
iterated integrals leads to a simple nonlinear generalization
of Heaviside symbolic calculus and to an easy implementation
on a computer. It is compared with the association of variables introduced by George (3) and which we shall now
briefly recall.
Transfer Function Approach: Association of Variables
If the Volterra kernels are known for a system, then the output y(t) for a given input u(t) could be obtained. Let us consider relation Eq. (8), and let us assume that the nth-order
Laplace transform of yn(t1, . . ., tn), denoted Yn(s1, s2, . . .,
sn), is given. The question is how to derive yn(t)? Obviously,
one can perform the nth-order inverse Laplace transform of
Yn(s1, s2, . . ., sn)

yn (t1 , . . ., tn ) =

n +i
1
(2i)n n i

+i
1

Yn (s1 ,s2 ,. . ., sn )es 1 t 1 ++s n t n ds1 dsn

1 i

where f ap(t) denotes the exponential polynomial


p1

j=0

j
p1
j!

a t eat

j j

From the previous example, we can see

y1 (t) =

0

t

(26)



1 j
1 j(t )
1 j
u( )
+
e
e
e
d
2 j
2 j
2 j


1 j
1 j
1 j(t )
e
e
e
d
u( )
+
2 j
2 j
2 j

and set t1 t2 tn t. However, this computation is

often unwieldy. In order to bypass this difficulty, George (3)
developed a method whereby the ti variables can be set equal
or associated without leaving the transform domain, leading
to a one-dimensional Laplace transform Yn(s). Indeed, let us
consider a two variable transform Y2(s1, s2); setting t1 t2 t
in Eq. (26) yields

1
y2 (t, t) =
(2i)

2 +i
2 i

es 2 t ds2

1
(2i)

1 +i
1 i

Y2 (s1 , s2 )es 1 t ds1

VOLTERRA SERIES

Changing the variable of integration s1 to s s1 s2 gives

1
y2 (t, t) =
(2i)

2 +i

2 i

1
(2i)

1 +i
1 i

Y2 (s s2 , s2 )e

ss 2 t

367

Its LaplaceBorel transform is

gu =

ds

an zn0

n0

es 2 t ds2
Example:
or by interchanging the order of integration

1
y2 (t, t) =
(2i)

1 +i

1 i

1
(2i)

2 +i
2 i

cos t =

Y2 (s s2 , s2 )ess 2 t ds2
es 2 t ds

Y2 (s) =

1
(2i)

2 +i
2 i

Y2 (s s2 , s2 )ess 2 t ds2

(27)

Similarly, a transform of any order can be reduced to a firstorder transform by successive pairwise associations. For example, let us consider the third-order term
1
(s1 + s2 + s3 + a)(s1 + a)(s2 + a)(s3 + a)
Associating the variables s2 and s3 yields
1
(s1 + s2 + a)(s1 + a)(s2 + 2a)
Then, associating s1 and s2 yields

The procedure for computing Yn(s) from Yn(s1, s2, . . ., sn) is

called association of variables. Although an explicit formula
for performing the associating operation in a large class of
Laplace transforms has been obtained in the literature (see
Rugh (4) and the references herein), this technique has seldom been used. The main reason for this seems to be the tedious manipulations involved and the difficulty in decomposing them onto a computer.
Algebraic Approach
In this part, we show how to compute the response of nonlinear systems to typical inputs. This method, based on the use
of the formal representation of the Volterra kernels Eq. (24),
is also easily implementable on a computer using formal languages like AXIOM (24). These algebraic tools for the first
time enable one to derive exponential polynomial expressions
depending explicitly on time for the truncated Volterra series
associated with response (19) and, therefore, lead to a finer
analysis than pure numerical results.
To continue our use of algebraic tools, let us introduce the
Laplace-Borel transform associated with a given analytic
function input

n0

1
1
(1 jtz0 )1 + (1 + jtz0 )1 = (1 + 2 z20 )1
2
2

Before seeing the algebraic computation itself in order to compute the first terms of the response to typical inputs, let us
introduce a new operation on formal power series, the shuffle
product.
Given two formal power series,
g1 =


wZ

(g1 , w)w and g2 =


wZ

(g2 , w)w

The shuffle product of two formal power series g1 and g2 is

given by
g1  g2 =


w 1 ,w 2 Z

(g1 , w1 )(g2 , w2 )w1  w2

where the shuffle product of two words is defined as follows:

1
(s + a)(s + 3a)

u(t) =

Its Borel transform is given by

gu =

Thus, the associated transform Y2(s) is

1 jt 1 jt
e + e
2
2

an

tn
n!

11 1
z Z, 1z z1 z
z, z Z, w, w Z*
zwzw z[wzw] z[zww]
This operation consists in shuffling all the letters of the two
words by keeping the order of the letters in the two words.
For instance,
z0 z1  z1 z0 = 2z0 z21 z0 + z0 z1 z0 z1 + z1 z0 z1 z0 + z1 z20 z1
It has been shown that the Laplace-Borel transform of expression Eq. (24), for a given input u(t) with the Laplace-Borel
transform gu, is obtained by substituting from the right each
variable z1 by the operator z0[gu ].
Therefore, in order to apply this result, we need to know
how to compute a shuffle product of algebraic expressions of
the form

gn = (1 + a0 z0 )1 zi (1 + a1 z0 )1 zi
1

. . . (1 + an1 z0 )1 zi n (1 + an z0 )1

(28)

where i1, i2, . . ., in 0, 1.

This computation is very simple; it amounts to adding
some singularities. For instance,
(1 + az0 )1  (1 + bz0 )1 = (1 + (a + b)z0 )1

368

VOLTERRA SERIES

Consider two generating power series of the form Eq. (28)

g p = (1 + a0 z0 )

zi (1 + a1 z0 )

(1 + a p1 z0 )

zi

Nonlinear resistor:

1. Current-controlled: v = f(i)
2. Voltage-controlled: i = g(v)

i
v

zi p (1 + a p z0 )1

and

gq = (1 + b0 z0 )1 z j (1 + b1 z0 )1 z j
1

(1 + bq1 z0 )

Nonlinear capacitor:

z j q (1 + bq z0 )

1. Current-controlled: v = f(i)
2. Voltage-controlled: i = d (v)
dt

i
v

where p and q N, the indices i1, i2, . . ., ip 0, 1, j1, j2,

. . ., jq 0, 1, and ai, bj C. The shuffle product of these
expressions is given by induction on the length

g p  gq = g p  gq1 z j q (1 + a p + bq )z0 )1

Nonlinear inductor:

+ g p1  gq zi p (1 + (a p + bq )z0 )1

d
1. Current-controlled: v = dt f(i)
2. Voltage-controlled: i = g(v)
v

See (25) for case-study examples and some other rules for
computing directly the stationary response to harmonic inputs or the response of a Dirac function, and see (26) for the
algebraic computation of the response to white noise inputs.
This previous computation of the rational power series g and
of the response to typical entries has been applied to the analysis of nonlinear electronics circuits (27) and to the study of
laser semi-conductors (28) and (29).

Controlled sources: Voltage-controlled voltage-source

Current-controlled voltage-source

w(t) =

n1

w(t) =



n

z( ) d

bn


I+
v = r(ix)

Description of Nonlinear Circuits. Most of the nonlinear

electronic circuits encountered can be described in terms of
elementary nonlinear components such as nonlinear resistors,
capacitors, inductors, and independent sources which are usually represented as shown in Fig. 4, where v and i denote,
respectively, the voltage across a branch of the circuit and the
current flowing in it; vx and ix are respectively, a voltage and
a current controlling variable. Representations 1 and 2 correspond, respectively, to impedance and admittance descriptions of the nonlinear element.
Note that elements that operate in a monotonic region of
their characteristic possess both representations. These components generally operate in a region where their behavior is
described by a power series expansion on their quiescent or
DC points. These expansions can be expressed in one of the
following general forms which correspond to the Taylor
expansions of the functions f, g, , r, and :

w(t) =
an zn (t)
n1

I+
v = (vx)

Application to Nonlinear Circuits

(29)

d 
cn zn (t)
dt n1

Depending on the nonlinear element considered and on its

representation (impedance or admittance), w and z may represent either a current or a voltage incremental variable. z is
called the controlling variable and w the controlled one. Note
that even when both representations 1 and 2 exist for an element, it may be preferable to use the one of which the power

Voltage-controlled current-source
i = g(vx)
Current-controlled current-source
i = (vx)
Figure 4. Representation of lumped electronic nonlinear elements.

series expansion Eq. (29) is more rapidly convergent. Separating the summations in Eq. (29) into a linear part plus secondand higher-order terms suggests that each nonlinear element
may be seen as a parallel (if w is a current) or a cascade (if w
is a voltage) combination of a linear element (n 1) and a
strictly nonlinear element (n 2). This leads to an equivalent
representation of the nonlinear elements given in Fig. 5.
Let us first consider these strictly nonlinear elements as
independent sources and modify the circuit by imbedding the
linear component of each nonlinear element into the linear
circuit. This results in a linear circuit called the modified linear circuit. Using Kirchhoff s current and voltage laws, a
standard linear analysis can be carried out.
To avoid dealing with certain types of networks whose
functional representation may fail to exist, we shall assume
that the networks meet certain requirements.
Consider each nonlinear capacitor (inductor) described by
an admittance (impedance) representation and its associated
nonlinear independent current (voltage) source. Let i and v
denote, respectively, the source current and its branch voltage. Assume that all the other independent current (voltage)
sources, inputs and sources associated with the other nonlin-

VOLTERRA SERIES
Impedance
representation
i

Admittance
representation

i(t)

369

v(t)

i
R = f1

R=

e(t)

1
g1

i(t)

I+ gNL(v)

I+ fNL(i)

i=

i
1
R=
f1

C = g1

I+

I+ fNL(i)

d
dt gNL(v)

i
L = f1

L=

1
g1

I+ gNL(v)

d
dt fNL(i)

I+

g(x) = g1x + gNL(x)

f(x) = f1x + fNL(x)

d 2
v
dt

Figure 7. Modified linear circuit.

cuit (shown on Fig. 7), the nonlinear capacitor, which consists

only of a strictly nonlinear element, has been replaced by an
independent current source. In order to show that the hypothesis H1 is not verified (the capacitor being described in an
admittance form), the independent voltage source is short circuited, and the linear transfer function, linking the current i
through the current source and the voltage across it, must be
searched for: here (v/i) R, which is obviously not a strictly
proper rational function. The nonlinear differential equation
describing the behavior of this circuit is
e + vv = v

I+
v = (vx)

I+ 1 vx

I+

I+ NL(vx)

r1 vx

I+ rNL(vx)

v = r(vx)

(x) = 1x + NL(x)

v0 = e,

1i x

gNL(v)

Figure 5. Equivalent representation of the nonlinear elements.

ear elements, are open circuited (short circuited), and that

all independent voltage (current) sources, inputs and sources
associated with nonlinear elements, are short circuited (open
circuited); then, the linear transfer function linking i and v
and associated with the resulting linear circuit must be
strictly proper. Recall that in linear system theory, a rational
function G(s) is said to be strictly proper if G() 0.
Circuits which do not satisfy H1 or H2 depend on an infinite
number of higher-order derivatives of some inputs. An example of this situation is provided by considering the circuit of
Fig. 6. For the modified linear circuit associated with this cir-

i(t)

e(t)

n1

v = e + ee + 2e(e)
2 + e2 e +

NL(v)

(x) = 1x + NL(x)

g(x) = g1x + gNL(x)

vn = e + vn1 v n1 ,

yielding

i = (vx)

i = g(vx)

(30)

which can be solved iteratively following the Picard iterative

scheme

r(x) = r1x + rNL(x)

g 1v x

I+

(31)

Expression Eq. (31) makes explicit the dependency of v on

the derivatives of the voltage input e. On the other hand, Eq.
(30) can be solved analytically, at least for a constant input
voltage e. One finds
!
v"
v + e log 1
=t
e
which must be considered only for t 0. This formula shows
that the solution has a nondefined first-order derivative at
zero which is a sufficient condition for the nonexistence of a
Volterra analytical functional expansion of the solution v(t).
The modified linear circuit must be well-behaved. This
means that the modified linear circuit possesses a unique defined solution, and that, in particular, no circuit variable
tends to infinity with the input frequency. For example, the
nonlinear circuit of Fig. 8 with its linear modified linear associated circuit shown on Fig. 9 does not satisfy H3.

i1

i3

v(t)
v1

i = d v2
dt
Figure 6. Example of a nonlinear circuit.

vs

is

v2

v3

i2
Figure 8. A nonlinear circuit: v1 f(i1); v2 h(i2); v3 r( i3).

370

VOLTERRA SERIES
+

f1
vs

v1

NL
+

v2NL

v3NL
+

Using E3, E1 and E2 can be written:


#
h(i2 ) + r( (i2 is )) = 0

vs = f (is ) + h(i2 )

is
h1

r1

Figure 9. Circuit obtained from that of Figure 8 by imbedding the

linear part of the nonlinear elements into the linear circuit.

(32)

Derivation of the Generating Power Series Associated with Nonlinear Circuits. Using the algebraic approach described earlier,
it is not difficult to derive the generating power series associated with the unknown variables of the set of equations obtained from E3, E1, and E2. Instead of showing this in general,
let us here illustrate the main ideas through the above example of Fig. 8. Given

Note that in practical circuits, H1, H2, and H3 are generally fulfilled.

f (i) =

f n in

n1

Descriptive Equations. Any lumped circuit obeys three basic

laws: Kirchhoff s voltage law (KVL), Kirchhoff s current law
(KCL), and the elements law (branch characteristics). Let
each passive nonlinear element (resistor, capacitor, inductor)
be described by its controlling variable: current, if it has an
impedance representation, or voltage for the admittance. Let
the current sources be described by the voltages across their
branches and the voltage sources by the currents flowing in
their branches. For a nonlinear circuit containing p branches
and n nodes, one may then write n 1 KCL equations and
p (n 1) KVL equations. Finally, if one keeps in these
equations only the descriptive variables using the branch
characteristics, one gets p equations linking the p unknown
variables. These equations are of three types:
E1: Dynamical equations. These are generally integrodifferential equations linking a set, as reduced as possible, of variables of the circuit to be described totally.
E2: Output equations. These are functions connecting
variables described by the dynamical equations to the
remaining variables.
E3: Reduction equations. These equations are linear;
they allow the number of unknowns in the previous set
of equations to be reduced. They correspond to
1. KCL at nodes joining only passive elements described in an admittance form or independent current input sources or dependent voltages sources if
the current flowing through their branch appears as
a controlling variable of another element.
2. KVL for loops containing only passive elements described in an impedance form or independent voltage
input sources or dependent current sources if the
voltage across their branch appears as a controlling
variable of another element.
For example, let us consider again the nonlinear circuit of
Fig. 8. This circuit is described by the following set of equations derived as shown previously:

#
E1 h(i2 ) + r( i3 ) = 0
E2 vs = f (i1 ) + h(i2 )

is = i1
E3
i1 + i3 = i2

h(i) =

hn in

n1

and

#
#
r( i) =
rn ( i)n
n1

If g2 and gs denote the generating power series associated respectively with i2 and is from Eq. (32), we obtain the following
set of algebraic equations


n
n
=0
n1 hn g2 +
n1 rn (x0 g2 x1 )
(33)


n
n
gs = n1 hn g2 + n1 f n gs
where gn g . . . g (n-times). From the algebraic rules
defined earlier, we can derive iteratively the expressions for
[g]i, the power series containing exactly i occurrences of the
letter x1 in g.
These computations are easily implementable on a computer using a formal computing software. In the same way,
we can systematically derive the response to typical inputs as
we previously described. In the last two parts, we use these
Volterra series expansions in a time domain in order to derive
physical quantities like signal distortions or intermodulation
products.
DISTORTION ANALYSIS
In this part, we are interested in the analysis of the response
of weakly nonlinear systems driven by harmonic inputs.
When the input signal is of the form sin(t), its response is
in general also periodic, but the output signal contains components with a multiple integer of the input pulsation. When
the signal input is composed of two harmonics of pulsation
1 and 2, respectively, then the output signal is a sum of
harmonics with pulsation p1 q2, where p and q are negative or positive integers.
The study of the harmonic components of the response is
of great importance in the study of distortions existing in nonlinear circuits, like the transistors, the amplifiers, the modulators, etc. One can cite, for instance, the works of Bedrosian
and Rice (15), Goldman (30), Narayanan (31,32), Bussgang,
Ehrman and Graham (16) and Crippa (33). A Volterra series
offers an efficient tool for this study because for weakly non-

VOLTERRA SERIES

linear systems, often only first, second, and third terms of the
Volterra series are sufficient in order to obtain significant
quantitative results.

with Ak Akeik, the response of the system is given by

Harmonic Analysis

with

Let us consider a stationary nonlinear system described by

the Volterra series




y(t) =

t1

tn

n=1 0

y(t) = y1 (t) + y2 (t) + + yn (t) +

yn (t) =

1
2n1


mM, m 0

n!
|A |(m 1 +m 1 )
(mK )! . . . mK !) 1

. . . |A1 |(m K +m K ) |Hn ()| cos(m t + m + Arg|Hn ()|)

(38)

hn (t 1 , t 2 , . . ., t n )u(1 )u(2 )

. . . u(n ) d1 d2 . . . dn

where

(34)

 = (K , . . ., K , . . . K , . . .K )
  
  

The output of this system driven by the input is

m K

1
u(t) = |A1 | cos(1t + 1 ) = (A1 ei 1 t + A1 ei 1 t )
2

and m (mK, . . ., m1, m1, . . ., mK) is such that mK

m1 m1 mK n. Therefore, in the terms of
yn with n 1 we find

y(t) = y1 (t) + y2 (t) + + yn (t) +

with
+1
+1


i
1 

A j . . . A j n Hn j , . . ., j n e
n
1
1
2 j =1 j =1

j ++ j
1

mK

m = (mK mK )K + + (m1 m1 )1

where A1 A*1 A1e i1 is given by

yn (t) =

371

Terms with the same pulsation as the input one

Terms with a pulsation equal to an integer multiple of
one of the input pulsations (harmonic terms)
Terms resulting in an interference between several input
pulsations (intermodulation terms)

(35)
Nonlinear Distortions
where Hn(j1, . . ., jn) is the multidimensional Laplace transform of hn(t1, t2, . . ., tn). The Laplace transform Hn is, like
hn, a symmetric function. This allows regrouping identical
terms in expression Eq. (35). In order to do so, let us denote
by m1(m1) the occurrence number of the pulsation 1(1) in
(j1, . . ., jn). Equation (35) may also be written

yn (t) =

1
2n


mM,m=(m 1 ,m 1 )

n!
(A )m 1 (A1 )m 1
(m1 )!m1 ! 1

Hn (1 , . . ., 1 , 1 , . . ., 1 )ei(m 1 m 1 ) 1 t

Distortion Rate. Let us consider the signal input

(36)

where M represents the set of the couples (m1, m1), such that
m1 m1 n. By regrouping conjugate complexes in Eq. (36),
we obtain

yn (t) =

1
2n1

mM,m 1 m 1

n!
|A |(m 1 +m 1 )
(m1 )!m1 ! 1

|Hn (1 , . . ., 1 , 1 , . . ., 1 )| cos((m1 m1 )1t (37)



   
m 1

The analysis of the resulting spectrum is of great importance

in numerous electronic applications. In order to characterize
nonlinear circuit performances, several nonlinear distortion
rates have been introduced in the literature depending on the
application considered. The most popular are described in the
following sections.

m1

u(t) = |E1 | cos 1t

of a weakly nonlinear system described by Eq. (34). As previously discussed, the first terms of the output are of the form
A0 + |A1 | cos(1t + 1 ) + |A2 | cos(21t + 2 ) +
The amplitude of the various harmonic terms is not really
significant. On the other hand, their ratio with respect to the
amplitude of the fundamental frequency of the input signal
may serve as a distortion measure. The distortion ratio of the
k-th harmonic is defined as

+ (m1 m1 )1 + Arg|Hn (m)|)

For a signal input with pulsation 1, the response of a weakly
nonlinear system is, therefore, periodic, and it is composed of
multiple integer terms of this pulsation.
More generally, it can be shown that for a multi-pulsation
input signal of the form

u(t) =

K

k=1

|Ak | cos(k t + k ) =

1
2

k=K

k=K ,k = 0

Ak ei k t

|A1 |
|Ak |
Harmonic Distortion Rate. The value of this rate indicates
the global relative importance of the output harmonic level
with respect to the fundamental frequency term. It is defined
by

|A2

|2

|A1 |2
+ |A3 |2 +

372

VOLTERRA SERIES

Gain Distortion. Let us consider again the input signal

u(t) = |E1 | cos 1t

Technical results on the output signal may be found in the

paper by Meyer, Shensa and Eschenbach (34).
Note that the algebraic framework described earlier allows
us to easily compute all the previous distortion rates (35).

and the fundamental frequency output

|A1 | cos(1t + 1 )
Given a linear system A1 E1H1(i1), where H1 is the transfer
function, the ratio
|A1 |
= |H1 (i1 )|
|E1 |
is a classic definition of the linear gain. For a nonlinear system, the contributions to the fundamental frequency of the
higher-order Volterra kernel are nonzero in general. For a
fixed input frequency, the gain is no longer constant but depends on the amplitude of the input:
|A1 |
3
= |H1 (i1 ) + |E1 |2 H3 (i1 , i1 , i1 ) + |
|E1 |
4
Intermodulation. Let us now consider an input of the following form
u(t) = |E1 | cos 1t + |E2 | cos 2 t
The 2nd-order intermodulation ratio (IMR2) is defined as the
difference (dB) between the level of the output signal at the
fundamental frequency and the level of the distortion term at
the frequency 1 2 or 1 2. The 3rd-order intermodulation ratio (IMR3) is defined in the same way, that is, the difference of the level of the output signal at the fundamental
frequency and the level of the distortion term at the frequency 21 2 or 1 22 or 21 2 or 1 22, and so
on. In general, the measure of the intermodulation terms is
taken by choosing the input with the same amplitude E,
|E1 | = |E2 | = |E|
and neighboring pulsations,
1 

and 2 

From the previous part it is not difficult to see that, for instance,
IMR2(1 2 ) =

|H1 ()|
|E H2 (, )|

and
IMR3(21 2 ) =

4|H1 ()|
3|E|2 |H3 (, , )|

BIBLIOGRAPHY
1. N. Wiener, Nonlinear Problems in Random Theory, New York:
Wiley, 1958.
2. J. Barrett, The use of functionals in the analysis of nonlinear
physical systems, J. Electronics Control, 15: 567615, 1963.
3. D. George, Continuous nonlinear systems, MIT RLE Technical
Report No. 355, 1959.
4. W. J. Rugh, Nonlinear System Theory, Baltimore, MD: John Hopkins Univ. Press, 1981.
5. M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems, New York: Wiley, 1980.
6. V. Volterra, Theory of Functionals (translated from the Spanish),
London: Blackie, 1930 (reprinted by Dover, New York, 1959).
7. M. Schetzen, Nonlinear system modeling based on the Wiener
theory, Proc. IEEE, 69 (12): 1981.
8. M. Brillant, Theory of the analysis of nonlinear systems, MIT
RLE Technical Report No. 345, 1958.
9. J. Blackman, The representation of nonlinear networks, Syracuse
University Research Institute, Report No. 81560 for Air Force
Cambridge Research Center, Cambridge, Mass,
10. C. Lesiak and A. J. Krener, The existence and uniqueness of Volterra series for nonlinear systems, IEEE Trans. Autom. Control,
23: 10901095, 1978.
11. R. W. Brockett, Volterra series and geometric control theory, Automatica, 12: 167176, 1976. R. W. Brockett and E. G. Gilbert,
An addendum to Volterra series and geometric control theory,
Automatica, 12: 635, 1976.
12. E. G. Gilbert, Functional expansions for the response of nonlinear
differential systems, IEEE Trans. Autom. Control, 22: 909921,
1977.
13. C. Bruni, G. Di Pillo, and G. Koch, On the mathematical models
of bilinear systems, Ricerche di Automatica, 2 (1): 1971.
14. S. Boyd and L. O. Chua, Fading memory and the problem of approximating nonlinear operators with Volterra series, IEEE Circuits Syst., 32 (11): 11501161, 1985.
15. E. Bedrosian and S. Rice, The output properties of Volterra systems (nonlinear systems with memory) driven by harmonic and
Gaussian input, Proc. IEEE, 59: 16881707, 1971.
16. J. Bussgang, L. Ehrman, and J. W. Graham, Analysis of nonlinear systems with multiples inputs, Proc. IEEE, 62: 10881119,
1974.
17. L. O. Chua and C. Y. Ng, Frequency domain analysis of nonlinear
systems: general theory, Electronics Circuits and Systems, 3 (4):
165185, 1979 and Frequency domain analysis of nonlinear systems: formulation of transfer functions, Electronics Circuits and
Systems, 3 (6); 257269, 1979.
18. R. H. Flake, Volterra series representation of nonlinear systems,
IEEE Trans. Ind. Appl., 81: 330335, 1963.
19. M. Fliess, M. Lamnabhi, and F. Lamnabhi-Lagarrigue, Algebraic
approach to nonlinear functional expansions, IEEE Circuits Syst.,
30: 550570, 1983.

Transmodulation. In order to analyze the transmodulation,

that is the effect that a modulation is transferred from one
signal to another through a weakly nonlinear system, the following input signal is considered

20. M. Fliess, Fonctionnelles causales non lineaires et indeterminees

non commutatives, Bull. Soc. Math. France, 109: 340, 1981.

u(t) = |E|(1 + m cos m t) cos 1t + |E| cos 2t

21. W. Grobner, Die Lie-Reihen und ihre Anwendungen (2e edition),

VEB Deutscher Verlag der Wissenschaften, Berlin: 1967.

VOLUME VISUALIZATION
22. F. Lamnabhi-Lagarrigue and G. Stefani, Singular optimal control
problems: On the necessary conditions for optimality, SIAM J.
Contr. Optim., 28: 823840, 1990.
23. F. Lamnabhi-Lagarrigue and M. Lamnabhi, Determination algebrique des noyaux de Volterra associes certains syste`mes non lineaires, Ricerche di Automatica, 10: 1726, 1979.
24. A. Martin, Calcul dapproximations de la solution dun syste`me
non lineaire utilisant le logiciel SCRATCHPAD, in G. Jacob and
F. Lamnabhi-Lagarrigue (eds.), Algebraic Computing in Control,
Lect. Note Contr. Inform. Sc., Springer Verlag, 165, 1991.
25. F. Lamnabhi-Lagarrigue, Analyse des syste`mes non lineaires, Ed.
Hermes, 1994.
26. M. Fliess and F. Lamnabhi-Lagarrigue, Application of a new
functional expansion to the cubic anharmonic oscillator, J. Math.
Physics, 23: 495502, 1982.
27. S. Baccar, F. Lamnabhi-Lagarrigue, and G. Salembier, Utilisation du calcul formel pour la modelisation et la simulation des
circuits electroniques faiblement non lineaires, Annales des Telecommunications, 46: 282288, 1991.
28. L. Hassine et al., Volterra functional series expansions for semiconductor lasers under modulation, IEEE J. Quantum Electron.,
30: 918928, 1994.
29. L. Hassine et al., Volterra functional series for noise in semiconductor lasers, IEEE J. Quantum Electron., 30: 25342546, 1994.
30. J. Goldman, A Volterra series description of crosstalk interference in communications systems, Bell Syst. Tech. J., 52: 649
668, 1973.
31. S. Narayanan, Transistor distortion analysis using Volterra series representation, Bell Syst. Tech. J., 46: 9911024, 1967.
32. S. Narayanan, Application of Volterra series to intermodulation
distortion analysis of a transistor feedback amplifier, IEEE
Trans. Circuit Theory, 17: 518527, 1970.
33. G. Crippa, Evaluation of distortion and intermodulation in nonlinear transmission systems by means of Volterra series expansion, Alta Frequenza, 38: 332336, 1969.
34. R. G. Meyer, M. J. Shensa, and R. Eschenbach, Cross-modulation
and intermodulation in amplifiers at high frequencies, IEEE
Solid State Circuits, 7: 1623, 1972.
35. M. Fliess and M. Lamnabhi, Application dune technique nouvelle
de calculs de developpements fonctionnels a` la determination de
distortions non lineaires, Proc. Huitie`me Colloque sur le Traitement du Signal et ses Applications, Nice, 1981.

FRANCOISE LAMNABHI-LAGARRIGUE
Laboratoire des Signaux et Syste`mes
Centre National de la Recherche
Scientifique
Ecole Superieure d Electricite
(Supelec)

VOLTOHM METERS. See MULTIMETERS.

VOLT RAMP GENERATION. See RAMP GENERATOR.

373

240

SYNCHRONOUS CONVERTER TO BOOST BATTERY VOLTAGE

SYNCHRONOUS CONVERTER TO BOOST

BATTERY VOLTAGE
Disposable alkaline batteries are used in many portable devices because of their low cost and their availability. Although
not typically exploited by the device power converter, a singlecell alkaline battery has useful capacity from 1.6 V down to
below 1 V. By extending the input voltage range of the converter to operate over the usable voltage range of the cell, the
runtime of the portable device can be increased significantly.
The boost converter presented in this article will start up and
deliver full rated current with a 1 V input and operate down
to 0.4 V. Maximum battery utilization is realized by integrating low on-resistance switches, synchronous rectification, and
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

SYNCHRONOUS CONVERTER TO BOOST BATTERY VOLTAGE

an adaptive current mode control scheme. The converter develops multiple output voltages from a single inductor using
a multiplexing technique.
BACKGROUND
The rapid growth of portable equipment has been fueled by
strong customer demand that has resulted from significant
advances in digital and radio frequency (RF) technologies.
Features such as e-mail, global positioning systems (GPS),
and two-way communications are making handheld portable
instruments more versatile, while many of these new features
increase the power demands on the battery. Although battery
performance is improving with the introduction of new chemistries, it has not kept pace with the increased functionality
found in todays portable equipment. Switch mode power conversion can offer efficiency improvements when compared to
linear techniques, increasing battery utilization. Unique challenges exist, however, in implementing a switch mode solution for a battery-powered system. Portable devices have a
wide dynamic load range that can vary from a few milliwatts
to hundreds of milliwatts. Many portable devices require the
converter to operate off the voltage of a single cell, which,
depending on the power level of the application, can pose a
significant challenge.

241

Open circuit voltage was measured by removing the load for

10 s each minute.
Battery equivalent series resistance (ESR) is shown in Fig.
1 to have a large influence on the actual voltage measured at
the terminals. A battery with 1.1 V at no load, for example,
will drop to 0.9 V with a 500 mA load. The power conversion
circuitry will need to handle the low-voltage droop during
these peak power durations. This can often be the limiting
factor in the ability to deliver sufficient output power to the
application.
ACHIEVING HIGH EFFICIENCY OVER A WIDE
DYNAMIC RANGE
The batterys energy capacity and the converters efficiency
will determine the available run-time of the device. Portable
equipment may require hundreds of milliamps when the device is fully functioning. In standby mode, where the device
spends a majority of time, the equipment may require less
than 1 mA. The amount of time the device spends in various
modes is heavily dependent upon the user. Because it is difficult to predict how the device will be used, it is important
that the converter operates efficiently over a wide dynamic
load range.
Discontinuous Mode Efficiency

Battery terminal voltage

Alkaline is the disposable battery of choice for portable devices because of a low self discharge (about 5% a year) and a
high energy density. For many applications, such as two-way
pagers, the average load on the alkaline battery is low but
the peak load can be over 500 mW. This can equate to peak
currents of more than 500 mA from a single cell. Figure 1
shows the voltage of an AA battery discharged at 500 mA.

An analysis of the converter losses can provide insight into

determining a control scheme that will operate efficiently.
Figure 2 shows a low-voltage synchronous boost converter
along with the equivalent circuit elements that are major contributors to power loss. Switch capacitance has been reflected
to the gate for simplicity.
To support a wide dynamic load range with a reasonably
small value of inductance, the boost converter must operate
in discontinuous conduction mode at medium and light loads.

1.5

0.55

1.4

0.5

1.3

0.45

1.2

0.4

1.1

0.35
0.3

1
0.9

0.25
Open circuit
500 mA load
Effective battery ESR

0.8
0.7
0.6

Battery ESR ()

DISPOSABLE ALKALINE CELL PERFORMANCE

10

20

30

40

50

60

0.2
0.15

70

Time (min)

80

90

100

110

0.1
120
Figure 1. AA alkaline battery voltage at
a 500 mA discharge rate.

SYNCHRONOUS CONVERTER TO BOOST BATTERY VOLTAGE

Rind

S2

Table 1. Input and Lost Energy for a Single Conversion

Cycle in Discontinuous Conduction Mode

Rs2

L
Rs1

Rbat

Vbat

Cg

S1

Rcap

Figure 2. Synchronous boost converter and equivalent circuit elements.

Inductor
current

Figure 3 shows inductor current in discontinuous conduction

mode.
Discontinuous mode efficiency can be calculated from the
input and loss energy for a single conversion cycle. Based of
Figs. 2 and 3, Table 1 gives approximate energy values and
the resulting overall efficiency.
These equations can now be used to determine the optimum peak inductor current for the converter in discontinuous
conduction mode. Figure 4 shows the losses and overall efficiency versus peak current of an integrated boost converter
with a 1.5 V input and a 3.3 V, 5 mA output.
As shown in Fig. 4, conduction losses dominate with large
peak currents, where switching losses dominate with small
peak currents. The optimum peak current in this case is
around 250 mA. It is interesting to note that if the load current is increased to 20 mA, or decreased to 1 mA, the optimum peak current is still 250 mA. In fact, in discontinuous
conduction mode, the optimum peak inductor current is independent of load current.
The reason this occurs can be seen by looking at the equations in Table 1 that detail the energy of a single conversion
cycle. Input energy is related to peak current and, for a given
value of peak current, is fixed with no dependence on the load
current. The conduction energy lost during a single conversion cycle is also fixed for a given peak current regardless
of the load. The switching energy lost is only related to gate
capacitance and gate drive voltage. The IDD energy lost during
a single conversion cycle is affected by the conversion period
Tcyc, which is a function of load current. As Tcyc increases at
light loads, the IDD energy lost will also increase, thereby reducing efficiency. IDD losses (EIDD /Ein) show up as an offset in
efficiency however (see Fig. 4), which means that IDD will

Tbst

Conduction energy
lost
Where

Cg
Cout

Tch

1
E in I peak V bat (T ch T bst )
2
I 2peak
E cond
(R ch T ch R bst T bst )
3

Input energy

Ipeak

Switching energy lost

R ch R bat R ind R s1
R bst R bat R ind R s2 R cap
E sv 2 C g V 2g

Control chip quiescent

current (I DD ) energy
lost

E IDD V DD I DD T cyc

Resulting efficiency
(%)

Efficiency 100 1

(E cond E sw E IDD )
E in

change the efficiency with respect to load current, but not to

the optimal peak current.
Because discontinuous mode efficiency (for a given converter) is optimized at only one peak current, a control technique that maintains a constant peak current should be selected. With a fixed frequency control technique, the amount
of energy delivered to the load is adjusted by keeping the cycle time fixed and by controlling the peak current in the inductor. Because peak current is varied, this technique does
not offer good efficiency over a wide dynamic load range. With
pulsed frequency modulation (PFM), the cycle time, rather
than the peak current, is adjusted to accommodate load variations. This allows an optimal peak current that will maximize
efficiency in discontinuous conduction mode to be chosen.
Synchronous Boost Converter Description
The UCC3941 is a 500 mW boost converter that incorporates
a PFM control technique. The part is available in three versions, depending on the voltage of the main output: 3.3 V, 5
V, or adjustable. Figure 5 shows a simplified block diagram of
the UCC3941s internal control circuitry along with a typical
applications circuit.
All necessary control circuitry is integrated into an eightpin chip along with synchronous MOSFET switches. Few ex-

Efficiency / losses (%)

242

Optimal
Peak
current

100

Efficiency
50

Switching losses
(Esw/Ein)

0.1

0.25

IDD losses
(EIDD /Ein)

0.5

Conduction losses
(Econd / Ein)

Peak current (A) 1.0

Vin = 1.5 V, Vout = 3.3 V, Iout = 5 mA, Vdd = 8 V, IDD = 20 A,

Cg = 400 pF, L = 22 H, Rch = 0.55, Rbst = 0.75

Tcycle
Figure 3. Discontinuous mode inductor current.

Figure 4. Boost converter efficiency vs. peak current for a 5 mA

output.

SYNCHRONOUS CONVERTER TO BOOST BATTERY VOLTAGE

10 F

243

+
0.08 V to Vout = 0.5 V

22 F

8V
VGD

Vin

SW

0.4
Start-up
circuitry

Vout
100 F

0.25

10 F

For adjustable version only

UCC3941-3 = 3.3 V
UCC3941-5 = 5.0 V
UCC3941-ADJ = 1.30 V to 6 V

Modulator control circuit

Synchronous rectification circuitry
Anti-cross conduction
Start-up
Multiplexing logic
Maximum input power control
Adaptive current control

SD

PLIM

Open = SD

UCC3941-ADJ

SGND

+
7

PGND

For UCC3941-ADJ Pin 7 = Sgnd & Pgnd. Pin 6 = Output sense feedback.
Figure 5. UCC3941 Simplified block diagram and application circuit.

ternal components are required, minimizing the board area

for the converter. Low quiescent currents are achieved by
turning off sections of control circuitry during periods of inactivity. Conduction losses are minimized through the use of
low RDSON switches. Equation (1) describes the relationships
that determine the RDSON for a MOSFET.

1

W
uCox
(VGS VT )
Leff

200

(1)

RDSON is inversely proportional to gate drive voltage (VGS) minus the threshold voltage (VT 0.7 V). Other parameters in
the equation are fixed for a given switch geometry and silicon
process. By generating an 8 V supply (VGS) for the gate drive
rather than using the main output voltage Vout, conduction
losses are lowered by a factor of 2 to 3. Using 8 V achieves
the best overall efficiency compromise between switching and
conduction losses for the converter. The 8 V output can be
used to support an additional 10 mA of load current for applications requiring an auxiliary output. By lowering conduction
losses, the converter can deliver more current to the load at
low battery voltages.
Figure 6 shows the output current capabilities of several
low power boost converters with integrated MOSFETs. As the
graph indicates, the load current capability of most converters

180
Maximum load current (mA)

RDSON = 

decreases significantly at low battery voltages. Converter 1

operates in discontinuous conduction mode and has limited
current capabilities. Converters 2 and 3 increase their output
current capabilities with continuous mode operation, but
their ability decreases at low input voltages. The UCC3941

160
140
UCC3941
Converter 1
Converter 2
Converter 3

120
100
80
60
40
20
0
0.8

0.9

1.1

1.2

1.3

1.4

1.5

Battery voltage (V)

Figure 6. Output current capabilities of boost converters with 3.3

V outputs.

244

SYNCHRONOUS CONVERTER TO BOOST BATTERY VOLTAGE

achieves improved capability by combining low RDSON switches

with continuous mode operation.

UCC394 Efficiency
L = 22 H
100

Continuous Mode Operation

Imax

1
Vbat

(2)

By using a hysteretic control technique, the stability problem

of crossing the continuous/discontinuous mode boundary has
been eliminated. A detailed description of how the converter
transitions between modes and controls the current in the inductor is given in the section entitled [Multiplexed Waveforms.]
Efficiency Curves
Continuous conduction mode allows increased output power,
whereas discontinuous PFM mode delivers optimal efficiency
at light loads. The modes of operation are controlled with an
internal state machine that adjusts charge times and current
limits. By providing efficient conversion over the usable battery voltage in both modes, operation time is maximized. Figure 8 shows UCC3941 efficiencies over a 200 : 1 load range.
The upper curve is typical of a Lithium-Ion input and a 5
V output. The lower curve is typical of a single-cell alkaline
input and a 3.3 V output. The converter can deliver 200 mA
to the load, while maintaining good efficiency down to 1 mA.

Inductor
current

Imax (varies with input voltage)

Ipeak(with input voltage)

90
Efficiency (%)

Discontinuous conduction mode results in a simple control

scheme; however, the average load current (reflected to the
input) is limited to less than half the peak current. If the
peak inductor current is increased, efficiency and the output
voltage ripple will suffer. In order to provide increased load
current, the UCC3941 is allowed to transition into continuous
conduction mode (see Fig. 7). In order to keep the control
scheme simple, while providing the ability to generate multiple outputs, a pseudo continuous conduction mode is implemented.
Referring to Fig. 7, if a single discontinuous mode energy
pulse is not sufficient to bring the main output into regulation, the current in the inductor is allowed to increase until a
maximum current Imax is reached. The Imax level is programmable for the load requirements of the device so that conduction losses can be minimized. The best continuous mode efficiency is achieved when Imax is set just high enough to provide
for the peak load current of the particular application. To
maintain constant input power capability, Imax is automatically varied when battery voltage decreases as follows:

80
70
Vin = 3.6 V, Vout = 5 V
Vin = 1.5 V, Vout = 3.3 V

60
50

10

100

1000

Load current (mA)

Figure 8. Efficiency as a function of load current and input and output voltage.

GENERATING MULTIPLE OUTLETS

In many portable applications, multiple output voltages are
required. The additional voltage may be needed to drive an
LCD display, interface logic circuits with a higher voltage
driver, provide bias voltage for op-amp circuits, or generate a
trickle charger for a backup battery. The design challenge is
to provide additional outputs without increasing board real
estate or compromising efficiency.
Traditional Choices
When multiple output voltages are required from a switching
regulator, the circuit designer has traditionally been limited
to a small number of topology choices. A multitap transformer
solution in a forward or flyback configuration can provide
multiple positive or negative outputs. This solution generally
requires custom magnetics with the associated design, cost,
and purchasing headaches. Typically, a single output is chosen for regulation, whereas the remaining outputs will have
some level of cross-regulation dependent upon the loading. If
more accurate regulation is required, a magnetic amplifier or
post regulator can be used, but the additional board real estate and cost are usually prohibitive for portable applications.
A linear regulator is generally employed if regulation on the
secondary outputs is required.
At low power levels, charge pump circuits are often used
to generate additional output voltages. Voltage doublers and
triplers, as well as voltage inverters, can be implemented
with inexpensive diodes and capacitors. Designed with discrete components, parts count can escalate with only a few
additional outputs. Efficiency is generally compromised with
this technique because of the presence of large currents during the charge transfer process. If the output voltage is not
an integer multiple of the source voltage, some sort of regulation is needed to bring the charge pumped voltage to a desired
value. Integrated charge pump solutions exist where the voltage is regulated and the charge current is controlled, thereby
improving efficiency; however, a separate integrated circuit
(IC) is generally required.
Multiplexed Coil Technique

Reduced load current

Increased load current

Figure 7. Adaptive current mode control.

Time

The UCC3941 incorporates a unique multiplexed coil technique to generate multiple outputs from a single inductor. En-

SYNCHRONOUS CONVERTER TO BOOST BATTERY VOLTAGE

Dpos
Vgd
Sout

Vout

+
8V

+
Vbat

Smain

3.3 V or
5V

Multiplexed Waveforms

The UCC3941 converter develops a hysteretic control technique by monitoring the output voltages with comparators. If
an output falls below its voltage threshold, the converter will
deliver a single or multiple energy pulses to the output until
the output comes into regulation. The inductor charge time is
controlled by: Ton 12 s/Vin. In discontinuous conduction
mode, this results in a constant peak current, regardless of
the input voltage. For a 22 H inductor, the resulting peak
current is approximately 500 mA. The on time control is
maintained, unless the inductor current reaches the Imax limit.
The inductor discharge time is fixed at Toff 1.7 s, unless
the output rises above its voltage threshold. The short off
time allows the inductor current to transition to the Imax limit
if a single pulse is not adequate. If the output voltage is satisfied after the 1.7 s off time, the charge switch will not be
activated, and the inductor current will decay to zero.
Figure 11 depicts typical voltage and current waveforms of
the converter servicing two outputs. At time t1, Vout drops below its lower threshold, and the inductor is charged for 12 s/
Vin. At time t2, the inductor begins to discharge with a minimum off time of 1.7 s. Under lightly loaded conditions, the
amount of energy delivered in this single pulse would satisfy
the voltage control loop, and the converter would not command any more energy pulses until the output again drops
below the lower voltage threshold.
At time t3, the Vgd supply has dropped below its lower
threshold, but Vout is still above its threshold point. This results in an energy pulse to the gate drive supply at t4. However, while the gate drive is being serviced, Vout has dropped
below its lower threshold, so the state machine commands an
energy pulse to Vout as soon as the gate drive pulse is completed (time t5).
Time t6 represents a transition between light and heavy
loads. A single energy pulse is not sufficient to force the output voltage above its upper threshold before the minimum off
time has expired and a second charge cycle is commanded.
Because the inductor does not reach zero current in this case,
the peak current is greater than 0.5 A at the end of the next
charge on time. The result is a ratcheting of inductor current
until either the output voltage is satisfied, or the converter
reaches its programmed current limit. At time t7, the gate
drive voltage has dropped below its threshold, but the converter continues to service Vout because it has highest priority,
unless Vgd drops below 7.6 V.
Between t7 and t8, the converter reaches its maximum current limit that is determined by the programmed power limit
and Vin. Once the limit is reached, the converter operates in
continuous mode with approximately 200 mA of ripple current. A time t8, the output voltage is satisfied, and the converter can service Vgd, which occurs at t9.

ergy pulses stored in the inductor are time shared between

the outputs depending upon loading. Figure 9 shows a simplified schematic of the basic topology.
When either output requires service, Smain turns on and
current ramps up in the inductor to the discontinuous or continuous peak value. The chip then determines which output
will be charged. When Vout is charged, Sout is closed at the
instant Smain is opened. When Vgd is charged, current is forced
through Dpos when Smain is opened. Because of the presence of
large peak currents in the inductor, low ESR capacitors
should be used to maintain low ripple voltages on the outputs.
Arbitration
A priority scheme is required to accommodate multiple supply
voltages, while providing effective start-up and servicing of
the outputs at various load conditions. The arbitration rules
for the 3.3 V version are as follows:
If Vgd 7.6 V, Vgd will get priority for service (start-up)
If Vgd 7.6 V and Vout 3.3 V, Vout will get priority for
service.
If Vgd 8.7 V and Vout 3.3 V, Vgd will get priority for
service.
In order to guarantee an orderly start-up with input voltages below 1V, the gate drive supply Vgd is given priority during start-up. Figure 10 shows oscilloscope waveforms of current and voltage during startup.
At time t0, an internal 200 kHz oscillator toggles the main
switch at 50% duty cycle, and Vgd starts to rise. Vgd gets to a

VGD
5V/DIV

IL
0.5 A/DIV
To

T1 T2 T3 T4
2 ms/DIV

Figure 10. Start-up waveforms.

sufficient voltage at time t1 to run the IC in a normal mode.

At time t2, Vgd has reached its lower threshold of 7.6 V and
the arbitration allows Vout to get started. Vout has reached 3.3
V at time t3, and Vgd is allowed to charge to 8.7 V. At time t4,
both outputs are in regulation, and the converter operates
normally, servicing the outputs as the load demands.

Figure 9. UCC3941 topology.

Vout
1V/DIV

245

Topology Extensions
The multiplexed coil topology can be extended to produce additional outputs. Figure 12 shows a single inductor providing

246

SYNCHRONOUS MOTOR DRIVES

t1

t2

t3

t4

t5

t6

t7

t8

t9

50 mV
P-P
typical

Vgd
voltage
ripple
Vout
voltage
ripple

10 mV
P-P
typical

Imax
Inductor
current
Figure 11. Multiplexed inductor servicing two outputs.

Ipeak

1.7 s

energy to three positive outputs and a negative output. The

generation of the main output Vout and gate drive output Vgd
has been explained. The VNiCd output is a trickle charger for a
nickel cadmium battery backup. In order to produce a fixed,
low-current, trickle charge, the converter delivers low peak
current pulses to the VNiCd output at fixed intervals of time.
A negative voltage Vneg is produced by using a flyback technique with Vout and Vb. Negative current is generated by backcharging the inductor through the Sout switch. When the inductor current reaches some negative peak, Sout is open. Current is then pulled through Dneg, charging the Vneg output. For
the flyback technique to operate correctly, the charge stored
in the Vout capacitor should be several times larger than the
charge stored in the Vneg capacitor.

1.7 s 1.7 s 1.7 s

is achieved with a constant power continuous current mode

and a fixed peak current discontinuous mode. A unique power
conversion topology is used, where multiple outputs are generated from a single inductor, resulting in efficient use of
board space.
BIBLIOGRAPHY
UCC3941 1 Volt Synchronous Boost Converter Data Sheet, Merrimack,
NH: Unitrode Integrated Circuit Corp.
D. Pnina, Make the Right Battery Choice for Portables, Tadiran Electronic Industries.

EDDY WELLS
MARK JORDAN
Unitrode Corporation

CONCLUSION
When selecting a power management solution for a portable
application, it is important that the converter operates efficiently over a wide dynamic range. In order to get the most
energy from a low-voltage power source, the converter should
be able to start up and operate below 1 V during peak load
demands. When additional outputs are required, issues relating to converter efficiency and board real estate can often be
critical.
The UCC3941 addresses these issues by incorporating an
adaptive control scheme that extends the batterys usable
voltage range. High efficiency over a wide dynamic load range

Dpos
SNiCd
Sout

Vbat

VNiCd

Vneg

Smain

Dneg

Vout

6V
+

2.5 V

3.3 V

Figure 12. Single inductor servicing four outputs.

Vgd
+
8V

SYNCHRONOUS GENERATORS. See HYDROELECTRIC

GENERATORS.

SYNCHRONOUS MACHINE DRIVES. See SYNCHRONOUS MOTOR DRIVES.