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Behavioral Description of Hardware

A hardware unit can be described by its input/output mapping without specifying its technology, netlist, or even its data path. It is described similar to
using a conventional programming language. We have mentioned already VHDL is capable of describing the behavior using sequential statements. All
sequential statements are enclosed within the PROCESS block.
Review of the Process Statement
A simple signal assignment is a process which is always active and executing concurrent with other processes within the same architecture. It is
sensitive to signals on its right hand side. As we already know, A process block starts with the key word PROCESS. It may or may not have a label.
It always ends with "END PROCESS;".
PROCESS
(Declarative part)
BEGIN
(Statement part)
END PROCESS

A process can assign value to more than one signal and contain sequential statements.
Declarative part: variable, file, or constant objects can be declared. They are only visible to this process. Signals and constants declared in an
architecture that encloses a process statement can be used inside the process. Such signals are the only means of communication between processes.
Initialization of the process objects is done only once at the beginning of a simulation run. It is not true for a subprogram.
Statement part: is sequential, when it is active, the program flow reaches the last sequential statement, the execution returns to the first statement and
continues. It executes in zero (delta time for signals) time. For selection and assignment: "IF", LOOP", and CASE" statements. Conditional and
selected assignments are strictly concurrent and are not allowed.
Sensitivity List.
Sensitivity list is a mechanism for suspending and subsequently conditionally activating a process. Remember it has the format:
PROCESS (a list of signals)
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-- the process is activated when an event occurs on any of these signals;

-- when the program flow reaches the last sequential statement, the
-- process becomes suspended until ...
-- regardless of any events, processes are executed once at the beginning
-- of simulation run.

Process Example 1:

Let us look at another example of PROCESS (text: Fig 9.8):

-- D-type flip-flop with asynchronous active-high set and reset inputs

-- internal state is used to record the status of the current memory;
-- when an event occurs on rst, set, or clk, the dff process becomes active;
-- when the value of state' changes, the signal assignments to q and qb
-- become active.
-- the 'IF' statement gives a higher priority to the asynchronous
-- inputs than to the clock.
ENTITY d_sr_flipflop IS
GENERIC (sq_delay : TIME := 6 NS; rq_delay : TIME := 6 NS;
cq_delay : TIME := 6 NS);
PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT);
END d_sr_flipflop;
-ARCHITECTURE behavior OF d_sr_flipflop IS
SIGNAL state : BIT := '0';
BEGIN
dff: PROCESS (rst, set, clk)
BEGIN
IF set = '1' THEN
state <= '1' AFTER sq_delay;
ELSIF rst = '1' THEN
state <= '0' AFTER rq_delay;
ELSIF clk = '1' AND clk'EVENT THEN
state <= d AFTER cq_delay;
END IF;
END PROCESS dff;
q <= state;
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qb <= NOT state;

END behavior;

Now internal state is realized by the use of a signal - state. There are three
concurrent statements in the architecture body : one is the PROCESS and the
other two are the dataflow assignment of q and qb. Therefore, there are two
simulation cycles between input and output changes: One for assignment of
values to state', and one for assignment state' to q (qb). So at least 2
delta delays is present.
Another architecture is shown in the following. For zero delay parameter
values, it reduces the delay to one delta.
-- one delta delay
ENTITY d_sr_flipflop IS
GENERIC (sq_delay : TIME := 5 NS; rq_delay : TIME := 4 NS;
cq_delay : TIME := 6 NS);
PORT (d, set, rst, clk : IN BIT; q : OUT BIT; qb : OUT BIT := '1');
END d_sr_flipflop;
-ARCHITECTURE one_delta OF d_sr_flipflop IS
SIGNAL state : BIT := '0';
BEGIN
dff: PROCESS (rst, set, clk)
VARIABLE state : BIT := 0;
BEGIN
IF set = '1' THEN
state := '1';
ELSIF rst = '1' THEN
state := '0';
ELSIF clk = '1' AND clk'EVENT THEN
state := d;
END IF;
q <= state AFTER (sq_delay+rq_delay+cq_delay)/3;
qb <= NOT state AFTER (sq_delay+rq_delay+cq_delay)/3;
END PROCESS dff;
END one_delta;

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Here, state' is a variable to hold the internal state. When this

process is suspended, state' retains the value assigned to it in the last
activation of the process. No delays are associated with state'.
We have averaged the three delay parameters and used a single
delay value for assigning state' to outputs. This architecture, therefore,
is less accurate.
We could write the process without an intermediate signal "state". By doing so
we reduce the delta delay to zero. This will tend to speed up the simulation
speed.
-ENTITY d_sr_flipflop IS
GENERIC (sq_delay : TIME := 5 NS; rq_delay : TIME := 4 NS;
cq_delay : TIME := 6 NS);
PORT (d, set, rst, clk : IN BIT; q : OUT BIT; qb : OUT BIT := '1');
END d_sr_flipflop;
-ARCHITECTURE no_delta OF d_sr_flipflop IS
SIGNAL state : BIT := '0';
BEGIN
dff: PROCESS (rst, set, clk)
BEGIN
IF set = '1' THEN
q <= '1' AFTER sq_delay;
qb <= '0' AFTER sq_delay;
ELSIF rst = '1' THEN
q <= '0' AFTER rq_delay;
qb <= '1' AFTER rq_delay;
ELSIF clk = '1' AND clk'EVENT THEN
q <= d AFTER cq_delay;
qb <= NOT d AFTER cq_delay;
END IF;
END PROCESS dff;
END no_delta;
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-- In order to remove all delta delays even in the case of zero propagation
-- delays, we have avoided the use of an intermediate signal. Because of
-- this, two assignments are needed for assigning values to q and qb.
-- Another side-effect of this method is that initially assignments to
-- the two outputs will not be executed, causing both outputs to start at
-- zero (initial value of BIT). To overcome this problem, a default value
-- of '1' is used for the qb output.
--- ns set rst d clk q qb
-- 0 0 0 0 0 0 1
-- 100 1 0 0 0 0 1
-- 105 1 0 0 0 1 0
-- 300 0 0 0 0 1 0
-- 400 0 1 0 0 1 0
-- 404 0 1 0 0 0 1
-- 500 0 1 1 0 0 1
-- 600 0 1 1 1 0 1
-- 800 0 0 1 1 0 1
--1000 0 0 1 0 0 1
--1200 0 0 1 1 0 1
--1206 0 0 1 1 1 0
--1400 0 0 0 1 1 0
--1600 0 0 0 0 1 0
--1700 0 0 0 1 1 0
--1706 0 0 0 1 0 1
--1800 1 0 0 1 0 1
--1805 1 0 0 1 1 0

More on Sequential statement - LOOP :

We have already examine the LOOP statement with indeices. We can also write loop statements
without an iteration scheme (i.e. without FOR or WHILE). It is an infinite loop.
The only way to exit is to use an exit statement. An example is shown in the following:
long_running: LOOP
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...
IF x=25 THEN EXIT;
END IF;
...
END LOOP long_running;

An exit statement causes the termination of the loop. The condition can be
satisfied also with the WHEN construct.
LOOP
WAIT ON a, b;
EXIT WHEN a = b;
END LOOP;
-- this is the same as WAIT UNTIL a = b;

Besides EXIT another construct that can be used with the LOOP statement is NEXT.
A NEXT statement (within a loop) causes the rest of the loop be skipped and the
NEXT iteration to be taken. The syntax takes the following form:
NEXT loop_label WHEN condition; -- without label, the innermost enclosing loop;
EXIT WHEN x=25

-- this equals to IF x=25 THEN EXIT;

An example is shown here:

FOR j IN 10 DOWNTO 5 LOOP
IF sum < total_sum THEN
sum := sum + 2;
ELSEIF sum := total_sum THEN
NEXT;
ELSE
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NULL;
END IF;
k := k + 1;
END LOOP;

In this example, when the NEXT statement is executed, execution jumps to the end of the loop (the
last statement, "k := k + 1;", is not executed!), decrement j and resume the LOOP with the new
value of j.
Inclusion of labels enables to go to selected outer loops. A simple example is given here:
Also see code in Fig. 9.16.
-- while in the loop_2, if after the execution of sequential_statement_4
condition_1 is TRUE, the next' statement causes the remainder of loop_2
and loop_1 to be skipped, and the next iteration of loop_1 is taken.
-- therefore, the value of i=i+1 and sequential_statement_1 will be executed.

Assertion Statement

It is for observing activity in a circuit or defining constraints or

conditions in the way a circuit operates. The general format:
ASSERT assertion_condition REPORT "message" SEVERITY level;
-------------------------------------------------------------------[optional] ...

ASSERT
(good condition)

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REPORT
(if good condition is violated)

SEVERITY

Some times it is easier to ASSERT the bad thingss ince there are too many
good things to list.

ASSERT (wanted case) = ASSERT (NOT (unwanted case)

ASSERT
NOT things should not happen
REPORT
message that a bad thing has happened

The statement is said to "occur" when the Boolean expression

`assertion_condition` becomes FALSE. At this point, the "message" is
issued, and the simulator takes the action specified by the parameter
`level` (NOTE, WARNING, ERROR, FAILURE). The ERROR and FAILURE severity
levels cause the simulator to stop after issuing the reporting message
and a simulation error or failure message.

Sequential Use of Assertion Statements

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Example of Fig. 9.17

-- it checks to see if the set and rst inputs are simultaneously
active. This case is undesirable.
-- if it detects such a situation, the message "..." is
issued and the simulation continues.
Be careful because of this negation! It may be confusing.

Concurrent Assertion Statements

It is for cases where violation of constraints must be continuously

checked and reported. Cases: checking of timing constraints such as pulse
width, setup time, and hold time.
This statement can be placed in the statement part of an
architecture or entity declaration -- it is observed at all times. Fig.
9.18 shows setup and hold times for a positive edge trigger clocked D
flip-flop.
The setup time statement
When (clock changes from zero to 1),
if the (data input has not been stable
at least for the amount of the setup
time), then a setup time violation has
occurred

The VHDL expression

(clock=`1` AND NOT
clock'STABLE)
AND
(NOT
data'STABLE(setup_time))

The assertion_condition is:

NOT ((clock=`1` AND NOT clock'STABLE) AND (NOT data'STABLE(setup_time)))

The hold time statement

When (there is a change on
data input), if (clock value is `1`)
and (clock has got `1` more recent
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The VHDL expression

(data'EVENT)
AND (clock=`1`)
AND
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than the amount of hold time),

then a hold time violation has occurred

(NOT
clock'STABLE(hold_time))

The assertion_condition is:

NOT ((data'EVENT) AND (clock=`1`) AND (NOT clock'STABLE(hold_time)))

Fig. 9.19 shows a new description of d_sr_flipflop.

-- It has setup and hold generic timing parameters.
-- each assertion statement in the entity declaration
issues a system warning and appropriate message if a
violation occurs.
The statements in the entity apply to all architectures,
rather than the one that contains them.
Sequential assertion statements execute only when
program flow reaches them.

Sequential Wait Statements

- They are for modeling delays, handshaking, and hardware dependencies.
- Used in procedures and processes (P) that do not have a sensitivity list.
- When a program flow reaches a wait statement, the P is suspended.
The
P resumes after the conditions specified by the wait statement
are met.
- There 4 different forms:
WAIT FOR waiting_time;
WAIT ON waiting_sensitivity_list;
WAIT UNTIL waiting_conditionn;
WAIT ;

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WAIT FOR waiting_time;

-- causes suspension of a sequential body until the waiting_time elapses.
WAIT ON waiting_sensitivity_list;
-- causes suspension of a sequential body until an event occurs on any
of the signals in the waiting_sensitivity_list. This list is equivalent
to the sensitivity list of a process statement.
WAIT UNTIL waiting_conditionn;
-- causes suspension of a sequential body until the Boolean
waiting_condition turns from FALSE to TRUE. If the flow of program
reaches the statement when waiting_condition is TRUE, suspension occurs,
and resumption does not occur until condition turns from TRUE to FALSE
and then from FALSE to TRUE.
WAIT ;
-- causes suspension of a sequential body forever.

A Behavioral State Machine

Example: The Moore implementation of the 1011 detector (Fig. 9.20).

Fig. 9.21 shows the VHDL description.
-- state is an enumeration type;
-- the`current` signal of `state` type is initiated to reset and
describes the present active state.
-- we have one case alternative for each of the states.
-- a case alternative sets the value of z (if any), waits for
the clock edge, and sets the `current` depending on the
input.
-- the WAIT 1NS suspends the process for 1ns (it gives
enough time for the new value to settle in `current`;
after resumption, z is set to 0, and the case statement
is executed again; alternative:
WAIT ON current'TRANSACTION;
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-- z <=`0` to reset this signal;

alternative: to introduce individual assignment in
case statements.

Two Phase Clocking

Two-phase nonoverlapping clocking is very common to insure input to

output isolation in master-slave registers. Fig. 9.25 shows generation of a
second clock phase, c2, from a periodic first phase, c1, with the period
of 1 us and 500 ns duty cycle.
...
phase2: PROCESS
BEGIN
WAIT UNTIL c1=`0`;
WAIT FOR 10 NS;
c2 <= `1`;
WAIT FOR 480 NS;
c2 <= `0`;
END PROCESS phase2;
...

Fig. 9.25

- The phase2 process stays suspended while c1 is `1`.

- Ten nanoseconds after c1 changes from `1` to `0`, c2 becomes `1`, and
the process goes into suspension again for 480 ns.
- While suspended, c2 stays at `1`.
- When phase2 resumes, it assigns a zero to c2, and becomes suspended
again, waiting for c1 to change from `1` to `0`.

Fig. 9.26 shows a timing diagram that results from a periodic

waveform on c1.
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Implementing Handshaking

Asynchronous communication between systems is done by handshaking - the

signaling that occurs between two systems as one transfers data to the
other. A sending system informs the receiving system that the data is
ready when it prepares data for transfer. The receiving system informs
the sending system that it has received it when the system accepts the data.
Handshaking can be
- fully responsive;
- or partially responsive. (Exchanging data without handshaking is
nonresponsive communication.)
Fully responsive. All events on the handshaking signals of one
system occur in response to events on the signals of the other system. It
requires at least 1 signal and can use as many as 6 for a two-way, fully
responsive communication. Fig. 9.27 shows two-line handshaking process
for transferring data on data_lines from system A to B.)

System A places valid data on data_lines and informs B by raising the

data_ready line. When system B is ready to accept data, it does so, and
it informs system A that it has accepted data by raising `accepted`. When
A sees that data on data_lines are no longer needed by B, it removes
valid data_lines, and lowers the data_ready line. System B acknowledges
this, and informs A that it can accept new data by lowering its
`accepted` signal.
Fig. 9.28 shows the VHDL code for the process in Fig. 9.30. Partial code
sections are sequentially executed by A and B when they need to talk to each
other.

Comprehensive example:
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Fig. 9.31: system_i works as an interface between

sustem_a and system_b. System_a uses hand-shaking to provide 4-bit
data, and system_b uses handshaking to receive 16-bit data. The interface
accumulates 4 data nibbles and makes a 16-bit data available to system_b.
The first nibble forms the least significant 4 bits of the data.
System_i is capable of talking to both systems simultaneously. It should
be possible for system_i to be involved in transmitting the previously
accumulated data to system_b, while accumulating a new 16 data from system_a.
When system_a has a nibble ready on the in_data lines, it places
a `1` on the in_ready line. The data and the in_ready line stay valid
until this system sees a `1` on its in_received input.

System_i waits in an idle state looking for in_ready to become `1`. When
this happens, it receives data from in_data and acknowledges it by
placing a `1` on in_received. The interface holds in_received active
until in_ready becomes `0`. On the other side, system_i talks to system_b
by providing data on the out_data output bus, and by activating the
out_ready line, informs the other system of the new data. When system_b
receives the data, it places a `1` on the out_received line,
and holds this line active until system_i deactivates its out_ready
output.

VHDL code is shown in Fig. 9.32.

It has 3 handshakings; one for talking to A,
one for talking to B,one for communica-tion between the
transmitting and receiving parts of system_i.
- a_talk process waits for in_ready=1,
it receives data, it places it in part of word_buffer indicated by `count`.
After completing, it places a `1` on in_received.
...

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