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4D1-04

Proceedings of APMC 2012, Kaohsiung, Taiwan, Dec. 4-7, 2012

A Differential Complementary Hartley CMOS


Voltage Controlled Oscillator
Sheng-Lyang Jang#, Heng-Fa Teng*, Wei-Hao Lee#, and Chia-Wei Chang#
#

Department of Electronic Engineering, National Taiwan University of Science and Technology,


Taipei City, Taiwan
*
Department of Computer and Communication Engineering, Nan Kai University of Technology,
NanTou, Taiwan
VDD

Abstract This letter presents a novel complementary low


phase noise differential CMOS Hartley voltage-controlled
oscillator (VCO), which uses only the supply voltage and the
tuning voltage as the biases. The low noise CMOS VCO has been
implemented with the TSMC 0.18 um 1P6M polycide CMOS
technology. The VCO operates from 5.49 GHz to 6.29 GHz with
13.58 % tuning range. The measured phase noise at 1-MHz
offset is -118.42 dBc/Hz at 5.65 GHz. The power consumption of
the VCO core is 1.694 mW. The VCO occupies a chip area of
0.529 0.674 mm2 and provides a figure of merit of -191.09
dBc/Hz. At the supply voltage of 1.1V, the core current of 1.54
mA, the core power consumption is 1.694 mW.
Index Terms CMOS, phase noise, balanced and crosscoupled oscillators, Hartley voltage-controlled oscillators
(VCOs).

VDD
LB

Vtune

M3

CT

LB
M4

L1T Cvar L3T

Vtune

M3

CT

M4

Cvar

CT

CT

L1T
L2T
L2T

L4T

M1

M2

M1

M2
LB

LB

(a)
(b)
Fig. 1. (a) Schematics of a balanced Colpitts VCO and (b) a
modified balanced VCO.
VDD

I. INTRODUCTION

CMOS voltage-controlled oscillator (VCO) plays a crucial


role in modern commercial radio-frequency RF transceiver
for generating the local signal to the mixer. Many popular
CMOS VCO topologies have been studied in the past, and
they include cross-coupled [1] and Colpitts oscillators [2].
Cross-coupled oscillators have been preferred over other
topologies due to easy implementation and differential
operation with moderate phase noise performance. The
Colpitts VCO uses the capacitive tapped signal as the
feedback signal to form a loop for oscillation and can
potentially achieve lower phase noise due to superior
cyclostationary noise properties [2]. The Hartley VCO taps
the inductive feedback signal for oscillation and a fullyintegrated CMOS Hartley VCO with high performance has
been demonstrated [3, 4]. The Hartley VCO uses all
pMOSFET topology [3] or complementary MOS topology [4]
and demands three control biases: the supply voltage, the
tuning voltage and the gate bias. The biasing difficulty of the
previous Hartley VCOs can be eliminated by using the selfbiasing Hartley VCO proposed in this work.
Hartley VCO can be designed with a balanced topology
just like a balanced Colpitts VCO [5], Armstrong VCO [6],
or Clapp VCO [7]. The balanced VCO consists of two singleended oscillators configured in a balanced topology. Fig. 1(a)
shows a balanced Colpitts VCO [8]. A composite of Hartley
VCO and other VCO such as Colpitts oscillator is also
possible. A balanced VCO shown in Fig. 1(b) [9] is actually

Out1

M1

L1

L3

L2

L4

M3

Vtune

M5
M2

Out2

M6

CV

CV

M4

(a)
Cbu
Cds
L3

L1
CV
Cgs

(b)
Fig. 2. (a) Simplified differential Hartley VCO. (b) Equivalent
small-signal half- circuit resonator of the circuit in Fig. 2(a).

a composite of Colpitts VCO and Hartley oscillator, and it


uses the Colpitts VCO and wiring the two inductors in Fig.
1(a) to form a virtual ground as a feedback port. Hartley
VCO also can be designed with a cross-coupled topology.
This letter proposes a differential complementary CMOS
Hartley VCO with less numbers of bias voltages than the
VCO in [3, 4] and with good performance. This letter is
organized as follows. Section II describes the operation
principle of the proposed VCO circuit, and the constituent
circuit components. Section III summarizes the experimental
results, and Section IV is a conclusion.

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4D1-04

Proceedings of APMC 2012, Kaohsiung, Taiwan, Dec. 4-7, 2012

Fig. 3. Chip microphotography of the proposed differential crosscoupled Hartley VCO.


Fig. 5. Measured frequency tuning range of the proposed circuit.

Fig. 4. Output spectrum of the proposed circuit at 5.65 GHz.

Fig. 6. Measured phase noise of the differential VCO.

From Fig. 2(b), the ideal oscillation frequency is derived as


II. CIRCUIT DESIGN
Figure 2(a) shows the schematic of the proposed crosscoupled Hartley VCO. The pMOSFET M1 and nMOSFET M2
form a CMOS inverter, and the pMOSFET M3 and
nMOSFET M4 forms the other inverter. The inductors L1 and
L2, L3 and L4, and accumulation-mode MOS varactors Cv
forms the LC resonator. Vtune is the voltage used to control
the capacitance of accumulation-mode MOS varactor and the
oscillation frequency. The varactors are configured in a
topology so that as Vtune increases the oscillation frequency
also increases. The inductors L1 and L2 are configured as a
transformer to increase the Q-factor of inductor and save die
area. If the inductors L3 and L4 are zero, the VCO becomes a
complementary
cross-coupled
VCO.
Optimized
complementary MOSFETs in the VCO perform better riseand fall-time symmetry, which results in less upconversion of
flicker noise to the phase noise. The nMOSFET M5 and M6
are common-source output buffers used for measurement
purpose. The output of the first inverter is wired to the
common node of inductors L2 and L4 and the output of the
second inverter is wired to the common node of inductors L1
and L3. The voltage swing is limited by the VDD and the
ground level though the turn-on of the pMOSFETs and
nMOSFETs respectively. Fig. 2(b) shows the equivalent LC
resonator with the parasitic capacitors. Cgs and Cds are
respectively the gate-source capacitance of nMOSFETs M2
and M1, and the drain-source capacitance of nMOSFETs M3
and M4. Cbu is the gate-source capacitance of buffer
nMOSFETs M5 and M6.

P r P 2  4Q
2Q

Z
P

C dbu L1  Cvgs ( L1  L3 )

Q Cvgs L3C dbu L1

(2)
(2a)
(2b)

where Cdbu=Cds+Cbu and Cvgs=Cgs+Cv. Considering the


mutual inductance, L1 in (2) is replaced by L1+M, where M is
the mutual inductance of the transformer (L1 and L2). The
Hartley VCO is a dual-resonant oscillator. However, if L3 and
L4 (or Cdbu) are small, the VCO becomes a single-resonance
oscillator. At low voltage the VCO will oscillate at the
resonant frequency with larger loop gain. When carefully
designed, the low frequency oscillation frequency is given by
Z

1
Cdbu ( L1  M )  Cvgs ( L1  M  L3 )

(3)

Eliminating the inductors (L3 and L4) increases the oscillation


frequency. The frequency of oscillator is written as
Z # Zo  'Z # Zo  k v 'Vtune
(4a)
where kv is the gain of oscillator and is given by
kv

L1  M  L3 wCv
wVtune
Z o3

(4b)

The gain of VCO determines the loop characteristics and


overall performance of the phase locked loop (PLL). A VCO
with linear frequency/voltage characteristics improves the
performance of PLL blocks. High VCO gain makes the VCO
phase noise susceptible to the noise on the control voltage.

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4D1-04

Proceedings of APMC 2012, Kaohsiung, Taiwan, Dec. 4-7, 2012

TABLE I.
PERFORMANCE COMPARISON WITH PREVIOUS REPORTS
Ref.
[3]
[9]
[10]
[11]
[12]
[13]
This

Freq.
GHz
4.5
5.6
5.4
5.0
5.35
5.3
5.6

Vdd
(V)
1.5
1.4
2.7
1.5
1.5
1.8
1.1

PN@1MHz
(dBc/Hz)
-122.47
-122.7
-117
-120.42
-117
-124
-118.42

PDC
(mW)
6.75
6.44
13.5
3
7.05
13.5
1.69

FOM
(dBc/Hz)
-187
-189.6
-180
-189.6
-183.1
-187.2
-191.1

FOMT
(dBc/Hz)
-189.5
-176.4
-180
-188
-179.2
-184.7
-193.8

IV. CONCLUSION

Tuning
Range(%)
11.3
2.8
11
8.3
6.4
7.5
13.6

III. MEASUREMENT RESULTS


The proposed differential Hartley VCO was fabricated by
the TSMC 0.18m 1P6M CMOS technology and the microphotograph of the fabricated chip is shown in Fig. 3. The
total chip area including pads is 0.5290.674 mm2. On the
left-hand side is the two-turn octagonal transformer (L1 and
L2). The rest two single-turn inductors are L3 and L4. The
ADS momentum is used to design the on-chip inductors. The
circuit simulation was carried out by the simulation tool
Spectre-RF. On board measurements of output spectra and
output power performances were obtained using the Agilent
E4407B spectrum analyzer. Figure 4 shows the output
spectrum at 5.65 GHz, with -1.9 dBm output power. With a
supply voltage of 1.1 V, the current and power consumption
are 1.54 mA and 1.694 mW respectively. The oscillating
frequency of the proposed differential Hartley VCO shown in
Fig. 5 is tuned from 5.49 GHz to 6.29 GHz with 13.58%
tuning range as the tuning voltage is varied from 0 V to 1.2 V.
The VCO gain is constant when Vtune is between 0.4 V and
1.1 V.
The measurement phase noise, shown in Fig. 6, is 118.42dBc/Hz at 1MHz offset frequency at 5.65 GHz. The
1/f2 phase noise is found between 300 KHz and 3 MHz. The
figure of merit (FOM) of the proposed VCO is about -191.09
dBc/Hz, it is calculated using the figure of merit defined as
Eq. (5) [3].
P
Z
(5)
FOM
L{Z }  10 log DC  20 log o
1mW
'Z
where Z o is the oscillating frequency, Z is the offset

frequency, L^Z` is the phase noise at Z , PDC is the dc


power consumption of the measured VCO. The second
figure of merit (FOMt) of this proposed VCO is about -193.8
dBc/Hz, and it is defined as [7]
FTR (6)
P
Z
FOM T L{Z }  10 log DC  20 log o u

1mW
'Z 10
where FTR is the frequency tuning range in percent. The
performance comparison between the proposed differential
Hartley CMOS VCO with other previous reports are also
summarized in TABLE I. It has better performance than other
Hartley related VCOs. In our point of view the VCO in [9] is
not well-designed because the tuning range is 160 MHz while
Vtune varies from 0 to 2 V. This VCO is not robust to process
and process variation.

In this letter, a differential complementary Hartley voltage


controlled oscillator has been proposed and eliminates one
control bias and simplifies the circuit control and design. This
differential Hartley VCO operates from 5.49 GHz to 6.29
GHz with 13.58% tuning range. The proposed VCO can be
reduced to the conventional cross-coupled VCO by
eliminating the inductors L3 and L4. With L3 and L4, an extra
design parameter, the VCO performance can be improved.
The experimental data shows the proposed circuit topology is
useful for low power RF circuit design.
ACKNOWLEDGEMENT
The authors would like to thank the Staff of the CIC for
the chip fabrication and technical supports.
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[2]

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