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Data Sheet
FEATURES
ADN4650
Multiple channel configurations are offered, and the LVDS receivers on the ADN4651/ADN4652 include a fail-safe mechanism
to ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not driven.
1
VDD2
DOUT1+
DIN1
DOUT1
LVDS
DIGITAL ISOLATOR
LVDS
DOUT2+
DIN2
DOUT2
13677-101
DIN2+
GND2
GND1
Figure 1.
VIN1
ADN4651
VIN2
ISOLATION
BARRIER
LDO
VDD1
LDO
VDD2
DIN1+
DOUT1+
DIN1
DOUT1
LVDS
DIGITAL ISOLATOR
LVDS
DIN2+
DOUT2
DIN2
13677-001
DOUT2+
GND2
GND1
Figure 2.
VIN1
VDD1
LDO
VIN2
ISOLATION
BARRIER
LDO
VDD2
DIN1+
DOUT1+
DIN1
DOUT1
LVDS
DIGITAL ISOLATOR
LVDS
DIN2+
DOUT2+
DIN2
DOUT2
LDO
DIN1+
APPLICATIONS
GENERAL DESCRIPTION
ISOLATION
BARRIER
LDO
VDD1
ADN4652
VIN2
GND1
GND2
13677-103
Figure 3.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead,
wide-body SOIC package with 5 kV rms isolation.
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. B
Document Feedback
ADN4650/ADN4651/ADN4652
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
ESD Caution...................................................................................8
Specifications..................................................................................... 3
Isolation ....................................................................................... 19
REVISION HISTORY
4/16Rev. A to Rev. B
Added ADN4652 ................................................................ Universal
Changes to Features Section and General Description Section....... 1
Added Figure 3; Renumbered Sequentially .................................. 1
Changes to Supply Current Parameter, Table 1 ............................ 3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 ................................................................................................ 4
Changes to Table 12 .......................................................................... 9
Moved Figure 7 ............................................................................... 10
Added Table 13 ............................................................................... 10
Added Figure 8 and Table 14, Renumbered Sequentially ......... 11
Changes to PCB Layout Section ................................................... 19
Changes to Ordering Guide .......................................................... 24
2/16Rev. 0 to Rev. A
Added ADN4650 ................................................................ Universal
Changes to Features Section and General Description Section........ 1
Added Figure 1; Renumbered Sequentially .................................. 1
Rev. B | Page 2 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. For all typical
specifications, VDD1 = VDD2 = 2.5 V, TA = 25C.
Table 1.
Parameter
INPUTS (RECEIVERS)
Input Threshold
High
Low
Symbol
Min
Typ
100
|VID|
VIC
100
0.5|VID|
IIH, IIL
CINx
|VOD|
|VOD|
VOS
VOS
VOS(PP)
IOS
250
310
1.125
1.17
Differential Output
Capacitance1
POWER SUPPLY
Supply Current
COUTx
COMMON-MODE TRANSIENT
IMMUNITY 2
1
2
mV
mV
Test Conditions/Comments
mV
V
+5
A
pF
450
50
1.375
50
150
20
12
mV
mV
V
mV
mV
mA
mA
pF
55
80
65
72
3.6
mA
mA
mA
mA
V
2.625
IDD1, IIN1,
IDD2, or IIN2
VIN1 or
VIN2
VDD1 or
VDD2
PSRR
3.0
58
50
60
3.3
2.375
2.5
|CM|
25
ADN4650 Only
100
2.4 0.5|VID|
ADN4651/ADN4652 Only
Unit
Max
75
dBc
50
kV/s
Rev. B | Page 3 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
TIMING SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. All typical
specifications, VDD1 = VDD2 = 2.5 V, TA = 25C.
Table 3.
Parameter
PROPAGATION DELAY
SKEW
Duty Cycle 2
Channel to Channel 3
Part to Part 4
Symbol
tPLH, tPHL
tSK(D)
tSK(CH)
Typ
4
200
150
tSK(PP)
JITTER 5
Random Jitter, RMS 6 (1)
Deterministic Jitter 7, 8
With Crosstalk
Total Jitter at BER 1 1012
Additive Phase Jitter
tRJ(RMS)
tDJ(PP)
tDJC(PP)
tTJ(PP)
tADDJ
RISE/FALL TIME
FAIL-SAFE DELAY 12
tR, tF
tFSH, tFSL
Min
2.6
30
30
70
387
376
1
600
Max 1
4.5
Unit
ns
100
500
300
600
500
ps
ps
ps
ps
ps
4.8
96
ps rms
ps
ps
ps
fs rms
fs rms
ps
s
151
350
1.2
Test Conditions/Comments
See Figure 37, from any DINx+/DINx to DOUTx+/DOUTx
See Figure 37, across all DOUTx+/DOUTx
ADN4650 only
ADN4650, ADN4651, ADN4652, or combinations
ADN4650 to ADN4650 only
See Figure 37, for any DOUTx+/DOUTx
300 MHz clock input
600 Mbps, 223 1 PRBS
600 Mbps, 223 1 PRBS
300 MHz/600 Mbps, 223 1 PRBS 9
100 Hz to 100 kHz, fOUT = 10 MHz 10
12 kHz to 20 MHz, fOUT = 300 MHz 11
See Figure 37, any DOUTx+/DOUTx, 20% to 80%, RL = 100 , CL = 5 pF
ADN4651/ADN4652 only; see Figure 37 and Figure 4, any
DOUTx+/DOUTx, RL = 100
Mbps
Rev. B | Page 4 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
Timing Diagram
>1.3V
DINx+
1.2V
(DINx = 1.2V)
<1.1V
+0.1V
VID
0V
0.1V
DOUTx+
~1.3V
DOUTx
~1.0V
~ +0.3V
+0.1V
+0.1V
VOD
~ 0.3V
tFSH
tFSL
13677-034
0V
Symbol
L (I01)
Value
5000
7.8
Unit
V rms
mm min
L (I02)
7.8
mm min
L (PCB)
8.1
mm min
CTI
17
>400
II
m min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 5.
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
JA
Min
Typ
1013
2.2
3.7
45.7
Max
Unit
pF
pF
C/W
Test Conditions/Comments
f = 1 MHz
Thermal simulation with 4-layer standard JEDEC PCB
The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
Input capacitance is from any input data pin to ground.
Rev. B | Page 5 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
REGULATORY INFORMATION
See Table 11 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 6.
UL (Pending)
To Be Recognized Under UL 1577
Component Recognition Program 1
Single Protection, 5000 V rms Isolation
Voltage
CSA (Pending)
To be approved under CSA
Component Acceptance Notice 5A
File E214100
File 205078
1
2
VDE (Pending)
To be certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, VIORM = 424 V peak, VIOSM =
6000 V peak
Basic insulation, VIORM = 424 V peak, VIOSM = 10,000 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage 6000 V rms for 1 sec.
In accordance with DIN V VDE V 0884-10, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage 795 V peak for 1 sec (partial discharge
detection limit = 5 pC).
Test Conditions/Comments
Symbol
Characteristic
Unit
VIORM
Vpd (m)
I to IV
I to IV
I to III
40/125/21
2
424
795
V peak
V peak
636
V peak
509
V peak
VIOTM
5000
V peak
VIOSM
VIOSM
10,000
6000
V peak
V peak
TS
PS
RS
150
2.78
>109
C
W
Vpd (m)
VIORM 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIO = 500 V
Rev. B | Page 6 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
3.0
2.5
Table 8.
Parameter
Operating Temperature
Supply Voltages
Supply to LDO
LDO Bypass, VINx Shorted to VDDx
2.0
1.5
1.0
50
100
150
200
13677-002
0.5
Rev. B | Page 7 of 24
Symbol
TA
Rating
40C to +125C
VIN1, VIN2
VDD1, VDD2
3.0 V to 3.6 V
2.375 V to 2.625 V
ADN4650/ADN4651/ADN4652
Data Sheet
Table 9.
Parameter
VIN1 to GND1/VIN2 to GND2
VDD1 to GND1/VDD2 to GND2
Input Voltage (DINx+, DINx) to GNDx on
the Same Side
Output Voltage (DOUTx+, DOUTx) to
GNDx on the Same Side
Short-Circuit Duration (DOUTx+, DOUTx)
to GNDx on the Same Side
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ Maximum)
Power Dissipation
ESD
Human Body Model (All Pins to
Respective GNDx, 1.5 k, 100 pF)
IEC 61000-4-2 (LVDS Pins to Isolated
GNDx Across Isolation Barrier)
Rating
0.3 V to +6.5 V
0.3 V to +2.8 V
0.3 V to VDD + 0.3 V
JA
45.7
Unit
C/W
ESD CAUTION
40C to +125C
65C to +150C
150C
(TJ maximum TA)/JA
4 kV
8 kV
Rating
Constraint
495 V peak
495 V peak
990 V peak
875 V peak
1079 V peak
536 V peak
The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Rev. B | Page 8 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
20
VIN2
GND1 2
19
GND2
VDD1 3
18
VDD2
GND1 4
17
GND2
DIN1 6
DIN2+ 7
ADN4650
DOUT1+
TOP VIEW
(Not to Scale) 15 DOUT1
14 DOUT2+
16
DIN2 8
13
DOUT2
VDD1 9
12
VDD2
GND1 10
11
GND2
13677-104
DIN1+ 5
Mnemonic
VIN1
2, 4, 10
3, 9
GND1
VDD1
5
6
7
8
11, 17, 19
12, 18
DIN1+
DIN1
DIN2+
DIN2
GND2
VDD2
13
14
15
16
20
DOUT2
DOUT2+
DOUT1
DOUT1+
VIN2
Description
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if
using a 2.5 V supply, connect VIN1 directly to VDD1.
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If
supplying 3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V
output of the internal LDO.
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If
supplying 3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V
output of the internal LDO.
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if
using a 2.5 V supply, connect VIN2 directly to VDD2.
Rev. B | Page 9 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
VIN1 1
20
VIN2
GND1 2
19
GND2
VDD1 3
18
VDD2
GND1 4
17
GND2
DIN1 6
DOUT2+ 7
ADN4651
DOUT1+
TOP VIEW
(Not to Scale) 15 DOUT1
14 DIN2+
16
DOUT2 8
13
DIN2
VDD1 9
12
VDD2
GND1 10
11
GND2
13677-003
DIN1+ 5
Mnemonic
VIN1
2, 4, 10
3, 9
GND1
VDD1
5
6
7
8
11, 17, 19
12, 18
DIN1+
DIN1
DOUT2+
DOUT2
GND2
VDD2
13
14
15
16
20
DIN2
DIN2+
DOUT1
DOUT1+
VIN2
Description
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if
using a 2.5 V supply, connect VIN1 directly to VDD1.
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If
supplying 3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V
output of the internal LDO.
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Output 2.
Inverted Differential Output 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If
supplying 3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V
output of the internal LDO.
Inverted Differential Input 2.
Noninverted Differential Input 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if
using a 2.5 V supply, connect VIN2 directly to VDD2.
Rev. B | Page 10 of 24
ADN4650/ADN4651/ADN4652
VIN1 1
20
VIN2
GND1 2
19
GND2
VDD1 3
18
VDD2
GND1 4
17
GND2
16
DIN1+
15
DIN1
DIN2+ 7
14
DOUT2+
DIN2 8
13
DOUT2
VDD1 9
12
VDD2
GND1 10
11
GND2
DOUT1+ 5
DOUT1 6
ADN4652
TOP VIEW
(Not to Scale)
13677-108
Data Sheet
Mnemonic
VIN1
2, 4, 10
3, 9
GND1
VDD1
5
6
7
8
11, 17, 19
12, 18
DOUT1+
DOUT1
DIN2+
DIN2
GND2
VDD2
13
14
15
16
20
DOUT2
DOUT2+
DIN1
DIN1+
VIN2
Description
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if
using a 2.5 V supply, connect VIN1 directly to VDD1.
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If
supplying 3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V
output of the internal LDO.
Noninverted Differential Output 1.
Inverted Differential Output 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If
supplying 3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V
output of the internal LDO.
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Input 1.
Noninverted Differential Input 1.
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if
using a 2.5 V supply, connect VIN2 directly to VDD2.
Rev. B | Page 11 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
60
60
30
20
IDD1
IDD2
IIN1
IIN2
10
0
0
50
150
100
250
200
300
20
0
50
60
60
70
50
40
30
20
IDD1
IDD2
IIN1
IIN2
0
0
100
50
150
200
250
300
0
2.35
30
20
75
100
125
2.40
2.45
2.50
(DIN2 ACTIVE)
(DIN2 ACTIVE)
(DIN1 ACTIVE)
(DIN1 ACTIVE)
2.55
2.60
2.65
50
40
30
20
IIN1 (DIN2 ACTIVE)
IIN2 (DIN2 ACTIVE)
IIN1 (DIN1 ACTIVE)
IIN2 (DIN1 ACTIVE)
10
13677-006
50
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
IIN1
IIN2
25
125
40
100
20
60
50
75
30
60
50
40
70
25
25
50
70
0
50
10
Figure 10. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN2 Input Clock Frequency
(DIN1 Not Switching)
10
25
Figure 12. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN2 with 300 MHz Clock Input, DIN1 Not Switching)
70
10
IDD1
IDD2
IIN1
IIN2
13677-005
30
10
Figure 9. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN1 Input Clock Frequency
(DIN2 Not Switching)
40
13677-008
40
50
Figure 11. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN1 with 300 MHz Clock Input, DIN2 Not Switching)
Rev. B | Page 12 of 24
0
3.00
3.15
3.30
3.45
3.60
13677-009
50
13677-007
70
13677-004
VDD1 = VDD2 = 2.5 V, TA = 25C, RL = 100 , 300 MHz input with |VID| = 200 mV, and VIC = 1.1 V, unless otherwise noted.
Data Sheet
ADN4650/ADN4651/ADN4652
1.60
2.55
2.50
2.45
2.40
2.35
3.0
VDD1
VDD2
3.1
3.2
3.3
3.4
3.5
3.6
1.40
1.35
1.30
VOH CHANNEL 1
VOH CHANNEL 2
2.40
2.45
2.50
2.55
2.60
2.65
Figure 18. Driver Output High Voltage (VOH) vs. Supply Voltage, VDD1/VDD2
1.25
330
320
310
300
290
280
270
VOD CHANNEL 1
VOD CHANNEL 2
260
50
100
150
200
250
300
350
1.10
1.05
1.00
0.95
0.90
2.35
VOL CHANNEL 1
VOL CHANNEL 2
2.40
2.45
2.50
2.55
2.60
2.65
Figure 19. Driver Output Low Voltage (VOL) vs. Supply Voltage, VDD1/VDD2
1.375
450
400
350
300
250
200
150
100
50
VOD CHANNEL 1
VOD CHANNEL 2
75
100
OUTPUT LOAD, RL ()
125
150
Figure 17. Driver Differential Output Voltage (VOD) vs. Output Load (RL)
1.325
1.275
1.225
1.175
1.125
2.35
13677-012
0
50
1.15
VOS CHANNEL 1
VOS CHANNEL 2
2.40
2.45
2.50
2.55
2.60
2.65
13677-015
1.20
13677-014
340
Figure 16. Driver Differential Output Voltage (VOD) vs. Input Clock Frequency
DRIVER DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV)
1.45
350
250
1.50
1.25
2.35
13677-011
Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2
1.55
13677-013
2.60
13677-010
2.65
Figure 20. Driver Output Offset Voltage (VOS) vs. Supply Voltage, VDD1/VDD2
Rev. B | Page 13 of 24
ADN4650/ADN4651/ADN4652
3.60
3.40
3.35
3.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2
3.8
3.7
3.6
3.5
3.4
3.3
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.2
3.1
3.0
50
25
25
50
75
100
125
3.50
3.45
3.40
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.35
3.30
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.5
1.0
1.5
2.0
2.5
240
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
220
200
180
160
140
120
2.35
2.40
2.45
2.50
2.55
2.60
2.65
Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2
3.55
3.35
Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage (VIC)
13677-019
3.60
3.40
3.9
3.45
3.30
13677-018
4.0
3.50
13677-020
3.45
3.55
13677-021
3.50
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
240
220
200
180
160
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
140
120
50
25
25
50
75
100
125
13677-022
3.55
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
13677-017
3.60
Data Sheet
Figure 26. Differential Output Transition Time vs. Ambient Temperature (TA)
Rev. B | Page 14 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
40
25
20
15
10
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
2.40
2.45
2.50
2.55
2.60
2.65
30
25
20
15
10
5
CHANNEL 1
CHANNEL 2
13677-023
0
2.35
35
100
200
300
400
500
600
Figure 27. Duty Cycle Skew (tSK(D)) vs. Supply Voltage, VDD1 and VDD2
13677-025
30
30
15
10
25
25
50
75
100
125
35
30
25
20
15
10
CHANNEL 1
CHANNEL 2
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
0
50
40
Figure 28. Duty Cycle Skew (tSK(D)) vs. Ambient Temperature (TA)
0
2.35
2.40
2.45
2.50
2.55
2.60
2.65
Rev. B | Page 15 of 24
13677-026
20
13677-024
45
25
ADN4650/ADN4651/ADN4652
Data Sheet
50
40
30
20
10
25
25
50
75
100
125
CH2 50mV
CH4 10mV
300ps/DIV
DELAY 61.0828ns
CH2 50mV
CH4 10mV
300ps/DIV
DELAY 61.0828ns
CH1 50mV
CH3 10mV
CH1 50mV
CH3 10mV
Rev. B | Page 16 of 24
13677-029
0
50
13677-027
CHANNEL 1
CHANNEL 2
13677-028
60
Data Sheet
ADN4650/ADN4651/ADN4652
VOS
VOD
R
DINx
D
DOUTx
NOTES
1. VTEST = 0V TO 2.4V
3.75k
SIGNAL
GENERATOR
RL
3.75k
DOUTx+
DINx+
VTEST
V VOD
50
13677-031
DOUTx+
DINx+
13677-032
VOUT+
VOUT
R
50 DINx
Rev. B | Page 17 of 24
RL
D
DOUTx
NOTES
1. CL INCLUDES PROBE AND JIG CAPACITANCE.
Figure 35. Driver Test Circuit (Full Load Across Common-Mode Range)
CL
CL
13677-033
RL/2
DOUTx
VOD
DOUTx
NOTES
1. VID = VIN+ VIN
2. VIC = (VIN+ + VIN)/2
3. VOD = VOUT+ VOUT
4. VOS = (VOUT+ + VOUT)/2
13677-030
DINx
RL/2
DINx
VIN
DOUTx+
VID
VIN+
DINx+
DOUTx+
ADN4650/ADN4651/ADN4652
Data Sheet
THEORY OF OPERATION
The ADN4650/ADN4651/ADN4652 are TIA/EIA-644-A LVDS
compliant isolated buffers. LVDS signals applied to the inputs are
transmitted on the outputs of the buffer, and galvanic isolation
is integrated between the two sides of the device. This integration
allows drop-in isolation of LVDS signal chains.
The LVDS receiver detects the differential voltage present across
a termination resistor on an LVDS input. An integrated digital
isolator transmits the input state across the isolation barrier,
and an LVDS driver outputs the same state as the input.
With a positive differential voltage of 100 mV across any DINx pin,
the corresponding DOUTx+ pin sources current. This current flows
across the connected transmission line and termination at the
receiver at the far end of the bus, while DOUTx sinks the return
current. With a negative differential voltage of 100 mV across
any DINx pin, the corresponding DOUTx+ pin sinks current, with
DOUTx sourcing the current. Table 15 and Table 16 show these
input/output combinations.
The output drive current is between 2.5 mA and 4.5 mA
(typically 3.1 mA), developing between 250 mV and 450 mV
across a 100 termination resistor (RT). The received voltage is
centered around 1.2 V. Note that because the differential voltage
(VID) reverses polarity, the peak-to-peak voltage swing across RT
is twice the differential voltage magnitude (|VID|).
VID (mV)
100
100
100 < VID < +100
Dont care
Logic
High
Low
Indeterminate
Dont care
Powered On
Yes
Yes
Yes
Yes
Output (DOUTx)
VOD (mV)
250
250
Indeterminate
250
Logic
High
Low
Indeterminate
High
Input (DINx)
VID (mV)
100
100
100 < VID < +100
Dont care
Logic
High
Low
Indeterminate
Dont care
Rev. B | Page 18 of 24
Powered On
Yes
Yes
Yes
Yes
Output (DOUTx)
VOD (mV)
250
250
250
250
Logic
High
Low
High
High
Data Sheet
ADN4650/ADN4651/ADN4652
100nF
VIN1
GND1
VDD1
100
20
19
VIN2
GND2
VDD2
18
GND1
17
GND2
DIN1+
16
TOP VIEW
(Not to Scale) 15
DOUT1+
DIN1
DOUT2+
14
DIN2+
DOUT2
13
DIN2
12
GND1
10
11
VDD1
ADN4651
100nF
DOUT1
100
VDD2
GND2
100nF
Figure 38. Required PCB Layout When Not Using the LDO (2.5 V Supply)
1F 100nF
1F
100
100nF 1F
1F
VIN2
VIN1
20
GND1
19
18
GND1
17
GND2
DIN1+
16
TOP VIEW
(Not to Scale) 15
DOUT1+
DIN1
DOUT2+
14
DIN2+
DOUT2
13
DIN2
12
GND1
10
11
VDD1
PCB LAYOUT
The ADN4650/ADN4651/ADN4652 can operate with high
speed LVDS signals up to 300 MHz clock, or 600 Mbps nonreturn
to zero (NRZ) data. With such high frequencies, it is particularly
important to apply best practices for the LVDS trace layout and
termination. Locate a 100 termination resistor as close as
possible to the receiver, across the DINx+ and DINx pins.
100nF
1
13677-035
VDD1
ADN4651
100nF
GND2
VDD2
DOUT1
100
VDD2
GND2
100nF
13677-036
ISOLATION
Figure 39. Required PCB Layout When Using the LDO (3.3 V Supply)
Rev. B | Page 19 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
1k
10
0.1
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
13677-037
0.01
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.92 kgauss induces a voltage
of 0.125 V at the receiving coil. This voltage is about 50% of the
sensing threshold and does not cause a faulty output transition.
If such an event occurs with the worst case polarity during a
transmitted pulse, it reduces the received pulse from >0.5 V to
0.375 V. This voltage is still higher than the 0.25 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADN4650/
ADN4651/ADN4652 transformers. Figure 41 expresses these
allowable current magnitudes as a function of frequency for
selected distances. The ADN4650/ADN4651/ADN4652 are
very insensitive to external fields. Only extremely large, high
frequency currents, very close to the component, can potentially
be a concern. For the 1 MHz example noted, a 2.29 kA current must
be placed 5 mm from the ADN4650/ADN4651/ADN4652 to
affect component operation.
DISTANCE = 1m
1k
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation barrier, pollution degree, and material group. The
material group and creepage for ADN4650/ADN4651/ADN4652
are presented in Table 4.
100
DISTANCE = 100mm
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
13677-038
10k
10
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
100
0.001
1k
Data Sheet
ADN4650/ADN4651/ADN4652
The working voltage across the barrier from Equation 1 is
(1)
(2)
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
or
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
VAC RMS
VPEAK
VDC
VRMS
TIME
Rev. B | Page 21 of 24
13677-039
ISOLATION VOLTAGE
ADN4650/ADN4651/ADN4652
Data Sheet
APPLICATIONS INFORMATION
Newer programmable logic controller (PLC) and input/output
modules communicate across an LVDS backplane, illustrating a
board to board LVDS interface, as shown in Figure 45. With a
daisy-chain type topology for transmit and receive to either
adjacent node, two ADN4651 (or ADN4652) devices on each
node can isolate four LVDS channels. The addition of galvanic
isolation allows a much more robust backplane interface port
on the PLC or input/output modules.
100
DCO
100
ISOLATION
ADN4650
100 D
100 DCO
FPGA/ASIC
100
CNV
100
100
CLK
100
CNV
13677-040
CLK
ISOLATION
AD7960
ADN4650
Figure 43. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4650)
CLK
100
100
ISOLATION
ADN4651
100 D
100
CLK
FPGA/ASIC
CNV
100
100 DCO
100
CNV
ADN4651
Figure 44. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4651)
Rev. B | Page 22 of 24
13677-040
100
DCO
ISOLATION
AD7960
Data Sheet
ADN4650/ADN4651/ADN4652
ISOLATION
100
ISOLATION
100
CONNECTOR
100
MODULE 1
100
100
100
100
ISOLATION
100
MODULE 2
100
100
ISOLATION
100
ISOLATION
100
100
CONNECTOR
100
13677-041
100
MCU 3
CONNECTOR
ISOLATION
100
ADN4651
100
MODULE 3
Figure 45. Example Isolated Backplane Implementation for PLCs and Input/Output Modules Using the ADN4651
SHIELDED
TWISTED PAIR
CABLE
Figure 46. Example Isolated LVDS Cable Application Using the ADN4651
Rev. B | Page 23 of 24
100
FPGA/
ASIC
100
13677-042
ISOLATION
100
ADN4651
CONNECTOR
100
CONNECTOR
100
FPGA/
ASIC
100
ADN4651
ISOLATION
CONNECTOR
ADN4651
100
MCU 2
ADN4651
MCU 1
ADN4650/ADN4651/ADN4652
Data Sheet
OUTLINE DIMENSIONS
13.00 (0.5118)
12.60 (0.4961)
11
20
7.60 (0.2992)
7.40 (0.2913)
10
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45
0.25 (0.0098)
8
0
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
ORDERING GUIDE
Model1
ADN4650BRWZ
ADN4650BRWZ-RL7
ADN4651BRWZ
ADN4651BRWZ-RL7
ADN4652BRWZ
ADN4652BRWZ-RL7
EVAL-ADN4650EB1Z
EVAL-ADN4651EB1Z
EVAL-ADN4652EB1Z
1
Temperature Range
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
Package Description
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
ADN4650 SOIC_W Evaluation Board
ADN4651 SOIC_W Evaluation Board
ADN4652 SOIC_W Evaluation Board
Rev. B | Page 24 of 24
Package Option
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20