TLC271

TLC271, TLC271A, TLC271B
LinCMOS PROGAMMABLE LOW-POWER

OPERATIONAL AMPLIFIERS
SLOS090B NOVEMBER 1987 REVISED AUGUST 1996
D
D
D
D
D
D
D
D
OFFSET N1
IN
IN +
GND
BIAS SELECT
VDD
OUT
OFFSET N2
FK PACKAGE
(TOP VIEW)
NC
OFFSET N1
NC
BIAS SELECT
NC
D, JG, OR P PACKAGE
(TOP VIEW)
Input Offset Voltage Drift . . . Typically

0.1 V/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0C to 70C . . . 3 V to 16 V
40C to 85C . . . 4 V to 16 V
55C to 125C . . . 5 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix
and I-Suffix Types)
Low Noise . . . 25 nV/Hz Typically at
f = 1 kHz (High-Bias Mode)
Output Voltage Range includes Negative
Rail
High Input Impedance . . . 1012 Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up Immunity
NC
IN
NC
IN +
NC
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
VDD
NC
OUT
NC
NC
GND
NC
OFFSET N2
NC
description
The TLC271 operational amplifier combines a

wide range of input offset voltage grades with low
NC No internal connection
offset voltage drift and high input impedance. In
addition, the TLC271 offers a bias-select mode
that allows the user to select the best combination of power dissipation and ac performance for a particular
application. These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset
voltage stability far exceeding the stability available with conventional metal-gate processes.
AVAILABLE OPTIONS
PACKAGE
TA
VIOmax
AT 25C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
0C
0C
to
70C
2 mV
5 mV
10 mV
TLC271BCD
TLC271ACD
TLC271CD
TLC271BCP
TLC271ACP
TLC271CP
40C
40 C
to
85C
2 mV
5 mV
10 mV
TLC271BID
TLC271AID
TLC271ID
TLC271BIP
TLC271AIP
TLC271IP
55C
to
125C
10 mV
TLC271MD
TLC271MFK
TLC271MJG
TLC271MP
The D package is available taped and reeled. Add R suffix to the device type (e.g.,
TLC271BCDR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265

DEVICE FEATURES
PARAMETER
BIAS-SELECT MODE
MEDIUM
PD
SR
3375
525
50
3.6
0.4
0.03
V/s
Vn
B1
25
32
68
0.5
0.09
MHz
170
480
V/mV
1.7
AVD
23
Typical at VDD = 5 V, TA = 25C
LOW
UNIT
HIGH
nV/Hz
description (continued)
Using the bias-select option, these cost-effective devices can be programmed to span a wide range of
applications that previously required BiFET, NFET or bipolar technology. Three offset voltage grades are
available (C-suffix and I-suffix types), ranging from the low-cost TLC271 (10 mV) to the TLC271B (2 mV)
low-offset version. The extremely high input impedance and low bias currents, in conjunction with good
common-mode rejection and supply voltage rejection, make these devices a good choice for new
state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are all easily designed with the TLC271. The
devices also exhibit low-voltage single-supply operation, making them ideally suited for remote and
inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and output are designed to withstand 100-mA surge currents without sustaining latch-up.
The TLC271 incorporates internal ESD-protection circuits that prevent functional failures at voltages up to 2000
V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices
as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized
for operation from 40C to 85C. The M-suffix devices are characterized for operation over the full military
temperature range of 55C to 125C.
bias-select feature
The TLC271 offers a bias-select feature that allows the user to select any one of three bias levels depending
on the level of performance desired. The tradeoffs between bias levels involve ac performance and power
dissipation (see Table 1).
DALLAS, TEXAS 75265

bias-select feature (continued)

Table 1. Effect of Bias Selection on Performance
MODE
TYPICAL PARAMETER VALUES

TA = 25
C, VDD = 5 V
25C,
HIGH BIAS
RL = 10 k
MEDIUM BIAS
RL = 100 k
LOW BIAS
RL = 1 M
UNIT
PD
SR
Power dissipation
3.4
0.5
0.05
mW
Slew rate
3.6
0.4
0.03
V/s
Vn
B1
Equivalent input noise voltage at f = 1 kHz
25
32
68
Unity-gain bandwidth
1.7
0.5
0.09
m
AVD
Phase margin
46
40
34
23
170
480
Large-signal differential voltage amplification
nV/Hz
MHz
V/mV
bias selection
Bias selection is achieved by connecting the bias select pin to one of three voltage levels (see Figure 1). For
medium-bias applications, it is recommended that the bias select pin be connected to the midpoint between the
supply rails. This procedure is simple in split-supply applications, since this point is ground. In single-supply
applications, the medium-bias mode necessitates using a voltage divider as indicated in Figure 1. The use of
large-value resistors in the voltage divider reduces the current drain of the divider from the supply line. However,
large-value resistors used in conjunction with a large-value capacitor require significant time to charge up to
the supply midpoint after the supply is switched on. A voltage other than the midpoint can be used if it is within
the voltages specified in Figure 1.
bias selection (continued)

VDD
Low
To the Bias
Select Pin
1 M
BIAS MODE
Medium
Low
High
1 M
BIAS-SELECT VOLTAGE
(single supply)
Medium
VDD
1 V to VDD 1 V
High
GND
0.01 F
Figure 1. Bias Selection for Single-Supply Applications
high-bias mode
In the high-bias mode, the TLC271 series features low offset voltage drift, high input impedance, and low noise.
Speed in this mode approaches that of BiFET devices but at only a fraction of the power dissipation. Unity-gain
bandwidth is typically greater than 1 MHz.
medium-bias mode
The TLC271 in the medium-bias mode features low offset voltage drift, high input impedance, and low noise.
Speed in this mode is similar to general-purpose bipolar devices but power dissipation is only a fraction of that
consumed by bipolar devices.
DALLAS, TEXAS 75265

low-bias mode
In the low-bias mode, the TLC271 features low offset voltage drift, high input impedance, extremely low power
consumption, and high differential voltage gain.
ORDER OF CONTENTS
TOPIC
BIAS MODE
schematic
all
absolute maximum ratings
all
recommended operating conditions
all
electrical characteristics
operating characteristics
typical characteristics
high
(Figures 2 33)
medium
(Figures 34 65)
low
(Figures 66 97)
parameter measurement information
all
application information
all
equivalent schematic
VDD
P3
P12
P9A
R6
P4
P1
P2
P5
P9B
P11
R2
IN
R1
P10
N5
IN +
N11
P6A
C1
R5
P6B
P7B
P7A
P8
N12
N3
N9
N6
N7
N1
N2
N4
R3
D1
D2
N13
R7
R4
OFFSET OFFSET
N1
N2
N10
OUT
GND
DALLAS, TEXAS 75265
BIAS
SELECT

absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Duration of short-circuit current at (or below) 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN .
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA 25C
POWER RATING
DERATING FACTOR
ABOVE TA = 25C
TA = 70C
POWER RATING
TA = 85C
POWER RATING
TA = 125C
POWER RATING
725 mW
5.8 mW/C
464 mW
377 mW
145 mW
FK
1375 mW
11.0 mW/C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/C
672 mW
546 mW
210 mW
1000 mW
8.0 mW/C
640 mW
520 mW
200 mW
recommended operating conditions
Supply voltage, VDD

Common-mode input voltage
voltage, VIC
VDD = 5 V
VDD = 10 V
Operating free-air temperature, TA
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MIN
MAX
MIN
MAX
MAX
16
16
16
0.2
3.5
0.2
3.5
3.5
0.2
8.5
0.2
8.5
8.5
70
40
85
55
125
DALLAS, TEXAS 75265
UNIT
V
V
C

HIGH-BIAS MODE
electrical characteristics at specified free-air temperature (unless otherwise noted)
TLC271C, TLC271AC, TLC271BC
TEST
CONDITIONS
PARAMETER
I
Input
offset
ff
voltage
l
TLC271AC
VO = 1
1.4
4V
V,
VIC = 0 V,
RS = 50 ,
RL = 10 k
TLC271BC
VIO
Average temperature coefficient

of input offset voltage
IIO
Input offset current (see Note 4)
IIB
Input bias current (see Note 4)
VICR
VOH
VOL
AVD
CMRR
Low-level
p voltage
L
l
l output
l g
Large-signal
Large
signal differential
voltage amplification
Common-mode
C
d rejection
j i ratio
i
1.1
Full range
0.9
Full range
0.34
1.8
VO = VDD /2,
VIC = VDD /2
25C
0.1
70C
VO = VDD /2,
VIC = VDD /2
25C
0.6
70C
40
25C
0.2
to
4
Full range
0.2
to
3.5
RL = 10 k,
k
See Note 6
VIC = VICRmin
i
1.1
0.9
10
5
6.5
0.39
3
V/C
0.1
300
300
0.7
600
50
0.2
to
9
600
0.3
to
9.2
3.2
3.8
8.5
0C
3.8
7.8
8.5
70C
3.8
7.8
8.4
25C
50
50
0C
50
50
50
50
25C
23
10
36
0C
27
7.5
42
70C
20
7.5
32
25C
65
80
65
85
0C
60
84
60
88
70C
60
85
60
88
25C
65
95
65
95
0C
60
94
60
94
70C
60
96
60
96
dB
II(SEL)
Input current (BIAS SELECT)
VI(SEL) = 0
25C
1.4
675
1600
950
2000
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
No
d
25C
IDD
0C
775
1800
1125
2200
70C
575
1300
750
Full range is 0C to 70C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
1700
DALLAS, TEXAS 75265
mV
V
V/mV
V/ V
VDD = 5 V to 10 V
VO = 1.4 V
pA
Supply-voltage
Supply
voltage rejection ratio
(VDD /VIO)
kSVR
pA
0.2
to
8.5
25C
70C
mV
V
0.3
to
4.2
UNIT
12
25C to
70C
100 mV
VID = 100
mV,
IOL = 0
10
6.5
25C
mV
VID = 100 mV,
RL = 10 k
VDD = 10 V
TYP
MAX
MIN
12
25C
Full range

range (see Note 5)
High l
High-level
l output
p voltage
l g
VDD = 5 V
MIN
TYP
MAX
25C
TLC271C
VIO
TA
dB
A
1.9
A
A

HIGH-BIAS MODE
TLC271I, TLC271AI, TLC271BI
TEST
CONDITIONS
PARAMETER
I
Input
offset
ff
voltage
l
TLC271AI
VO = 1
1.4
4V
V,
VIC = 0 V,
RS = 50 ,
RL = 10 k
TLC271BI
VIO

IIO
IIB
VICR
VOH
VOL
AVD
CMRR
Low-level
p voltage
L
l
l output
l g
Large-signal
Large
signal differential
Common-mode
C
d rejection
j i ratio
i
0.9
Full range
25C
0.34
VO = VDD /2,
VIC = VDD /2
25C
0.1
85C
24
VO = VDD /2,
VIC = VDD /2
25C
0.6
85C
200
RL = 10 k,
k
See Note 6
VIC = VICRmin
i
VDD = 5 V to 10 V
VO = 1.4 V
II(SEL)
VI(SEL) = 0
IDD
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
No
d
1.1
25C
0.2
to
4
0.9
Full range
0.2
to
3.5
10
5
7
0.39
V/C
0.1
1000
26
1000
0.7
2000
220
0.2
to
9
2000
0.3
to
9.2
3.2
3.8
8.5
3.8
7.8
8.5
85C
3.8
7.8
8.5
25C
50
50
40C
50
50
50
50
25C
23
10
36
40C
3.5
32
46
85C
3.5
19
31
25C
65
80
65
85
40C
60
81
60
87
85C
60
86
60
88
25C
65
95
65
95
40C
60
92
60
92
85C
60
96
60
96
mV
V
V/mV
V/ V
dB
dB
A
25C
1.4
25C
675
1600
950
2000
40C
950
2200
1375
2500
85C
525
1200
725
1600
DALLAS, TEXAS 75265
pA
25C
pA
0.2
to
8.5
40C
85C
mV
V
3.5
2
0.3
to
4.2
UNIT
13
3.5
1.8
VID = 100
100 mV
mV,
IOL = 0
10
25C to
85C
VID = 100 mV
mV,
RL = 10 k
VDD = 10 V
TYP
MAX
MIN
13
25C
Full range
Supply-voltage
Supply
(VDD /VIO)
kSVR
1.1
Full range
Common mode input

Common-mode
voltage range (see Note 5)
High l
High-level
l output
p voltage
l g
VDD = 5 V
MIN
TYP
MAX
25C
TLC271I
VIO
TA
1.9
A
A

HIGH-BIAS MODE
PARAMETER
VIO
I
ff
l
Input
offset
voltage
VIO

IIO
IIB
VICR
VOH
VOL
AVD
CMRR
TEST
CONDITIONS
VO = 1.4 V,
VIC = 0 V,
RS = 50 ,,
RL = 10 k
TA
25C
Low-level
L
l
l output
p voltage
l g
Large-signal
Large
signal differential
C
Common-mode
d rejection
j i ratio
i
11
1.1
10
11
1.1
VO = VDD /2,
VIC = VDD /2
VO = VDD /2,
VIC = VDD /2
10
12
12
25C to
125C
2.1
2.2
V/C
25C
0.1
0.1
pA
125C
1.4
25C
0.6
125C
25C
0
to
4
Full range
0
to
3.5
15
1.8
15
0.7
35
0.3
to
4.2
10
0
to
9
35
0.3
to
9.2
0
to
8.5
25C
3.2
3.8
8.5
3.8
7.8
8.5
125C
3.8
7.8
8.4
25C
50
50
100 mV
VID = 100
mV,
IOL = 0
55C
50
50
50
50
RL = 10 k,
k
See Note 6
VIC = VICRmin
i
Supply-voltage
Supply
(VDD /VIO)
VDD = 5 V to 10 V
VO = 1.4 V
II(SEL)
VI(SEL) = 0
IDD
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
No
d
25C
23
10
36
55C
3.5
35
50
125C
3.5
16
27
25C
65
80
65
85
55C
60
81
60
87
125C
60
84
60
86
25C
65
95
65
95
55C
60
90
60
90
125C
60
97
60
25C
1.4
dB
dB
97
A
1.9
25C
675
1600
950
2000
1000
2500
1475
3000
125C
475
1100
625
1400
DALLAS, TEXAS 75265
mV
V
V/mV
V/ V
55C
nA
V
55C
125C
nA
pA
mV
VID = 100 mV,
RL = 10 k
kSVR
UNIT
V
mV
Full range
Common mode input voltage

Common-mode
range (see Note 5)
High l
High-level
l output
p voltage
l g
TLC271M
VDD = 5 V
VDD = 10 V
MIN
TYP
MAX
MIN
TYP
MAX
A
A

HIGH-BIAS MODE
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
i gain
i
Slew
rate at unity
RL = 10 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH ,
RL = 10 k,
CL = 20 pF
pF,
See Figure 98
B1
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
mV
VI = 10 mV,
See Figure 100
mV
VI = 10 mV,
CL = 20 pF,
CL = 20 pF
pF,
f = B1,
See Figure 100
TYP
25C
3.6
0C
70C
25C
2.9
0C
3.1
70C
2.5
25C
25
25C
320
0C
340
70C
260
25C
1.7
0C
70C
1.3
25C
46
0C
47
70C
44
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
MHz
MH

PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 10 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
bandwidth
M i
p
i gb
d id h
VO = VOH,
RL = 10 k,
CL = 20 pF
pF,
See Figure 98
B1
Unity-gain
U i y g i bandwidth
b d id h
Ph
Phase
margin
gi
mV
VI = 10 mV,
See Figure 100
f = B1,
CL = 20 pF,
CL = 20 pF
pF,
mV
VI = 10 mV,
See Figure 100
DALLAS, TEXAS 75265
TYP
25C
5.3
0C
5.9
70C
4.3
25C
4.6
0C
5.1
70C
3.8
25C
25
25C
200
0C
220
70C
140
25C
2.2
0C
2.5
70C
1.8
25C
49
0C
50
70C
46
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
MHz
MH

HIGH-BIAS MODE
PARAMETER
TEST CONDITIONS
TA
TLC271I, TLC271AI,
TLC271BI
MIN
VI(PP) = 1 V
SR
Sl
i gain
i
Slew
rate at unity
RL = 10 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 10 k
k,
CL = 20 pF
pF,
See Figure 98
B1
U i y g i bandwidth
Unity-gain
b d id h
Phase
margin
gi
Ph
VI = 10 mV,
mV
See Figure 100
VI = 10 mV,
mV
CL = 20 pF,
pF
CL = 20 pF
pF,
f = B1,
See Figure 100
TYP
25C
3.6
40C
4.5
85C
2.8
25C
2.9
40C
3.5
85C
2.3
25C
25
25C
320
40C
380
85C
250
25C
1.7
40C
2.6
85C
1.2
25C
46
40C
49
85C
43
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
MH
MHz

PARAMETER
TEST CONDITIONS
TA
TLC271I, TLC271AI,
TLC271BI
MIN
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 10 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
bandwidth
M i
p
i gb
d id h
VO = VOH,
RL = 10 k
k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV,
mV
See Figure 100
CL = 20 pF
pF,
B1
10
Unity-gain
U i y g i bandwidth
b d id h
Ph
Phase
margin
gi
VI = 10 mV,
mV
CL = 20 pF,
pF
f B1,
f=
See Figure 100
DALLAS, TEXAS 75265
TYP
25C
5.3
40C
6.8
85C
25C
4.6
40C
5.8
85C
3.5
25C
25
25C
200
40C
260
85C
130
25C
2.2
40C
3.1
85C
1.7
25C
49
40C
52
85C
46
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
MHz
MH

HIGH-BIAS MODE
PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 10 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
BOM
B1
f = 1 kHz,
See Figure 99
RS = 20 ,
M i
Maximum
output-swing
p
i gb
bandwidth
d id h
VO = VOH,
RL = 10 k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV,
mV
See Figure 100
CL = 20 pF
pF,
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
VI = 10 mV,
mV
CL = 20 pF,
f = B1,
See Figure 100
TA
MIN
TLC271M
TYP
MAX
25C
3.6
55C
4.7
125C
2.3
25C
2.9
55C
3.7
125C
25C
25
25C
320
55C
400
125C
230
25C
1.7
55C
2.9
125C
1.1
25C
46
55C
49
125C
41
UNIT
V/s
nV/Hz
kH
kHz
MHz
MH

PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 10 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
M i
Maximum
output-swing
p
i gb
bandwidth
d id h
VO = VOH,
RL = 10 k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV,
mV
See Figure 100
CL = 20 pF
pF,
B1
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
f = B1,
CL = 20 pF,
VI = 10 mV,
mV
See Figure 100
DALLAS, TEXAS 75265
TA
MIN
TLC271M
TYP
MAX
25C
5.3
55C
7.1
125C
3.1
25C
4.6
55C
6.1
125C
2.7
25C
25
25C
200
55C
280
125C
110
25C
2.2
55C
3.4
125C
1.6
25C
49
55C
52
125C
44
UNIT
V/
V/s
nV/Hz
kH
kHz
MHz
MH
11

TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)

Table of Graphs
FIGURE
12
VIO
VIO
Input offset voltage
Distribution
2, 3
Temperature coefficient
Distribution
4, 5
VOH
High l
High-level
l output
p voltage
l g
vs High-level
High level output current
vs Supply
pp y voltage
g
vs Free-air temperature
6, 7
8
9
VOL
L
l
l output voltage
l
Low-level
vs Common-mode input voltage

vs Differential input voltage
p
vs Low-level output current
10, 11
12
13
14, 15
AVD
Large-signal
plifi i
L g ig l differential
diff
i l voltage
l g amplification
vs Supply voltage
p
vs Frequency
16
17
28, 29
IIB
IIO
Input bias current
18
Input offset current
18
VIC
vs Supply voltage
19
IDD
Supply current
vs Supply voltage
20
21
SR
Slew rate
vs Supply voltage
22
23
Bias-select current
vs Supply voltage
24
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
25
B1
vs Free
Free-air
air temperature
vs Supply voltage
26
27
AVD
Large-signal differential voltage amplification
vs Frequency
Phase
margin
gi
Ph
vs Supply voltage
p
vs Load capacitance
Vn
vs Frequency
33
Phase shift
vs Frequency
28, 29
DALLAS, TEXAS 75265
28, 29
30
31
32


DISTRIBUTION OF TLC271
INPUT OFFSET VOLTAGE
Percentage of Units %
50
60
40
30
20
753 Amplifiers Tested From 6 Wafer Lots

VDD = 10 V

VDD = 5 V
TA = 25C
P Package
50
60
TA = 25C
P Package
40
30
20
10
10
0
5 4 3 2 1 0
1
2
3
VIO Input Offset Voltage mV
0
1
2
3
5 4 3 2 1 0
Figure 2
40

VDD = 5 V
TA = 25C to 125C
P Package
Outliers:
(1) 20.5 V/C
30
20
10
TEMPERATURE COEFFICIENT
60
50
50
Figure 3
60
40
324 Amplifiers Tested From 8 Wafer lots

VDD = 10 V
TA = 25C to 125C
P Package
Outliers:
(1) 21.2 V/C
30
20
10
0
10 8 6 4 2 0
2
4
6
8
VIO Temperature Coefficient V/C
10
0
10 8 6 4 2 0
2
4
6
8
Figure 4
10
Figure 5
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
DALLAS, TEXAS 75265
13


HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT

vs
16
VID = 100 mV
TA = 25C
VOH High-Level Output Voltage V

VOH

VOH
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
14
VDD = 16 V
12
10
VDD = 10 V
4
2
0
0
0
2
4
6
8
IOH High-Level Output Current mA
10
15 20 25
30
35 40
Figure 7

vs
SUPPLY VOLTAGE

vs
FREE-AIR TEMPERATURE
16
VDD 1.6
VID = 100 mV
RL = 10 k
TA = 25C
14

VOH
VOH
10
Figure 6
VID = 100 mV
TA = 25C
12
10
8
6
4
2
0
0
4
6
8
10
12
VDD Supply Voltage V
14
16
1.7
VDD = 5 V
IOH = 5 mA
VID = 100 mA
1.8
1.9
2
VDD = 10 V
2.1
2.2
2.3
2.4
75
Figure 8
50 25
0
20
50
75
100
TA Free-Air Temperature C
Figure 9
14
DALLAS, TEXAS 75265
125


LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE

vs
500
VDD = 5 V
IOL = 5 mA
TA = 25C
650
600
VOL
VOL Low-Level Output Voltage mV
VOL
700
550
VID = 100 mV
500
450
450
400
VID = 100 mV
VID = 1 V
350
VID = 2.5 V
400
VID = 1 V
350
300
250
300
0
VDD = 10 V
IOL = 5 mA
TA = 25C
1
2
3
VIC Common-Mode Input Voltage V
1
3
5
7
9
2
4
6
8
Figure 11
Figure 10
vs
DIFFERENTIAL INPUT VOLTAGE

vs
900
IOL = 5 mA
VIC = VID/2
TA = 25C
700
VOL
VOL
800
600
500
VDD = 5 V
400
300
10
VDD = 10 V
200
100
0
0
2 3 4 5 6 7 8 9 10
VID Differential Input Voltage V
800
IOL = 5 mA
VID = 1 V
VIC = 0.5 V
700
VDD = 5 V
600
500
400
VDD = 10 V
300
200
100
0
75
50
Figure 12
25
0
25
50
75
100
125
Figure 13
DALLAS, TEXAS 75265
15


vs
LOW-LEVEL OUTPUT CURRENT

vs
3
VID = 1 V
VIC = 0.5 V
TA = 25C
0.9
0.8
VOL
VOL
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
VID = 1 V
VIC = 0.5 V
TA = 25C
2.5
2
VDD = 10 V
1.5
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
IOL Low-Level Output Current mA
0.5
5
10
15
20
25
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
AAVD
VD Differential Voltage Amplification V/mV
RL = 10 k
50
40
0C
85C
125C
10
0
2
4
6
8
10
12
14
16
RL = 10 k
45
20
50
TA = 55C
25C
30
LARGE-SIGNAL
vs
AVD
AVD Large-Signal Differential
Voltage Amplification V/mV
60
40
VDD = 10 V
35
30
25
20
VDD = 5 V
15
10
5
0
75
50
25
0
25
50
75
100
Figure 17
Figure 16
16
30
Figure 15
Figure 14
VDD = 16 V
DALLAS, TEXAS 75265
125


INPUT BIAS CURRENT AND INPUT OFFSET
CURRENT
vs
10000
16
V IC Common-Mode Input Voltage V
IIB
I IO Input Bias and
IIB and IIO
Input Offset Currents nA
VDD = 10 V
VIC = 5 V
See Note A
1000
IIB
100
IIO
10
0.1
25

(POSITIVE LIMIT)
vs
SUPPLY VOLTAGE
45
65
85
105
TA = 25C
14
12
10
8
6
4
2
0
125
IDD
I DD Supply Current mA
TA = 55C
0C
1.5
25C
1
70C
125C
0.5
0
0
VO = VDD /2
No Load
4
6
8
10
12
14
16
IDD
I DD Supply Current mA
VO = VDD /2
No Load
16
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
14
Figure 19
Figure 18
2.5
4
6
8
10
12
1.5
VDD = 10 V
VDD = 5 V
0.5
0
75
50
25
0
25
50
75
100
125
Figure 21
Figure 20
NOTE A: The typical values of input bias current and input offset current below 5 pA were determined mathematically.
DALLAS, TEXAS 75265
17


SLEW RATE
vs
SLEW RATE
vs
SUPPLY VOLTAGE
AV = 1
VI(PP) = 1 V
RL = 10 k
CL = 20 pF
TA = 25C
See Figure 98
SR Slew Rate V/ us
s
SR Slew Rate V/ us
s
5
4
3
4
3
2
4
6
8
10
12
14
VDD = 10 V
VI(PP) = 1 V
VDD = 10 V
VI(PP) = 5.5 V
VDD = 5 V
VI(PP) = 1 V
50
TA = 25C
VI(SEL) = 0
Bias-Select Current ua
A
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
4
6
8
10
12
14
16
VO(PP) Maximum Peak-to-Peak Output Voltage V
10
VDD = 10 V
9
8
TA = 125C
TA = 25C
TA = 55C
7
6
5
VDD = 5 V
4
3
RL = 10 k
See Figure 98
2
1
0
10
100
1000
f Frequency kHz
Figure 25
Figure 24
18
125
MAXIMUM PEAK-TO-PEAK OUTPUT

VOLTAGE
vs
FREQUENCY
BIAS-SELECT CURRENT
vs
SUPPLY VOLTAGE
25
0
25
50
75
100
Figure 23
Figure 22
2.7
VDD = 5 V
VI(PP) = 2.5 V
0
75
16
AV = 1
RL = 10 k
CL = 20 pF
See Figure 99
DALLAS, TEXAS 75265
10000


UNITY-GAIN BANDWIDTH
vs
2.5
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 100
B1
B1 Unity-Gain Bandwidth MHz
B1
vs
SUPPLY VOLTAGE
2.5
1.5
1
75
50
25
0
25
50
75
100
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 100
1.5
125
4
6
8
10
12
14
16
Figure 27
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
105
104
30
AVD
103
60
102
90
Phase Shift
AVD
Voltage Amplification
106
VDD = 5 V
RL = 10 k
TA = 25C
Phase Shift
101
120
150
0.1
10
100
1k
10 k
100 k
f Frequency Hz
1M
180
10 M
Figure 28
DALLAS, TEXAS 75265
19


LARGE-SCALE DIFFERENTIAL VOLTAGE
vs
FREQUENCY
107
VDD = 10 V
RL = 10 k
TA = 25C
105
104
30
Phase Shift
AVD
106
AVD
103
60
102
90
Phase Shift
101
120
150
0.1
100
10
1k
10 k
100 k
f Frequency Hz
1M
180
10 M
Figure 29
PHASE MARGIN
vs
PHASE MARGIN
vs
SUPPLY VOLTAGE
53
50
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 100
52
48
m
m Phase Margin
m
m Phase Margin
51
50
49
48
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 100
47
46
45
0
4
6
8
10
12
14
16
46
44
42
40
75 50 25
0
25
50
75
100
Figure 30
Figure 31
20
DALLAS, TEXAS 75265
125


PHASE MARGIN
vs
CAPACITIVE LOAD
VDD = 5 mV
VI = 10 mV
TA = 25C
See Figure 100
45
40
35
30
VN
nV/ Hz
V n Equivalent Input Noise Voltage nV/Hz
400
50
m
m Phase Margin
EQUIVALENT NOISE VOLTAGE

vs
FREQUENCY
VDD = 5 V
RS = 20
TA = 25C
See Figure 99
350
300
250
200
150
100
50
0
25
0
20
40
60
80
CL Capacitive Load pF
100
10
100
f Frequency Hz
1000
Figure 33
Figure 32
DALLAS, TEXAS 75265
21

MEDIUM-BIAS MODE
PARAMETER
I
offset
ff
l
Input
voltage
TLC271AC
VDD = 5 V
MIN
TYP
MAX
25C
TLC271C
VIO
TA
TEST CONDITIONS
VO = 1.4
1 4 V,
V
VIC = 0
RS = 50 ,
RI = 100 k
TLC271BC
1.1
Full range
0.9
Full range
25C
0.25
Full range
IIO
VO = VDD /2,,
VIC = VDD /2
25C
0.1
70C
IIB
VO = VDD /2,,
VIC = VDD /2
25C
0.6
70C
40
VOL
AVD
CMRR
25C to
70C
1.7
25C
0.2
to
4
High-level
High l
l output
p voltage
l g
Full range
0.2
to
3.5
Low-level
p voltage
L
l
l output
l g
mV
VID = 100 mV,
RL = 100 k
100 mV,
mV
VID = 100
IOL = 0
Large-signal
Large
signal differential
RL = 100 k,
k
See Note 6
C
Common-mode
d rejection
j i ratio
i
VIC = VICRmin
i
0.9
10
5
6.5
0.26
3
V/C
0.1
300
300
0.7
600
50
0.2
to
9
600
0.3
to
9.2
3.2
3.9
8.7
0C
3.9
7.8
8.7
70C
7.8
8.7
25C
50
50
0C
50
50
50
50
25C
25
170
25
275
0C
15
200
15
320
70C
15
140
15
230
25C
65
91
65
94
0C
60
91
60
94
70C
60
92
60
94
25C
70
93
70
93
0C
60
92
60
92
70C
60
94
60
dB
VDD = 5 V to 10 V
VO = 1.4 V
II(SEL)
VI(SEL) = VDD /2
25C
130
25C
105
280
143
300
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
d
No
0C
125
320
173
400
70C
85
220
110
280
DALLAS, TEXAS 75265
dB
94
160

mV
V
V/mV
V/ V
Supply-voltage
Supply
(VDD /VIO)
22
pA
kSVR
IDD
pA
0.2
to
8.5
25C
70C
V
mV
2.1
0.3
to
4.2
UNIT
12
VIO
VOH
1.1
6.5

VICR
10
12
25C
Common-mode input
p
VDD = 10 V
TYP
MAX
MIN
nA
A

MEDIUM-BIAS MODE
PARAMETER
I
ff
l
Input
offset
voltage
TLC271AI
VO = 1.4
1 4 V,
V
VIC = 0 V,,
RS = 50 ,
RL = 100 k
TLC271BI
VIO

IIO
IIB
VICR
VOH
VOL
AVD
CMRR
Low-level
p voltage
L
l
l output
l g
1.1
Full range
VDD = 10 V
TYP
MAX
0.9
Full range
10
1.1
25C
0.25
0.9
1.7
VO = VDD /2,,
VIC = VDD /2
25C
0.1
85C
24
VO = VDD /2,,
VIC = VDD /2
25C
0.6
85C
200
25C
0.2
to
4
Full range
0.2
to
3.5
5
7
0.26
3.5
25C to
85C
10
13
5
7
Full range
V/C
0.1
1000
26
2000
220
1000
0.7
0.2
to
9
2000
0.3
to
9.2
pA
25C
3.2
3.9
8.7
mV
VID = 100 mV,
RL = 100 k
40C
3.9
7.8
8.7
85C
7.8
8.7
25C
50
50
100 mV,
mV
VID = 100
IOL = 0
40C
50
50
50
50
25C
25
170
25
275
Large-signal
Large
signal differential
RL = 100 k,
k
See Note 6
40C
15
270
15
390
85C
15
130
15
220
25C
65
91
65
94
C
Common-mode
d rejection
j i ratio
i
VIC = VICRmin
i
40C
60
90
60
93
85C
60
90
60
94
25C
70
93
70
93
40C
60
91
60
91
85C
60
94
60
mV
V
V/mV
V/ V
dB
kSVR
Supply-voltage
Supply
(VDD /VIO)
VDD = 5 V to 10 V
VO = 1.4 V
II(SEL)
VI(SEL) = VDD /2
25C
130
25C
105
280
143
300
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
d
No
40C
158
400
225
450
85C
80
200
103
260
IDD
pA
0.2
to
8.5
85C
V
mV
3.5
2.1
0.3
to
4.2
UNIT
MIN
13
25C
Common-mode input
p
High-level
High l
l output
p voltage
l g
VDD = 5 V
MIN
TYP
MAX
25C
TLC271I
VIO
TA
TEST CONDITIONS
dB
94
160
nA
A

DALLAS, TEXAS 75265
23

MEDIUM-BIAS MODE
PARAMETER
VIO
TEST
CONDITIONS
VO = 1.4 V,
VIC = 0 V,
25C
RS = 50 ,
RL = 100 k
Full range
VIO

IIO
VO = VDD /2,,
VIC = VDD /2
VO = VDD /2,,
VIC = VDD /2
IIB
VICR
VOH
VOL
AVD
CMRR
kSVR
II(SEL)
IDD
TA
TLC271M
VDD = 5 V
VDD = 10 V
MIN
TYP
MAX
MIN
TYP
MAX
1.1
1.1
12
25C to
125C
1.7
25C
0.1
125C
1.4
25C
0.6
125C
25C
0
to
4
Full range
0
to
3.5
Common-mode input
p
10
V/C
2.1
0.1
15
1.8
pA
15
0.7
35
0.3
to
4.2
10
0
to
9
0.3
to
9.2
0
to
8.5
25C
3.2
3.9
8.7
3.9
7.8
8.6
125C
7.8
8.6
25C
50
50
100 mV,
mV
VID = 100
IOL = 0
55C
50
50
125C
50
50
25C
25
170
25
275
Large signal differential

Large-signal
RL = 10 k
See Note 6
55C
15
290
15
420
125C
15
120
15
190
25C
65
91
65
94
Common-mode
C
d rejection
j i ratio
i
VIC = VICRmin
i
55C
60
89
60
93
125C
60
91
60
93
25C
70
93
70
93
55C
60
91
60
91
125C
60
94
60
94
dB
VDD = 5 V to 10 V
VO = 1.4 V
VI(SEL) = VDD /2
25C
130
VO = VDD /2,
VIC = VDD /2,
N lload
d
No
25C
105
280
143
300
55C
170
440
245
500
125C
70
180
90
240
DALLAS, TEXAS 75265
mV
V
V/ V
V/mV
Supply-voltage
Supply
(VDD /VIO)
Supply
S pply current
nA
V
55C
Low-level
p voltage
L
l
l output
l g
nA
pA
35
mV
VID = 100 mV,
RL = 100 k
High-level
p voltage
High l
l output
l g
mV
12
dB
160

24
10
UNIT
nA
A

MEDIUM-BIAS MODE
PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
i gain
i
Slew
rate at unity
RL = 100 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 100 k
k,
CL = 20 pF
pF,
See Figure 98
B1
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
VI = 10 mV,
mV
See Figure 100
VI = 10 mV,
mV
CL = 20 pF,
pF
CL = 20 pF
pF,
f = B1,
See Figure 100
TYP
25C
0.43
0C
0.46
70C
0.36
25C
0.40
0C
0.43
70C
0.34
25C
32
25C
55
0C
60
70C
50
25C
525
0C
600
70C
400
25C
40
0C
41
70C
39
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
kHz
kH

PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 100 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 100 k
k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV,
mV
See Figure 100
CL = 20 pF
pF,
B1
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
Ph
gi
VI = 10 mV,
mV
CL = 20 pF,
pF
f = B1,
See Figure 100
DALLAS, TEXAS 75265
TYP
25C
0.62
0C
0.67
70C
0.51
25C
0.56
0C
0.61
70C
0.46
25C
32
25C
35
0C
40
70C
30
25C
635
0C
710
70C
510
25C
43
0C
44
70C
42
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
kHz
kH
25

MEDIUM-BIAS MODE
PARAMETER
TEST CONDITIONS
TA
TLC271I, TLC271AI,
TLC271BI
MIN
VI(PP) = 1 V
SR
Sl
i gain
i
Slew
rate at unity
RL = 100 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 100 k
k,
CL = 20 pF
pF,
See Figure 98
B1
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
VI = 10 mV
mV,
See Figure 100
VI = 10 mV
mV,
CL = 20 pF,
pF
CL = 20 pF
pF,
f = B1,
See Figure 100
TYP
25C
0.43
40C
0.51
85C
0.35
25C
0.40
40C
0.48
85C
0.32
25C
32
25C
55
40C
75
85C
45
25C
525
40C
770
85C
370
25C
40
40C
43
85C
38
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
MHz
MH

PARAMETER
TEST CONDITIONS
TA
TLC271I, TLC271AI,
TLC271BI
MIN
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 100 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,3
3
RL = 100 k
k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV
mV,
See Figure 100
CL = 20 pF
pF,
B1
26
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
Ph
gi
VI = 10 mV
mV,
CL = 20 pF,
pF
f = B1,
See Figure 100
DALLAS, TEXAS 75265
TYP
25C
0.62
40C
0.77
85C
0.47
25C
0.56
40C
0.70
85C
0.44
25C
32
25C
35
40C
45
85C
25
25C
635
40C
880
85C
480
25C
43
40C
46
85C
41
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
kHz
kH

MEDIUM-BIAS MODE
PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 100 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
BOM
B1
f = 1 kHz,
See Figure 99
RS = 20 ,
Maximum
output-swing
M i
p
i g bandwidth
b d id h
VO = VOH,
RL = 100 k
k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV
mV,
See Figure 100
CL = 20 pF
pF,
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
VI = 10 mV
mV,
CL = 20 pF,
pF
f = B1,
See Figure 100
TA
TLC271M
MIN
TYP
25C
0.43
55C
0.54
125C
0.29
25C
0.40
55C
0.50
125C
0.28
25C
32
25C
55
55C
80
125C
40
25C
525
55C
850
125C
330
25C
40
55C
43
125C
36
MAX
UNIT
V/
V/s
nV/Hz
kHz
kH
kHz
kH

PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 100 k,
k
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
BOM
B1
f = 1 kHz,
See Figure 99
RS = 20 ,
M i
Maximum
output-swing
p
i gb
bandwidth
d id h
VO = VOH,
RL = 100 k
k,
CL = 20 pF
pF,
See Figure 98
VI = 10 mV
mV,
See Figure 100
CL = 20 pF
pF,
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
VI = 10 mV
mV,
CL = 20 pF,
pF
f = B1,
See Figure 100
DALLAS, TEXAS 75265
TA
TLC271M
MIN
TYP
25C
0.62
55C
0.81
125C
0.38
25C
0.56
55C
0.73
125C
0.35
25C
32
25C
35
55C
50
125C
20
25C
635
55C
960
125C
440
25C
43
55C
47
125C
39
MAX
UNIT
V/
V/s
nV/Hz
kH
kHz
kHz
kH
27

TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)

Table of Graphs
FIGURE
28
VIO
VIO
Distribution
34, 35
Distribution
36, 37
VOH
High l
High-level
l output
p voltage
l g
vs High-level
vs Supply
pp y voltage
g
38, 39
40
41
VOL
L
l
l output voltage
l
Low-level

p
42, 43
44
45
46, 47
AVD
Large-signal
plifi i
diff
i l voltage
l g amplification
vs Supply voltage
p
vs Frequency
48
49
60, 61
IIB
IIO
Input bias current
50
50
VI
Maximum Input voltage
vs Supply voltage
51
IDD
Supply current
vs Supply voltage
52
53
SR
Slew rate
vs Supply voltage
54
55
Bias-select current
vs Supply voltage
56
VO(PP)
vs Frequency
57
B1
vs Free
Free-air
air temperature
vs Supply voltage
58
59
Phase
margin
gi
Ph
vs Supply voltage
p
vs Load capacitance
62
63
64
Vn
vs Frequency
65
Phase shift
vs Frequency
60, 61
DALLAS, TEXAS 75265


50
40
60

VDD = 5 V
TA = 25C
N Package

VDD = 5 V
TA = 25C
N Package
50
60
30
20
10
40
30
20
10
0
5
3 2 1
0
1
2
3
Figure 34
60
224 Amplifiers Tested From 6 Water Lots

VDD = 5 V
TA = 25C to 125C
P Package
Outliers:
(1) 33.0 V/C
50
60
40
Figure 35
50
3 2 1 0
1
2
3
30
20
10
40
224 Amplifiers Tested From 6 Water Lots

VDD = 10 V
TA = 25C to 125C
P Package
Outliers:
(1) 34.6 V/C
30
20
10
0
10 8 6 4 2
0
2 4
6
8
10
0
10 8 6 4 2
0
2 4
6
8
10
Figure 37
Figure 36
DALLAS, TEXAS 75265
29


vs

vs
16
VID = 100 mV
TA = 25C
V
VOH
OH High-Level Output Voltage V
V
VOH
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
VID = 100 mV
TA = 25C
14
VDD = 16 V
12
10
8
VDD = 10 V
6
4
2
0
0
0
2
4
6
8
10
5 10 15 20 25 30 35 40
Figure 39
Figure 38

vs

vs
SUPPLY VOLTAGE
VDD 1.6
VID = 100 mV
RL = 10 k
TA = 25C
14
V
VOH
V
VOH
16
12
10
8
6
4
2
0
0
4
6
8
10
12
14
16
IOH = 5 mA
VID = 100 mA
1.7
VDD = 5 V
1.8
1.9
2
VDD = 10 V
2.1
2.2
2.3
2.4
75
50 25
0
20
50
75
100
Figure 40
Figure 41
30
DALLAS, TEXAS 75265
125


vs

vs
500
VDD = 5 V
IOL = 5 mA
TA = 25C
650
VOL
VOL
700
600
550
VID = 100 mV
500
450
450
400
VID = 100 mV
VID = 1 V
350
VID = 2.5 V
400
VID = 1 V
350
300
250
300
0
VDD = 10 V
IOL= 5 mA
TA = 25C
1
2
3
1
2
3
4
5 6
7
8
9
Figure 43
Figure 42
vs
VOL
IOL = 5 mA
VIC = |VID/2|
TA = 25C
700
600
500
VDD = 5 V
400
300

vs
900
VOL
800
10
800
IOL = 5 mA
VID = 1 V
VIC = 0.5 V
700
VDD = 5 V
600
500
400
VDD = 10 V
300
VDD = 10 V
200
100
200
100
0
0
2 3 4 5 6 7 8
9 10
0
75
50
Figure 44
25
0
25
50
75
100
125
Figure 45
DALLAS, TEXAS 75265
31


vs
1
3
VOL
VOL Low-Level Output Voltage V
VID = 1 V
VIC = 0.5 V
TA = 25C
0.9
VOL

vs
0.8
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
VID = 1 V
VIC = 0.5 V
TA = 25C
2.5
VDD = 10 V
1.5
0.3
0.2
0.1
0.5
0
0
1
2
3
4
5
6
7
5
10
15
20
25
LARGE-SIGNAL
vs
SUPPLY VOLTAGE
RL = 100 k
AVD
450
400
LARGE-SIGNAL
vs
0C
25C
300
70C
85C
200
TA = 125C
150
100
50
0
0
4
6
8
10
12
14
16
RL = 100 k
450
40C
350
250
500
TA = 55C
AVD
500
400
350
VDD = 10 V
300
250
200
150
VDD = 5 V
100
50
0
75
50
25
0
25
50
75
100
Figure 49
Figure 48
32
30
Figure 47
Figure 46
VDD = 16 V
DALLAS, TEXAS 75265
125


CURRENT
vs
16
TA = 25C
VDD = 10 V
VIC = 5 V
See Note A
14
VII Maximum Input Voltage V
V
IIB
I IO Input Bias and
IIB and IIO
Input Offset Currents pA
10000
MAXIMUM INPUT VOLTAGE

vs
SUPPLY VOLTAGE
1000
IIB
100
IIO
10
12
10
8
6
4
2
0.1
25
0
35
45
55
65
75
85
95 105 115 125
10
12
14
16
SUPPLY CURRENT
vs
400
250
VO = VDD/2
No Load
225
TA = 55C
200
300
40C
250
0C
200
25C
150
70C
100
125C
50
IIDD
DD Supply Current mA
IIDD
Figure 51
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VO = VDD/2
No Load
Figure 50
350
175
150
VDD = 10 V
125
100
VDD = 5 V
75
50
25
0
0
4
6
8
10
12
14
16
0
75
50
25
0
25
50
75
100
125
Figure 53
Figure 52
DALLAS, TEXAS 75265
33


SLEW RATE
vs
SLEW RATE
vs
SUPPLY VOLTAGE
AV = 1
VI(PP) = 1 V
RL = 100 k
CL = 20 pF
TA = 25C
See Figure 99
0.7
0.6
0.5
0.7
VDD = 10 V
VI(PP) = 1 V
0.6
0.5
0.4
0.4
VDD = 5 V
VI(PP) = 1 V
0.3
0.2
75
0.3
0
4
6
8
10
12
14
16
50
300
TA = 25C
VI(SEL) = 1/2 VDD
Bias-Select Current nA
240
210
180
150
120
90
60
30
0
2
25
0
25
50
75
100
4
6
8
10
12
14
16
10
9
VDD = 10 V
8
7
6
VDD = 5 V
4
3
TA = 125C
TA = 25C
TA = 55C
RL = 100 k
See Figure 99
2
1
0
1
Figure 56
10
100
f Frequency kHz
Figure 57
34
125
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

vs
FREQUENCY
BIAS-SELECT CURRENT
vs
SUPPLY VOLTAGE
VDD = 5 V
VI(PP) = 2.5 V
Figure 55
Figure 54
270
AV = 1
RL = 10 k
CL = 20 pF
See Figure 99
VDD = 10 V
VI(PP) = 5.5 V
0.8
SR Slew Rate V/ s
SR Slew Rate V/ s
0.8
0.9
0.9
DALLAS, TEXAS 75265
1000


vs
SUPPLY VOLTAGE
vs
800
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 101
800
700
750
B1
B1
900
600
500
400
300
75
700
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 101
650
600
550
500
450
400
50
25
0
25
50
75
100
125
4
6
8
10
12
14
16
Figure 59
Figure 58
vs
FREQUENCY
VDD = 5 V
RL = 100 k
TA = 25C
106
105
104
0
30
AVD
103
102
60
90
Phase Shift
AVD
107
Phase Shift
101
120
150
0.1
10
100
1k
10
f Frequency Hz
100 K
180
1M
Figure 60
DALLAS, TEXAS 75265
35


vs
FREQUENCY
VDD = 10 V
RL = 100 k
TA = 25C
106
105
104
30
AVD
103
60
102
90
Phase Shift
AVD
107
Phase Shift
101
120
150
0.1
1
10
100
1k
10 k
f Frequency Hz
100 k
180
1M
Figure 61
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
45
50
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 100
43
m
m Phase Margin
m
m Phase Margin
48
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 100
46
44
42
41
39
37
40
38
0
4
6
8
10
12
14
16
35
75
50
Figure 62
25
0
25
50
75
100
Figure 63
36
DALLAS, TEXAS 75265
125

44
VDD = 5 V
VI = 10 mV
TA = 25C
See Figure 100
m
m Phase Margin
42
40
38
36
34
32
30
EQUIVALENT INPUT NOISE VOLTAGE

vs
FREQUENCY
Vn
V n Equivalent Input Noise Voltage nnV/Hz
V/ Hz
PHASE MARGIN
vs
CAPACITIVE LOAD
300
VDD = 5 V
RS = 20
TA = 25C
See Figure 99
250
200
150
100
50
28
0
20
40
60
80
100
10
100
f Frequency Hz
1000
Figure 65
Figure 64
DALLAS, TEXAS 75265
37

LOW-BIAS MODE
TEST
CONDITIONS
PARAMETER
TA
MIN
25C
TLC271C
VIO
I
Input
offset
ff
voltage
l
TLC271AC
Average temperature coefficient of input offset voltage
IIO
IIB
VICR
VOH
VOL
AVD
CMRR
Low-level
p voltage
L
l
l output
l g
Large-signal
Large
signal differential
Common-mode
C
d rejection
j i ratio
i
0.9
Full range
25C
0.24
1.1
VO = VDD /2,
VIC = VDD /2
25C
0.1
70C
VO = VDD /2,
VIC = VDD /2
25C
0.6
70C
40
25C
0.2
to
4
Full range
0.2
to
3.5
VIC = VICRmin
i
0.9
10
5
6.5
0.26
3
V/C
0.1
300
300
0.7
600
50
0.2
to
9
600
0.3
to
9.2
0.2
to
8.5
3.2
4.1
8.9
0C
4.1
7.8
8.9
70C
4.2
7.8
8.9
25C
50
50
0C
50
50
50
50
25C
50
520
50
870
0C
50
700
50
1030
70C
50
380
50
660
25C
65
94
65
97
0C
60
95
60
97
70C
60
95
60
97
25C
70
97
70
97
0C
60
97
60
97
70C
60
98
60
98
dB
VI(SEL) = VDD
25C
65
10
17
14
23
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
No
d
25C
IDD
0C
12
21
18
33
70C
14
11
20
DALLAS, TEXAS 75265
dB
95

mV
V
V/mV
V/ V
II(SEL)
pA
VDD = 5 V to 10 V
VO = 1.4 V
38
pA
Supply-voltage
Supply
(VDD /VIO)
kSVR
mV
V
0.3
to
4.2
UNIT
12
25C
70C
RL= 1 M
M,
See Note 6
1.1
25C to
70C
VID = 100
100 mV
mV,
IOL = 0
10
6.5
Full range
VID = 100 mV
mV,
RL= 1 M
VDD = 10 V
TYP MAX
MIN
12
25C
Common mode input

Common-mode
High l
High-level
l output
p voltage
l g
1.1
Full range
VO = 1
1.4
4V
V,
VIC = 0 V,
RS = 50 ,
RI = 1 M
TLC271BC
VIO
VDD = 5 V
TYP MAX
nA
A
A

LOW-BIAS MODE
TEST
CONDITIONS
PARAMETER
I
Input
offset
ff
voltage
l
TLC271AI
VO = 1
1.4
4V
V,
VIC = 0 V,
RS = 50 ,
RL = 1 M
TLC271BI
VIO

IIO
IIB
VICR
VOH
VOL
AVD
CMRR
Low-level
p voltage
L
l
l output
l g
Large-signal
Large
signal differential
Common-mode
C
d rejection
j i ratio
i
0.9
Full range
25C
0.24
VO = VDD /2,
VIC = VDD /2
25C
0.1
85C
24
VO = VDD /2,
VIC = VDD /2
25C
0.6
85C
200
RL= 1 M
See Note 6
VIC = VICRmin
i
VDD = 5 V to 10 V
VO = 1.4 V
II(SEL)
VI(SEL) = VDD
IDD
Supply
S pply current
VO = VDD /2,
VIC = VDD /2,
N lload
No
d
1.1
25C
0.2
to
4
0.9
Full range
0.2
to
3.5
10
5
7
0.26
V/C
0.1
1000
26
1000
0.7
2000
220
0.2
to
9
2000
0.3
to
9.2
4.1
8.9
4.1
7.8
8.9
85C
4.2
7.8
8.9
25C
50
50
40C
50
50
50
50
25C
50
520
50
870
40C
50
900
50
1550
85C
50
330
50
585
25C
65
94
65
97
40C
60
95
60
97
85C
60
95
60
98
25C
70
97
70
97
40C
60
97
60
97
85C
60
98
60
98
65
pA
25C
25C
pA
0.2
to
8.5
40C
85C
mV
V
3.5
1
0.3
to
4.2
UNIT
13
3.5
1.1
mV
VID = 100 mV,
IOL = 0
10
25C to
85C
mV
VID = 100 mV,
RL= 1 M
VDD = 10 V
TYP MAX
MIN
13
25C
Full range
Supply-voltage
Supply
(VDD /VIO)
kSVR
1.1
Full range
Common mode input

Common-mode
High l
High-level
l output
p voltage
l g
VDD = 5 V
MIN
TYP MAX
25C
TLC271I
VIO
TA
mV
V
V/mV
V/ V
dB
dB
95
nA
25C
10
17
14
23
40C
16
27
25
43
85C
17
13
10
18
A
A
Full range is 40 to 85C.

DALLAS, TEXAS 75265
39

LOW-BIAS MODE
PARAMETER
VIO
TEST
CONDITIONS
VO = 1.4 V,
VIC = 0 V,
RS = 50 ,
RL = 1 M
TA
TLC271M
VDD = 5 V
VDD = 10 V
MIN
TYP MAX
MIN
TYP MAX
25C
1.1
12

IIO
VO = VDD /2,
VIC = VDD /2
IIB
VO = VDD /2,
VIC = VDD /2
25C
0.6
125C
25C to
125C
1.4
25C
0.1
125C
1.4
25C
Common mode input
Common-mode
Full range
VOH
VOL
AVD
CMRR
High l
High-level
l output
p voltage
l g
Low-level
p voltage
L
l
l output
l g
Large-signal
Large
signal differential
Common-mode
C
d rejection
j i ratio
i
VID = 100 mV
mV,
RL= 1 M
VID = 100 mV,

mV
IOL = 0
RL= 1 M
M,
See Note 6
VIC = VICRmin
i
1.1
10
mV
Full range
VIO
VICR
10
0
to
4
12
V/C
1.4
0.1
15
1.8
pA
15
0.7
35
0.3
to
4.2
10
0
to
9
0
to
3.5
0.3
to
9.2
0
to
8.5
25C
3.2
4.1
8.9
55C
4.1
7.8
8.8
125C
4.2
7.8
25C
50
50
55C
50
50
125C
50
50
25C
50
520
50
870
55C
25
1000
25
1775
125C
25
200
25
380
25C
65
94
65
97
55C
60
95
60
97
125C
60
85
60
91
25C
70
97
70
97
55C
60
97
60
97
125C
60
98
60
98
dB
VI(SEL) = VDD
25C
65
VO = VDD /2,
VIC = VDD /2,
N lload
No
d
25C
10
17
14
23
55C
17
30
28
48
125C
7
12
9
15
40
Supply
S pply current
DALLAS, TEXAS 75265
mV
V
V/mV
V/ V
IDD
nA
V
VDD = 5 V to 10 V
VO = 1.4 V
II(SEL)
nA
pA
35
Supply-voltage
Supply
(VDD /VIO)
kSVR
UNIT
dB
95
nA
A
A

LOW-BIAS MODE
PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
i gain
i
Slew
rate at unity
RL = 1 M,
M
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 1 M,
M
CL = 20 pF
pF,
See Figure 98
B1
Unity-gain
bandwidth
U iyg i b
d id h
Phase
margin
gi
Ph
mV
VI = 10 mV,
See Figure 100
mV
VI = 10 mV,
CL = 20 pF,
pF
CL = 20 pF
pF,
f = B1,
See Figure 100
TYP
25C
0.03
0C
0.04
70C
0.03
25C
0.03
0C
0.03
70C
0.02
25C
68
25C
0C
70C
4.5
25C
85
0C
100
70C
65
25C
34
0C
36
70C
30
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
kHz
kH

PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 1 M,
M
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 1 M,
M
CL = 20 pF
pF,
See Figure 98
VI = 10
10mV,
mV
See Figure 100
CL = 20
20pF,
pF
VI = 10 mV
mV,
CL = 20 pF,
pF
f = B1,
See Figure 100
B1
Unity-gain
U i y g ibandwidth
b d id h
Phase
margin
Ph
gi
DALLAS, TEXAS 75265
TYP
25C
0.05
0C
0.05
70C
0.04
25C
0.04
0C
0.05
70C
0.04
25C
68
25C
0C
1.3
70C
0.9
25C
110
0C
125
70C
90
25C
38
0C
40
70C
34
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
kHz
kH
41

LOW-BIAS MODE
PARAMETER
TEST CONDITIONS
TA
TLC271I, TLC271AI,
TLC271BI
MIN
VI(PP) = 1 V
SR
Sl
i gain
i
Slew
rate at unity
RL = 1 M,
M
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum
output-swing
p
bandwidth
M i
i gb
d id h
VO = VOH,
RL = 1 M,
M
CL = 20 pF
pF,
See Figure 98
B1
Unity-gain
U i y g i bandwidth
b d id h
Phase
margin
gi
Ph
mV
VI = 10 mV,
See Figure 100
mV
VI = 10 mV,
CL = 20 pF,
pF
CL = 20 pF
pF,
f = B1,
See Figure 100
TYP
25C
0.03
40C
0.04
85C
0.03
25C
0.03
40C
0.04
85C
0.02
25C
68
25C
40C
85C
25C
85
40C
130
85C
55
25C
34
40C
38
85C
28
UNIT
MAX
V/
V/s
nV/Hz
kHz
kH
MHz
MH

PARAMETER
TEST CONDITIONS
TA
TLC271C, TLC271AC,
TLC271BC
MIN
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 1 M,
M
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
f = 1 kHz,
See Figure 99
RS = 20 ,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 M,
M
CL = 20 pF
pF,
See Figure 98
mV
VI = 10 mV,
See Figure 100
CL = 20 pF
pF,
B1
42
Phase margin
mV l
VI = 10 mV,l
CL = 20 pF,
pF
f = B1,
See Figure 100
DALLAS, TEXAS 75265
TYP
25C
0.05
40C
0.06
85C
0.03
25C
0.04
40C
0.05
85C
0.03
25C
68
25C
40C
1.4
85C
0.8
25C
110
40C
155
85C
80
25C
38
40C
42
85C
32
UNIT
MAX
V/
V/s
nV/Hz
kHz
MHz

LOW-BIAS MODE
PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 1 M,
M
CL = 20 pF,
pF
See Figure 98
VI(PP) = 2.5
25V
Vn
BOM
B1
f = 1 kHz,
See Figure 99
RS = 20 ,
Maximum
output-swing
bandwidth
M i
p
i gb
d id h
VO = VOH,
RL = 1 M,
M
CL = 20 pF
pF,
See Figure 98
VI = 10 mV
mV,
See Figure 100
CL = 20 pF
pF,
Unity-gain
bandwidth
U iyg i b
d id h
Phase
margin
gi
Ph
VI = 10 mV
mV,
CL = 20 pF,
pF
f = B1,
See Figure 100
TA
TLC271M
MIN
TYP
25C
0.03
55C
0.04
125C
0.02
25C
0.03
55C
0.04
125C
0.02
25C
68
25C
55C
125C
25C
85
55C
140
125C
45
25C
34
55C
39
125C
25
MAX
UNIT
V/
V/s
nV/Hz
kHz
kH
kHz
kH

PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Sl
Slew
rate at unity
i gain
i
RL = 1 M,
M
CL = 20 pF,
pF
See Figure 98
VI(PP) = 5.5
55V
Vn
BOM
B1
f = 1 kHz,
See Figure 99
RS = 20 ,
M i
Maximum
output-swing
p
i gb
bandwidth
d id h
VO = VOH,
RL = 1 M,
M
CL = 20 pF
pF,
See Figure 98
VI = 10
10mV,
mV
See Figure 100
CL = 20
20pF,
pF
Unity-gain
U i y g ibandwidth
b d id h
Phase
margin
gi
Ph
VI = 10 mV
mV,
CL = 20 pF,
pF
f = B1,
See Figure 100
DALLAS, TEXAS 75265
TA
TLC271M
MIN
TYP
25C
0.05
55C
0.06
125C
0.03
25C
0.04
55C
0.06
125C
0.03
25C
68
25C
55C
1.5
125C
0.7
25C
110
55C
165
125C
70
25C
38
55C
43
125C
29
MAX
UNIT
V/
V/s
nV/Hz
kH
kHz
kHz
kH
43

TYPICAL CHARACTERISTICS (LOW-BIAS MODE)

Table of Graphs
FIGURE
44
VIO
VIO
Distribution
66, 67
Distribution
68, 69
VOH
High l
High-level
l output
p voltage
l g
vs High-level
vs Supply
pp y voltage
g
70, 71
72
73
VOL
L
l
l output voltage
l
Low-level

p
74, 75
76
77
78, 79
AVD
Large-signal
plifi i
diff
i l voltage
l g amplification
vs Supply voltage
p
vs Frequency
80
81
92, 93
IIB
IIO
Input bias current
82
82
VI
Maximum input voltage
vs Supply voltage
83
IDD
Supply current
vs Supply voltage
84
85
SR
Slew rate
vs Supply voltage
86
87
Bias-select current
vs Supply voltage
88
VO(PP)
vs Frequency
89
B1
vs Free
Free-air
air temperature
vs Supply voltage
90
91
Phase
margin
gi
Ph
vs Supply voltage
p
vs Load capacitance
94
95
96
Vn
vs Frequency
97
Phase shift
vs Frequency
92, 93
DALLAS, TEXAS 75265


60
70

VDD = 5 V
TA = 25C
P Package
50
40
30
20
50
40
30
20
10
10
0

VDD = 10 V
TA = 25C
P Package
60
70
0
5
3 2 1 0
1
2
3
Figure 66
70
VDD = 5 V
TA = 25C to 125C
P Package
Outliers:
(1) 19.2 V/C
(1) 12.1 V/C
60
70
50
Figure 67
60
3 2 1 0
1
2
3
40
30
20
10
50
40

VDD = 10 V
TA = 25C to 125C
P Package
Outliers:
(1) 18.7 V/C
(1) 11.6 V/C
30
20
10
0
10 8
10
2
4
6
8
10 8 6 4 2 0
Figure 68
10
Figure 69
DALLAS, TEXAS 75265
45


vs

vs
16
VID = 100 mV
TA = 25C
V
VOH

VOH
VDD = 5 V
VDD = 4 V
VDD = 3 V
VID = 100 mV
TA = 25C
14
VDD = 16 V
12
10
8
VDD = 10 V
6
4
2
2
4
6
8
10
5 10 15 20 25 30 35
Figure 71
Figure 70
vs
SUPPLY VOLTAGE

vs
1.6
VID = 100 mV
RL = 1 M
TA = 25C
14
V
VOH
V
VOH
16
12
10
8
6
IOH = 5 mA
VID = 100 mV
1.7
VDD = 5 V
1.8
1.9
2
VDD = 10 V
2.1
4
2
0
0
4
6
8
10
12
14
16
2.2
2.3
2.4
75
Figure 72
50
25
0
25
50
75
100
Figure 73
46
40
DALLAS, TEXAS 75265
125


vs

vs
500
VDD = 5 V
IOL = 5 mA
TA = 25C
650
VOL
VOL
700
600
550
VID = 100 mV
500
450
450
400
VID = 100 mV
VID = 1 V
350
VID = 2.5 V
400
VID = 1 V
350
300
300
250
0
VDD = 10 V
IOL = 5 mA
TA = 25C
1
2
3
2
4
6
8
1
3
5
7
9
Figure 75
Figure 74
vs

vs
900
IOL = 5 mA
VIC = VID/2
TA = 25C
600
VOL
VOL
800
700
500
VDD = 5 V
400
300
VDD = 10 V
200
100
0
0
10
4 5
9 10
800
IOL = 5 mA
VID = 1 V
VIC = 0.5 V
700
VDD = 5 V
600
500
400
VDD = 10 V
300
200
100
0
75
50
Figure 76
25
0
25
50
75
100
125
Figure 77
DALLAS, TEXAS 75265
47


vs
1
0.8
VOL
VOL
VID = 1 V
VIC = 0.5 V
TA = 25C
0.9
LOW-LEVER OUTPUT VOLTAGE

vs
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
0.3
VID = 1 V
VIC = 0.5 V
TA = 25C
2.5
VDD = 16 V
2
VDD = 10 V
1.5
0.2
0.1
0
0.5
5
10
15
20
25
Figure 79
Figure 78
LARGE-SIGNAL
vs
SUPPLY VOLTAGE
AVD
1800
1600
RL = 1 M
1400
2000
TA = 55C
25C
70C
800
85C
600
400
125C
200
1600
TA = 0C
1000
RL = 1 M
1800
40C
1200
LARGE-SIGNAL
vs
AVD
2000
1400
VDD = 10 V
1200
1000
800
600
VDD = 5 V
400
200
0
0
4
6
8
10
12
14
16
0
75
50
25
0
25
50
75
100
Figure 81
Figure 80
48
30
DALLAS, TEXAS 75265
125


CURRENT
vs
MAXIMUM INPUT VOLTAGE

vs
SUPPLY VOLTAGE
VDD = 10 V
VIC = 5 V
See Note A
TA = 25C
VII Maximum Input Voltage V

V
14
1000
IIB
I IO Input Bias and
IIB and IIO
Input Offset Currents pA
16
10000
IIB
100
IIO
10
12
10
8
6
4
2
0
0.1
25
35
45
55
65
75
85
95 105 115 125
10
16
SUPPLY CURRENT
vs
30
45
VO = VDD/2
No Load
TA = 55C
VO = VDD/2
No Load
35
40C
30
25
0C
A
IIDD
25
A
IIDD
14
Figure 83
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
25C
15
70C
10
125C
5
0
0
12
Figure 82
40
4
6
8
10
12
14
16
20
VDD = 10 V
15
10
VDD = 5 V
5
0
75
50
25
0
25
50
75
100
125
Figure 85
Figure 84
DALLAS, TEXAS 75265
49


SLEW RATE
vs
SUPPLY VOLTAGE
0.07
0.07
AV = 1
VI(PP) = 1 V
RL = 1 M
CL = 20 pF
TA= 25C
See Figure 98
0.05
0.04
0.03
0.02
0.01
0.05
VDD = 10 V
VI(PP) = 1 V
0.04
0.03
VDD = 5 V
VI(PP) = 1 V
0.02
VDD = 5 V
VI(PP) = 2.5 V
0.01
0.00
0
4
6
8
10
12
14
0.00
75
16
50
25
0
25
50
75
100
BIAS-SELECT CURRENT
vs
SUPPLY VOLTAGE
Bias-Select Current nA
120
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

vs
FREQUENCY
135
TA = 25C
VI(SEL) = VDD
105
90
75
60
45
30
15
0
0
4
6
8
10
12
14
16
10
9
8
VDD = 10 V
7
6
5
TA = 125C
TA = 25C
TA = 55C
VDD = 5 V
RL = 1 M
See Figure 98
2
1
0
0.1
Figure 88
1
10
f Frequency kHz
Figure 89
50
125
Figure 87
Figure 86
150
RL = 1 M
CL = 20 pF
AV = 1
See Figure 98
VDD = 10 V
VI(PP) = 5.5 V
0.06
SR Slew Rate V/s s
0.06
SR Slew Rate V/s s
SLEW RATE
vs
DALLAS, TEXAS 75265
100


vs
140
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 100
130
130
B1
B1 Unity-Gain Bandwidth kHz
B1
B1 Unity-Gain Bandwidth kHz
150
vs
SUPPLY VOLTAGE
110
90
70
50
120
110
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 100
100
90
80
70
60
30
75
50
50
25
0
25
50
75
100
125
4
6
8
10
12
14
16
Figure 91
Figure 90
vs
FREQUENCY
107
VDD = 5 V
RL = 1 M
TA = 25C
105
104
30
AVD
103
102
60
90
Phase Shift
AVD
106
Phase Shift
101
120
1
0.1
150
10
100
1k
10 k
f Frequency Hz
100 k
180
1M
Figure 92
DALLAS, TEXAS 75265
51


vs
FREQUENCY
107
VDD = 10 V
RL = 1 M
TA = 25C
105
104
30
AVD
103
102
60
90
Phase Shift
AVD
106
Phase Shift
101
1
0.1
10
120
150
100
1k
10 k
f Frequency Hz
100 k
180
1M
Figure 93
PHASE MARGIN
vs
PHASE MARGIN
vs
SUPPLY VOLTAGE
42
40
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 100
38
36
38
m
m Phase Margin
m
m Phase Margin
40
VDD = 5 mV
VI = 10 mV
CL = 20 pF
See Figure 100
36
34
32
30
34
28
26
24
32
22
30
0
4
6
8
10
12
14
16
20
75
50
25
0
25
50
75
100
Figure 95
Figure 94
52
DALLAS, TEXAS 75265
125


PHASE MARGIN
vs
CAPACITIVE LOAD
VDD = 5 mV
VI = 10 mV
TA = 25C
See Figure 100
35
33
31
29
27
VN
nV/ Hz
V n Equivalent Input Noise Voltage nV/Hz
200
37
m
m Phase Margin
EQUIVALENT INPUT NOISE VOLTAGE

vs
FREQUENCY
VDD = 5 V
RS = 20
TA = 25C
See Figure 99
175
150
125
100
75
50
25
0
25
0
10
20
30 40 50 60 70 80
90 100
10
100
f Frequency Hz
1000
Figure 97
Figure 96
DALLAS, TEXAS 75265
53

PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits
Because the TLC271 is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.
VDD
VDD +
VO
VO
+
CL
VI
VI
RL
CL
RL
VDD
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 98. Unity-Gain Amplifier

2 k
2 k
VDD
20
VDD +
1/2 VDD
VO
VO
20
20
20
VDD
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 99. Noise-Test Circuit

10 k
VDD
VDD +
100
100
VI
10 k
VI
VO
VO
+
1/2 VDD
CL
CL
VDD
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 100. Gain-of-100 Inverting Amplifier
54
DALLAS, TEXAS 75265


input bias current
Because of the high input impedance of the TLC271 operational amplifiers, attempts to measure the input bias current
can result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pA,
a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous
measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 101). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers us the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop
across the series resistor is measured and the bias current is calculated). This method requires that a device be
inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this
method.
8
V = VIC
Figure 101. Isolation Metal Around Device inputs (JG and P packages)
low-level output voltage

To obtain low-supply-voltage operation, some compromise is necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to the Typical Characteristics section of this data sheet.
input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
DALLAS, TEXAS 75265
55


full-power response
Full-power response, the frequency above which the amplifier slew rate limits the output voltage swing, is often
specified two ways: full-linear response and full-peak response. The full-linear response is generally
measuredby monitoring the distortion level of the output while increasing the frequency of a sinusoidal input
signal until the maximum frequency is found above which the output contains significant distortion. The full-peak
response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 98. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 102). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 100 Hz
(b) BOM > f > 100 Hz
(c) f = BOM
(d) f > BOM
Figure 102. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices, and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
VDD
single-supply operation
VI
R2
VO
+
56
R4
R1
While the TLC271 performs well using dual power

supplies (also called balanced or split supplies),
the design is optimized for single-supply
operation. This includes an input common mode
voltage range that encompasses ground as well
as an output voltage range that pulls down to
ground. The supply voltage range extends down
to 3 V (C-suffix types), thus allowing operation
with supply levels commonly available for TTL and
HCMOS; however, for maximum dynamic range,
16-V single-supply operation is recommended.
Vref
+ VDD R1 R3
) R3
V + (V
* VI) R4
) Vref
ref
O
R2
V
R3
C
0.01 F
ref
Figure 103. Inverting Amplifier With Voltage

Reference
DALLAS, TEXAS 75265

single-supply operation (continued)
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 103).
The low input bias current consumption of the TLC271 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC271 works well in conjunction with digital logic; however, when powering both linear devices and digital
logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 104); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.
OUT
Logic
Logic
Logic
Power
Supply
(a) COMMON SUPPLY RAILS
OUT
Logic
Logic
Logic
Power
Supply
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 104. Common Versus Separate Supply Rails
DALLAS, TEXAS 75265
57

input offset voltage nulling
The TLC271 offers external input offset null control. Nulling of the input off set voltage may be achieved by
adjusting a 25-k potentiometer connected between the offset null terminals with the wiper Connected as
shown in Figure 105. The amount of nulling range varies with the bias selection. In the high-bias mode, the
nulling range allows the maximum offset voltage specified to be trimmed to zero. In low-bias and medium-bias
modes, total nulling may not be possible.
IN
VDD
IN +
OUT
N2
N1
IN
25 k
IN +
N2
25 k
N1
GND
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 105. Input Offset Voltage Null Circuit
58
DALLAS, TEXAS 75265
OUT

bias selection
Bias selection is achieved by connecting the bias select pin to one of the three voltage levels (see Figure 106).
For medium-bias applications, R is recommended that the bias select pin be connected to the mid-point
between the supply rails. This is a simple procedure in split-supply applications, since this point is ground. In
single-supply applications, the medium-bias mode necessitates using a voltage divider as indicated. The use
of large-value resistors in the voltage divider reduces the current drain of the divider from the supply line.
However, large-value resistors used in conjunction with a large-value capacitor requires significant time to
charge up to the supply midpoint after the supply is switched on. A voltage other than the midpoint may be used
if it is within the voltages specified in the table of Figure 106.
VDD
Low
To BIAS SELECT
1 M
BIAS MODE
Medium
Low
High
1 M
BIAS-SELECT VOLTAGE
(single supply)
Medium
VDD
1 V to VDD 1 V
High
GND
0.01 F
Figure 106. Bias Selection for Single-Supply Applications
input characteristics
The TLC271 is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD 1 V at TA = 25C and at VDD 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC271 very good input
offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset
voltage drift with time has been calculated to be typically 0.1 V/month, including the first month of operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC271 is well
suited for low-level signal processing; however, leakage currents on printed circuit boards and sockets can
easily exceed bias current requirements and cause a degradation in device performance. It is good practice to
include guard rings around inputs (similar to those of Figure 101 in the Parameter Measurement Information
section). These guards should be driven from a low-impedance source at the same voltage level as the
common-mode input (see Figure 107).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC271 results in a very low noise current,
which is insignificant in most applications. This feature makes the devices especially favorable over bipolar
devices when using values of circuit impedance greater than 50 k, since bipolar devices exhibit greater noise
currents.
DALLAS, TEXAS 75265
59

noise performance (continued)
VO
(a) NONINVERTING AMPLIFIER
VO
VI
VO
VI
VI
(b) INVERTING AMPLIFIER
(c) UNITY-GAIN AMPLIFIER
Figure 107. Guard-Ring Schemes
feedback
VO
Operational amplifier circuits almost always

employ feedback, and since feedback is the first
prerequisite for oscillation, a little caution is
appropriate. Most oscillation problems result from
driving capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 108). The value of this
capacitor is optimized empirically.
Figure 108. Compensation for Input

Capacitance
electrostatic discharge protection

The TLC271 incorporates an internal electrostatic-discharge (ESD) protection circuit that prevents functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised,
however, when handling these devices as exposure to ESD may result in the degradation of the device
parametric performance. The protection circuit also causes the input bias currents to be temperature dependent
and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC271 inputs
and output were designed to withstand 100-mA surge currents without sustaining latchup; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 F typical) located across the supply rails
as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
60
DALLAS, TEXAS 75265

output characteristics
(a) CL = 20 pF, RL = NO LOAD
2.5 V
VI
All operating characteristics of the TLC271 were

measured using a 20-pF load. The devices drive
higher capacitive loads; however, as output load
capacitance increases, the resulting response
pole occurs at lower frequencies, thereby causing
ringing, peaking, or even oscillation (see Figures
110, 111, and 112). In many cases, adding some
compensation in the form of a series resistor in the
feedback loop alleviates the problem.
The output stage of the TLC271 is designed to

sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this high
current capability can cause device damage
under certain conditions. Output current capability
increases with supply voltage.
VO
CL
TA = 25C
f = 1 kHz
VI(PP) = 1 V
2.5 V
Figure 109. Test Circuit for Output

Characteristics
(b) CL = 130 pF, RL = NO LOAD
(c) CL = 150 pF, RL = NO LOAD
Figure 110. Effect of Capacitive Loads in High-Bias Mode
Figure 111. Effect of Capacitive Loads in Medium-Bias Mode
DALLAS, TEXAS 75265
61

output characteristics (continued)
Figure 112. Effect of Capacitive Loads in Low-Bias Mode

Although the TLC271 possesses excellent high-level output voltage and current capability, methods are
available for boosting this capability, if needed. The simplest method involves the use of a pullup resistor (RP)
connected from the output to the positive supply rail (see Figure 113). There are two disadvantages to the use
of this circuit. First, the NMOS pulldown transistor, N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between
approximately 60 and 180 , depending on how hard the operational amplifier input is driven. With very low
values of RP, a voltage offset from 0 V at the output occurs. Secondly, pullup resistor RP acts as a drain load
to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the
output current.
VI
VDD
IP
RP
R
VO
IF
+ I V)DDI V)OI
F
L
P
IP = Pullup current required
by the operational amplifier
(typically 500 A)
R2
R1
IL
RL
Figure 113. Resistive Pullup to Increase VOH
62
DALLAS, TEXAS 75265

output characteristics (continued)
10 k
10 k
10 k
5V
VI
5V
10 k
TLC271
0.016 F
0.016 F
BIAS SELECT
10 k
5V
TLC271
BIAS SELECT
TLC271
Low Pass
BIAS SELECT
High Pass
5 k
Band Pass
R = 5 k(3/d-1)
(see Note A)
NOTE A: d = damping factor, I/O
Figure 114. State-Variable Filter

VO (see Note A)
9V
10 k
C = 0.1 F
9V
100 k
BIAS
SELECT
9V
TLC271
10 k
R2
VO (see Note B)
TLC271
BIAS SELECT
F
1
+ 4C(R2)
R1
R3
R1, 100 k
R3, 47 k
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 115. Single-Supply Function Generator
DALLAS, TEXAS 75265
63

APPLICATION INFORMATION (HIGH-BIAS MODE)
5V
VI
10 k
100 k
TLC271
BIAS
SELECT
5V
5 V
TLC271
5V
VO
BIAS
SELECT
10 k
5 V
10 k
95 k
TLC271
+
VI +
BIAS SELECT
R1, 10 k
(see Note A)
5 V
NOTE A: CMRR adjustment must be noninductive.
F i g u r e 11 6 . L o w - P o w e r I n s t r u m e n t a t i o n A m p l i f i e r
5V
R
10 M
R
10 M
TLC271
VI
2C
540 pF
VO
BIAS SELECT
f NOTCH
+ 2p1RC
R/2
5 M
C
270 pF
C
270 pF
Figure 117. Single-Supply Twin-T Notch Filter
64
DALLAS, TEXAS 75265

APPLICATION INFORMATION (HIGH-BIAS MODE)

VI
(see Note A)
1.2 k
4.7 k
TL431
20 k
100 k
0.47 F
1 k
TLC271
0.1 F
TIP31
15
BIAS SELECT
TIS 193
250 F,
25 V
VO
(see Note B)
10 k
47 k
22 k
110
0.01 F
NOTES: A. VI = 3.5 to 15 V
B. VO = 2.0 V, 0 to 1 A
Figure 118. Logic-Array Power Supply
12 V
VI
TLC271
12 V
H.P.
5082-2835
BIAS
SELECT
TLC271
0.5 F
Mylar
N.O.
Reset
VO
BIAS
SELECT
100 k
Figure 119. Positive-Peak Detector
DALLAS, TEXAS 75265
65

APPLICATION INFORMATION (MEDIUM-BIAS MODE)

1N4148
470 k
100 k
5V
47 k
TLC271
100 k
VO
BIAS
SELECT
2.5 V
R2
68 k
1 F
100 k
R1
68 k
C2
2.2 nF
C1
2.2 nF
NOTES: A. VO(PP) = 2 V
B.
fo
1
+ 2p R1R2C1C2
Figure 120. Wein Oscillator

5V
0.01 F
1 M
VI
0.22 F
VO
TLC271
+
BIAS
SELECT
2.5 V
100 k
1 M
100 k
10 k
0.1 F
Figure 121. Single-Supply AC Amplifier
66
DALLAS, TEXAS 75265

APPLICATION INFORMATION (MEDIUM-BIAS MODE)

5V
Gain Control
1 M
(see Note A)
1 F
+
100 k
1 F
0.1 F
+
10 k
TLC271
BIAS
SELECT
1 k
100 k
2.5 V
100 k
NOTE A: Low to medium impedance dynamic mike
Figure 122. Microphone Preamplifier

10 M
VDD
1 k
TLC271
15 nF
VDD
VO
TLC271
BIAS
SELECT
VDD / 2
VREF
150 pF
BIAS
SELECT
VDD / 2
100 k
NOTES: A. NOTES: VDD = 4 V to 15 V
B. Vref = 0 V to VDD 2 V
Figure 123. Photo-Diode Amplifier With Ambient Light Rejection
5V
VI
IS
TLC271
BIAS
SELECT
2N3821
2.5 V
R
NOTES: A. VI = 0 V TO 3 V
V
I
B. I S
R
Figure 124. Precision Low-Current Sink
DALLAS, TEXAS 75265
67

APPLICATION INFORMATION (LOW-BIAS MODE)
VDD
VI
BIAS SELECT
TLC271
VI
VDD
S1
C
A
Select
AV
S1
S2
10
S2
100
C
A
90 k
X1
TLC4066
9 k
X2
Analog
Switch
1 k
NOTE A: VDD = 5 V to 12 V
Figure 125. Amplifier With Digital Gain Selection

5V
BIAS SELECT
TLC271
500 k
VO1
5V
500 k
BIAS
SELECT
VO2
TLC271
0.1 F
500 k
500 k
Figure 126. Multivibrator
68
DALLAS, TEXAS 75265

APPLICATION INFORMATION (LOW-BIAS MODE)

10 k
VDD
20 k
BIAS SELECT
VI
VO
TLC271
100 k
Figure 127. Full-Wave Rectifier

10 k
VDD
100 k
Set
100 k
Reset
BIAS
SELECT
TLC271
33
Figure 128. Set/Reset Flip-Flop

0.016 F
5V
10 k
10 k
Vi
0.016 F
BIAS
SELECT
TLC271
VO
NOTE A: Normalized to FC = 1 kHz and RL = 10 k
Figure 129. Two-Pole Low-Pass Butterworth Filter
DALLAS, TEXAS 75265
69
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (Critical Applications).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1996, Texas Instruments Incorporated

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TLC271, TLC271A, TLC271B

LinCMOS PROGAMMABLE LOW-POWER

Input Offset Voltage Drift . . . Typically

The TLC271 operational amplifier combines a

PRODUCTION DATA information is current as of publication date.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TLC271, TLC271A, TLC271B

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TLC271, TLC271A, TLC271B

bias-select feature (continued)

TYPICAL PARAMETER VALUES

Equivalent input noise voltage at f = 1 kHz

Large-signal differential voltage amplification

bias selection (continued)

Figure 1. Bias Selection for Single-Supply Applications

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TLC271, TLC271A, TLC271B

absolute maximum ratings

recommended operating conditions

parameter measurement information

POST OFFICE BOX 655303

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TLC271, TLC271A, TLC271B

recommended operating conditions

Supply voltage, VDD

Operating free-air temperature, TA

POST OFFICE BOX 655303

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TLC271, TLC271A, TLC271B

Average temperature coefficient

Input offset current (see Note 4)

Input bias current (see Note 4)

Input current (BIAS SELECT)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Common-mode input voltage

TLC271, TLC271A, TLC271B

Average temperature coefficient

Input offset current (see Note 4)

Input bias current (see Note 4)

Input current (BIAS SELECT)

DALLAS, TEXAS 75265

POST OFFICE BOX 655303

Common mode input

TLC271, TLC271A, TLC271B

Average temperature coefficient

Input offset current (see Note 4)

Input bias current (see Note 4)

Input current (BIAS SELECT)

POST OFFICE BOX 655303

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Common mode input voltage

TLC271, TLC271A, TLC271B

Equivalent input noise voltage

operating characteristics at specified free-air temperature, VDD = 10 V

Equivalent input noise voltage

POST OFFICE BOX 655303

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TLC271, TLC271A, TLC271B

Equivalent input noise voltage

operating characteristics at specified free-air temperature, VDD = 10 V