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IEEE Asian Solid-State Circuits Conference

6-3

November 12-14, 2012/Kobe, Japan

A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC


using Capacitor-Swapping Technique
Meng-Hsuan Wu1, Yung-Hui Chung1,2 and Hung-Sung Li1
1

MediaTek Inc., Hsinchu, Taiwan


National Taiwan University of Science and Technology, Taipei, Taiwan
Email: meng-hsuan.wu@mediatek.com

AbstractThis paper presents a 12-bit 1-MS/s SAR ADC


incorporating a sampling capacitor-swapping technique. The
proposed swapping technique effectively removes the
capacitor- DAC middle-code transition error, resulting in
improved linearity, without needing large capacitor size for
good capacitor matching. Moreover, an on-the-fly
programmable dynamic comparator is adopted in the design
for meeting fast comparison as well as low-noise requirements
with small power consumption. The ADC was fabricated in
0.11 Pm CMOS. It consumes 16.47 PW at 0.9 V supply.
Measured DNL and INL are 0.3 LSB and 0.56 LSB
respectively. Measured SNR and SFDR are 67.5 dB and 87 dB
respectively. ENOB is measured at 10.92 b, equivalent to a
FOM of 8.47 fJ/conversion-step.

I.

INTRODUCTION

As CMOS process advances, successive approximation


register (SAR) ADCs have drawn a lot of attention due to
their unique features of low voltage operation, excellent
conversion efficiency and small footprint. For energyefficient and low voltage applications, such as wireless
sensor network, biomedical sensors and portable
instruments, power-efficient ADCs play a crucial role in
enabling autonomous operation. Several SAR ADCs [1-3]

CP11,1

CP11,2

CP11,3

with >10b resolution have been reported in the past with


Figure-of-Merit (FOM) in the range from 30 to 200
fJ/conversion-step. To have high capacitor-DAC (C-DAC)
linearity without using large capacitors, a digital calibration
[2] was proposed to compensate the mismatch. Reference [3]
used a capacitor rotation technique in a subranged-SAR
ADC to linearize the capacitor array. Here we present a 12bit SAR ADC with capacitor swapping which achieves a
FOM of 8.47 fJ/conversion-step.
Figure 1 shows the schematics of the proposed 12-bit
SAR ADC. It consists of a capacitor-swapping hybrid-DAC,
an on-the-fly programmable dynamic comparator and a
SAR digital control unit. Two capacitor banks (plus-bank
and minus-bank) are used for differential operation. Topplate sampling and monotonic switching techniques reduce
the total input capacitance by a factor of two [4].
Asynchronous clocking scheme is applied to speed up the
ADC conversion while avoiding the use of PLL for higher
frequency clock source [5]. The top and bottom reference
voltages are labeled as VREF and GND in the figure,
respectively. In this design, VREF is provided by the ADC
supply voltage.
For a bottom-plate sampling binary-weighted 12-bit

CP11,1=CP10
CP11,2=CP9
CP11,3=CP9C

V2P

VREF

3R

GND

VREF/4

VREF
GND

CKs

CP11

CP10

CP9

CP9C

CP8

CP7

CP6

CP6C

CP5

CP4

CP3

CP3C

CP2

CP1

CP0

V1P
V1N
Bootstrapping
switch

CP0C

Configurable
Comparator

V2P

dc

V2N

SAR
valid Control Unit
ckc

CN11

CN10

CN9

CN9C

CN8

CN7

CN6

CN6C

CN5

CN4

CN3

CN3C

CN2

CN1

CN0

VREF

CN0C

Variable Delay
Time Control

VREF/4

GND

Figure 1. Proposed SAR ADC schematics with capacitor swapping.

978-1-4673-2771-8/12/$31.00 2012 IEEE

157

CKs

LN_mode
CKi

12

Dout

SAR ADC using C-DAC, MSB capacitor is 211CU, where


CU being the LSB unit capacitor. The single-ended total
capacitance would be around 20 pF with a 5 fF unit
capacitor. Such a large capacitor incurs excessive driving
power for the ADC input and reference buffers. To
minimize the input capacitance thus power, the hybrid-DAC
uses resistor-DAC (R-DAC) to generate sub-reference
voltage (VREF/4) for the last three bits. Taking plus capacitor
bank as an example, first nine capacitors (CP11~CP3,
CPk=2k-3CU) are connected to VREF directly by their
respective control switches. The last three capacitors
(CP2=2CU, CP1=CP0=CU) are connected to the sub-reference
voltage VREF/4. As shown in Figure 1, the total single-ended
capacitance is thus reduced to 2.56pF, which still meets the
noise requirement for the capacitance size. Four redundant
capacitors (CP9C=CP9, CP6C=CP6, CP3C=CP3 and CP0C=CP0)
are added for implementing the digital redundancy [4]. The
digital redundancy provides additional reference settlingerror tolerance for achieving speedup ADC operation at low
power consumption. The total capacitance is slightly
increased to 2.93 pF with the redundancy. The minus
capacitor bank has the same circuit topology as the plus
capacitor bank.
The SAR control unit is clocked by CKs in the figure. At
the beginning of each sampling period, all capacitors are
connected to their reference voltages through switches. At
the falling edge of CKs, the analog input signals, V1P and
V1N, are sampled on the capacitor array and the
comparators input nodes, V2P and V2N. At the beginning
of hold mode (CKs is 0), the comparator makes the first
comparison to yield the comparator output (d1). If
V2P>V2N, d1 is 1; otherwise, d1 is 0. After the
comparison is finished, a valid signal is also generated
from the differential comparator outputs and passed to the
variable delay time control (VDTC) in a self-loop and
triggers the next comparison. Once the SAR control unit
detects the valid signal it then generates the next control
signal (CK1). Based on the comparator output d1, it decides
the switch connection for capacitors CP11 and CN11. If d1 is
1, CP11 is connected to GND; otherwise, CN11 is
connected to GND. The process cycles 17 times and a total
of 17 comparator output data, d1 ~ d17, are gathered in the
SAR control unit. Digital correction is performed afterwards
and 12-bit ADC output DOUT is spit out at the end of the
sampling period.
II.

CAPACITOR-SWAPPING TECHNIQUE

For our binary-weighted C-DAC, capacitor-swapping is


performed to exchange DAC capacitors for consecutive subconversions, either in regular or random fashions, to
represent the DAC feedback. Statistically speaking it
averages out the opposite mismatch errors among the
capacitor array, resulting in an averaged error of zero.
Capacitor-swapping can be implemented in different bitlevel in a binary-weighted C-DAC. When the MSB
capacitor is swapped with MSB-1 and the rest of LSB
capacitors, it is called MSB swapping. If swapping is
applied to the first k MSB capacitors, it is referred as MSBk swapping.
Referring to Figure 2a, a 3-bit C-DAC is used to
illustrate this idea. Capacitors C3, C2, C1 and C0 have the
capacitance values of 4C, 2C, C and C respectively. The
capacitor array has four capacitors, controlled by switches
SW3~SW0. In this example, MSB swapping is used. To

S3 S2

S3 S1

S3 S0

S2 S3

S1 S3

S0 S3

0 1

0 1

0 1

0 1

0 1

0 1

swap

SW3
VREF

C3

SW3A V
REF

SW3B V
REF

C3B

C3A

SW3C V
REF

C3C

SW2

SW1

VREF

C2

VREF

C1

SW0

C0
V2P

(a)

k-th
sample

3b capacitor-swapping DAC.

C3A

C3B

C3C

VREF

VREF VREF

C2

C1

C0
V2P

(k+1)-th
sample

C2

C1

C0

VREF

VREF VREF

C3A

C3B

C3C
V2P

(b)

Swapping scheme for adjacent samples.

Figure 2. A 3-bit binary C-DAC as an example for MSB swapping.

(a)

Capacitor-swapping off.

(b)

Capacitor-swapping on.

Figure 3. DNL/INL plots with 1000 Monte-Carlo simulation

implement the swapping, the MSB capacitor C3 is split into


three LSB capacitors, C3A, C3B and C3C, with the following
relationships: C3A=C2, C3B=C1 and C3C=C0. Considering the
capacitor mismatch ('C) between MSB and other LSB
capacitors, the MSB capacitance is equal to 4C+'C/2,
while the total capacitance of the rest LSB capacitors is 4C'C/2. In connection with the split capacitors, the MSB
switch SW3 is also split into three smaller switches: SW3A,
SW3B and SW3C. Although the numbers of switch and
capacitor increases, the total switch size and capacitance
remain the same as those of the original binary C-DAC.
Figure 2b shows the swapping scheme for adjacent subconversions with the condition of S3=1, S2=S1=S0=0. In
general, the maximum DAC error occurs at the middle-code
transition. For the k-th sub-conversion, the MSB capacitor
constitutes of C3A, C3B and C3C. The DAC error can be
written as C(k)=4C+'C/2. For the adjacent (k+1)-th subconversion, the MSB capacitor composition is changed to
C2, C1 and C0. The DAC error is so changed to C(k+1)=4C'C/2. If there is no capacitor-swapping, the DAC error is

158

('C/8C) VREF. However, with the capacitor-swapping, the


averaged DAC error is null out. The above example
demonstrates that the capacitor-swapping technique is
capable of suppressing the middle-code transition error,
which is the biggest contributor to a SAR ADCs nonlinearity.

VDD

ckc

M13 M7

M8

M14

von

outp

M0
outn

To further verify the proposed swapping technique, a 12-bit


SAR ADC was simulated with 1000 Monte-Carlo runs. The
simulated ADC architecture is shown in Figure 1. Capacitor
mismatch data is extracted from UMC 0.11um CMOS
process. The single-ended total capacitance is 2.93 pF.
Figure 3a depicts the DNL and INL results without
capacitor swapping. As evidenced in the figure, missing
code is observed in the DNL plot and maximum INL
exceeds r1.5 LSB since the total capacitance is insufficient
to keep the capacitor mismatch low. Figure 3b shows the
DNL and INL results with the capacitor swapping on. The
capacitor mismatch value is the same as that used for
simulations in Figure 3a. Here capacitor swapping is
applied to the MSB. As one can see in Figure 3b, there is
no more missing code in the DNL plot. The maximum INL
is reduced to within r1 LSB. The middle-code transition
error is gone.
III.

vop

I0

V2P

M1

VDD

V2N

M2

vop

M10 M16

vn

vp

von

Cp

Cn
LN_mode

M15 M9

vop

von

VDD

M5

M3

ckc

M4

M6

CKi

LN_mode vop

VTDC

ckc

outp
outn

von

M12

M11

Latch

dC
valid

Figure 4. Proposed configurable dynamic comparator.

CIRCUIT IMPLEMENTATION

The comparator in the 12-bit SAR ADC is crucial


because its noise performance limits the overall converter
resolution. Common practice utilizes low input-referred
noise comparator built with a continuous-on pre-amplifier
and latch for low noise but it consumes more power. Here
we design an on-the-fly programmable dynamic comparator
to achieve low noise with lower power. Figure 4 shows the
circuit schematic of the proposed comparator. The dynamic
pre-amplifier is followed by a regenerative latch [6]. A
current source I0, controlled by internal clock signal ckc, is
switched on and off to save power. The pre-amplifier is
activated by the falling edge of ckc. Then the amplified
differential signal (vop-von) is passed onto the regenerative
circuit. After regeneration, both outp and outn yield the
comparator output dC and generate the SAR control signal
valid.
At the output nodes of the pre-amplifier, vop and von are
conditionally connected to two capacitors Cp and Cn
respectively by the control signal, LN_mode. The
comparator operates in two modes: fast comparison and
low-noise. If LN_mode signal is low, the comparator
operates at fast comparison mode because Cp and Cn are
floated and the comparators input-referred noise is larger.
Whereas when LN_mode is high, the comparator operates at
the low-noise mode since Cp and Cn filter the preamplifiers output noise. We use the programmable feature
to optimize comparator power consumption. During MSB
comparisons, the comparator is operated at faster speed and
its higher input-referred noise can be tolerated by the digital
redundancy error correction. But for the last LSBs
comparisons, the comparator is switched to low-noise mode
to meet 12-bit noise requirement.

Figure 5. The ADC chip micrograph.

During each bit-cycling of SAR ADCs, the settling time


requirement for capacitor switching is not equal. We take
advantage of it for power savings. As shown in Figure 4, a
VTDC delay circuit is proposed not only to serve as a self
loop, but also to adjust the time allocated for each DAC
settling cycle. It conditionally allocates appropriate timing
margin for each DAC switching. In this design, three timing
delays are sequentially selected following the internal clock
signal CKi, i=5 and 11.
IV.

MEASUREMENT RESULT

Figure 5 is the chip micrograph of the SAR ADC,


fabricated in 1P6M 0.11 Pm digital CMOS and occupies
0.075 mm2. The single-ended total input capacitance is 3.1
pF. Operating at 1 MHz sampling rate, the ADC consumes
16.47 PW from a 0.9 V supply. Figure 6 shows the
measured DNL and INL with the capacitor-swapping turned
off. The measured DNL and INL are -0.55/+0.3 LSB and 0.76/+0.84 LSB respectively. As shown in Figure 7, with
the capacitor-swapping turned on, the measured DNL and
INL are improved to -0.4/+0.31 LSB and -0.54/+0.56 LSB
respectively.

159

TABLE I.

>10-BIT SAR ADC PERFORMANCE COMPARISON.

Specification (Unit)

This work

Supply Voltage (V)

[2]

[3]

0.9

1.0

1.2

0.9

0.0165

0.025

3.02

0.32

0.1

22.5

10

SNDR (dB)

67.3

65.3

71.1

61.34

SFDR (dB)

87

71

90.3

70.83

Power (mW)
Sampling rate (MS/s)

DNL/INL (LSB)

0.4/0.56

0.66/0.68

NA

0.4/0.65

Input capacitance (pF)

3.1

NA

3.6

1.3

FOM (fJ/conv.-step)

8.47

165

51.3

32.4

12

12

12

11

Core Area (mm2)

0.092

0.63

0.09

0.06

Technology (nm)

110

180

130

90

Resolution (bit)

Figure 6. Measured DNL and INL with capacitor-swapping off.

[1]

67.28 dB respectively. The measured SFDR is 87.3 dB. For


the 500 kHz input, the measured SNR, SNDR and SFDR are
67.5 dB, 67.3 dB and 87 dB respectively. The measured
SFDR is improved over 6dB, compared to the case without
swapping. The measured ENOB maintains at 10.92 bits at
the Nyquist sampling rate. Table 1 shows the performance
summary and comparison to the state-of-the-art 11-bit and
12-bit SAR ADCs. This ADC achieves the lowest FOM of
8.47 fJ/conversion-step.
V.

CONCLUSION

A 12-bit 1-MS/s SAR ADC fabricated in a 0.11 Pm


digital CMOS process is presented. The proposed capacitorswapping technique is proven to effectively linearize the
SAR ADC performance without beefing up capacitor sizes,
thus keeping both small die area and low power
consumption. The proposed on-the-fly programmable
dynamic comparator helps to maintain fast operation while
generates little noise. The designed ADC consumes 16.47
PW from a power supply of 0.9 V and achieves good power
efficiency, with a FoM of 8.47 fJ/conversion-step. The ultra
low power consumption feature finds itself useful for
battery-powered applications.

Figure 7. Measured DNL and INL with capacitor-swapping on.

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[2]

[3]

[4]

Figure 8. Measured FFT for Fin=100kHz and 500kHz at 1MS/s.

[5]

The dynamic performance of this converter is shown in


Figure 8. The ADC is tested with -1dBFS input signals at
100 kHz and 500 kHz. With capacitor-swapping on and 100
kHz input, the measured SNR and SNDR are 67.3 dB and

[6]

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