Vol. 34, No.

11

Journal of Semiconductors

November 2013

A digital input class-D audio amplifier with sixth-order PWM

Luo Shumeng()1 and Li Dongmei()2;
1 Institution
2 Electronic

of Microelectronics, Tsinghua University, Beijing 100084, China

Engineering Department, Tsinghua University, Beijing 100084, China

Abstract: A digital input class-D audio amplifier with a sixth-order pulse-width modulation (PWM) modulator is
presented. This modulator moves the PWM generator into the closed sigmadelta modulator loop. The noise and
distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the
sigmadelta modulator. Therefore, at the output of the modulator, a very clean PWM signal is acquired for driving
the power stage of the class-D amplifier. A sixth-order modulator is designed to balance the performance and the
system clock speed. Fabricated in standard 0.18 m CMOS technology, this class-D amplifier achieves 110 dB
dynamic range, 100 dB signal-to-noise rate, and 0.0056% total harmonic distortion plus noise.
Key words: PWM; class-D digital audio; sigmadelta
DOI: 10.1088/1674-4926/34/11/115001
EEACC: 1265H

2. Architecture of digital class-D amplifiers

1. Introduction
The class-D audio amplifier is getting more and more
attention due to its high efficiency, which arises from the
switching-mode operation of its output stage. Along with
switching-mode operation, class-D audio amplifiers are able
to be digitalized. Today, most of the signals are stored, transferred, and processed in the digital domain. Audio is not
the only example. MP3 players, cellphones, computer multimedia, and some other audio formats are all in digital form.
Traditionally, to transfer a digital audio signal to be heard
though a speaker, high performance digital-to-analog converters (DACs) and power amplifiers are necessary. First, the DAC
finishes the operation of transforming the digital audio signal
to analog domain and then an analog audio amplifier is used to
amplify the analog audio signal to drive the speaker. However,
as the process technology goes into the very deep submicron
(VDSM) level, the performance of the analog integrated circuit
improves much less than digital integrated circuits when process technology improves. At the same time, designing high
precision DACs has become a critical challenge. True digital
class-D amplifiers eliminate the need for high precision DACs,
which makes them very flexible for process technologies and
simplifies the whole system of the transformation from digital
audio signal to power audio signal.
This paper presents an open loop digital class-D audio amplifier with a sixth-order pulse-width modulation (PWM) modulator that generates PWM signal in a sigmadelta loop. The
amplifier achieves 110 dB dynamic range (DR), 100 dB signalto-noise rate (SNR), 0.0056% total harmonic distortion plus
noise (THD+N), and 92% efficiency when driving a 32  load.
Then, we introduce the architectures of some digital class-D
audio amplifiers and that of the one in this paper, and give
a detailed implementation of the core modules of the amplifier.

Figure 1 shows the typical architecture of a true digital class-D amplifier. Unlike analog class-D amplifiers, direct
feedback from output to input is not easy to realize in digital
class-D amplifiers, since the input is digital and the output is
analog. Thus, different varieties of open loop digital class-D
audio amplifiers have been proposed. These amplifiers have
also achieved very good performance1 3 . However, it should
be noted that a good performance low dropout regulator (LDO)
is necessary for achieving a stable power supply in open loop
class-D amplifiers. To overcome this weak point, some designs
add an analog stage to construct a feedback loop between the
output stage and the output end of the modulator to enhance
the power supply rejection ratio (PSRR)4; 5 .
Either PWM signal or pulse-density-modulation (PDM)
signal can be used to drive the digital class-D power stage.
The comparison of PDM signal and PWM signal is shown in
Fig. 2. In PDM signal, the pulse density varies with the amplitude of input signal. The density increases at zero crossing
and decreases at peaks. In PWM signal, the pulse width varies

Fig. 1. Typical architecture of a true digital class-D amplifier.

* Project supported by the National High Technology Research and Development Program of China (No. 2012AA012301) and the National
Natural Science Foundation of China (No. 61171001).
Corresponding author. Email: lidmei@tsinghua.edu.cn
Received 26 March 2013, revised manuscript received 9 June 2013
2013 Chinese Institute of Electronics

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Fig. 2. The comparison of PDM and PWM.

with the input signal amplitude. When the input signal level is
zero, the duty circle of the output of PWM modulator is 50%.
The PWM signal has a fixed oscillation frequency, shown as
the arc in Fig. 2, and the toggling frequency of the PWM signal is much lower than that of the PDM signal. The advantage of PWM is obvious: it helps to reduce switching errors
and dynamic power. The function of PDM is just the same
as in a 1 bit sigmadelta modulator. There have been many
excellent analog class-D audio amplifiers implemented with a
PDM6; 7 modulator. However, PDM switching has one drawback in comparison with PWM. The wide-band spread spectrum and tones of the PDM switching interfere with AM/FM
radio signals, while the PWM switching scheme is able to control the carrier frequency to avoid such interference. In digital
class-D amplifier design, it is not easy to design an overall feedback loop to suppress the errors generated at the forward loop
of the amplifier as the analog class-D amplifier. Therefore, a
PWM signal is the better choice for digital class-D amplifiers.
The digital pulse-code modulation (PCM) signal could be
transformed to a PWM signal by uniform PWM (UPWM)8
directly. Unfortunately, a significant difficulty arises with a
PWM based conversion system: clock rate. The modulator
clock speed is required to resolve 2k distinct pulse-widths per
pulse time interval, where the k represents the bit width of PCM
signal. It means that when transforming a 48 kHz frequency
PCM signal with a bit width of 16 to PWM signal directly, the
clock rate should be as high as 216  48 kHz D 3.146 GHz.
This makes it very hard to realize in hardware implementation.
A deltasigma modulator could reduce the bit width of a
signal and keep a high resolution at the same time by oversampling and noise shaping. So, most digital class-D audio amplifiers are implemented using the structure shown in Fig. 3. The
input signal is an N bits PCM signal at an audio sampling frequency, such as 48 kHz. After interpolation at a rate of OSR
by the interpolation filter, the signal frequency reaches Fs 
OSC. This function is the same as the oversampling in the analog domain. Then the deltasigma modulator reduces the bit
width of the signal to k bits, where k is much smaller than
N . Owing to the noise shaping function of the delta-sigma
modulator, the resolution of the signal in the audio band can
still keep almost the same as the input signal. Then the PWM

generator transforms the k bits PCM signal to PWM signal.

Natural PWM (NPWM) is the best way in terms of precision to transfer a signal to PWM signal9 . However in digital
PWM, NPWM cannot be realized. The comparison of NPWM
and UPWM is discussed in Ref. [9]. Compared with NPWM,
uniform PWM (UPWM) introduces unacceptable baseband
harmonic distortion. Although a lot of works have improved
the performance of UPWM, the noise and distortion generated
at the PWM generator cannot be eliminated. So, an idea is to
move the PWM generator into the deltasigma modulator loop
to create a PWM modulator10 . The architecture of this kind
of class-D audio amplifier is shown in Fig. 4(a).
The quantization of the PWM modulator is realized by
comparing the output of the H(z) module with a digital triangle
waveform whose step length is 1/fs  OSR and oscillation frequency is fosc . All the modules of this PWM modulator work
at fs  OSR Hz. So the output of the modulator is a PWM signal that toggles at the rate of fosc . This PWM signal feeds back
to the input of the modulator, making sure that timing distortion errors due to the uniform sampling of the comparator are
suppressed by the high gain of the forward loop. The PWM
modulator can be simply modeled as Fig. 4(b). The transfer
function of the modulator is:
Y .z/ D STF  X.z/ C NTF  E.z/;
H.z/
;
1 C H.z/
1
NTF D
:
1 C H.z/

(1)

STF D

(2)

This equation is the same as a deltasigma modulator. NTF

is short for noise transfer function and STF is short for signal
transfer function. By designing a proper high pass filter for the
NTF, the noise could be suppressed in the audio band. At the
same time, H.z/ in the audio band provides a high gain that
leads to the STF being almost equal to 1 in the audio band. So
the noise and distortions introduced by the PWM quantization
are suppressed and the signal X.z/ is transferred to Y .z/ with
quite low noise and distortions. As a result, the output PWM
signal of the modulator can achieve very high SNDR.
Because the quantization of the PWM modulator is implemented by comparing the output of the H.z/ module with
a digital triangle waveform, the stabilization of the system
should be reconsidered. In direct view, the inverse of the output
of the H.z/ module should not be faster than the fosc . Theoretically, the oscillation frequency (defined as fosc / of the triangle
wave should at least be times of the unit gain frequency of
H.z/11 .
This paper presents a class-D amplifier that is implemented
with a PWM modulator working at 256  fs Hz, where fs is
the frequency of the input signal. The detailed design of the
core blocks of the amplifier are discussed in Section 3.

3. Main function block design

3.1. PWM modulator
The design of the PWM modulator follows four considerations. First, the toggling rate of the PWM signal should be

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Fig. 3. A kind of digital class-D audio amplifier architecture.

Fig. 4. (a) Architecture of a class-D amplifier with PWM modulator. (b) Model of a PWM modulator.

as low as possible, since the lower toggling rate helps to reduce the impact of the switching errors and dynamic power.
The fewer transitions there are during any given time, the lower
the switching errors and dynamic power will be. The second
is to reduce the system clock. Since all the modulator blocks
are clocked at the rate of fs  OSR, the lower OSR the better.
Thirdly, maximize the input range at the precondition that the
modulator is stable. The fourth, a higher resolution of the digital triangle waveform leads to better results and higher power
utilization. The resolution of the digital triangle waveform determines the maximum modulation depth of the PWM modulator. For example, when the resolution of the digital triangle
waveform is 20, the maximum modulation depth is 19/20, since
at least one toggling is needed at a PWM circle.
As fosc is at least  times of the unity gain frequency of
the H.z/ and H.z/ has direct connection with the NTF, it is
deduced that an NTF with a short transition zone fits the demand. It is certificated that Chebyshevs high pass filter is one
of the best choices for the NTF. When the NTF is a sixth-order
Chebyshev high pass filter, the unity gain frequency of H.z/
could be about 200 kHz. So, fosc could be 200 kHz   
628 kHz. The system clock frequency equals the product of
fosc and the resolution of the digital triangle waveform. When
OSR equals 256, the digital triangle wave form could have 20
stages. Therefore in order to reduce the unity gain of H.z/ and
the system clock frequency as well as improve the precision of
the digital triangle waveform, the balanced result is: the NTF
is a 6th order Chebyshev high pass filter; the system clock is
256 times of fs ; the digital triangle has 20 stages.
To realize the NTF, a different structure could be implemented and a Matlab toolbox named delsig is very helpful.
Unlike an analog modulator where nonideal factors impact

Fig. 5. Error-feedback structure.

the choice of modulator structure, the only consideration for

choosing a digital modulator is hardware efficiency. In direct
view, the Error-Feedback structure is the simplest, as shown
in Fig. 5. F .z/ has a direct connection with the NTF: 1F .z/ D
NTF. However, in this design, the NTF is a sixth-order Chebyshev high pass filter; to obtain stabilization, the precision of
the coefficients of this filter should be as high as 64 bits. F .z/
shares the same denominator as the NTF, so the hardware cost
is much too high. This paper chooses a sixth-order cascade-ofintegrators, feedback form (CIFB) structure, as shown in Fig. 6.
The delsig toolbox is very helpful for transferring the NTF
to different modulator typology. The toolbox will also perform some optimizations to the coefficients during the transfer. As the multiplier coefficient unit is realized by shifting and
adding, to minimize the hardware cost, it is necessary to quantize these coefficients and use CSD coding to minimize the operations. The coefficients of this modulator after quantization
and CSD coding are shown as below: g1 D 2 6 C 2 9 C 2 10 ,
g2 D 2 7 C 2 9 C 2 11 C 2 13 C 2 14 , g3 D 3 C 2 3 C 2 7 ,
c1 D 2 9 2 12 , c2 D 2 6 2 9 C 2 12 C 2 14 , c3 D
2 6 C 2 7 C 2 10 C 2 12 C 2 14 , c4 D 2 5 C 2 7 C 2 13 c5 D
2 4 ; c6 D 2 3 .

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Fig. 6. The architecture of the PWM modulator.

Fig. 7. The comparison of the original NTF, the NTF of the modulator,
and the quantized NTF of the modulator.

Fig. 8. The power spectral density (PSD) of the output of the PWM
modulator.

The NTF will change with the changing of coefficient

values. The comparison of the amplitude-frequency response
(AFR) of the original designed NTF and the NTF of the modulator after transfer and the NTF of the modulator after the
coefficients are quantized is shown in Fig. 7. After transferring the NTF to a CIFB typology modulator, the stop band of
the NTF of the modulator becomes lower than the original designed NTF, which leads to better noise shaping performance.
After quantization, the AFR of the NTF almost keeps the same;
this means that the quantization does not affect the performance
of the modulator.
The bit width of each wire in the modulator also affects
the performance and it can be estimated by doing histogram
analysis to each wire.
The interpolation filter and PWM modulator block is realized through Verilog. Figure 8 shows the FFT result of the
PWM signal of the output of the modulator. In audio analysis,
an A-weighing filter is always used to account for the relative
loudness perceived by a human ear. The A-weighted SNDR of
the output of the PWM modulator is 110.5 dB. The measured
result in chapter IV will show that the DR of the amplifier just
equals the peak SNDR of the modulator.

25.3 mm and 10.5 mm respectively, since by means of width

scanning, the simulation shows that the on resistance of the
PMOS and NMOS is almost the same in this width ratio. To
drive these power MOS, a driver with a drive rate of 5 is designed as shown in Fig. 9. The determination of the drive rate
is a balance of performance and die area. The higher drive rate
leads to a smaller die area. The performance decreases seriously when the drive rate is higher than 5 and the performance
improves lightly when the drive rate is less than 5. This design
does not include a consideration of deadtime, since the simulation shows that the break through time of the power MOS
is less than 0.2 ns. The efficiency of no deadtime design and
deadtime design are almost the same.

3.2. Power stage

The output of the modulator is synchronised by the system
clock and then fed to the power stage of the amplifier, shown
in Fig. 9. The power stage in this design employs an open
loop structure. The widths of the power PMOS and NMOS are

4. Measurement result
Fabricated in a 1P6M 0.18 m standard technology, the
amplifier occupies an active area of 1.32 mm2 . The total area
of the chip is 2.52 mm2 . Figure 10 shows a picture of the amplifier.
The amplifier is fed with a 24 bit PCM signal at a frequency
of 48 kHz. Therefore, the system clock of the chip is 48 kHz 
256 D 12.288 MHz. Since the open loop class-D amplifier is
short of PSRR, a high performance LDO is needed as the power
supply of the amplifier. Figure 11 shows the PSD of the output
power signal with a 1.007 kHz input sine wave with an output power of 23 mW and 23 nW. A fully-balanced differential
second-order Butterworth low pass filter with cutoff frequency
of 24 kHz is used to remove the out-of-band quantization noise.

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Fig. 9. The power stage of the amplifier.

Fig. 10. The picture of the amplifier.

Figure 12(a) shows the measured SNDR versus the input signal level. All results are A-weighted. According to the AES17
definition, a 60 dBFS stimulus is applied to measure the dynamic range of the chip, which equals the measured SNDR plus
60 dB. Therefore the measured dynamic range of this amplifier is 110 dB. When the input level is above 30 dBFS, the
THD decreases obviously with the increase of the input signal level. The reason is that at large signal levels, the supply
current flows through the nonideal power supply, and the non
zero source impedance causes the variation of the power supply. When the input signal level is above 1 dBFS, the digital modulator is over-driven. The peak SNDR is 86 dB, which
means a 0.0056% THD C N and the peak SNR is 100 dB. The
power efficiency performance is shown in Fig. 12(b). The peak
power efficiency is 92% when driving a 32  load. A comparison with the present design is given in Table 1.

5. Conclusion
This paper presents a digital class-D audio amplifier. Benefitting from a sixth-order PWM modulator, the output stage

Fig. 11. Measured PSD for 1.001 kHz sine waves.

of the class-D amplifier is driven by a high performance PWM

signal. The DR of the amplifier is the same as the peak SNDR
of the digital PWM signal. This amplifier employs an open
loop power stage and the power stage is short of PSRR, which
leads to the decrease of the THD when the input signal level is
above 30 dB. A closed loop power stage can be designed to
improve the PSRR to conquer this weakness. This class-D amplifier achieves 110 dB DR, 100 dB SNR, and 0.0056% THD
C N. The peak power efficiency is 92% when driving a 32 
load.

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Fig. 12. Measured SNDR and power efficiency.

Parameter
Process
DR (dB)
Efficiency (%)
SNDR (dB)
SNR (dB)
Output power (W)
Area
Structure

Ref. [9]
65 nm
120
0.88
91.5
0.4
0.76
Open loop PWM

Table 1. Performance comparison.

Ref. [5]
Ref. [4]
0.14 m
90 nm
103
93
0.9
0.83
76.5
82
93
2.7
0.5
Open loop
PDMPWM
PDMPWM
Analog FB

References
[1] Minsheng W, Xicheng J, Jungwoo S, et al. A 120 dB dynamic
range 400 mW class-D speaker driver with fourth-order PWM
modulator. IEEE J Solid-State Circuits, 2010, 45(8): 1427
[2] Guanziroli F, Bassoli R, Crippa C, et al. A 1 W 104 dB SNR filterless fully-digital open-loop class D audio amplifier with EMI reduction. IEEE J Solid-State Circuits, 2012, 47(3): 686
[3] Lee Y H, Seok C K, Kim B J, et al. A 1.3 mW per-channel 103dB SNR stereo audio DAC with class-D head-phones amplifier
in 65 nm CMOS. IEEE Symposium on VLSI Circuits, 2008
[4] Berkhout M, Dooper L. A 3.4 W digital-in class-D audio amplifier. Proceedings of the ESSCIRC, 2011
[5] Ramaswamy S, Krishnan J, Forejt B, et al. A high-performance
digital-input class-D amplifier with direct battery connection in
a 90nm digital CMOS process. Digest of Technical Papers, IEEE
International Solid-State Circuits Conference, 2008: 436
[6] Teplechuk M A, Gribben T, Amadi C. True filterless class-D au-

Ref. [7]
65 nm
96
0.8
103
0.0125
DACPDM
closed loop

This work
0.18 m
112
0.92
84
103
0.022
1.4
Open loop PWM

dio amplifier. IEEE J Solid-State Circuits, 2011, 46(12): 2784

[7] Gaalaas E, Liu B Y, Nishimura N. Integrated stereo deltasigma
class D amplifier. Digest of Technical Papers, IEEE International
Solid-State Circuits Conference, 2005: 120
[8] Goldberg J M, Sandler M B. New high accuracy pulse width
modulation based digital-to-analogue convertor/power amplifier.
IEE Proceedings Circuits, Devices and Systems, 1994, 141(4):
315
[9] Nielsen K, Olufsen B, Denmark. A review and comparison of
pulse width modulation (PWM) methods for analog and digital input switching power amplifiers. AES E-Library, 1997, 102:
4446
[10] Berkhout M, Dooper L. Class-D audio amplifiers in mobile applications. IEEE Trans Circuits Syst I: Regular Papers, 2010, 57(5):
992
[11] Berkhout M. An integrated 200-W class-D audio amplifier. IEEE
J Solid-State Circuits, 2003, 38(7): 1198

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