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Chapter 1
Introduction to Digital System

Design
1.
2.
3.
4.
5.
6.
Why Digital?
Device Technologies
System Representation
Abstraction
Development Tasks
Development Flow
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Design
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Design
Advantage of digital devices
Moores law
Reproducibility of information
Flexibility and functionality: easier to store,
transmit and manipulate information
Economy: cheaper device and easier to design
Transistor geometry
Chips double its density (number of transistor) in
every 18 months
Devices become smaller, faster and cheaper
Now a chip consists of hundreds of million gates
And we can have a wireless-PDA-MP3-playercamera-GPS-cell-phone gadget very soon
Chapter 1

Design
Digitization has spread to a wide range of

applications, including information
(computers), telecommunications, control
systems etc.
Digital circuitry replaces many analog systems:
Audio recording: from tape to music CD to MP3 (MPEG
Layer 3) player
Image processing: from silver-halide film to digital
camera
Telephone switching networks
Control of mechanical system: e.g., flight-by-wire
Chapter 1

Design
transmitter
info
A
/
D
Data
compression
Data
encryption
Error
correction
coding
Modulation
digital implementation
info
D
/
A
Data decompression
Data
decryption
Error
correction
de-coding
Demodulation
digital implementation
receiver
Chapter 1

Design
A
/
D
set point
Controller
D
/
A
actu
ator
Plant
Sen
sor
output
digital
implementation
Chapter 1

Design
No two applications are identical and every one

needs certain amount of customization
Basic methods for customization
General-purpose hardware with custom software
General purpose processor: e.g.,
performance-oriented processor (e.g., Pentium),

cost-oriented processor (e.g., PIC micro-controller)
Special purpose processor: with architecture to perform a

specific set of functions: e.g.,
DSP processor (to do multiplication-addition),
network processor (to do buffering and routing),
graphic engine (to do 3D rendering)
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Design
Custom hardware
Custom software on a custom processor (known
as hardware-software co-design)
Trade-off between Programmability, Cost,

Performance, Size and Power consumption
A complex application contains many
different tasks and uses more than one
customization methods
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Chapter 1

Design
10
Transistors and connection are made from many

layers (typical 10 to 15 in CMOS) built on top of
one another
Each layer has a special pattern defined by a mask
One important aspect of an IC is the length of a
smallest transistor that can be fabricated
It is measured in micron (mm, 10-6 meter)
E.g., we may say an IC is built with 0.50 mm
process
The process continues to improve, as witnessed
by Moores law
The state-of-art process approaches less than
a fraction of 0.1 mm (known as deep sub-micron)
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Where customization is done:
Classification:
In a fab (fabrication facility): ASIC (Application

Specific IC)
In the field: non-ASIC
Full-custom ASIC
Standard cell ASIC
Gate array ASIC
Complex field programmable logic device
Simple field programmable logic device
Off-the-shelf SSI (Small Scaled IC)/MSI (Medium
Scaled IC) components
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Design
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All aspects (e.g., size of a transistor) of a circuit are

tailored for a particular application from scratch.
Circuit fully optimized and best performance
possible
Design very flexible, but extremely complex and
involved
Large amount of design effort needed and so
expensive
Only feasible for small components
Masks needed for all layers
Major application to design basic logic components
that can be used as basic building blocks of larger
system.
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Circuit made of a set of pre-defined logic, known as

standard cells
Limited flexibility in design, design effort reduced
Work limited to gate level, rather than transistor level
E.g., basic logic gates, 1-bit adder, D FF etc
Layout of a cell is pre-determined, but layout of the
complete circuit is customized
Masks needed for all layers
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Circuit is built from an array of a single type of cell

(known as base cell)
Base cells are pre-arranged and placed in fixed
positions, aligned as one- or two-dimensional array
More sophisticated components (macro cells) can be
constructed from base cells
Masks needed only for metal layers (connection
wires)
Fabrication is much simpler as only interconnect
need to be customized (unique for each application)
Custom layers reduce from 10 15 to 3 -5 layers
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Most versatile device technology

Device consists of an array of generic logic cells
and general interconnect structure
Logic cells and interconnect, both can be
programmed by utilizing semiconductor fuses
or switches
Customization is done in the field field
programmable
Two categories (as per complexity and structure):
No custom mask needed
CPLD (Complex Programmable Logic Device)

FPGA (Field Programmable Gate Array)
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Programmable device with simple internal structure

Constructed as two level array of and plane and an
or plane
Interconnect of one or both planes can be
programmed to perform a logic function
E.g.,
PROM (Programmable Read Only Memory)
PAL (Programmable Array Logic)
PLA (Programmable Logic Array)
No custom mask needed

Functionality is limited
Replaced by CPLD/FPGA
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Small parts with fixed, limited functionality

E.g., 7400 TTL series (more than 100 parts)
Tailored PCB is needed for each separate
application
Resources (e.g., power, board area,
manufacturing cost etc.) is consumed by
package but not silicon
None of todays synthesis software can use these
components, so automation is impossible
No longer a viable option
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Standard Cell ASIC

Gate Array ASIC
FPGA/CPLD
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Area (Size): silicon real-estate
Standard cell is the smallest since the cells

and interconnect are customized
FPGA is the largest
Overhead for programmability
Capacity cannot be completely utilized
Speed (Performance)
Time required to perform a task
Power
Cost
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20
Types of cost:
NRE (Non-Recurrent Engineering) cost: onetime, per-design cost

Part cost: per-unit cost
Time-to-market cost loss of revenue
Standard cell: high NRE, small part cost

and large lead time
FPGA: low NRE, large part cost and small
lead time
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Chapter 1

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22
Trade-off between optimal use of

hardware resource and design effort/cost
No single best technology
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24
View: different perspectives of a system

Behavioral view:
Structural view:
Describe functionalities and i/o behavior

Treat the system as a black box
Describe the internal implementation (components

and interconnections)
Essentially block diagram
Physical view:
Add more info to structural view: component size,

component locations, routing wires
E.g., layout of a print circuit board
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Chapter 1

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Chapter 1

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27
How to manage complexity for a chip with 100

million transistors?
Abstraction: simplified model of a system
show the selected features
Ignore associated details
High Level Abstraction Focused, contains most

vital data
Low Level Abstraction Detailed, contains
previously ignored information, complex but
more accurate and closer to the real circuit
Development process starts with high level
abstraction, concentrating on most vital
characteristics.
As the system is better understood, more details
are included to obtain low level abstraction

Design
Chapter 1
28
Levels of Abstraction
Transistor level
Gate level
Register transfer (RT) level
Processor level
Based on size of basic building blocks transistors,

logic gates, function modules and processors resp.
Level of abstraction and the view (representation)
are two independent dimensions of a system, and
each level has its own views.
The levels of abstraction and views can be

combined in a Y-chart
Chapter 1

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29
Each axis
represents a view
and the levels of
abstraction increase
from center to the
outside
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30
5 Characteristics exist at each level of abstraction

o Basic building blocks most commonly used parts at
that level (components used in structural view)
o Signal representation How to express a signals
value
o Time representation - How the value of signal
changes over time
o Behavioral representation Description for
behavioral view
o Physical representation Description for physical
view
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Lowest level of abstraction

Basic building blocks are transistors, resistors,
capacitors, etc.
Behavior description is done by differential
equations or V I Diagram
SPICE s/w can be used to obtain desired I/O
characteristics
At transistor level, digital circuit is treated as
analog system signals are time-varying
(voltage)
E.g. output response of an inverter
Physical description detailed layout of
components and their interconnections. It
defines the masks of various layers and is the
final result of the design process
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33
Building blocks logic gates, 1-bit mux, latch

and flip-flop.
Signals voltage is interpreted as logic 1 or logic
0 w.r.t. a threshold value.
Timing info is given as propagation delay(time
interval for a system to obtain a stable output
response)
I/O behavior is described by Boolean equations.
This level converts a continuous system to a
discrete system discarding complex diff. eqns
Physical description is the placement of gates
and routing of interconnecting wires
Area/Size term is used to describe the Si real
estate of circuit. Alternatively, gate count can
also be used to measure area.
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Building blocks Modules constructed from gates

(functional units like adders, comparators, registers,
multiplexers)
RT (Register Transfer) is a misleading term
Should use module-level
Two meanings:
Loosely: represent the module level

Formally: a design methodology in which the system
operation is described by how the data is manipulated and
transferred among registers
Major feature common clock signal for sampling

and synchronizing pulse, hence propagation delay
differences and glitches have no effect on system
operation.
Timing is measured in terms of no. of clock cycles
rather than propagation delays
Signals grouped together to form datatypes like
unsigned integer or system state
Behavioral description specifies functional operation
by using extended FSM to describe the system
Physical layout is called Floor Plan
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Highest level of abstraction

Basic Building blocks Intellectual Properties (IP),
include processors, memory modules, bus
interfaces, etc.
Signals grouped and interpreted as datatypes
Time measurement is in terms of computation
step (set of operations between two successive
synchronization points) or event sequence
Behavioral description is like program coded in
conventional programming language like C
Physical layout is called Floor Plan (components
used here are much larger than RT-level system)
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Chapter 1

Design
37
Chapter 1

Design
38
Developing a digital system is a refining and

validating process
System is gradually transformed from high
level abstraction to final mask layouts
Along with each refinement, systems
function should be validated to ensure that
the final product works correctly and meets
performance goals
Main Design Tasks:
Synthesis
Physical design
Verification
Testing
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A refinement process - realizes a

description with components from the
lower abstraction level.
Original description may be in either
Behavioral view or Structural view, and the
resulting description is a structural view in
the lower abstraction level
In Y-chart, process either moves from
behavioral to structural view or moves from
a high level abstraction to low level
abstraction
As synthesis progresses, more details are
added
Final result is the gate level structural
representation using primitive cells
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Design
40
To make synthesis process manageable, it

is divided into several smaller steps:
High-level synthesis transforms algorithm into

RT-level description. Complex hence used for
simple algorithms
RT-level synthesis analyzes RT-level behavioral
description and derives structural implementation
using RT-level components. Limited optimization
is done to reduce components
Gate-level synthesis Similar to RT-level
synthesis. Gates used in structural
implementation. Multilevel optimization done to
minimize circuit size or meet timing constraint
Technology mapping To implement gate-level
circuit in a particular device technology, generic
components have to map into cells of chosen
technology and this transformation is called
technology mapping. Last step in synthesis and is
technology dependent
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Design
41
Includes two major parts:
Main tasks in physical design are:
Refinement process between structural and physical views

derives a layout for netlist
Analysis and tuning of circuits electrical characteristics
Floor planning Derives layout at processor and RT levels. It

partitions the system into large function blocks and places these
blocks in proper locations to reduce future routing congestion or
to achieve timing goals. Global plan also possible for power and
clock distribution schemes
Placement and routing Derives a layout at gate level. It involves
detailed placement of cells and routing of interconnecting wires
Circuit extraction After placement and routing, exact length and
location of interconnects are known along with their parasitic
capacitance and resistance. This process is called circuit
extraction. This data is used to construct a resistance-capacitance
network, which is used to calculate propagation delays
In addition, physical design also includes Design Rule Checking,
Derivation of power grid and clock distribution network, power
use estimation and signal integrity
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Process of checking whether a design meets

the specification and performance goals.
Concerns the correctness of the initial design
as well as the refinement processes during
synthesis and physical design
Two aspects of verification:
Functionality checks whether a system generates
the desired output response
Performance (timing) represented as timing
constraints
Performed at various levels of abstraction

Two types of verification: Functional and
Timing
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Design of custom system begins with high-level

behavioral description.
First, primary concern is whether design functions as per

specs check its opn and compare its response to that
desired.
After verifying functionality, refinement process is done
gradually until we get gate-level structural description
If the initial design is not delay-sensitive, then the
functionality is maintained through the refinement
process
Ideally, design should be correct by construction and
require no further functional verification
But in reality, slight errors may arise during refinement
and so functional verification is still performed after
each process to ensure that new refined description
works correctly
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Checks whether a system meets its performance

goals expressed as maximal propagation delay
or minimal clock frequency
At processor or RT level, propagation delay of an
i/o path can be calculated by identifying the
components in the path and summating the
individual delays
Since these components are further refined,
information is just a rough estimation
At gate-level, propagation delay is affected by
delays of components or interconnection wires.
Wiring delay depends on their locations and lengths

Exact values can be obtained after placement and
routing
As transistor size shrinks, effect of wiring delay becomes
more dominant making timing verification more difficult
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Simulation
Timing analysis
Formal verification
Hardware emulation
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46
Model of system is constructed and executed with

input test patterns in a computer, and examining the
output responses
Model can be actual or hypothetical circuit that
includes functionality and timing information
It can be applied at any level of abstraction and
views
It allows us to examine a systems operation and to
detect errors without actually constructing the system
Drawbacks:
It provides a sequence of snapshots of system operation,
defined by a set of input stimuli, but there is no guarantee
that selected stimuli can exercise every part of system and
verify its correctness entirely
It is computationally complex as it is time consuming to
model a h/w design (which operates concurrently) in a
computer which operates sequentially
Serious problem when simulating low-level models, which
may consist of millions of components
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Design
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Focus on Timing aspects of circuit

Analyzes structure of circuit,
Determines all possible i/o paths,
Calculates propagation delays of these paths
Determines relevant timing parameters (worst
case propagation delay)
Simulation provides timing info. for selected
test patterns, but they may not consider
critical paths, so timing analysis is needed to
verify that system meets all timing specs
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Applies formal mathematical techniques to

analyze a circuit
Equivalence Checking popular method
which compares two representations of a
system and determines whether they perform
same function
Frequently used in synthesis to verify that the
synthesized circuit is identical to original one
Unlike simulation, formal verification is based
on rigorous mathematical reasoning and
ensures that synthesis is completely errorfree
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Design
49
Physically constructs a prototyping circuit

that mimics operation of a system
Common application FPGA circuit to
emulate a complex ASIC design
Although, FPGA based system is normally
larger and slower than the ASIC system, it is
much faster than simulation and it can be
physically interfaced with other circuits and
studied in detail
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Appears similar in meaning to Verification, but are

different tasks in system development
It is the process of detecting physical defects of a die
or a package occurred during manufacturing
During testing, we already know that design is
correct, and only purpose is to ensure that the
particular part is properly fabricated
At first glance, it appears to be easy apply all
possible input combinations and check output
responses. But, this is not feasible for large no. of
inputs
Special algorithms are used for generating small set
of test patterns - called test pattern generation
Difficult for large circuit
Need to add auxiliary testing circuit in design called
Design for - test
E.g., built-in self test (BIST), scan chain etc.
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EDA (Electronic Design Automation)

Developing a large digital circuit is complicated
involves complex algorithms and large amount of
data
EDA software can automate some tasks
Can software replace human hardware designer?
automating the development process completely
Ideally, human designers would only need to
develop a high-level behavioral description and
EDA s/w would perform the synthesis, placement
and routing and derive the optimal circuit
implementation itself unfortunately not possible
Synthesis software
should be treated as a tool to perform transformation and

local optimization
cannot change the original architecture or convert a poor
design into a good one
Efficiency of final circuit depends mainly on initial
description
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Chapter 1

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53
Developing a digital circuit is refining and

validating process - gradually transforming an
abstract high-level description to a detailed lowlevel structural description
Though all development flows follow refinementvalidation process, detailed flows depend on :
size of circuit and
target device technology
Optimization algorithms used in synthesis s/w

are complex computation time and memory
space needed increase drastically as circuit size
grows
Size is a limiting factor in synthesis software
S/W is effective for intermediate size circuit

For larger system, circuit must be partitioned into
smaller blocks and each must be processed individually
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54
Another factor is target device technology

Fabrication process of FPGA and ASIC are very
different
FPGA chip is off-the-shelf part prefabricated and
pretested
ASIC design goes through lengthy, complex
fabrication process where many extra steps are
needed to ensure correctness of final circuit
Typical development flow of three different

types of designs are discussed:
Medium sized design targeting FPGA
Large design targeting FPGA
Large design targeting ASIC
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Design
55
Medium-sized -> design that does not need

any partition or predesigned IP cores
Circuit containing about 50,000 gates
Current synthesis s/w can effectively process
e.g. Moderately complex circuit like simple
processor or bus interface
Development flow consists of three columns:

Synthesis track
Physical design track
Verification track
Chapter 1

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56
Flow starts with Design file (RT-level

description of circuit) with a set of
constraints specifying timing requirements
Separate file called TestBench provides virtual
experiment bench for simulation and
verification contains code to generate input
stimuli and monitor output responses
Circuit can be constructed and verified once
these files are created

Design
Chapter 1
57
data file
process
Synthesis
netlist
Physical Design
RTL
description
synthesis
Verification
simulation
simulation
simulation/
timing
analysis
delay file
placement &
routing
configuration
file
device
programming

Design
testbench
FPGA
chip
54
delay file
8
Chapter
1
58
Steps in an ideal flow are as follows:
1. Develop the design file and testbench

2. Use design file as circuit description, perform a simulation to
verify that the design functions as desired
3. Perform a synthesis
4. Use the output netlist file of the synthesizer as the circuit
description, perform a simulation and timing analysis to verify
the correctness of synthesis and to check preliminary timing
5. Perform placement and routing
6. Annotate the accurate timing info. to the netlist, perform a
simulation and timing analysis to verify correctness of placement
and routing and to check whether circuit meets timing
constraints
7. Generate the configuration file and program the device
8. Verify operation of physical part
Above steps are meant for ideal process. In reality, flow may contain
many iterations to correct functional errors or timing issues.
Original design file may need to be revised or fine-tune the
parameters in synthesis and placement-routing s/w.
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Design
59
Large digital circuit contains millions of gates

Synthesis tools dont perform transformation and
optimization effectively in this range
It is necessary to partition the circuit into smaller
blocks and process them individually
Partition process also allows use of previously
designed subsystems or IP cores
For larger design, additional processes must be
added to the flow of medium-sized design
Initial design description is a high-level
behavioural description
In Synthesis track, a partition process is needed
to divide the systems into blocks of adequate
size and functionality
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Design
60
Output of partition process is a netlist of large

blocks
Some blocks may be already designed subsystems,
other blocks must be designed individually
In Verification track, an extra step is needed to verify
correctness of partition results and initial timing
Because of large no. of components, gate-level
netlist becomes very complex and simulation
consumes a lot of time.
So, Formal verification techniques are used
In Physical design track, a floor planning process
may be needed for performing initial placement for
processor level blocks
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Design
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Complexity of ASIC fabrication results in complex

development flow
Additional requirements inclusion of Testing
track and expansion of Physical design track
Testing is used to detect defects in fab. process
FPGA devices tested by vendors before shipping
so we dont need to worry about physical defects.
But, testing is integral part of ASIC design where
additional BIST circuits and special scanning
control circuits are added for final testing and need
to synthesized and verified
Finally test vectors are generated for combinational
circuit blocks and simulated to ensure that vectors
provide proper fault coverage
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Design
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In FPGA-based flow, Physical design track involves

only floor-planning and placement and routing,
which is accomplished by configuring FPGA
devices programmable interconnect structure
Physical design process of ASIC device is much
more complicated since it involves development
and verification of masks.
After placement and routing several additional
steps are needed like Design Rule Checking,
physical verification and circuit extraction
Due to high NRE cost of ASIC device, circuit must
be simulated and checked thoroughly before
fabrication. So, Verification track of ASIC-based
design flow is more comprehensive and exhaustive
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Design
63
Digital system can be described at different

levels of abstraction and from different points
of view.
As design process progresses, level and view
changes, either by human designers or s/w
So a common framework is needed to
exchange info. among designers and various
s/w tools
Hardware Description Languages (HDLs) serve
this purpose
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Design
64
Wide varieties of computer programming

languages (PL) Fortran, C, Java not adequate to
model digital h/w
Programming language is characterized by its
syntax grammatical rules used to write a program
semantics meaning of language constructs
When new language is developed, designers first
study the underlying processes and then develop
the syntactic constructs and semantics
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Design
65
Traditional general-purpose PL like C, are

modelled on sequential process operations
performed in sequential order, one operation at a
time
Since an operation depends on result of earlier
operation, order of operation cant be changed
Sequential process has two advantages:
At abstract level, it helps in developing an algorithm stepby-step

At implementation level, sequential process resembles
operation of a computer model and allows efficient
translation of algorithm to machine instructions
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Design
66
Characteristics of digital h/w are different from a sequential

model
Digital system is built by smaller parts, with customized
wiring connecting the i/o ports of these parts
When signal changes, parts connected to signal are
activated and a set of new operations is performed
These operations are performed concurrently and each
operation takes specific amount of time propagation delay
After completion, each part updates the value of
corresponding o/p port
If value is changed, o/p signal will activate all parts
connected to it and initiate another round of operations
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Design
67
Unique characteristics of a digital system

connection of parts, concurrent operations,
propagation delay and timing concepts
Sequential model used in traditional languages
cannot capture these characteristics of digital h/w
Hence, there is a need of special languages HDLs
which are designed to model digital h/w
Chapter 1

Design
68
In traditional language, program is coded to

solve a problem it takes certain input values
and generates output accordingly
Program is compiled to machine instructions
and run on a host computer
The application of an HDL program is
different
It has three major roles:
Formal Documentation
Input to a simulator
Input to a synthesizer
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69
library ieee ;
Chapter 1

Design
70
library ieee ;
use ieee.std_logic_1164.all ;
Chapter 1

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71
library ieee ;
entity xor2 is
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Design
72
library ieee ;
entity xor2 is
port( a, b: in std_logic;
Chapter 1

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73
library ieee ;
entity xor2 is
y: out std_logic);
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74
library ieee ;
entity xor2 is
y: out std_logic);
end xor2;
Chapter 1

Design
75
library ieee ;
entity xor2 is
y: out std_logic);
end xor2;
architecture beh_arch of xor2 is
Chapter 1

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76
library ieee ;
entity xor2 is
y: out std_logic);
end xor2;
begin
Chapter 1

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77
library ieee ;
entity xor2 is
y: out std_logic);
end xor2;
begin
y <= a xor b;
Chapter 1

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78
library ieee ;
entity xor2 is
y: out std_logic);
end xor2;
begin
y <= a xor b;
end beh_arch;
Chapter 1

Design
79

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Chapter 1

Introduction to Digital System

Introduction to Digital System

Introduction to Digital System

Advantage of digital devices

Introduction to Digital System

Digitization has spread to a wide range of

Introduction to Digital System

Introduction to Digital System

Introduction to Digital System

No two applications are identical and every one

performance-oriented processor (e.g., Pentium),

Special purpose processor: with architecture to perform a

Introduction to Digital System

Trade-off between Programmability, Cost,

Introduction to Digital System

Introduction to Digital System

Transistors and connection are made from many

Introduction to Digital System

Where customization is done:

In a fab (fabrication facility): ASIC (Application

Introduction to Digital System

All aspects (e.g., size of a transistor) of a circuit are

Introduction to Digital System

Circuit made of a set of pre-defined logic, known as

Introduction to Digital System

Circuit is built from an array of a single type of cell

Introduction to Digital System

Most versatile device technology

No custom mask needed

CPLD (Complex Programmable Logic Device)

Introduction to Digital System

Programmable device with simple internal structure

No custom mask needed

Introduction to Digital System

Small parts with fixed, limited functionality

Introduction to Digital System

Standard Cell ASIC

Introduction to Digital System

Area (Size): silicon real-estate

Standard cell is the smallest since the cells

Time required to perform a task

Introduction to Digital System

NRE (Non-Recurrent Engineering) cost: onetime, per-design cost

Standard cell: high NRE, small part cost

Introduction to Digital System

Introduction to Digital System

Trade-off between optimal use of

Introduction to Digital System

Introduction to Digital System

View: different perspectives of a system

Describe functionalities and i/o behavior

Describe the internal implementation (components

Add more info to structural view: component size,

Introduction to Digital System

Introduction to Digital System

Introduction to Digital System

How to manage complexity for a chip with 100

High Level Abstraction Focused, contains most

Introduction to Digital System

Based on size of basic building blocks transistors,

The levels of abstraction and views can be

Introduction to Digital System