Birla Institute of Technology and Science Pilani (Rajasthan)

Department of Electrical and Electronics Engineering

ANALOG & DIGITAL VLSI DESIGN (EEE/INSTR F313)
Date: 29/09/2016

Tutorial - 6

Q.1) Fig. 1 implements a logic function F. Find out the

Boolean expression for F. Implement the function F using
DCVSL and CPL logic family.

Fig.1

Q.2)
a) Find out the logic function F, in Fig.2.
b) Find out the eqivalent (W/L)eq for the pull down network.
c) Size the load transistor such that VOL does not exceed 0.2 V .
Given, VTdriver = 0.7 V, VTdriver = -1.2 V. (neglect body bias
effect)
d) Compare the driving capacity of nMOS depletion type load
with that of pseudo nMOS load.

Fig.2