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Nicols Quiroz
F
P
G
A
P
I
N
E
S
SPARTAN3
XC3S200
FT256
-4
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Pines
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Slices de un CLB
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Slice de un
Spartan3
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Xilinx Spartan-3
Starter Kit Board
Block Diagram
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sw7
sw6
sw5
sw4
sw3
sw2
sw1
sw0
FPGA Pin
K13
K14
J13
J14
H13
H14
G12
F12
Push Button
FPGA Pin
L14
L13
M14
M13
LED
led7
led6
led5
led4
led3
led2
led1
led0
FPGA Pin
P11
P12
N12
P13
N14
L12
P14
K12
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Anodo Control
AN3
AN2
AN1
AN0
FPGA Pin
E13
F14
G14
D14
Habilita con 0
LED
DP
FPGA Pin
P16
N16
F13
R16
P15
N15
G13
E14
Enciende con 0
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Persistencia
La persistencia de la visin, el cerebro percibe que
los 4 caracteres aparecen simultneamente
encendidos.
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DCBA
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
'0';
end Behavioral;
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Comparador 4 bits
A=B entonces Z= 11
A<B entonces Z= 01
A>B entonces Z= 10
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Entidad
entity Compa4x4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC_VECTOR (1 downto 0));
end Compa4x4;
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Arquitectura
comparador 4 bits
architecture Behavioral of Compa4x4 is
begin
process(a, b)
begin
if a=b then
z<= "11";
elsif a<b then
z<= "01";
else
z<= "10";
end if;
end process;
end Behavioral;
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10
Decodificador
Binario a 7 segmentos
Disear un decodificador de binario a 7 segmentos en VHDL.
Implementar en el FPGA (Spartan3).
Mostrar las letras a, b, c, d, f para las combinaciones de 1010 a 1111
a
f
Datos
Binarios
b
c
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Display 7Seg
a
f
b
c
e
d
Dec
21
0
1
2
3
4
5
Hex Bin
pg
C0 1 1
F9
11
A4 1 0
B0 1 0
99
10
92
10
fedcba
000000
111001
100100
110000
011001
010010
6
7
8
9
82
B8
80
98
0
1
0
0
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1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
22
11
Ejemplo
Describir en VHDL un circuito que multiplexe dos lneas (a y b)
de un bit, a una sola lnea (salida) tambin de un bit; la seal
selec sirve para indicar que a la salida se tiene la lnea a
(selec = '0') o b (selec = '1').
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Entidad
Define las entradas y salidas del circuito, es decir, la caja
negra que lo define.
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12
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RTL
ARCHITECTURE transferencia OF mux IS
SIGNAL nosel, ax, bx: bit;
BEGIN
nosel <= NOT selec;
ax <= a AND nosel;
Descripcin concurrente o tambin
bx <= b AND selec;
llamada de transferencia entre
registros:
salida <= ax OR bx;
END transferencia;
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13
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componentes
ARCHITECTURE estructura OF mux IS
COMPONENT and2
PORT(e1,e2: IN bit; y: OUT bit);
END COMPONENT;
COMPONENT or2
PORT(e1,e2: IN bit; y: OUT bit);
END COMPONENT;
Seal
COMPONENT inv
componente
PORT(e: IN bit; y: OUT bit);
Entidad de top
END COMPONENT;
SIGNAL ax,bx,nosel: bit;
BEGIN
u0: inv PORT MAP(e=>selec, y=>nosel);
u1: and2 PORT MAP(e1=>a, e2=>nosel, y=>ax);
u2: and2 PORT MAP(e1=>b, e2=>sel, y=>bx);
u3: or2 PORT MAP(e1=>ax, e2=>bx, y=>salida);
END estructura;
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14
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I/O PINS:
CLK : input free-running clock
LEFT : input signal to shift left (active-low switch)
RIGHT : input signal to shift right (active-low switch)
STOP : input signal to stop counting (active-low switch)
Q3-Q0 : counter outputs (active-low LEDs; Q0 is right-most)
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15
RTL
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16
Arquitectura
architecture jcounter_arch of jcounter is
begin
process (CLK)
begin
if (CLK'event and CLK='1') then -- CLK rising edge
if (CE='1') then
if (LEFT='1') then
Q(3 downto 1) <= Q(2 downto 0); -- Shift lower bits (Left Shift)
Q(0) <= not Q(3);
-- Circulate inverted MSB to LSB
else
Q(2 downto 0) <= Q(3 downto 1); -- Shift upper bits (Right Shift)
Q(3) <= not Q(0);
-- Circulate inverted LSB to MSB
end if;
end if;
end if;
end process;
end jcounter_arch;
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Funciones de conversin
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17
Contador de 0 a 9
entity conta0a9 is
Port (
ce : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (3 downto 0));
end conta0a9;
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Display 7Seg
a
f
b
c
e
d
Dec
35
0
1
2
3
4
5
Hex Bin
pg
C0 1 1
F9
11
A4 1 0
B0 1 0
99
10
92
10
fedcba
000000
111001
100100
110000
011001
010010
6
7
8
9
82
B8
80
98
0
1
0
0
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1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
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18
FSM
inputs
Mealy FSM
next
state
circuits
FF
output
circuits
output
clk
inputs
Moore FSM
next
state
circuits
FF
output
circuits
output
clk
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19
Read/Write controller
START=0
RW=1
IDLE
RW=0
WRITING
READING
LAST=1
LAST=1
WAITING
Entradas:
Salidas:
39
Entidad
entity Control is
Port ( CLK :
START :
RW :
LAST :
RDSIG :
WRSIG :
DONE :
end Control;
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
out STD_LOGIC;
out STD_LOGIC;
out STD_LOGIC);
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20
Estados
Utilice un tipo enumerativo para los diferentes estados
type STATE_TYPE is (ST1_IDLE, ST2_READING, ST3_WRITING, ST4_WAITING);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
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COMBINACIONAL
ST1_IDLE
ST2_READING
ST3_WRITING
ST4_WAITING
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21
Secuencial
SEC: process (clk)
begin
if (clk'event and clk = '1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
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Entradas y salidas
Entradas: switchs
CLK : T9
START : F12
RW : G12
LAST : H14
RST : M13
Salidas: LEDs
RDSIG : K12
WRSIG : P14
DONE : L12
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22
Diseo 1
Letrero con desplazamiento
Realizar un desplegador de mensajes que muestre
Ideas
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rst
4
4
4
4
Q0
Q1
Q2
Q3
ROM
16x8
d0
d1
d2
d3
mux
dir
sel
clk
dato
rst
MEF
Div frec
50 MHz
clk
sel
clk1
rst
clk2
clk
AN
clk1?
11 12 1
2
10
9
3
8
4
7 6 5
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clk2?
46
23
ROM
dir
dato
entidad?
ROM
16x8
dir
dato
entity ROM_C is
Port ( DIRECCION : in STD_LOGIC_VECTOR (3 downto 0);
DATO : out STD_LOGIC_VECTOR (7 downto 0));
end ROM_C;
10
11
12
13
14
15
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ROM
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24
MEF
Cuntos estados?
MEF
S0
sel
AN
sel
0111
00
AN
sel
1011
01
AN
sel
1101
10
AN
sel
1110
11
rst
AN
S1
clk
S2
S3
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Contadores
rst
Q0
Q1
Q2
Q3
49
Contadores
4 contadores de 4 bits
Contadores?
clk
Q0
"0000"
Q1
"0001"
Q2
"0010"
Q3
"0011"
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25
Multiplexor 4 a 1
4
4
4
4
d0
d1
d2
d3
mux
sel
2
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Cartas ASM
26
Diseo 2
Letrero por palabras
Realizar un desplegador de mensajes que muestre
H O L A
b U A P
Ideas
F C E
2 0 1 0
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S0
Carte ASM
AN
Cuntos estados?
11
01
S1
AN
H O L A
0
11
1011
00
m=?
01
10
F C E
S2
AN
2 0 1 0
00
m=?
10
S0 S1 S2 S3
b U A P
0111
11
1101
00
m=?
10
01
S3
AN
11
10
1110
00
m=?
01
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27
Diseo 2
case (estado) is
when s0 =>
an <= "0111";
if m= "00" then
sal <= "cod H";
elsif m = "01" then
sal <= "cod b";
elsif m = "10" then
sal <= "cod F";
else
sal <= "cod 2";
when s1 =>
<statement>;
when s2=>
<statement>;
when s3 =>
<statement>;
when others =>
<statement>;
end case;
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Spartan 3AN
28
S
p
a
r
t
a
n
3
A
N
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Push-Button
Los Pulsadores no tienen conectado una resistencia, estn
conectados de forma directa, por lo tanto deben
conectarse las resistencias de pulldown.
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29
C
o
n
f
i
g
u
r
a
c
i
n
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Spartan 3AN
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30
LEDs
NET
NET
NET
NET
NET
NET
NET
NET
"LED<7>"
"LED<6>"
"LED<5>"
"LED<4>"
"LED<3>"
"LED<2>"
"LED<1>"
"LED<0>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
61
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Interruptores deslizables
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32
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66
33
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34