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1.7 CPUs: Supervisor mode, Exceptions, Traps

and CO-PROCESSORS
These are mechanisms to handle internal conditions and they are very similar to interrupts in form.

1. Supervisor mode
Complex systems are often implemented as several programs that communicate with each
other.
These programs may run under the command of an operating system.
system
It may be desirable to provide hardware checks to ensure that the programs do not interfere
with each other-for example, by erroneously writing into a segment of memory used by another
program.
Normal programs run in user mode. The supervisor mode has privileges that user modes do not.
Control of the memory management unit is typically reserved for supervisor mode to avoid the
obvious problems that could occur when program bugs cause inadvertent changes in the
memory management registers, effectively moving code and data in the middle of program
execution.

ARM supervisor
i
mode
d
The ARM instruction that puts the CPU in supervisor mode is called SWI:
SWI CODE_1
It can, of course, be executed conditionally, as with any ARM instruction. SWI causes
the CPU to go into supervisor mode and sets the PC to 0x08.
In supervisor mode, the bottom five bits of the CPSR are all set to 1 to indicate that the
CPU is in supervisor mode. The old value of the CPSR just before the SWI is stored in a
register is called the saved program status register (SPSR).

1.7 CPUs: Supervisor mode, Exceptions, Traps and Co-Processors

2. Exceptions
An exception is an internally detected error. A simple example is division by
zero.
The exception mechanism provides a way for the program to react to such
unexpected events. Resets, undefined instructions, and illegal memory
accesses are other typical examples of exceptions.
Just as interrupts can be seen as an extension of the subroutine mechanism,
exceptions are generally implemented as a variation of an interrupt. Because
both deal with changes in the flow of control of a program, it makes sense to
use similar mechanisms.
mechanisms However,
However exceptions are generated internally.
internally
Exceptions in general require both prioritization and vectoring. Exceptions
must be prioritized because a single operation may generate more than one
exception.

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1.7 CPUs: Supervisor mode, Exceptions, Traps and Co-Processors

3. Traps

A trap, also known as a software interrupt, is an instruction that explicitly generates

an exception condition. The most common use of a trap is to enter supervisor mode.
The entry into supervisor mode must be controlled to maintain security.
The ARM provides the SWI interrupt for software interrupts. This instruction causes
p
mode. An opcode
p
is embedded in the instruction that can
the CPU to enter supervisor
be read by the handler.

Syntax: SWI {cond} <24 bit immediate>

The 24-bit immediate field does not influence the operation of the instruction but may be
interpreted by the system code.
1 Save the address of the instruction after the SWI (PC) into r14_svc.
1.
r14 svc
2. Save the CPSR into SPSR_svc.
3. Enter supervisor mode & disable IRQ by setting CPSR[4:0] to 100112 and CPSR[7] to l.
4. Set the PC to 0816 and begin executing the instructions there.
To return to the instruction after the SWI the system routine must not only copy r14_svc
back into the PC, but it must also restore the CPSR from SPSR_svc.

1.7 CPUs: Supervisor mode, Exceptions, Traps and Co-Processors

4. Co-Processors

CPU architects often want to provide flexibility in what features are implemented in
the CPU. One way to provide such flexibility at the instruction set level is to allow
co-processors, which are attached to the CPU and implement some of the
instructions. For example, floating-point arithmetic was introduced into the Intel
p
chips
p that implemented
p
the floating-point
gp
architecture byy pprovidingg separate
instructions.
To support co-processors, certain opcodes must be reserved in the instruction set for
co-processor operations. Because it executes instructions, a co-processor must be
tightly coupled to the CPU. When the CPU receives a co-processor instruction, the
CPU must activate the co-processor and pass it the relevant instruction.
A CPU may, of course, receive co-processor instructions even when there is no coprocessor attached. Most architectures use illegal instruction traps to handle these
situations.

Coprocessors in ARM
The ARM architecture provides support for up to 16 co-processors attached to a CPU.
Co-processors are able to perform load and store operations on their own registers. They
can also move data between the co-processor registers and main ARM registers.
An example ARM co-processor is the floating-point unit. The unit occupies two coprocessor units in the ARM architecture, numbered 1 and 2, but it appears as a single
unit to the programmer. It provides eight 80-bit floating-point data registers, floatingpoint status registers, and an optional floating-point status register.