Sequential Circuits Lecture on Flip-Flops, Counters and State Machines

Lecture 4
Sequential Circuits
Konstantinos Masselos
Department of Electrical & Electronic Engineering
Imperial College London
URL: http://cas.ee.ic.ac.uk/~kostas
E-mail: k.masselos@imperial.ac.uk
Sequential Circuits
Introduction to Digital Integrated Circuit Design
Lecture 4 - 1
Based on slides/material by
P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
Digital Integrated Circuits: A Design Perspective, Prentice Hall
D. Harris http://www.cmosvlsi.com/coursematerials.html
Weste and Harris, CMOS VLSI Design: A Circuits and Systems
Perspective, Addison Wesley
W. Wolf http://www.princeton.edu/~wolf/modern-vlsi/Overheads.html
Modern VLSI Design: System-on-Chip Design, Prentice Hall
Sequential Circuits
Lecture 4 - 2
Recommended Reading
J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective:

Chapter 7
Weste and Harris, CMOS VLSI Design: A Circuits and Systems

Perspective: Chapter 1 (1.4.9), Chapter 7 (7.3.1 7.3.5)
Sequential Circuits
Lecture 4 - 3
Outline
Bi Stability / Meta Stability
Latches
Flip flops
Schmitt Trigger
Multivibrator circuits
Counters and sequential machines
Sequential Circuits
Lecture 4 - 4
Combinational vs. Sequential Logic
In
Logic
In
Out
Circuit
Logic
Out
Circuit
State
(a) Combinational
Output = f(In )
Sequential Circuits
(b) Sequential
Output = f(In, Previous In)
Lecture 4 - 5
Sequential Logic
FFs
LOGIC
Out
tp,comb
In
2 storage mechanisms
positive feedback
charge-based
Sequential Circuits
Lecture 4 - 6
Positive Feedback: Bi-Stability

Vo1 =Vi2
Vi1
Vo1
Vi2 = Vo1
Vo2
Vi2 = Vo1
Vi1
Vo2
A
C
B
Vi1 = Vo2
Sequential Circuits
Lecture 4 - 7
Vi2 = Vo1
Vi2 = Vo1
Meta-Stability
Vi1 = Vo2
Vi1 = Vo2
Gain should be larger than 1 in the transition region
Sequential Circuits
Lecture 4 - 8
Outline
Latches
Flip flops
Schmitt Trigger
Sequential Circuits
Lecture 4 - 9
D Latch
When CLK = 1, latch is transparent

D flows through to Q like a buffer
When CLK = 0, the latch is opaque

Q holds its old value independent of D
transparent latch or level-sensitive latch
Sequential Circuits
Latch
CLK
CLK
D
Q
Q
Lecture 4 - 10
D Latch Design
Multiplexer chooses D or old Q
CLK
D
CLK
Q
Q
0
CLK
CLK
CLK
Sequential Circuits
Lecture 4 - 11
D Latch Operation
Q
D
CLK = 1
Q
D
CLK = 0
CLK
D
Q
Sequential Circuits
Lecture 4 - 12
Latch Design
Pass Transistor Latch

Pros
+ Tiny
+ Low clock load
Cons
-
Vt drop
nonrestoring
backdriving
output noise sensitivity
dynamic
diffusion input
Sequential Circuits
Used in 1970s
Lecture 4 - 13
Latch Design
Transmission gate
+ No Vt drop
- Requires inverted clock
Sequential Circuits
Lecture 4 - 14
Latch Design
Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
Output noise sensitivity

Or diffusion input
- Inverted output
Sequential Circuits
Lecture 4 - 15
Latch Design
Tristate feedback
+ Static
- Backdriving risk
Static latches are now essential
Sequential Circuits
Lecture 4 - 16
Latch Design
Buffered input
+ Fixes diffusion input
+ Noninverting
Sequential Circuits
Lecture 4 - 17
Latch Design
Buffered output
+ No backdriving
Widely used in standard cells

+
-
Very robust (most important)

Rather large
Rather slow
High clock loading
Sequential Circuits
Lecture 4 - 18
Latch Design
Datapath latch
+ Smaller, faster
- unbuffered input
Q
X
Sequential Circuits
Lecture 4 - 19
Outline
Latches
Flip flops
Schmitt Trigger
Sequential Circuits
Lecture 4 - 20
D Flip-flop
When CLK rises, D is copied to Q

At all other times, Q holds its value
positive edge-triggered flip-flop, master-slave flip-flop
CLK
CLK
D
Flop
Q
Q
Sequential Circuits
Lecture 4 - 21
D Flip-flop Design
Built from master and slave D latches
CLK
CLK
CLK
QM
D
CLK
QM
Latch
Latch
CLK
CLK
Q
CLK
Q
CLK
Sequential Circuits
CLK
CLK
Lecture 4 - 22
D Flip-flop Operation
D
QM
CLK = 0
QM
CLK = 1
CLK
D
Q
Sequential Circuits
Lecture 4 - 23
Flip-Flop: Timing Definitions
tsetup
thold
In
DATA
STABLE
Out
tpFF
DATA
STABLE
Sequential Circuits
Lecture 4 - 24
Maximum Clock Frequency
FFs
LOGIC
tp,comb
Sequential Circuits
Lecture 4 - 25
Flip-Flop Design
Flip-flop is built as pair of back-to-back latches
Sequential Circuits
Lecture 4 - 26
Enable
Enable: ignore clock when en = 0

Mux: increase latch D-Q delay
Clock Gating: increase en setup time, skew
Symbol
Multiplexer Design
Clock Gating Design

en
D
Q
en
en
1
0
Q
D
en
Flop
Flop
Flop
en
Latch
Latch
Latch
en
Sequential Circuits
Lecture 4 - 27
Reset
Force output low when reset asserted

Synchronous vs. asynchronous
reset
Synchronous Reset
reset
D
Q
Q
Asynchronous Reset
reset
reset
D
reset
reset
Sequential Circuits
reset
reset
D
Flop
Symbol
Latch
Lecture 4 - 28
Set / Reset
Set forces output high when enabled
Flip-flop with asynchronous set and reset
reset
set
D
set
reset
Sequential Circuits
Lecture 4 - 29
SR-Flip Flop
Sequential Circuits
0
1
0
1
0
0
1
1
Q
1
0
0
Q
0
1
0
1
0
1
0
1
1
0
0
Q
1
0
1
Q
0
1
1
Lecture 4 - 30
JK- Flip Flop
(a)
Kn
Qn+1
0
0
1
1
0
1
0
1
Qn
0
1
Qn
Jn
(c)
Q
(b)
Sequential Circuits
Lecture 4 - 31
Other Flip-Flops
Toggle Flip-Flop
Sequential Circuits
Delay Flip-Flop
Lecture 4 - 32
Master-Slave Flip-Flop
SLAVE
MASTER
SI
RI
PRESET
Q
Q
CLEAR
Sequential Circuits
Lecture 4 - 33
Edge Triggered Flip-Flop
J
S
>
K
Sequential Circuits
Lecture 4 - 34
Race Condition
Back-to-back flops can malfunction from clock skew

Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
CLK1
CLK2
Q1
Flop
Flop
CLK1
CLK2
Q2
Q1
Q2
Sequential Circuits
Lecture 4 - 35
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races

As long as nonoverlap exceeds clock skew
Can be used for safe design

Industry manages skew more carefully instead
2
1
QM
D
2
Q
1
1
2
Sequential Circuits
Lecture 4 - 36
CMOS Clocked SR- FlipFlop
VDD
M2
M4
Q
Sequential Circuits
M6
M1
M5
M8
M7
M3
Lecture 4 - 37
Flip-Flop: Transistor Sizing
(1.8/1.2)
4.0
(3.6/1.2)
VQ
(7.2/1.2)
2.0
0.0
0.0
Sequential Circuits
1.0
2.0
3.0
4.0
5.0
Lecture 4 - 38
6 Transistor CMOS SR-Flip Flop
VDD
M2
M4
Q
Q
R
M5
M1
Sequential Circuits
M3
Lecture 4 - 39
Charge-Based Storage
In
(b) Non-overlapping clocks
(a) Schematic diagram
Pseudo-static Latch
Sequential Circuits
Lecture 4 - 40
Master-Slave Flip-Flop
In
Overlapping Clocks Can Cause

Race Conditions
Undefined Signals
Sequential Circuits
Lecture 4 - 41
2 phase non-overlapping clocks
In
1
2
t12
Sequential Circuits
Lecture 4 - 42
2-phase dynamic flip-flop

1
In
Input Sampled
1
2
Output Enable
Sequential Circuits
Lecture 4 - 43
Flip-flop insensitive to clock overlap

VDD
VD D
M2
M6
M4
In
M3
CL1
M8
D
M1
M7
CL2
M5
section
section
C2MOS LATCH
Sequential Circuits
Lecture 4 - 44
C2MOS avoids Race Conditions
VDD
M2
VD D
VDD
VDD
M6
M2
M6
In
1
M3
M1
D
1
In
M8
D
M7
M5
(a) (1-1) overlap
Sequential Circuits
M4
M1
M5
(b) (0-0) overlap
Lecture 4 - 45
Sequential Circuits
Non-pipelined version
REG
log
REG
Out
REG
log
REG
REG
REG
a
REG
REG
Pipelining
Out
Pipelined version
Lecture 4 - 46
Pipelined Logic using C2MOS

VDD
In
VDD
VDD
F
C1
C2
Out
C3
NORA CMOS
What are the constraints on F and G?
Sequential Circuits
Lecture 4 - 47
NORA CMOS Modules

VD D
In1
In2
In3
VDD
VDD
PUN
PDN
(a) -module
Combinational logic
VDD
VDD
Latch
VDD
VD D
In 4
In 1
In 2
In 3
PDN
Sequential Circuits
Out
Out
In4
(b) -module
Lecture 4 - 48
Doubled C2MOS Latches
VDD
VDD
VDD
VDD
Out
In
In
Doubled n-C2MOS latch
Sequential Circuits
Out
Doubled n-C2 MOS latch
Lecture 4 - 49
TSPC - True Single Phase Clock Logic
VD D
VDD
VDD
VDD
PUN
In
Static
Logic
Out
PDN
Including logic into

the latch
Sequential Circuits
Inserting logic between

latches
Lecture 4 - 50
Master-Slave Flip-flops
VDD
(a) Positive edge-triggered D flip-flop
VDD
VD D
VDD
VDD
VDD
VDD
VDD
(b) Negative edge-triggered D flip-flop
VDD
(c) Positive edge-triggered D flip-flop

using split-output latches
Sequential Circuits
Lecture 4 - 51
Outline
Latches
Flip flops
Schmitt Trigger
Sequential Circuits
Lecture 4 - 52
Schmitt Trigger
V OH
Vou t
In
Out
VTC with hysteresis

Restores signal slopes
V OL
VM
Sequential Circuits
VM+
Vi n
Lecture 4 - 53
Noise Suppression using Schmitt Trigger
Vin
Vout
VM+
VM
t0
Sequential Circuits
t0 + tp
Lecture 4 - 54
CMOS Schmitt Trigger
VDD
M2
X
Vin
M1
Sequential Circuits
M4
Vout
M3
Lecture 4 - 55
Schmitt Trigger Simulated VTC
5.0
6.0
4.0
4.0
Vout (V)
VX (V)
3.0
2.0
V M+
2.0
V M-
1.0
0.0
0.0
Sequential Circuits
1.0
2.0
3.0
Vin (V)
4.0
5.0
0.0
0.0
1.0
2.0
3.0
V in (V)
4.0
5.0
Lecture 4 - 56
CMOS Schmitt Trigger (2)
VDD
M4
M6
M3
In
Out
M2
X
M5
VD D
M1
Sequential Circuits
Lecture 4 - 57
Outline
Latches
Flip flops
Schmitt Trigger
Sequential Circuits
Lecture 4 - 58
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
Sequential Circuits
Lecture 4 - 59
Transition-Triggered Monostable
In
DELAY
td
Sequential Circuits
Out
td
Lecture 4 - 60
Monostable Trigger (RC-based)

VDD
R
In
Out
(a) Trigger circuit.
In
VM
Out
t
t1
Sequential Circuits
(b) Waveforms.
t2
Lecture 4 - 61
Astable Multivibrators (Oscillators)

0
N-1
Ring Oscillator
V1
V3
V5
V (Volt)
5.0
3.0
1.0
-1.0
t (nsec)
simulated response of 5-stage oscillator
Sequential Circuits
Lecture 4 - 62
Voltage Controller Oscillator (VCO)
VD D
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
In
M1
Iref
Vcontr
Iref
M3
M5
Current starved inverter
t pH L (nsec)
6
4
2
0.0
0.5
Sequential Circuits
1.5
V co ntr (V)
2.5
propagation delay as a function

of control voltage
Lecture 4 - 63
Relaxation Oscillator
Out1
Out2
I2
I1
C
Int
T = 2 (log3) RC
Sequential Circuits
Lecture 4 - 64
Outline
Latches
Flip flops
Schmitt Trigger
Sequential Circuits
Lecture 4 - 65
One-bit counter implementation
Sequential Circuits
Lecture 4 - 66
One-bit counter operation
All operations are performed as s2.

XOR computes next value of this bit of counter.
NAND/inverter compute carry-out.
Sequential Circuits
Lecture 4 - 67
n-bit counter structure
Sequential Circuits
Lecture 4 - 68
Sequential machines
Use memory elements to make primary output values depend on state +

primary inputs.
Varieties:
Mealyoutputs function of present state, inputs;
Mooreoutputs depend only on state.
Sequential Circuits
Lecture 4 - 69
Sequential machine definition
Machine computes next state N, primary outputs O from current state S,

primary inputs I.
Next-state function:
N = (I,S).
Output function (Mealy):

O = (I,S).
Sequential Circuits
Lecture 4 - 70
FSM structure
Sequential Circuits
Lecture 4 - 71
Summary
Bi-stable sequential circuits

Latches (level sensitive circuits)
Flip flops (edge triggered circuits)
Non bi-stable sequential circuits

Schmitt Trigger (responds fast to a slowly changing input)
Monostable (only one stable state generates pulse of predetermined width)
Astable (no stable states output oscillates between two quasi stable states)
Sequential Circuits
Lecture 4 - 72

Sequential Circuits Lecture on Flip-Flops, Counters and State Machines

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Sequential Circuits Lecture on Flip-Flops, Counters and State Machines

Uploaded by

Copyright:

Available Formats

Lecture 4

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective:

Weste and Harris, CMOS VLSI Design: A Circuits and Systems

Introduction to Digital Integrated Circuit Design

Bi Stability / Meta Stability

Counters and sequential machines

Introduction to Digital Integrated Circuit Design

Combinational vs. Sequential Logic

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

Positive Feedback: Bi-Stability

Introduction to Digital Integrated Circuit Design

Gain should be larger than 1 in the transition region

Introduction to Digital Integrated Circuit Design

Bi Stability / Meta Stability

Counters and sequential machines

Introduction to Digital Integrated Circuit Design

When CLK = 1, latch is transparent

When CLK = 0, the latch is opaque

transparent latch or level-sensitive latch

Introduction to Digital Integrated Circuit Design

Multiplexer chooses D or old Q

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

Pass Transistor Latch

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

Output noise sensitivity

Introduction to Digital Integrated Circuit Design

Static latches are now essential

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

Widely used in standard cells

Very robust (most important)

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

Bi Stability / Meta Stability

Counters and sequential machines

Introduction to Digital Integrated Circuit Design

When CLK rises, D is copied to Q

Introduction to Digital Integrated Circuit Design

Built from master and slave D latches

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

Flip-Flop: Timing Definitions

Introduction to Digital Integrated Circuit Design

Maximum Clock Frequency

Introduction to Digital Integrated Circuit Design

Flip-flop is built as pair of back-to-back latches

Introduction to Digital Integrated Circuit Design

Enable: ignore clock when en = 0

Clock Gating Design

Introduction to Digital Integrated Circuit Design

Force output low when reset asserted

Introduction to Digital Integrated Circuit Design

Set forces output high when enabled

Flip-flop with asynchronous set and reset

Introduction to Digital Integrated Circuit Design

Introduction to Digital Integrated Circuit Design

JK- Flip Flop

Introduction to Digital Integrated Circuit Design