DIXESH PATEL

Vandana PG, 1st Cross, Samrat Layout

Arekere,Bengaluru, Karnataka- 560076

Mobile: +91 9429429607

Email: dixesh1992@gmail.com

Career Objective:
To seek a position as VLSI Engineer in an organization where I can contribute my skills for
organizational development as well as my professional career growth.
Overview:

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models in Verilog HDL and Testbenches in
System Verilog and UVM
Keen interest in the areas of digital design
knowledge of CMOS VLSI design, Verilog RTL coding, Simulation, Synthesis, MAP, Place
& Route

Experience in using industry standard EDA tools for the front-end design

Professional Qualification:

Maven Silicon Certified Advanced VLSI Design and Verification Course

o From: Maven Silicon VLSI Design and Training Center, Bangalore
o Duration: Jan 2016 Pursuing (6 months)

Master of Engineering in Electronics & Communication 2015

o Parul Institute of Engineering & Technology Vadodara, Gujarat
o --Cumulative Percentage: 8.10(CGPA)

Bachelors of Engineering in Electronics & Communication 2013

o Sigma Institute of Engineering & Technology, Vadodara, Gujarat
o --Cumulative Percentage: 8.03(CGPA)

Tool and Technical Skill:

HDL
HVL
TB Methodology
EDA Tool
Protocols
Domain
Knowledge

: Verilog HDL
: System Verilog
: UVM
: Xilinx-ISE, Questa Verification Platform, Riviera-PRO,Proteus
: AHB APB BRIDGE
: ASIC/FPGA front-end Verification

: Static Timing Analysis, RTL Coding, FSM based design,

Simulation, Code Coverage, Functional Coverage, Synthesis
Operating System : Windows & Linux

Projects:
[1] Router 1x3 RTL design and Verification
HDL: Verilog
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Riviera-PRO and Xilinx-ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of
the three output channels, channel0, channel1 and channel2.
Architected the class based verification environment using SV & UVM
Prepared various test cases and verified RTL using SV & UVM
Involved in generating functional and code coverage for the RTL verification sign-off
[2] AHB2APB Bridge IP Core Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tool: Riviera-PRO
Description: The AHB to APB Bridge is an AHB slave which works as an interface between
the high speed AHB and the low performance APB buses.
Architected the class based verification environment in UVM
Verified the RTL module with single master and single slave
Generated functional and code coverage for the RTL verification sign-off
[3] AXI UVC - AMBA AXI4 VIP Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tool: Riviera-PRO
Description: The AMBA AXI protocol is targeted at high-performance, high-frequency
system and includes a number of features that make it suitable for a high-speed submicron
Interconnects.

Single Master and Single Slave VIP

Burst Mode Supported are Increment, Wrapped and Fixed.

Data Transfer for Aligned address & Unaligned Address

Architected the class based verification environment in UVM

Constrained based Random Stimulus Generation using Sequences.

Implemented Test cases for VIP

Academic Projects:
Combine spatial domain and Transform domain image denoising As Compared to
BM3D
M.E Thesis under the guidance of Mr. Hardik Patel
Tool :MATLAB
Description: In this project I was written matlab code for dual domain image denoising, It
detects the noise automatically from the noisy image and remove the noise using bilateral filter
and remaining noise is filtered by transform domain noise filtering techniques and compared
to Block matching 3d filtering techniques that is more complex compared to my technique,

Pick and Place robot with smart industrial wireless communication

B.E PROJECT
EDA Tools: Proteus simulator & KEIL.
Description: The task given by company was to design pick and place robot with industrial
wireless communication. It transfers object between two places. Robot is designed using
combination of relay and transmitter and receiver .we interface RS-232 to LCD wirelessly
using ATMEGA for transmitting information one office to another office with wireless
communication we have also made Water level alarm with LCD display. It is water indicator
and display the level of water. It is also used in boiler, water tank
Vocational Training & Visit:

Visit at Bhaskaracharya Institute For Space Applications and Geo-Informatics,

Gandhinagar
Training of Embedded in C Programming from SOFCON INDIA PRIVATE
LIMITED
Vocational Training in JCT ELECTRONICS LIMITED

Papers Presented/Published in International, National Journals:

"An Analytical Study of Spatial Domain Image Denoising Techniques"IJRET-2015

"A Comparative Analysis of Different Multi-focus Image Fusion Techniques"IJSRD2015

Extra-Curricular & Activities:

Participated in "Short Term Training Program on Linux and Raspberry PI"

Participated in "National Conference on Emerging Vistas of Technology in
21st Century"2014
Participated in "National Conference on Emerging Vistas of Technology in
21st Century"2015

Personal Profile:
Name

Dixesh P. Patel

Date of Birth

24th June 1992.

Age

24

Fathers name

Piyushbhai B. Patel

Mothers name

Raxaben P. Patel

Gender

Male

Marital Status

Single

Languages Known

English, Hindi & Gujarati

Nationality

Indian

Permanent Address

Societyjin, At:Dhokaliya , Po&Ta:Bodeli,

Di:Vadodara,Gujarat-391135

Declaration:
I hereby declare that the information given above is true to the best of my knowledge & belief.
Date: /
Place:

/
Dixesh Patel