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Contents
LM3481 Description ......................................................................................................... 2
Principle of Flyback Converter ............................................................................................. 2
Flyback Parameters Design ................................................................................................ 4
LM3481 Flyback Parameters Design ..................................................................................... 9
Bench Verification .......................................................................................................... 16
Conclusion .................................................................................................................. 17
References .................................................................................................................. 17
List of Figures
10
11
12
13
14
15
16
17
18
......................................................................................
.............................................................................
15
LM3481 Description
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19
20
21
22
23
24
....................................................................................
17
List of Tables
Design Specifications
.......................................................................................................
LM3481 Description
The LM3481 is a versatile low-side N-FET controller which has a wide input supply voltage range of 2.97
V to 48 V and can easily configured in topologies like boost, SEPIC, and flyback. Current mode control
provides superior bandwidth and transient response in addition to cycle-by-cycle current limiting. Figure 1
shows the pin configuration of LM3481.
ISEN
UVLO
COMP
FB
AGND
10
LM3481
VIN
VCC
DR
PGND
FA/SYNC/SD
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In CCM mode (see Figure 3), the amount that the inductor current increases can be calculated by using a
version of the familiar relationship:
di
'T
VL L L ; 'iL VL
dt
L
where
(1)
The inductor current increase during the ON period can be approximated as:
D u Ts
VIN u
Lpri
'IL
where
(2)
The inductor current decrease during the OFF state is given by:
VOUT u NPS u 1 D T
'IL
Lpri
(3)
In steady-state conditions, the current increase, IL(+), during the ON time and the current decrease during
the OFF time, IL(), must be equal. Otherwise, the inductor current would have a net increase or decrease
from cycle-to-cycle which would not be a steady-state condition. Then the relationship of VIN, VOUT and
duty cycle could be derived in Equation 4.
VIN
D
VOUT
u
Nps 1 D
where
Nps:1
Vin
Cin
Lm
Vout
D
Cout
(4)
RL
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VQ1gate
IQ1
t
ID1
IOUT
t
VIN+NpsVOUT
VDS
t
VOUT
Vsec
t
-VIN/Nps
Figure 3. Flyback Main Waveform in CCM
3.1
Transformer Design
Flyback can be designed in CCM, DCM, or CRM mode based on the application requirements. CCM has
smaller ripple as well as RMS current, lower MOSFET conduction and turnoff losses, better full load
efficiency, and so forth. While DCM has no diode reverse recovery loss, lower inductance value which
may result into smaller transformer, better no load efficiency, and so forth. For the DC-DC application,
where the input voltage is low, CCM is an attractive option to minimize the primary RMS current
particularly in higher power systems even though the system's dynamic behavior is considerably difficult to
maintain. CCM is taken as an example in this report for a lower input voltage design application. The
transformer turn ratio Nps could be derived as shown in Equation 5.
VIN _ min
Dmax
NPS
u
VOUT
1 Dmax
where
Dmax is the maximum duty cycle allowed in the design at lowest input voltage.
(5)
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Suppose the efficiency of the flyback converter is , the input power and output power relationship could
be derived as shown in Equation 6.
VIN u ILM u D u K PO
where
ILM is the average current flowing in the transformer primary winding, which is also equals to the input
average current
(6)
where
(7)
According to Equation 2, Equation 4, Equation 6, and Equation 7, LM function could be derived as shown
in Equation 8.
2
2
2
u Nps
VOUT
uK
VIN
u
KL u PO u S
VIN VOUT u Nps
LM (VIN )
where
PO is output power
fs is flyback converter frequency
(8)
From this equation, it also could be observed that LM has positive correlation with VIN. That means the
magnetizing inductor should be designed at highest input voltage to ensure the converter could run at
CCM during all the input voltage range.
The peak current flowing in the primary winding can be calculated as:
Ipk _ L
IN
OUT u K u Nps
(9)
The calculated turns ratio, primary winding inductance and peak current can be used to determine the
magnetic core of the transformer, number of turns on primary and secondary windings, as well as wire
thickness.
3.2
Vds _ MOS
VR _ diode
VOUT u Nps
VIN _ MAX
Nps
(10)
The current RMS rating of MOSFET and Diode could be derived as shown in Equation 11.
IdsRMS
IR _ diode
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2
V
uI
D u OUT OUT
VIN u D
2
1 D u IOUT
KL u ILM
KL u ILM u Nps
3
(11)
The current rating of MOSFET and Diode should at least be Ipk_LM and IOUT respectively.
3.3
Switching period
Hvoi(s)
Sn
HEA(s)
Se
External ramp
Hdiv(s)
Ri
He(s)
Hdi(s)
Hvi(s)
Figure 6 is the average small signal model of flyback converter. According to the KCL and KVL principle,
use Equation 13 and Equation 14:
D u v s
V
N uV
u d s sL u i s N u v
s
in
1 D u Nps u iLm s
IN
ps
OUT
VOUT
d s
RLd
sCout u V out s
Lm
ps
out
(13)
v out s
RL
(14)
To separate the small signal disturbance, the gain function from duty cycle to inductor current could be
calculated as shown in Equation 15.
V
1 VIN
sCout u IN
VIN u D u Nps
u
i
1 D RL 1 D
Lm s
Hdi s
2
d s
VIN u D
Lm
s s2LmCout
V
R
L
OUT
(15)
Considering the practical crossover frequency is much higher than the corner frequency with PCM control,
simplify Equation 15 to Equation 16:
VIN
VIN u D u Nps
i
Lm s
|1 D
Hdi s
Lm u s
d s
(16)
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Shutdown Detect
VIN
SYNC/Fixed
Frequency detect
FA/SYNC/SD
Oscillator
Set/Blankout
Slope
Compensation
6V
Soft-start
UVLO
Bias
Voltages
UVLO
Thermal
Shutdown
40 A
1.275V
Reference
Ramp
Adjust
I-V
Converter
COMP
+
V-I
Converter
EA
FB
Vfb + Vovp
Overvoltage
Comparator
Switch
Logic
PWM
Comparator
R
S
Q
+
VCC
220 mV
ISEN
Short-circuit
Comparator
One Shot
+
Switch
Driver
DR
Level Shifter
AGND
PGND
vi
vc
Hvi(s)
Fm
i L
Hdi(s)
He(s)
Ri
GEA(s)
Hdiv(s)
Hivo(s)
vo
i s
iin s
Lm
Cout
RLd
vout s
Nps I d s
D vin s
vin s
Nps 1 D i s
D i s
1 D N ps vout s
I d s
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The gain function from magnetizing inductor current to output voltage could be calculated as shown in
Equation 17.
Hivo s
L u VOUT
Nps u 1 m
u s
VIN u RL
s u Cout
1 1
D u Nps
u
1 D
RL 1 D
v 0 s
i
Lm s
(17)
He s
TS u S
eTSuS
|1
1
s2
s
2
TS
S
T
S
(18)
Ignore the disturbance of VIN, the control block for current regulation loop could be found in Figure 5 as
below:
vc
Fm
He(s)
Hdi(s)
iLm
Ri
3.4
The gain function from comp voltage to inductor current is shown in Equation 19.
i
F u Hdi s
Lm s
H s
v c s
1 He s u Ri u Fm u Hdi s
(19)
The gain function from comp voltage to output voltage is shown in Equation 20.
v o s
Fm u Hdi s u Hivo s
PS s
v c s
1 He s u Ri u Fm u Hdi s
(20)
v comp s
v o s
K optoRup R1 Rfb1 u C1 u s 1
Ropto
Rfb1C1 u s
R2C2 u s 1
R2RupC2Copto u s
C2Rup
CoptoRup
R2C2 u s 1
(21)
(22)
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VDD
vo
Ropto
Rup
vcomp
K
Rfb1
vx
R2
C2
R1
C1
Copto
Rfb2
4.1
PARAMETER
EXAMPLE VALUE
Vin min
5 VDC
Vin max
32 VDC
Vout
12 VDC
Iout
2 max
130 kHz
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Lm(uH)
12.0
8.0
4.0
0
5
14
23
32
Vin(V)
Figure 9. The Curve of Lm and Vin Relationship
Peak Primary Winding current can be calculated as shown below:
Ipk _ Lm
9.13 A
(24)
Use 30% to 40% headroom on the Peak primary current to calculate the current sense resistor.
The limit on the ISEN pin of LM3481 is 100 mV so the current sense resistance can be chosen as
100 mV / 12 A = 8.33 m. A current sense resistance of 6 m was chosen for this application.
4.2
Vds _ diode
IdsRMS
IR _ diode
Vo
uI
D u OUT OUT
VIN u D
2
1 D u IOUT
44 V
(25)
KL u ILM
KL u ILM u Nps
3
10.86 A
9.31 A
(26)
To get good thermal performance, reasonable package for diode and MOSFET are needed to be chosen
beside ensuring required voltage/current rating. Here MOSFET CSD19502Q5B (80V/100A, DNK0008A)
and diode V10P-M3/86A (100V/10A, TO-227) are chosen.
4.3
10
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XFRMR detils :
Primary - Secondary Ration 4-2:8-12 =1.:1
Primary Peak Current = 12 A
Primary RMS current = 9.3A
Secondary Peak Current= 12.2A
Secondary RMS=5.5A
Primary Inductance=12uH
EFD25 Core (N87/CF139)
C1
2200pF
2000V
PWRGND
C2
2200pF
2000V
Vin
J1
GND
GND
BAT+
1
2
3
5V-32V
575-4
C3
TP_GND
330F
C4
10F
C5
3.3F
R19
1.0k
R20
1.0k
T1
10
11
12
C6
0.22F
D_SW
J2
D1
Vout
VOUT
R1
10.0
PWRGND
4
5
6
D2
575-4
R2
60.4k
PWRGND
7
8
9
J3
C7
22F
V10P10-M3/86A
12H
C22
12V@2A
C8
22F
C9
22F
C10
22F
C20
270F
C21
270F
575-4
ISOGND
J4
DFLS1100-7
SW
4.7
R5
25.5k
Q1
CSD19502Q5B
R3
49.9
1,2,3
R4
5,6,
7,8
0.1F
PWRGND
575-4
C11
GND
330pF
ISEN
Loop_1
R6
100
PWRGND
C12
2200pF
R8
0
R9
0.006
Loop_2
U1
R10
4.70k
R12
374
3
4
6
9
7
C15
1F
R13
162k
C16
0.22F
COMP
UVLO
FB
VIN
FA/SYNC/SD
DR
VCC
PGND
ISEN
AGND
R11
10.0k
10
D4
BAS16W-7-F
PWRGND
8
1
1
KA
D5
BAS16W-7-F
LM3481MM/NOPB
Freq=130KHz
R14
3.00k
AK
C17
1F
R16
3.83k
U2
PWRGND
GND
R17
LTV-817S
PWRGND
U3
TL431AIDBZR
3
C19
1F
374
R18
1.00k
PRE
GND
11
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According to Equation 11 to Equation 16, Hdi(s), Hivo(s), He(s) and H(s) transfer function could be
derived. Figure 11 shows the Mathcad calculated Bode plot of LM3481 flyback converter, and Figure 12
shows the simplis simulation schematic and results. It could be observed that the right half plane zero of
flyback converter is at 33.2 kHz. The calculated results match the simulation results very well.
0
Phase_Powerstage(deg)
Gain_Powerstage(dB)
60
40
20
0
s 20
s 40
s 60
1
10
105
106
12
s 100
s 200
s 300
s 400
10
105
106
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13
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4.4
4.4.1
4.4.2
(28)
4.4.3
R1
14
10
16.2 20
u Rfb1 u Ropto
K opto u Rup
374 :;
(29)
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To reduce the variables and simplify the design, setting R2=R1=374 . Then the compensation transfer
function could be considered as one-pole one-zero system.
4.4.4
40
Phase_Compensation(deg)
Gain_Compensation(dB)
Figure 15 shows the Mathcad calculated Bode plot of compensation circuit, and Figure 17 shows the
simplis simulation schematic and results. It could be observed that the calculated results and simulation
results matched well.
20
s 20
10
105
106
180
160
140
120
100
80
1
10
105
106
4.5
15
Bench Verification
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200
Phase_TLoop(deg)
Gain_TLoop(dB)
50
25
0
s 25
s 50 2
10
103
104
Frequency(Hz)
0
s 100
s 200 2
10
105
100
103
104
Frequency(Hz)
105
Bench Verification
Figure 21 and Figure 22 show the output voltage ripple and rectifier diode switching waveform (anode to
ISO GND) for the LM3481-FlybackEVM. The output current is the rated full load of 2 A and at of VIN = 5.5
V and 28 V respectively. It can be observed that the design works in CCM mode over wide input range.
16
Conclusion
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Figure 23 shows the LM3481-Flyback load transients performance. The current step is from 50% to 100%
of maximum rated load at VIN = 12 V with 70-mA/s slew rate. Figure 24 shows the loop-response
characteristics. Gain and phase plots are shown for VIN voltage of 12 V with load current of 2 A, which is
verified with the previous theory analysis.
Conclusion
The LM3481 device is a versatile low-side N-FET high-performance controller which can support Wide Vin
of 2.97 V to 48 V and can easily be configured in flyback topology in various isolated as well as nonisolated single or multiple output applications.
References
1.
2.
3.
4.
LM3481 High-Efficiency Controller for Boost, SEPIC, and Flyback DC-DC Converters (SNVS346)
LM3481 Flyback-EVM User Guide (SNVU528)
How to Configure LMZ30604 Power Module with Ceramic Capacitor (SNVA732)
Under the Hood of Flyback SMPS Designs (SLUP261)
17
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