Computer Organization

Curs 2017
Patricia Santos Rodriguez

Why/What we need to know

about computer architectures?
Computer architectures describe the elements
of a computer and the relations between
them.
A F1 pilot have to know about mechanics.

Machine language
Computer instructions can be represented as
sequences of bits. Generally, this is the lowest possible
level of representation for a program each instruction
is equivalent to a single, indivisible action of the CPU.
This representation is called machine language, since it
is the only form that can be understood directly by
the machine.
A slightly higher-level representation (and one that is
much easier for humans to use) is called assembly
language.
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Assembly language
Assembly language is very closely related to
machine language, and there is usually a
straightforward way to translate programs
written in assembly language into machine
language.
This algorithm is usually implemented by a
program called the assembler.
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From High level to

machine language
High level language
(e.g. C language)
Assembly language
(e.g. MIPS)
compile

assembly
Machine
language

But where and how?

We need to understand the computer
arquitecture

Von Neumann architecture

ALU

CPU
COMPUTER
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Von Neumann architecture

The major components of a computer include:
The CPU
Memory
Peripherals that make the computer useful, such as
the disk, printer, and mouse.

The CPU consists of a control unit and the

arithmetic/logic unit (ALU).
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Processor
CPU must:
Fetch instructions
Interpret instructions
Fetch data
Process data
Write data

The Central Processor Unit

(CPU)

The major components of the CPU are:

A unit to load instructions from memory to the CPU.
The arithmetic-logic unit (ALU) or datapath, to process data.
Registers to hold arguments and results of ALU processing.
A control unit to decode instructions and initiate ALU action.
.

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The ALU
The ALU (Arithmetic-Logic Unit, or Patterson and Hennessys
datapath) is the figuring unit of the computer, providing
the calculation capability.
The ALU is connected to storage elements (registers for
holding data to be processed and the results of the
processing) by data buses.
The ALU processor is normally composed of single-element
(one-bit) processors (primarily adders), which are
assembled together to form a 32-bit processor (in the case
of the MIPS R2000). It also includes some other processing
elements.
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ALU Components
As noted above, the ALU needs other components as well:
Registers to store arguments and results.
Buses to carry data from registers to the ALU and results back to
the register unit.
Two memory access units, with associated buses:
An instruction fetch unit to get instructions from computer
memory as needed. This includes a program counter, which
always points to the address of the next instruction to be
accessed.
A second path to memory to obtain data to be used in the
program and to store data back into memory as required.
A control unit that tells the ALU what to do .
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ALU Components

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ALU Program Counter (PC)

The program counter (PC) is a
register that addresses the next
instruction in memory.
Since the PC always points to the
next instruction, this address
must be readily updated.
The usual method is to add 4 to the
current address (since the
instruction is a 32-bit word and
each 32-bit word has an address 4
bytes higher than the last word).
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ALU Components

For the ALU, we need some more components: (1) a register

block (group of registers) in which to store operands and
results, and (2) the ALU itself, which is primarily combinational
logic, as mentioned earlier. Since the ALU is largely an adder
plus other logic, we use the adder symbol.
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ALU Architecture
for Processing
In the MIPS CPU, all
arguments used in
processing are stored in
registers.
This requires two buses
to route data to the ALU.
All registers are tied to
both output buses.
A single input bus carries
results back to all 32
registers.
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ALU: Data Memory

In addition to instruction
memory, we need data
memory.
Now in reality, memory is
memory, so when we say
Data memory, we simply
mean we need a path to
the single computer
working memory to
load/store data in
load/store instructions.
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MIPS: Registers vs Memory

Registers are faster to access than memory
Operating on memory data requires loads and
stores
More instructions to be executed
Compiler must use registers for variables as
much as possible
Only spill to memory for less frequently used
variables
Register optimization is important!
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MIPS: Registers

We will learn more about Registers when we see the MIPS R-format instructions!
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MIPS: Memory
Main memory used for composite data
Arrays, structures, dynamic data

To apply arithmetic operations

Load values from memory into registers
Store result from register to memory

Memory is byte addressed

Each address identifies an 8-bit byte

Words are aligned in memory

Address must be a multiple of 4
We will learn more about this in following lessons!
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The Sign extender

We will see when studying MIPS
instructions and MARS that many
instructions have immediate parts that are
16 bits in length.
The immediate is added to a 32-bit operand
(register or PC contents) to create an
operand or perhaps a new address, for
instance in a branch instruction.
Since the immediate may be + or , then to
add it to a 32-bit argument, we must sign
extend it to 32-bits (as we discussed in the
MIPS/SPIM lectures).
The sign extension unit performs this
function.

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Example
Data bus connection in a Load Instruction

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A Complete ALU
Over the last slides, we have designed many of the elements
that, when assembled, will make up the ALU of our MIPS
computer.
We now connect the various sections of the ALU together to
produce a final single cycle ALU; an ALU that executes one
instruction each time the clock ticks.
Note that up to now, we have NOT considered any of the
Control elements of the ALU; that is, the circuits that interpret
the instructions and direct the ALU as to (1) which operation to
execute, and (2) what operands or variables to process.
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The Single Cycle ALU

What we have accomplished in this ALU design is to come up
with all the processing hardware necessary to implement the
MIPS instruction set. Note that we are NOT considering the
control circuits.
This basic MIPS processor design is referred to as the single cycle
ALU (or sometimes the single cycle CPU). Why is this?
The reason is that this MIPS CPU (more or less the original implementation
of the MIPS instructions) is designed so that ANY instruction can be
processed in one cycle of the CPU clock.

Lets consider how this single cycle CPU works.

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Single Cycle Timing

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ALU Summary
We have now seen how the common elements we studied
earlier are combined to make the MIPS ALU.
This design is a solid, single-cycle implementation that
supports the MIPS instruction we are going to study in the
following lectures on assembly language programming.
We will study the control logic for this in the next slides.

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The CPU Control Unit

Having designed the ALU or datapath so that it can perform the

necessary instructions, we now have to do the same thing for the
control unit, which decodes instructions and provides direction to the
CPU.
The MIPS control unit decodes the six bits on either end of the 32-bit
instruction word, that is, the op code and function code* fields, to
determine each instruction sequence.
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Control Unit: functionality

The control unit determines ALU functions in each instruction and

selects operands for the ALU.
The operation code (the left six bits of the instruction)
determines the type of operation and in some cases (such as
jump instructions) the actual instruction itself.
In the case of register-register instructions, the function code
determines the instruction (for example, in the R/R instruction
above, the function code 0x 20 means add).
We will learn more about Registers when we see the MIPS R-format instructions!

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Control Unit: functionality

The control unit is a
collection of decoders
and multiplexers.
The decoded instruction
fields tell (1) the ALU
what function to
perform, (2) what
operands to use.

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Current Architecture
The ALU control uses instruction bits 0-5 to obtain information
about the ALU operation in register-to-register instructions.
Note in the following diagram (next slide) that some of the
decoding is done in the register block, which has the decoding
mechanism that identifies source and destination registers in
load/store and register/register operations.
The ALU control also has input control lines from the
operation code decoder which decodes bits 26-31.

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Example: ALU will full

Control Blocks

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Op Code Control
block Signal Identifier

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Making the ALU

more efficient
We have now completed design of the basic MIPS R-2000 CPU.
Although a good basic design, it has a serious drawback:
Our processor is designed so that all instructions complete in one clock
cycle.
While this assures that there is sufficient time to complete any
instruction, it also means that one clock period must be long enough to
accommodate the longest and most complicated instruction.
Thus, ALL instructions take as long as the longest instruction.
Since many (most!) instructions in the MIPS architecture take less time to
execute than the longest instructions (which are usually the lw memory
reference instructions), this means that we are slowing execution of our CPU
a large part of the time to accommodate instructions that occur substantially
less frequently.
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Multicycle implementation
A solution to the single-cycle problem is stated as follows:
Each instruction has several phases, such as fetch/decode, register
selection, ALU processing, etc.
Instead of using a single clock cycle for the whole instruction, run
the clock much faster, and have a single clock cycle for each of the
elements or phases of the instruction process.
Many instructions take fewer phases (for example, jump, branch
[the fewest phases], register-register or store instructions), so
these instructions execute much faster.
As most instructions execute faster than the longest instructions
(such as lw), the average instruction time will be reduced
substantially.
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MIPS Multicycle concept

Split the processing into five processing segments.

Run the clock much faster (essentially 5X faster!).
Do one instruction segment per clock cycle.
PC updates, branches and jumps take 3 processing segments since
they are simpler; they run much faster.
Register-register instructions do not require memory access. They take
four instruction segments and finish in about 30% more time than
jumps and branches.
Only load memory-access instructions take a full five processing
segments (store takes only four), but do not slow down the other
instructions to their speed.

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Multicycle Implementation

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The Fetch, Decode, Execute

cycle
With the structure of registers, units, memory and buses laid out,
let us be clear that the overall operational aim is very simple.
We want our CPU repeatedly to:

FETCH the next instruction from memory into the instruction

register
DECODE the instruction (that is, work out which it is)
EXECUTE the instruction

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The Fetch, Decode, Execute

cycle
Fetching and an Executing an
instruction simply require the
CPUs Control Section to issue
Levels and Pulses which set up
pathways and fire register
transfers so that
Data is moved from
memory to registers, and
between registers
Data is passed (sometimes)
through the ALU, and
Data is stuffed back into
the memory

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The Fetch, Decode, Execute

cycle

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Step 1: Fetch
The Control Unit sends a signal to the RAM in order to fetch the
program and data, which is then stored in one of the CPUs
register. To do so, the CPU makes use of a vital hardware path
called the address bus along which the program and data
travels.
The Control Unit then increments the Program Counter (PC). The
PC is an important register that keeps track of the running order
of the instructions and shows which instruction in the program is
due to be executed next.
The CPU then places the address of the next item to be fetched
on to the address bus. Data from this address then moves from
main memory into the CPU by travelling along another hardware
path called the data bus.
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Step 2: Decode
The instruction set of the CPU is designed to understand a
specific set of commands, which serves to make sense of
the instruction it has just fetched. This process is called
decode.
A single piece of program code might require several
instructions.

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Step 3: Execute
This is the part of the cycle when data processing takes
place, and the instruction is executed.
Once the execute stage is complete, the CPU begins the
cycle all over again.

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Architectures
CISC vs RISC

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RISC
RISC (Reduced Instruction Set Computer)
At 80s Smaller instructions.

Reduce the complexity of the instructions

Low complexity.
Increase the speedup.
Less error-prone.
Reduce design-time.
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RISC
Smaller instructions.
Uniform instructions (same size) a Easier
decoding.
Regular format.
Easier addressing.
Use of registers a Faster access.
Memory access load/store.
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RISC
No stack, but registers
Few parameters.
Few local variables.
Simpler hardware Less space.
Von Newmann scheme.
VLSI (Very Large Scale Integration)
Hardwired design No microprogramming.
Optimise the instruction Pipeline.
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RISC
RISC Compiler
Optimization is done by the compiler.
Less instructions optimized job.
Less instructions Less errors.
Between the program and the microprocessor.
Examples of RISC micro-processors:
ARM Mobile phones
MIPS Playstation 2, Nintendo 64
SPARC Sun Mycrosystems
Cell Playstation 3
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MIPS
MIPS (Microprocessor without Interlocked Pipeline Stages)
MIPS Computer Systems Inc. was founded in 1984 by a
group of researchers from Stanford University that
included John L. Hennessy, one of the pioneers of the RISC
concept. See: www.mips.com

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MARS (MIPS Simulator)

MARS is going to be used in our labs lessons as the main software!

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Acknowledgements
Part of the content of this collection of slides is based from:
- The University of Texas Dallas (UTD) Erik Jonsson School of
Engineering and Computer Science

- In most cases, the MIPS illustrations shown are from the

Patterson and Hennessy book (David A. Patterson and John
L. Hennessy, Computer Organization and Design, 2nd
Edition)

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