Class Test - 2016: Ec + Ee

Serial No.
: A_Digital Electronics_240716_EC + EE_ND
CLASS TEST - 2016

Electronics and Electrical Engineering
Digital Electronics
EC + EE
Date : 24/07/2016
ANSWERS
1.
(c)
7.
(a)
13.
(c)
19.
(b)
25.
(d)
2.
(a)
8.
(b)
14.
(a)
20.
(a)
26.
(b)
3.
(c)
9.
(d)
15.
(b)
21.
(d)
27.
(b)
4.
(a)
10.
(b)
16.
(a)
22.
(c)
28.
(a)
5.
(a)
11.
(b)
17.
(c)
23.
(d)
29.
(d)
6.
(b)
12.
(c)
18.
(a)
24.
(a)
30.
(b)
CTEC16 | Digital Electronics
Explanation
1.
(c)
For mod-10 ripple counter, no. of flip-flops = n = 4
Total delay = n = 4 tpd flip-flop= 40 nsec.
2.
(a)
For digital ramp ADC, Tmax = (2n 1) Tclk
For successsive approximation ADC, Tmax = nTclk
ratio =
3.
2n 1 255
=
= 31.875
8
n
(c)
Degenerate logic combinations are those in which the result can be generated with single gate operation.
NAND - NOR
Degenerate form
4.
(a)
QB
QC
QA
QA
1
QC
After 5 clock pulses QA QB QC will be 011.
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8
5.
ELECTRONICS ENGINEERING
(a)
The output Z will be
Z = ABC + ABC + ABC + ABC

= AC (B + B ) + AC (B + B )
= AC + AC
Z = AC
6.
(b)
Vout Decimal equivalent of input binary code.
4.5 Vout
=
9
3
For (1001)2 output is 4.5 V, then for (0011)2 output will be 1.5 V.
7.
(a)
Redrawing the digital circuit
A2 B2
A1 B1
A0 B0
From the figure we get,
Y = A0 B0 A1 B1 A2 B2
With 6 variables, 26 = 64 = 32 with odd 1s + 32 with even 1s.
So, Y is XOR of six boolean variable and Y will be 1 when odd number of variable are 1. Thus there will be
32 cases for the output to be 1.
8.
(b)
If the counter is of MOD-N, then output frequency is given by
f0 =
fi
f
or, N = i
f0
N
From the given data we have

f i = 256 kHz
f0 = 2 kHz
So MOD number is N =
9.
256 kHz
= 128
2 kHz
(d)
If
Qn = 1 then Qn+1 = 0
If
Qn = 0 then Qn+1 = 1
So, the output Q will toggle between 0 and 1.
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10.
11.
12.
(b)
(b)
(c)
S1 = A B
C 1 = AB
S = (A B) AB = (A B) AB + (A B ) AB
= (AB + AB) (A + B ) + (AB + AB ) (AB)
= AB + AB + AB = A + B
C = (A B) AB
= (AB + AB) AB
= 0
13.
(c)
Let a number N is given to the system
output after 1s compliment = 15 N
output after 2s compliment = 16 15 + N = N + 1
3 such systems are connected in cascade.
so final output = Input + (3)10 = 1010 + 0011
= 1101
14.
(a)
f = A + B + C (AB + AC )
= A B + C (AB + AC )
= A B + C (AB AC )
= A B + C(A + B)(A + C)
= A B + C(A + BC)
= A B + AC = AB + AAC
= AB
A
AB
B
Minimum number of NOR gates required = 3
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10
15.
(b)
The K-map of the given function will be as shown below.
yz
00
01
00
01
wx
11
10
x
11
10
So, F ( w, x, y, z) = (w + y )(w + x)
16.
(a)
Since 4X1 MUX, there must be two select lines i.e. S1(MSB) and S0 respectively.
E is the enable terminal
Substituting
We get,
F ( x, y, z) = E S 1 S 0 I 0 + S 1S0 I1 + S1 S 0 I 2 + S1S0 I 3
E = z , S1 = y , S0 = z, I0 = x, I1 = x, I2 = y, I3 = y
F (x, y, z) = x y z
17.
(c)
The input D is Q0 Q2 Q3 .
Clock
Q3
Q2
Q1
Q0
Hence, the pattern 0001 appears at 6th pulse.

18.
(a)
Since, % accuracy is 0.02 thus the maximum error will be
= maximum output
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(0.02)
(0.02)
= 5
= 1 mV
100
100
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19.
11
(b)
Lets assume that initial state of the counter is 00
CLK Initial state J1 = Q0, K1 = 1 J0 = Q1 , K0 = 1 Next state
Q1 Q0
J1 K1
J0 K0
Q1 Q0
0 0
0 1
1 1
0 1
0 1
1 1
1 1
1 0
1 0
0 1
0 1
0 0
0 0
0 1
1 1
0 1
State diagram of the counter is
00
01
10
Synchronous sequential circuit has 3 states, since there are two flip flops in the circuit it can have 4 states
thus there is only 1 unused state in the above circuit.
20.
(a)
Resistance of LSB = 2n1 2 k
= 25 2 k
= 64 k
smallest quantized output current
=
10
64 k
= 156.25 A
21.
(d)
A
B
C
S
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=
=
=
=
=
(EC)16 (1032)6
(20)10 (32)6
(15)8 (21)6
A+B+C
(1085)10
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12
22.
(c)
Output of counter
D3 D2 D1 D1
0
0
0
0
0
0
0
1
I1
I0
Y2
0
1
1
1
0
0
3
Duty cycle =
100 = 30%
10
23.
(d)
From the conditions given
1.
A(B + C )
2.
3.
A B
C (A + B )
Boolean expression = A(B + C ) + AB + C (A + B )

= AB + AC + AB + AC + CB = B + A + CB
= A+B+C
24.
(a)
Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0
0
511 0
512 1
999 1
Duty cycle of MSB =
999 511
100
1000
= 48.8%
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25.
(d)
Excitation table of J-K flip flop.
Qn
0
0
0
0
1
1
1
1
26.
Qn+1
0
0
1
1
0
0
1
1
J
0
0
1
1
0
1
0
1
K
0
1
0
1
1
1
0
0
(b)
Y = A(B + C ) = A + (B + C ) = A + B C
= A + BC
27.
(b)
(0111111001)2 (0111110100)2 = (101)2 = (5)10
Resolution =
25 mV
5
FSD = resolution (2n 1)

= 5 103 1023 = 5.115 volts
5.12 volts
28.
(a)
A
BC
DE
BC
00
DE 00
BC
01
BC
11
BC
10
1
DE 01
BC
11
BC
10
DE 11
DE 10
A
BC
DE
BC
00
BC
01
DE 00
DE 01
DE 11
DE 10
F = A BE+BDE + A CE
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13
14
29.
(d)
30. (b)
Spatial to temporal conversion can be done by a parallel-IN serial-OUT shift register.
Operation Clock Pulses

Write
0
Read
(n 1)
Total clock pulses = 0 + (n 1)
= (n 1)
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Serial No.

: A_Digital Electronics_240716_EC + EE_ND

CLASS TEST - 2016

CTEC16 | Digital Electronics

After 5 clock pulses QA QB QC will be 011.

Z = ABC + ABC + ABC + ABC

From the figure we get,

From the given data we have

CTEC16 | Digital Electronics

Minimum number of NOR gates required = 3

Hence, the pattern 0001 appears at 6th pulse.

CTEC16 | Digital Electronics

State diagram of the counter is

Boolean expression = A(B + C ) + AB + C (A + B )

Duty cycle of MSB =

CTEC16 | Digital Electronics

FSD = resolution (2n 1)

Operation Clock Pulses

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