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PULSE MODULATION SCHEME.......9-18 2.1 Pulse amplitude modulation 2.2 Pulse width mo
ion 2.3 Pulse position modulation 2.4 Pulse code modulation 2.5 Advantage of PWM
2.6 Single pulse width modulation 2.7 Multiple pulse width modulation 2.8 Sinus
oidal pulse width modulation 2.9 Single phase full bridge voltage source inverte
r 2.10 Unipolar switching scheme 2.11 Performance parameter of inverter
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CIRCUIT DESCRIPTION........................................................19-34
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 IGBT(Insulated gate bipolar transistor) Con
structional feature of an IGBT Operating principle of an IGBT Switching characte
ristic of an IGBT Parameter of an IGBT Comparison with Power MOSFET The design o
f bilevel dc/ac inveter Simulation of single phase bridge inverter Simulation of
single phase bridge inverter using unipolar switching
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ANALYSIS OF MULTILEVEL INVERTER....................35-43 4.1 4.2 4.3 4.4 4.5 Int
roduction Basic principle of operation of cascade multilevel inverter Simulation
of multilevel inverter Merits of multilevel inverter Demerits of multilevel inv
erter
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DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW
PULSE MODULATION SCHEME 2.1 Analog signal, s(t). (b) Pulse-amplitude modulation.
(c) Pulse-width Modulation (d) Pulse position modulation.10 2.2 sine modulated, unm
ted signal .11 2.3 Circuit configuration of a single-phase, full-bridge inverter
orms for unipolar voltage switching scheme.16
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ANALYSIS OF MULTILEVEL INVERTER 4.1 Cascaded five level inverter.37 4.2 simuli
ded multilevel inverter..38 4.3 Simulink model of an inverter block ..39 4.
witching block..39 4.5 output voltage waveform at ma1=0.8 & ma2=0.8.40 4.6
at ma1=0.8 & ma2=0.6.41 4.7 output voltage waveform at ma1=0.8 & ma2=0.4.41
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DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW
CIRCUIT DESCRIPTION 5.1 Harmonic evaluation of single phase inverter when ma1=0.
8 & ma2=0.8...48 5.2 Harmonic evaluation of multilevel inverter when ma
l inverter when ma1=0.8 & ma2=0.649 5.4 Harmonic evaluation of multile
.4 ...49 5.5 Generalized block diagram for active power filter
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DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW
2 Vrms
V12
V1
Where Vrms is the rms value of the output voltage.
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DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW
2 , 3...
(V
n
/ n2 )2
DF
V1
2.12.4 Lowest-order harmonics (LOH)
The lowest harmonic frequency, with a magnitude greater than or equal to three p
ercent of the magnitude of the fundamental component of the output voltage, is c
alled the lowest order harmonic. Higher the frequency of the LOH, lower will be
the distortion in the current waveform.
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DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW
The reverse bias rating of the N- drift region to collector P+ diode is usually
only of tens of volts, so if the circuit application applies a reverse voltage t
o the IGBT, an additional series diode must be used.
The minority carriers injected into the n- drift region take time to enter and e
xit or recombine at turn on and turn off. This results in longer switching time
and hence higher switching loss compared to a power MOSFET.
The on-state forward voltage drop in IGBTs behaves very differently to that in p
ower MOSFETS. The MOSFET voltage drop can be modeled as a resistance, with the v
oltage drop proportional to current. By contrast, IGBT has a diode like voltage
drop (typically of the order of 2V) increasing only with the log of the current.
Additionally, MOSFET resistance is typically lower for smaller blocking voltage
s meaning that the choice between IGBTs and power MOSFETS depend on both the blo
cking voltage and current involved in a particular application, as well as the d
ifferent switching characteristics mentioned above. In general high voltage, hig
h current and low switching
frequencies favor IGBTs while low voltage, low current and high switching freque
ncies are the domain of the MOSFET.
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DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW
The circuit topology provides full utilization of semiconductor devices like GTO
s where voltage stress of each switch is limited to certain lower value than dc
link whereby increased handling power capability of the inverter.
They are suitable for high voltage and high current application. They have highe
r efficiency because the devices can be switched at low frequency.
4.7 Demerits of Multilevel Inverter
The drawbacks are the isolated power supplies required for each one of the stage
s of the multiconverter and its also lot harder to build, more expensive, harder
to control in software.
Switching utilization and efficiency are poor for real t
ransmission. The large number of capacitors are both more expensive and bulky th
an clamping diodes in multilevel diode clamped converters. Packaging is also mor
e difficult in inverters with high number of levels.
51
DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING, INTEGRAL UNIVERSITY, LUCKNOW