CONSTRUCTION OF OPTIMUM COMPOSITE FIELD

ARCHITECTURE FOR COMPACT HIGH-THROUGHPUT AES

S-BOXES
ABSTRACT:
In this work, we derive three novel composite field arithmetic (CFA) Advanced
Encryption Standard (AES) S-boxes of the field GF (((2 2)2)2). The best construction is selected
after a sequence of algorithmic and architectural optimization processes. Furthermore, for each
composite field constructions, there exist eight possible isomorphic mappings. Therefore, after
the exploitation of a new common sub expression elimination algorithm, the isomorphic
mapping that results in the minimal implementation area cost is chosen.

EXISTING SYSTEM:
In Existing System Performs the 8-bit Galois field inversion of the S-box using subfields
of 4 bits and of 2 bits. This work describes a refinement of this approach that minimizes the
circuitry, and hence the chip area, required for the S-box but compare to our proposed system
this values is very high. For applications using larger chips.

EXISTING SYSTEM ALGORITHM:

The S-box function of an input byte a is defined by two sub steps:
1. Inverse: Let c = a1, the multiplicative inverse in GF (28) (except if a =
0 then c = 0).
2. Affine Transformation: Then the output is s = M c b, where M is a
specified 8 8 matrix of bits, b is a specified byte, and the bytes c, b,
s are treated as vectors of bits.

EXISTING SYSTEM DRAWBACKS:

Compare to our proposed system,

The longest critical path

The maximum area of occupancy

Low speed

PROPOSED SYSTEM BLOCK DIAGRAM:

The physical placement of the fine-grained pipelining stages for each our ANF-CFA AES Sboxes are as depicted in Figure. For the purpose of illustration, the GF (2 4) multiplications are
now divided into two pipelined stages; stage 2 and 3, and stage 5 and 6, respectively. Each of the
parallel paths consists of exactly two LEs.
All of the proposed CFA AES S-boxes (Case I, Case II, and Case III) had been implemented in
FPGA Spartan 3 and were synthesized using Xilinx 13.2.

Fig. ANF-CFA AES S-box with seven stages fine-grained pipelining for Case III

PROPOSED SYSTEM TECHNIQUE (ALGORITHM):

There are four major considerations in constructing the CFA combinatorial circuit, namely the
1. Field of mapping
2. Basis representation
3. Field polynomials
4. Isomorphic mapping

PROPOSED SYSTEM ADVANTAGES:

The optimality that we seek for is one with the shortest possible critical path while
preserving the minimum area of occupancy.

We propose a novel architectural optimization scheme to cater the drawback of CFA in

achieving higher speed of implementation.

SOFTWARE REQUIREMENTS:

ModelSim 6.4c
Xilinx 13.2

HARDWARE REQUIREMENTS:

FPGA Spartan 3 (xc3s400 pq208)

REAL TIME EXAMPLE:

Image Encryption
Network security
Satellite communication

FUTURE ENHANCEMENT:
Apart from AES S-box, the methodologies proposed in this work are also applicable for
development of any similar cryptographic circuits that involved finite field arithmetic.
Specifically the ANF representation along with a strategic fine-grained registers insertion is an
effective method to overcome the drawback of complicated CFA architecture. Our future works
will focus on constructing composite field with field polynomials in multi-level representation as
well as the exploitation of direct computation of GF (28) in CFA.