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AbstractIn this paper, a phase shifted semi-bridgeless boost In the two-stage architecture, the PFC stage rectifies the
power factor corrected converter is proposed for plug in input AC voltage and transfers it into a regulated
hybrid electric vehicle battery chargers. The converter features intermediate DC link bus. At the same time, power factor
high efficiency at light loads and low lines, which is critical to correction is achieved [4]. The boost circuit-based PFC
minimize the charger size, charging time and the amount and topology operated in CCM is employed in this study as the
cost of electricity drawn from the utility; the component count, main candidate for front end single-phase solutions for AC-
which reduces the charger cost; and reduced EMI. The DC power factor corrected converters used in PHEV battery
converter is ideally suited for automotive level I residential chargers.
charging applications.
A. Conventional Boost Converter
A detailed converter description and steady state operation
The conventional boost topology shown in Fig.1 uses a
analysis of this converter is presented. Experimental results of
a prototype boost converter, converting universal AC input
dedicated diode bridge to rectify the AC input voltage to DC,
voltage to 400 V DC at 3.4 kW are given and the results are which is then followed by the boost section. In this topology,
compared to an interleaved boost converter to verify the proof the output capacitor ripple current is very high [5] and is the
of concept, and analytical work reported. The results show a difference between diode current and the dc output current.
power factor greater than 0.99 from 750 W to 3.4 kW, THD Furthermore, as the power level increases, the diode bridge
less than 5% from half load to full load and a peak efficiency of losses significantly degrade the efficiency, so dealing with
98.6 % at 240 V input and 1000 W load. the heat dissipation in a limited area becomes problematic.
Due to these constraints, this topology is good for a low to
I. INTRODUCTION medium power range up to approximately 1kW. For power
A plug in hybrid electric vehicle (PHEV) is a hybrid levels >1kW, typically, designers parallel semiconductors in
vehicle with a storage system that can be recharged by order to deliver greater output power. The inductor volume
connecting a plug to an external electric power source. The also becomes a problematic design issue at high power
charging AC outlet inevitably needs an on-board AC-DC because of permeability drops at higher load and heat
charger with power factor correction [1]. An on-board 3.4 associated with core and copper losses.
kW charger could charge a depleted battery pack in PHEVs
to 95% charge in about four hours from a 240 V supply [2].
A variety of circuit topologies and control methods have
been developed for PHEV battery chargers. The two-stage
approach with cascaded PFC AC-DC and DC-DC converters
is the common architecture of choice for PHEV battery
chargers, where the power rating is relatively high, and
lithium-ion batteries are used as the main energy storage
system [3]. The single-stage approach is generally only
suitable for lead acid batteries due to large low frequency
ripple in the output current. Figure 1. Conventional PFC boost topology
I v D T (1)
L L
1 (3)
I D T (4)
L L
The three unique operating interval circuits of the Interval 3 [t2-t3]: At t2, Q1/Q2 are off again, and interval
proposed converter are given in Fig. 9 to Fig. 11 for duty 1 is repeated, as shown in Fig. 9. During this interval, the
cycles smaller than 0.5 during the positive half-cycle. The current in series inductances L1 and L2 increases linearly
waveforms of the proposed converter during these conditions
and stores the energy in these inductors. The ripple currents proposed phase shifted semi-bridgeless boost are 17% lower
in D1 and body diode of Q2 are the same as the ripple than the benchmark conventional boost and 7% lower than
current in series inductances L1 and L2, as shown in the interleaved boost . Since the benchmark converter bridge
equation (1). rectifier losses are large, it is expected that phase shifted
semi-bridgeless boost converter should have the lowest
Interval 4 [t3-t4]: At t3, Q1 is off and Q2 is on, as shown I losses among the topologies investigated. Additionally, it is
Fig. 11. During this interval, the energy stored in L1 and L2 noted that the losses in the input bridge rectifiers are 63% of
is released to the output through L1, D1, Q2 and L2. The total losses in the conventional PFC converter and 71% of
ripple currents in D1 and Q2 are the same as the ripple total losses in the interleaved PFC converter. Therefore,
currents in L1 and L2: eliminating the input bridge in PFC converters is justified
despite that the introduction of new losses.
(6)
V. EXPERIMENTAL RESULTS
The operation of converter during the negative input Prototypes of a phase shifted bridgeless boost converter
voltage half-cycle is similar to the operation of converter and an interleaved boost converter were built to verify the
during the positive input voltage half-cycle. proof-of-concept and analytical work presented in this paper
and to benchmark the proposed converter. The devices used
IV. LOSS EVALUATION in experimental prototypes are provided in Table 1.
The estimated loss distribution of the semiconductors is
provided in Fig. 13 at 70 kHz switching frequency, 240V TABLE I. DEVICES/COMPONENTS USED IN EXPERIMENTAL PROTOTYPES
input and 3300W load for benchmark conventional boost and Components Used in Prototype Unit Head
interleaved boost converters and the proposed phase shifted Topology
Device Part # / Value # of Devices
semi-bridgeless boost converter. The currents in regular
Regular Diode 25ETS08S 2
diodes Da and Db were assumed to be split with the current Semi-bridgeless
PFC converter
Phase Shifted
going through intrinsic body diodes for phase shifted semi- Fast Diode IDB06S60C 2
bridgeless topology. The regular diodes in input bridge
MOSFET IPB60R099CP 2
rectifiers have the largest share of losses among the
topologies with the input bridge rectifier. The phase shifted Inductors 400 H 2
semi-bridgeless topology nearly eliminates this large loss
Regular Diode 25ETS08S 4
component (~30W). However, the tradeoff is that the FET
Interleaved PFC
losses are higher and the intrinsic body diodes of FETs IDB06S60C 2
converter
Fast Diode
conduct, producing new losses (~8W). The fast diodes in the
MOSFET IPB60R099CP 2
conventional and interleaved PFC have slightly lower power
losses, since the boost RMS current is higher in these Inductors 400 H 2
topologies.
60
Pictures of the proposed phase shifted bridgeless boost
47.7W
50
board, a capacitor bank of 820 F and an IMS power board
Interleaved Boost attached to a heatsink with the PFC inductors.
39.4
30.0W
30.0W
30
21.6
10.8W
20
6.9W
6.9W
9.8
5.4W
10
4.1
4.1
0.0W
0.0W
0
Diodes
Intrinsic
Regular
FETs
Losses
Diodes
Diodes
Total
Body
Fast
Semiconductor Losses
Figure 13. Comparison of the estimated loss distribution in the
semiconductors at 70kHz switching frequency, 240V input, 3300W load at
400V
98
0
97
1000
1200
1400
1600
1800
0
200
400
600
800
Interleaved PFC Converter
96 Output Power (W)
Phase Shifted Semi-
95 Figure 18. Loss reduction as a function of output power at Vin = 120V,
Bridgeless PFC Converter
Vo=400V and 70kHz switching frequency
94
From the results, it is noted that proposed semi-bridgeless
0
500
1000
1500
2000
2500
3000
3500
PFC converter achieves a peak efficiency of 98.6% at 1 kW
Output Power (W) output power. Additionally, the light load efficiency of the
Figure 15. Efficiency as a function of output power at Vin = 240V, proposed converter is significantly better than that of the
Vo=400V and 70kHz switching frequency interleaved PFC due to the absence of input bridge rectifier.
However, as the load increases, the efficiency drops due to
70 additional heat dissipation in the intrinsic body diodes of the
60
FETs.
Loss Reduction for PFC
Loss Reduction (%)
25 Vin=120
20 20
10 15
10
0
5
500
1000
1500
2000
2500
3000
3500
0
0
500
1000
1500
2000
2500
3000
3500
0
96
0.98
Power factor
95 0.96
94 0.94
Interleaved PFC Converter
0.92
93 Vin=240
Phase Shifted Semi- 0.9
92 Bridgeless PFC Converter 0.88 Vin=120
91 0.86
0.84
0
200
400
600
800
1000
1200
1400
1600
1800
500
1000
1500
2000
2500
3000
3500
2
EN 61000-3-2 Class D Limits (A) Output Voltage
Amplitude (A)
1.5
Amplitude (A) Vin = 120 V
1
Amplitude (A) Vin = 240 V
0.5
0
Inductor
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Current
Harmonics Order Input Voltage Input Current
Figure 21. Harmonics orders at Vin = 120 V and 240V, compared against
EN61000-3-2 standard.
In order to verify the quality of the input current, the input Figure 23. Inut current, inducotr current, input voltage and output voltage.
Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch3= IL1 10A/div. Ch4= Iin
current THD is shown in Fig.19. The power factor and 10A/div.
harmonic orders are given and compared with EN 61000-3-2
standard in Fig.20 and 21. It is noted that mains current THD
is less than 5% from 50% load to full load and it is compliant
to IEC 6100-3-2 (Fig. 19 and Fig. 21). The converter power Sensed FET Current
factor is shown over entire load range for 120 and 240V
input in Fig. 20. The power factor is greater than 0.99 from
50% load to full load.
Input
Experimental waveforms from the proposed converter Current Inductor
prototype are provided in Fig. 22 through Fig. 26. The input Current
current, input voltage and output voltage are given in Fig. 22.
As it can be seen, the input current is in phase with the input
voltage and has a sinusoidal shape. Additionally, there is a
low frequency ripple on output voltage, which is inversely
proportional to the value of PFC bus output capacitors.
In Fig. 23, the inductor current is provided in addition to
the above mentioned waveforms from Fig. 22. It is noted that
during the positive half-cycle, the inductor current is the Figure 24. Inductor current, input current and sensed FET current.
same as input current. However, during the negative half- Ch1= Sensed IQ1 2V/div. Ch3= IL1 / IDb 10A/div. Ch4= Iin 10A/div
cycle, the input current is partially flowing through slow
diodes, Da and Db.
Inductor Current
Output Voltage
Sensed FET
Current
Gating Signal
Input Voltage Input Current
Figure 25. Gating signal, Inductor and sensed FET current for D < 0.5
Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div
Figure 22. Inut current, input voltage and output voltage.
Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch4= Iin 10A/div. In Fig.24 the inductor current, input current and current
sensed in the FET through a current transformer are given.
The gating signals, sensed FET current and the inductor [2] K. Morrow, D. Karner, and J. Francfort, "Plug-in Hybrid Electric
current are provided for duty cycles less than 0.5, Fig 25, and Vehicle Charging Infrastructure Review," U.S. Departent of Energy -
Vehicle Technologies Program, 2008.
greater than 0.5, Fig. 26. These waveforms match the
[3] Petersen, L.; Andersen, M.; "Two-Stage Power Factor Corrected
theoretical models. Power Supplies: The Low Component-Stress Approach " in Proc.
IEEE Applied Power Electronics Conference and Exposition, APEC.
vol. 2, 2002, pp. 1195 - 1201.
[4] Singh, B.; Singh, B.N.; Chandra, A.; Al-Haddad, K.; Pandey, A.;
Kothari, D.P.; "A Review of Single-Phase Improved Power Quality
AC-DC Converters," IEEE Trans. on Industrial Electronics, vol. 50,
pp. 962 - 981, 2003.
Inductor Current [5] Dehong Xu; Jindong Zhang; Weiyun Chen; Jinjun Lin; Lee, F.C.;
"Evaluation of output filter capacitor current ripples in single phase
PFC converters " in Proc. IEEE Power Conversion Conference, PCC.
Sensed FET Current vol. 3 Osaka, Japan, 2002, pp. 1226 - 1231.
[6] Lu, B.; Brown, R.; Soldano, M.; "Bridgeless PFC implementation
using one cycle control technique," in Proc. IEEE Applied Power
Electronics Conference and Exposition, APEC, vol. 2, 2005, pp. 812 -
817.
[7] Petrea, C.; Lucanu, M.; "Bridgeless Power Factor Correction
Gating Signal Converter Working at High Load Variations," in Proc. International
Symposium on Signals, Circuits and Systems, ISSCS. vol. 2, 2007, pp.
1-4
Figure 26. Gating signal, Inductor and sensed FET current for D > 0.5 [8] U. Moriconi, "A Bridgeless PFC Configuration based on L4981 PFC
Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div Controller ": STMicroelectronics Application Note AN1606, 2002.
[9] J. M. Hancock, "Bridgeless PFC Boosts Low-Line Efficiency,"
Infineon Technologies, 2008.
VI. CONCLUSIONS
[10] Yungtaek Jang; Jovanovic, M.M.; Dillman, D.L.; "Bridgeless PFC
A new high performance phase shifted semi-bridgeless boost rectifier with optimized magnetic utilization," in Proc. IEEE
AC-DC Boost converter topology has been presented in this Applied Power Electronics Conference and Exposition, APEC, 2008,
pp. 1017 1021.
paper for the front-end AC-DC converter in PHEV battery
[11] Yungtaek Jang; Jovanovic, M.M.; "A Bridgeless PFC Boost Rectifier
chargers. The proposed converter features high efficiency at With Optimized Magnetic Utilization," IEEE Trans. on Power
light loads and low lines, which is critical to minimize the Electronics, vol. 24, pp. 85 - 93 2009.
charger size, charging time and the amount and cost of [12] Woo-Young Choi; Jung-Min Kwon; Eung-Ho Kim; Jong-Jae Lee;
electricity drawn from the utility; the component count, Bong-Hwan Kwon; "Bridgeless Boost Rectifier With Low
which reduces the charger cost; and reduced EMI. The Conduction Losses and Reduced Diode Reverse-Recovery Problems,"
converter is ideally suited for automotive level I residential IEEE Trans. on Industrial Electronics, vol. 54, pp. 769 780, April
2007.
charging applications in North America where the typical
supply is limited to 120V and 1.44kVA. [13] Huber, L.; Yungtaek Jang; Jovanovic, M.M.; "Performance
Evaluation of Bridgeless PFC Boost Rectifiers," IEEE Trans. on
An analysis and performance characteristics are presented. Power Electronics, vol. 23, pp. 1381 - 1390 2008.
A breadboard converter circuit has been built to verify the [14] Pengju Kong; Shuo Wang; Lee, F.C.; "Common Mode EMI Noise
proof-of-concept. The theoretical waveforms were compared Suppression for Bridgeless PFC Converters," IEEE Trans. on Power
Electronics, vol. 23, pp. 291 297, January 2008 2008.
with the results taken from prototype unit. Additionally, key
[15] Baur, T.; Reddig, M.; Schlenk, M.; "Line-conducted EMI-behaviour
experimental waveforms were provided and input current of a High Efficient PFC-stage without input rectification," Infineon
harmonics at each harmonic order were compared more Technology Application Note, 2006.
explicitly with the IEC 6100-3-2 standard limits. [16] Frank, W.; Reddig, M.; Schlenk, M.; "New control methods for
rectifier-less PFC-stages," in Proc. EEE International Symposium on
Experimental results demonstrate that the mains current Industrial Electronics. vol. 2, 2005, pp. 489 - 493
THD is smaller than 5% from 50% load to full load and the [17] M. OLoughlin;, "An Interleaved PFC Preregulator for High-Power
converter is compliant with the IEC 6100-3-2 standard. The Converters." vol. Topic 5: Texas Instrument Power Supply Design
converter power factor was also provided for full power Seminar, 2007, pp. 5-1, 5-14.
range at 120 and 240V input. The power factor is greater [18] Yungtaek Jang; Jovanovic, M.M.; "Interleaved Boost Converter With
than 0.99 from 50% load to full load. The proposed Intrinsic Voltage-Doubler Characteristic for Universal-Line PFC
converter achieves a peak efficiency of 98.6 % at 240 V Front End," IEEE Trans. on Power Electronics, vol. 22, pp. 1394
1401, July 2007.
input and 1 kW output power.
[19] Balogh, L.; Redl, R.; "Power-factor correction with interleaved boost
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