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Front-end IC design engineer

Savarti Company Limited

16 Ngo Thoi Nhiem, P7, Quan 3, TP Ho Chi Minh


Work Location:Da Nang,Ho Chi Minh

What you will do


- We are looking for talented RTL design and verification engineers who will work with our team
to develop the PHY and Controller for SPI and DDR interface

- Beside doing RTL design, you will collaborate closely with verification team to make the design
succeeded.

Responsibilities:

Responsibilities will include all, or some, of the following:


- Develop the RTL for the controller of SPI or DDR for PHY and AMS chip
- Create SDC, perform timing analysis and verification at the block and chip level
- Working with verification team to develop the test plan and coverage target for the design
- Working with physical design to implement the design from RTL to GDSII

What are you good at


- BS/MS in Electrical/Electronic Engineering
- 2-5 years of digital ASIC design/verification experience
- Have strong interest and experience in:
o RTL design.
o SDC and timing analysis a plus
o System Verilog, SVA and functional coverage a plus
o Verification methodology such as OVM/UVM/VMM a plus
o EDA tools such as CVS/NC, Design-Compiler, Formality/Conformal
* Experience with the JEDEC standard such as SPI and DDR a plus
* Familiar to the emulation system like Veloce or Zebu
- Good English communications skills, both verbal and writing. Logic thinking, enthusiasm and
a solid work ethic.

Benefits
- 15 months committed salary
- 14+ annual leave for permanent staff
- Medical insurance for employee's family and sponsor 50% for parent
- Annual company trip
- Annual health screening
- Flexible working time
- Open working environment to develop your career path
- Dynamic team

About Our Company

16 Ngo Thoi Nhiem, P7, Quan 3, TP Ho Chi Minh


Company size: 25-99

Our company is founded on March 2015, we focus on the Analog & Mix-Signal IC design
specialized in the high speed interface, Analog Mix-Signal Chip design, layout and RTL to GDSII
for digital portion of Analog Mix-Signal Chip. We also focus to develop the interface IP
(Controller and PHY) for the JEDEC memory standard such as SPI, DDR, eMMC.

Savarti focused on technologies from 65nm and beyond. Our team has an extensive experience
in advance nodes such as 28nm to 16FF.

For further information, please contact Ms.Tuong Minh through:

Email : minhvo@savarti.com

Tel : 0905 488 380

Please email us your CV

MAXIM INTEGRATED PRODUCT l mt trong nhng cng ty vi mch hng u ca M ang c


nhu cu tuyn dng v tr Layout IC.

website: https://www.maximintegrated.com/en.html

Yu cu: c kinh nghim v giao tip ting Anh tt


H s d tuyn vit bng Ting Anh

H s cc bn gi v email: taylor.bui@maximintegrated.com
Maxim ang tm kim nhn s xy dng nhm thit k vi mch ti Vit Nam nn y l c hi
cho cc bn lm v thit k vi mch mc back-end

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