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I. NUMBER SYSTEM
1. GENERALIZATIONS
a. Decimal System
Said to be of the base 10 because it uses 10 digits and the coefficients are
multiplied by powers of 10
Highest digit is 9
b. Binary System
There are only two possible values 0 and 1
Used in digital systems
c. Octal System
With radix of 8
Highest digit is 7
d. Hexadecimal System
Uses 15 characters of numbers (0 9) and letters(A F)
Often used in registers addressing
1 0 1. 01
2 2 = 0 . 2 5
2 1 = 0
20 = 1
21 = 0
22 = 4
5 .2 5
b. Decimal to any base (r)
For the integer part, divide the integer part repeatedly by base (r), then use the
remainder to form the required base (r) number in an up-ordered manner
For the fractional part, multiply the decimal part repeatedly by base (r) until you
find digits less significant, and then use the integer part to form the base (r)
fractional number. To illustrate:
0 .6 8 7 5 b in a r y
c o e ffic ie n t
1
0 .6 8 7 5 x 2 = 1 .3 7 5
0
0 .3 7 5 x 2 = 0 .7 5
0 .7 5 x 2 = 1 .5 1
0 .5 x 2 = 1 .0 1
0 .6 8 7 5 0 .1 0 1 1 2
c. Binary to Octal
group bits by three and convert each group to its equivalent
0 1 0 1 1 0 .1 1 1 0 1 1
2 6 . 7 3
d. Octal to binary
each Octal digit can be represented in its equivalent 3 bits.
e. Binary to Hexadecimal
group bits by four and convert each group to its equivalent hexadecimal
character. To illustrate:
0 0 0 1 0 1 1 0 .1 1 1 0 1 1 0 0
1 6 . E C
f. Hexadecimal to Binary
each hexadecimal character can be represented in its equivalent 4 bits
g. Other Conversion
if there is no direct conversion as shown previously, make a sequence
conversion or practically makes use of the calculator even for the conversions
given previously.
4. COMPLEMENTS
Used in digital systems and computers for simplifying the subtraction
operations and for logical manipulations
Note:
1. The 10s complement of a decimal number can be formed by leaving all the least
significant zeroes unchanged, subtracting the 1 st non-zero least significant digit from
10 and subtracting all other significant digit from 9.
Example:
9s complement 10s complement
2513 7486 7487
a. Duality Principle
Every algebraic expression deducible from the postulates of Boolean Algebra
remains valid if the operators and identity elements are interchanged
If the dual of an algebraic expression is desired we simply interchange OR and
AND operators and replace 1s by 0s and 0s by 1s.
x+0 =x x1 = x
x + x = 1 xx = 0
x+x=x xx = x
x+1=1 x0 = 0
(x) = x (involution)
x +y = y + x (commutative)
x + (y + z) = (x + y) + z (associative)
x (y + z) = xy +xz (distributive)
b. De Morgans Theorem
A B = A B
A B = A +B
Minterms
logical product of all the function variables that may or may not be
complemented
Product Terms
logical product of the function variables but not necessarily all the variables
that may or may not be complemented
Maxterms
sum of all the function variables that may or may not be complemented
Sum terms
sum of the function variables but not necessarily all the variables that may or
may not be complemented
Canonical Forms
Sum of Minterms: f (x,y,z) = xyz + x yz + x y z
Product of Maxterms: f(x,y,z) = (x + y +z)( x y z )
Standard Forms
Sum of Products: f (x,y,z) = xyz + y z + x y
Product of Sums: f (x,y,z) = (x+y)( x y z )
a. Truth Table
A table that describes a logic function by listing all possible combinations of the
inputs and indicating the logical output value
xy
zw 00 01 11 10
00
01
11
10
4 -Variable
1. LOGIC GATES
Block of hardware that produces a logic 1 or logic 0 output signal if input logic
requirements are satisfied
Used in digital and switching circuits
Follows the rule of Boolean Algebra
a. AND Gate
A logic circuit where output is high only when all inputs are high represented by
a dot in Boolean operation
b. OR Gate
Logic circuit whose output is high as long as one of its inputs is high and
represented by plus sign in Boolean operation
c. NOT (Inversion)
A gate with only one input and one output(complement) and is represented by a
prime or a bar in logical operation
d. NAND Gate
Complement of AND
Abbreviation of Not-AND
e. NOR gate
Complement of the OR function and its name is an abbreviation of Not-OR
f. Exclusive OR Gate
Similar to OR but excludes the combination of both inputs equal to 1
h. Buffer
Produces the transfer function but does not produce any particular logic
operation since the binary value of the output is equal to the binary value of the
input.
An isolating device used to prevent a driven circuit from the influence of the
driving circuit
Fan Out
Specifies the number of standard loads that the output of the gate can drive
without impairment of its normal operation
Fan In
Number of standard inputs
Power Dissipation
Power consumed by the gate which must be available from the power supply
Propagation Delay
The average transition delay time for the signal to propagate from input to
output when the signal change in value
Noise Margin
The limit of a noise voltage which may be present without impairing the proper
operation of the circuit.
2. UNIVERSAL GATES
a. Nand Gate
b. NOR Gate
3. LOGIC FAMILIES
Consists of logic gates whose outputs at any time are determined directly from
the present combination of inputs without regard to previous output.
a. Half Adder
Performs addition of 2 binary inputs with two binary outputs including the sum
and the carry
b. Full Adder
A combinational circuit that performs the arithmetic addition of three input bits
(two binary inputs and the previous carry) producing an output that is the sum
digit and a new carry digit
c. Decoder
A combinational logic circuit that recognizes the presence of a specific binary
number or word
Converts binary information from n inputs to a maximum of 2 n unique output
lines
d. Encoder
A digital function that produces a reverse operation from that of a decoder
Generates a number or code in response to an input
e. Multiplexer
Data selector switch
An electronic switch that permits any one of the number of inputs to be chosen
and routed to the output
Main function is to control the routing of data from one place to another
f. Demultiplexer
A combinational circuit that receives information on a single line and transmits
this information on 1 of 2n possible output lines
a. Flip Flops
Are memory elements capable of storing a bit of information
Memory elements present in sequential circuits
Also called bistable multivibrator
An external can trigger the output
It has two outputs that are complement to each other
RS Flip Flop
D Flip Flop
D latch
Eliminate the possibility of race condition
Can be clocked or unclocked
JK Flip Flop
Ideal memory element when it comes to circuit that counts
Also it eliminates the undefined state of the RS flip flop
Can be positive edge triggered or negative edge triggered
x dont care
T Flip Flop
Toggle Flip flop
JK Flip Flop with both inputs tied together
Edge Triggering
Changing the output state of a flip flop on the rising and falling edge of a clock
pulse
Hold Time
Minimum amount of time the input signals must be held constant after the clock
edge has struck
Set-up time
Minimum amount of time the inputs to a flip flop must be present before the
clock edge arrives
Propagation Delay time
Time it takes for the output of a gate or flip flop to change after the inputs have
changed
Level Clocking
Type of triggering in which the output of a F/F responds to the level of the clock
signal
Latch
Simplest type of F/F consisting of 2 cross coupled NAND and NOR latches
c. Registers
Group of memory elements that work together as a unit
Primary purpose is to store a word
Buffer Registers
A register that temporarily stores a word during data processing
Shift Register
A register that can shift the stored bits one position to the left or to the right
Serial Loading
Means storing a word in the shift register by entering 1 bit per clock pulse
Parallel Loading
Loading all bits of a word in parallel during one clock pulse
d. Counters
Register capable of counting the number of clock pulses that has arrived at its
clock input
Controlled Counter
Count pulses only when commanded to do so
Synchronous Counters
A counter in which the clock drives each F/F to eliminate the ripple delay
Ring Counter
A counter producing words with 1 high bit which shifts one position per clock
pulse
UP/DOWN Counter
Bidirectional counter, can count up or down
Presettable Counter
A counter that allows you to preset a number from which the count begins
e. Memories
Where the programs and data are being stored before operations begin
Read/Write Memory
Popularly known as Random Access Memory (RAM)
Uses bipolar or MOS F/Fs for static RAM (SRAM) wherein data will be retained
without the need of refreshing
Uses MOSFETS and capacitors for dynamic RAM (DRAM) whose time interval
to undertake a refresh operation is a bout 2 ms
Volatile memories-data is lost when power is turned off
Bubble Memory
Sandwiches a thin film with magnetic material between two permanent bias
magnets
Logical 1s and 0s are represented by magnetic bubbles in the thin film
TEST YOURSELF 15
Review Questions
Answer a. 10.24
c. 56327
d. 67437
Answer c. 56327
Solution
7s KPL = 6666-1035 +1 = 5632
Answer b. 63
Answer a. 2
Answer d. 100
Note: The succeeding term is binary 1 + previous term of the progression
Answer a. 1
Answer c. A
Answer d. OR gate
Answer a. OR gate
Answer b. 3
Answer d. 1
16. The bubble or small circle on the output of a NAND gate and NOR gate represents;
a. addition
b. subtraction
c. product
d. complementation
Answer d. complementation
17. Current drawn when the number 8 is on the LED display is________.
a. 140 nA
b. 140A
c. 560 mA
d. 5.6 A
Answer a. 140 nA
18. Current displayed for a four-digit liquid crystal display that reads the number 8888 is of the
order of
a. 560 nA
b. 560 A
c. 560 mA
d. 2.6 A
Answer c. 560 mA
c. 8 TTL
d. 10 TTL
Answer a. 2 TTL
Answer a. weight
Answer b. 2 milliseconds
24. Emitter Coupled Logic (ECL) has a very fast switching speed as compared to the rest of logic
families, what is then its typical switching time?
a. 5 sec
b. 5 millisec
c. 5 microsec
d. 5 nanosec
Answer d. 5 nanosec
25. Logic circuits can be sequential or combinational, what is the output of a sequential circuit?
a. present input states
b. past input states
26. For a TTL gate, the recommended and standard fan out is _____.
a. 5
b. 10
c. 15
d. 20
Answer b.10
Answer c. 6
29. When a logic circuit rejects an unwanted signal, this is termed as______.
a. logic levels
b. noise margin
c. power consumption
d. propagation delay
30. In a system with MOS devices, the main bus loading factor is likely to be:
a. resistive
b. current
c. capacitive
d. inductive
Answer c. capacitive
c. multiplexer
d. demultiplexer
Answer c. multiplexer
32. Refers to the ability of a logic circuit to withstand noise superimposed on its input signal
a. low noise immunity
b. high noise immunity
c. noise immunity
d. noise figure
33. CMOS, NMOS and PMOS belong to MOS family, what is (are) their significance?
a. they have lower power dissipation than bipolar devices
b. they are slower than bipolar devices
c. they are most sensitive to electrostatic
d. all of the above
Answer a. Multiplexer
35. It is an undesirable condition which may exist in a system when 2 or more inputs change
simultaneously.
a. race condition
b. contest
c. drive condition
d. noise immunity
36. What is the memory element used in clocked sequential logic circuit?
a. gates
b. Flip-flop
c. Static Ram
d. Read Only Memory
Answer b. Flip-flop
c. relay data
d. makes decision
Answer d. register
39. ______is a device that stay on once triggered and store one or two conditions as a digital
circuit.
a. gate
b. latch
c. integrator
d. differentiator
Answer b. latch
40. A flipflop whose output is the same as its input. This is sometimes used as a delay element.
a. RS flipflop
b. D flipflop
c. T flipflop
d. JK flipflop
Answer b. D flipflop
41. Memory whose contents are lost when electrical power is removed.
a. non volatile
b. volatile
c. dynamic
d. static
Answer b. volatile
b. RAM
c. PROM
d. EPROM
Answer d. EPROM
44. In register index addressing mode the effective address is given by:
a. index register value
b. sum of the index register value and operand
c. the operand
d. difference of the index register value and the operand
45. The Integration Injection Logic has higher density of integration than TTL because it
a. does not require transistors with high current gain
b. uses compact bipolar transistor
c. does nor require isolation diffusion
d. uses dynamic logic instead of static logic
46. Dynamic RAM uses capacitor as its data storage element, while static RAM uses_____.
a. inductor
b. register
c. flip flop
d. magnet
47. An electronic counter in which bistable units are cascaded to form a loop
a. ring counter
b. twisted ring counter
c. bistable counter
d. UP/DOWN counter
48. This type of memory sandwiches a thin film with magnetic material between two permanent
bias magnets
a. bubble memory
b. soap memory
c. magnetic memory
d. RAM
49. A memory circuit has 9 address inputs has how many storage locations?
a. 255
b. 256
c. 512
d. 511
Answer c. 512
Solution
# of address = 2n = 29
= 512