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MC6808
MC6802NS
A1O[ 19 22 ]A12
,//,
.*,.,
~,
~,.<.}:
~~,
,.:~ :1,
,,,..,~$.
,,!, $~:::,,t,.
.,.,.,. , ~$
, ~,~ POWER CONSIDERATIONS
.... ,,.~.$)
:* :.,
~v~,.
,i,.
The average chip-juncti~~%p~rature, TJ, in C can be obtained from:
TJ = TA+ (pD.Q$A) ?~~$ (1)
,Jj:.:~$+
Where: *]~?{i>, .t!i~.
~:~,~$%~ient Temperature, C
~~~~~Package Thermal Resistance, Junction-to-Ambient, OC/W
CONTROL TIMING (VCC=5.O V +5%, VSS=O, TA=TL to TH, unless otherwjw ri~$,j
r ) \?*..L
MC6802
Mcmo2Ns MC6BA02 I MC68B02 \
Characteristics MC6B08
Min Max
~1:.,,,-\\ f. 0.1 1.0
Frequency of Operation >:,..
5
Crystal Frequency .<? t,)
. fXTAL 1.0 4,0 1.0 I1 6.0 1.0 1 8.0 I MHz
T
I 1 1
,,;t..!.,:,
External Oscillator Frequency ,.,, +$9 ,,. 4xfo 0.4 4.0 0.4 I 6.0 I 0.4 8.0 I MHz
I I 1 I
s,,,. >,.
Crystal Oscillator Start Up Time .,\,,\ trc 100 lMI 11001 Ims
*!\*\*.,!.,\.!,.
Processor Controls (HALT, MR, RE, RESET, ~ ~lk,.,wt~,.
200 140 110 ns
Im lW Im ns
I I I I
2 Pulse Width, E Low pWEL 450 500 280 5000 210 5000 n~>,,
?{.
3 Pulse Width, E H)gh PWEH 450 9500 280 9700 220 9700 , A$*.J 8+
R/~, Address
(Non- Muxed)
Read Data
Non-Muxed
,
Write Data
Non- Muxed
,*i: ~
NOTES: ~: ~{ f
1. ~@&~~<Wvels
,.,,,\,, shown are VLSO.4 V, VH z2,4 V, unless otherwise specified.
z,~~$<ufement points shown are 0.8 V and 2.0 V, unless otherwise noted.
**~,$$..\ .
~ji~~~.~lectricals shown for the MCN02 apply to the MCM02NS and MC~08, unless otherwise noted.
4.& sable access time is computed bv: 12+ 3+4 17.
5. If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 ap-
plies. For normal data storage in the on-board RAM, this extended delav does not apply. Programs cannot be executed from on-board
RAM when using A and B parts (M C68A02, MCMA08, MC~B02, MC68B08). On-board RAM can be used for data storage with all parts
6. All electrical and control characteristics are referenced from: TL=OOC minimum and TH = 70C maximum.
..
~ 400
5
u
z
G 300
>
a
d
0 200
100
CL fncludesstrav capacitance
o
0 100 200 300 400 500 600
..::\ . I
FIGURE 6 EXPANd%@:~*OCK DIAGRAM
A15 A14 A13 A12 All AlQ,.+ A~w A8 A7 A6 A5 A4 A3 A2 Al AO
25 24 23 22 2SX 19 18 17 16 15 14 13 12 11 10 9
L i
I
: m36
: =A35
AMEnabe
Ccstandb,
Instruction
Register
I
~ m
VCC= Pin 8
m
Vcc= Pin 35 for MCW02NS
VSS=Pins 1, 21
VSS= P\n 36 for MC~08
26 27 28 29 30 31 32 33
D? D6 D5 D4 D3 D2 DI DO
MPU REGISTERS
A general block diagram of the MCW02 is shown in Figure read/write memory that may have any location (address)
6. As shown, the number and configuration of the registers that is convenient. In those applications that require storage
are the same as for the MCWOO. The 128x 8-bit RAM* has of information in the stack when power is lost, the stack
been added to the basic MPU. The first 32 bytes can be re- must be non-volatile.
tained during power-up and power-down conditions via the
RE signal.
The MC6802NS is identical to the MC6802 except for the
standby feature on the first 32 bytes of RAM, The standby
feature does not exist on the MC6802NS and thus pin 35
must be tied to 5 V.
The MC6808 is identical to the MC6802 except for on-
board RAM. Since the MC6808 does not have on-board
RAM pin 36 must be tied to ground allowing the processor to
utilize up to WK bytes of external memory.
(ALU).
The MPU has three 16-bit registers and three 8-bit
registers available for use by the programmer (Figure 7).
CONDITION CODE REq{$FEF
The condition cq~#:~t~]M~er indicates the results of an
PROGRAM COUNTER
Arithmetic Logic U*#~~&~eration: Negative (N), Zero (Z),
The program counter is a two byte (16-bit) register that
Overflow (V), ,Q#~~y,frorn bit 7 (C), and Half Carry from bit 3
points to the current program address.
(H). These,~i+~+~~~fle Condition Code Register are used as
testable .$d$dit]pns for the conditional branch instructions.
STACK POINTER Bit 4 is.$@~@Y@rupt mask bit (1), The unused bits of the Con-
The stack pointer is a two byte register that contains the diti~p ?&$e Register (b6 and b7) are ones.
address of the next available location in an external push- .+@~ure 8 shows the order of saving the microprocessor
down/pop-up stack. This stack is normally a random access ,$&?~Ju~~Within the stack.
:*\i
:!:.,$!ti,.~$:>.~r.&
i ~.. .-
If programs are not executed from on-board RAM, TAVI applies. If b~-s are to be stored and executed from on-board RAM, TAV2 ap-
plies. For normal data storage in the on-board RAM, this extended dela~does not apply. Programs cannot be executed from on-board RAM
when using A and B parts (M C68A02, MC68A08, MC68B02, ,~d M&68 B08). On-board RAM can be used for data storage with all parts.
UNIT
I lx ] Index Register
15 0
Pc Program Counter
15 0
SP Stack Pointer
7 0
Condition Codes
Register
Overflow
Zero
I
I
1 I
m-9
H b
SP = Stack Pointer
CC = Condition Codes (AI= called the Proce$sor Status Byte!
ACCB = Accumulator B
ACCA = Accumulator A
IX H = I ndex Register, Higher Order B Bits
I XL = Index Register, Lower Order B Bits
PCH = Program Counter, Higher Order 8 Bits
PCL = Program Counter, Lower Order B Bits m-2
m -1
H-
m
m+l
m+2
MPU SIGNAL
., .:;.,.
.iJ.\ .,..:,.>, ..
Proper operation of the MPU requires that certain control , ~~on~ bus available will be at a high state, valid memory ad-
and timing signals be provided to accomplish specific func- .,~+,ws will beat a low state. The address bus will display the
tions and that other signal lines be monitored to determine %~~*LEddress of the next instruction.
,..
the state of the processor. These control and timing signals ,f~,
~ To ensure single instruction operation, transition of the
are similar to those of the MCM~ except that TSC, D&~, HALT line must occur tpcs before the falling edge of E and
~1, 42 input, and two unused pins have been elimin~td~:w the HALT line must go high for one clock cycle.
and the following signal and timing lines have been ~*~Q: HALT should be tied high if mt used. This is good
.~,4,.: +$\.
\
RAM Enable (RE) .>::~,,,.1:, ~ engineering design practice in general and necessary to en-
Crystal Connections EXTAL and XTAL ~::\>$.(.,f:l> sure proper operation of the part.
> qk$~i., *F
Memory Ready (MR) .:+>.~,,>>!.,L,k
,>L~,,,
*;>, \ ,f,$:,
VCC Standby \ +&,? READ/WRITE (R/~)
$+::+,>,..,,.
Enable +2 Output (E) ,t:,f.>!.:l.+.;>~ This TTL-compatible output signals the peripherals and
.,.,
The following is a summary of the?~,P~ signals: memory devices whether the MPU is in a read (high) or write
,~~
:\J
* \?.:t,.,,.
/?.~.~,.ici. (low) state. The normal standby state of this signal is read
ADDRESS BUS (AO-A15) .,, ,~,,:$t
<r..,,,.,, ~ (high). When the processor is halted, it will be in the read
Sixteen pins are used for t%~a~dress bus. The outputs are state. This output is capable of dtiving one standard TTL
capable of driving one >a~~dar&TTL load and 90 pF, These load and 90 pF.
lines do not have thr~~k~t~?capability.
~.
:,.$
.:.!},.. !:\.
,,,, VALID MEMORY ADDRESS (VMA)
DATA BUS (DO@p This output indicates to peripheral devices that there is a
Eight pins,~~ti~d for the data bus. It is bidirectional, valid address on the address bus, In normal operation, this
transferrin~~da~$?{o and from the memory and peripheral signal should be utilized for enabling peripheral interfaces
devicest~~$ {w has three-state output buffers capable of such as the PIA and AC IA. This signal is not three-state. One
drivin~!~~~tandard TTL load and 130 pF. standard TTL load and 90 pF may be directly driven by this
D~~J$~s will be in the output mode when the internal active high signal.
RA~$~s accessed and RE will be high. This prohibits external
data entering the MPU. It should be noted that the internal BUS AVAILABLE (BA) The bus available signal will nor-
RAM is fully decoded from $~ to $W7F. External RAM at mally be in the low state; when activated, it will go to the
$~0 to $W7F must be disabled when internal RAM is ac- high state indicating that the microprocessor has stopped
cessed. and that the address bus is available (but not in a three-state
condition). This will occur if the ~ line is in the low state
HALT or the processor is in the WAIT state as a result of the execu-
When this input is in the low state, all activity in the tion of a WAIT instruction. At such time, all three-state out-
machine will be halted. This input is level sensitive, In the put drivers will go to their off-state and other outputs to their
HALT mode, the machine will stop at the end of an instruc- normally inactive level. The processor is removed from the
WAIT state by the occurrence of a maskable (mask bit I = O) tion of a routine to initialize the processor from its reset con-
or nonmaskable interrupt. This output is capable of driving dition. All the higher order address lines will be forced high.
one standard TTL load and 30 pF. For the restart, the last two ($ FFFE, $FFFF) locations in
memory will be used to load the program that is addressed
INTERRUPT REQUEST (~Q) by the program counter. During the restart routine, the inter-
A low level on this input requests that an interrupt se- rupt mask bit is set and must be reset before the MPU can be
quence be generated within the machine. The processor will interrupted by ~Q. Power-up and reset timing and ~ower-
wait until it completes the current instruction that is being down sequences are shown in Figures 9 and 10, res~~~~:ly.
excuted before it recognizes the request. At that time, if the RESET, when brought low, must be held low~$~~~~~ttiree
interrupt mask bit in the condition code register is not set, clock cycles. This allows adequate time to res~:~:~;t$ternally
the machine will begin an interrupt sequence. The index to the reset. This is independent of the tk~~pb~~?-up reset
register, program counter, accumulators, and condition
code register are stored away on the stack. Next the MPU
will respond to the interrupt request by setting the interrupt high threshold without bouncing{JF@~/~f~$?ng, or otherwise
mask bit high so that no further interrupts may occur. At the causing an erroneous reset (less ?k~:~~three clock cycles).
end of the cycle, a 16-bit vectoring address which is located This may cause improper MPmu~era~lon until the next valid
in memory locations $FFF8 and $FFF9 is loaded which reset.
causes the MPU to branch to an interrupt routine in memory.
The HALT line must be in the high state for interrupts to NON-MASKABLE lNT<KN&T (NMI)
,}.,.,*.;S!,5 *8S
be serviced. Interrupts will be latched internally while HALT A low-going ed~b$:+~~}this input requests that a non-
is low, maskable interr,~~~ se@ence be generated within the pro-
A nominal 3 k~ pullup resistor to VCC should be used for cessor. As .w~~%:i{*@tnterrupt request signal, the processor
wire-OR and optimum control of interrupts. ~Q may be tied will compl~e ?%J#current instruction that is being executed
directly to VCC if not used. before i~~?q~~~~~zes the NM I signal, The interrupt mask bit in
the con~~~on code register has no effect on NMI.
RESET ~Xfi+e,in~~x register, program counter, accumulators, and
This input is used to reset and start the MPU from a ,,,,modwn code registers are stored away on the stack. At the
power-down condition, resulting from a power failure or an ~,en~of the cycle, a 16-bit vectoring address which is located
.\;\).~<s:,
,.,
initial start-up of the processor. When this line is low, the ~.?wmemory
,:.~i,~,
1,,.\%:,, locations $FFFC and $FFFD is loaded causing the
MPU is inactive and the information in the registers will be *{~j;:+MPU to branch to an interrupt service routine in memory.
,.
lost. If a high level is detected on the input, this will sig;al +,
.\.,~ A nominal 3 k~ pullup resistor to VCC should be used for
the MPU to begin the restart sequence. This will start eKwu- wire-OR and optimum control of interrupts. ml may be tied
$~*:$)t:.,>
*!. .....
Vcc
RESET
Option 2
(See Figure 10 for
Power-down Condition)
RE
* .-
Vector
Description
MS LS
$FFFE $FFFF Restart
$FFFC $FFFD Non-Maskable Interrupt
$FFFA $FFFB Software Interrupt
$FFF8 $FFF9 Interrupt Request
1
FIGURE 1
Execute
Interrupt Routine I
,V,
Bb
Execute
Instruction NM I TQ
$FFFC $FFF8
$FFFD $FFF9
a m
FIGURE 12 CRYSTAL SPECIFICATIONS
-.
38 39
n
1 , , I
coutT T Cin
AA
Crystal Loading
.
,
~!
These are representative +$~cut parallel resonance crystal parameters only.
Crystals of other types ~~ cR% may also be used.
and 39 Pin
-.
m MOTOROLA Semiconductor
10
Products
FIGURE14 MEMORY READY SYNCHRONIZATION
r 4xfo
Oscillator
The E clock will resume normal operation at the end of the fi cycle during which MR assertion meets the tpcs setup time, The tpcs setup time
is referenced to transitions of E were it not stretched. If tpcs setup time is not met, E will fail at the second possible transition time after MR is
asserted. There is no direct means of determining when the tpcs references occur, unless the svnchron!zing circuit of Figure 14 is used.
AOC8 B+ M+CB j
Co,.plernen(, 1s COM
COMA . .
COMB 9
Cornplen>erll, 2s NEG . .
Negate) NEGA . .
NEGB *
lee, rdl Adlsl, A DAA . .
Jecre(er, t DEC *
OECA . .
DEC8 *
Excl. s,.e OR EORA . .
EORB .*
,Icre,,,erll INC . .
INCA . .
INCB *
Load Acmltr LOAA .*
LDAB . .
ROLB . .
?ota:e Rtght ROR . .
RORA . .
RORB
. .
Sht7R, ght, LogIc 2 7463 . ., I
A 0-[1311!1 -n .,1
bl bO C I
B 1
2~B753 A P,l . .
STAB 2F753 B M . .
SU8A 2~B043 A P,l A . .
SUEB 2iFOC3 8M. E . .
SBA I ABA *
S8CA 2B243 A !,1 C A . .
L
S6 CB 2F243 8 MCB *
TAB A B . .
TEA B A . .
TST 27063 !A 00 . .
TSTA A-DO .
TSTB B-00 . .
HIP
i
MSP cO.te,~lS .t memo.f IoCat,o<l oo,. !ed to be Slack Po(r>ter, c Carry from b,t 7
R Reset Albvays
Note - Acc,nla!or addressing mode ,Ils!rct,ons aft ,ncl,, ded t,, the COIL,,I)II for IMP LIEO addressing s Set Always
TeSI and stl f lrue, cleared olherw, se
. No! Affected
II ME
o IE(
.
lNOEX EXTNO
I
Ifi LIED
I
POINTER OPERATIONS MNEMONIC OP = OP OP-= OP BOOLEAN/Arithmetic OPERATION H I N Z V C
Compare Index lleg CPX F T 3 9C 4 Y AC62 y <
Decrement Index Reg DEX 09 4
Decrement Stack Pntr OES 34 4
Increment Irldex Reg INx 08 4
Irlcrement Stack Pntr INS 31 4
Load Index Reg LOX CE 3 3 DE 4 2 EE 62 FE 5 3
Load Stack Pntr LoS 8E 3 3 9E 4 2 AE 62 BE 5 3
T
Store Irldex Reg ST X DF 5 2 EF 1 2 FF 6 3
Store Stack Pntr STS 9F 5 2 AF 7 2 BF 6 3
Irldx Reg Stack Pntr TXS 35 4
Stack Prltr . lrldx Rea TSX 30 4
RELATIVE INOEX EXTNO
IMPLIEO T T
T T 10
T
OPERATIONS MNEMONIC OP
H
I
N
z Vc
L 1**
Return From Subroutine 39 1*
MftWre Interrupt 3F See Special Operations 9*
m MOTOROLA Semiconductor
15
Products Inc.
I
+ SP2 ---
SP-1 [n+2] H
SP [.+21 L
H
K = 8-Bit Unsigned Value [.+2] Had[+2]LFormn+2
JMP, JUMP:
.
RTI, RETURN FROM INTERRUPT: ,.j&
Stack
I
Condltlon Code
1
:* 1 I
H
Acmllr B
Acmltr A
Index Reql$Ier(XH)
Index Register
pCH
pCL
.+.?>
. .?..?:*,)* TABLE 6 CONDITION
**1 ,,,. CODE REGISTER MANIPULATION INSTRUCTIONS
$?.,,
,,*,t-*
,,:,,..
,t..i. CO ND. CO OEREG
IMPLIED 5 4 3 2 1 0
1 (Bit Vl Test Result =lOOOOOOOq 7 (Bit N) Test: Sign bat of most significant (MS) bvte = 1?
2 (B!t Cl Test Result #OOOOOOOO~ 8 (Bit V) Test: 2scomplement ouerflow from subtracttonof MS bvtes~
3 (Bit C) Test Decimal ualueof most s[gnlficant BCD Character greater than rl!ne~ 9 (B!t N) Test: Result less than zero7(Blt15=l)
(Not cleared If prevlouslv set )
.-
10 (All) Load Condlt!on Code Register from Stack. (See Special Dperatlonsl
4 (Bit V) Test: Operand =10000 OOOprior toexecut(on? 11 (Bit 1) Set when interrupt occurs. If previously set, a Non Maskable
5 (Bit V) Test: Operand =Olllllll pr!ortoexecut[on? Interrupt IS required to ex!t the wait state
6 (B,t V) Test: Setequalto result of N@ Caftershdt hasoccurred 12 (All) Set accordjng to the contents of Accumulator A.
ABA 20
ADC xc 2 : : :*O
ADD X* 2345. .
AND x 2345, .
ASL ;. .67..
ASR 2 ..67..
BCC **** . 4
BCS **9* 4
BEA 9009 4
BGE ***e* 4
BGT ****e 4
BHI 9 ., 4
BIT X* ; ;45, .
BLE e***@ 4
BLS ee ***o 4
BLT *e *e* 4
BM I *a*** 4
BNE ***** 4
BPL 4
BRA **** 4
BSR e. . . . 8
BVC 9*9** 4
BVS ***** 4
CBA ***** 2*
CLC **** 2.
CLI *9** 2,
CLR 2oe 670 ,.*
CLV Swl *9** 12
CMP TAB **** 2
COM TAP .* *** 2
CPX TBA **** 2
DAA TPA oe** 2
DEC TST 2..67
DES TSX **** :
DEX TSX ***O 4
EOR WAI *9** 9
NOTE
:3,, ::
ADC EOR 1 1 Op Code Address 1 Op cd%> ~. ,
, t/+\.\t\e,\
ADD LDA
2 1 Op Code Address + 1 1 ~~~q~~~ta
AND ORA 2 ,... ..,}
BIT SBC ..~}:,,. ,~\
. .<,.,
CMP SUB ~~
.:.hi
*::?i:>, ~ $
.
$: s*@,.,
CPX 1 1 Op Code Address 1 $%, P Code
LDS
3 2 1 Op Code Address + 1 ,$% Operand Data (High Order BVte)
LDX :~..!$<t \ +).
3 1 Op Code Address + 2 ,.i.,..:~~.~,/t,&
.\,,>\,.1, Operand Data (Low Order Bvte)
DIRECT
ADC EOR 1 1 1 Op Code
ADD LDA
AND ORA 3 2 1 1 Address of Operand
BIT SBC 3 1 1 Operand Data
CMP SUB
CPX 1 1 Op Code
LDS
LDX 4
1 1 Address of Operand
1
.-
1 Operand Data (High Order BVte}
1 1 Operand Data (Low Order Byte)
STA
I Op Code
Destination Address
4
Irrelevant Data (Note 1)
Data from Accumulator
STS Op Code
STX 1,
+ +%$YP
Op Code Address+ 1 1 Address of Operand
?O 1
I
5 Address of Operand Irrelevant Data (Note 1)
1 Address of Operand 0 Register Data (High Order BVte)
,.<,:
.x 1 Address of Operand + 1 0 Register Data (Low Order Byte)
:.?.
:,:.;
INDEXED
JMP 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Offset
3 0 Index Register 1 Irrelevant Data (Note 1)
4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Offset
5 3 0 Index Register 1 Irrelevant Data (Note 1)
L SUFFIX
CERAMIC PACKAGE
CASE 71W5
NOTES
1. POSITIONAL TOLERANCE OF LEAOS (0),
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CO NO ITION, IN
RELATION TO SEATING PLANE ANO
EACH OTHER.
2. DIMENSION LTOCENTEROFLEAOS
WHEN FORMEO PARALLEL. ,-
3. OIMENSION B DOES NOT INCLUOE
MOLD FLASH.
-
Motorola reserves the right to make changes to any products herein to improve reliability, function or design, Motorola does not assume any Iiabilitvarising
out of the application or use of anv product or circuit described herein; neither does it convevanv license under its patent rights nor the rights of others.
S-981,-*,
TABLE 8 OPERATIONS SUMMARY (CONTINUED)
m MOrOROLA Semiconductor
19
Products Inc.
TABLE 8 OPERATIONS SUMMARY (CONTINUED)
Address Mode
and I rsstructions
EXTENDED (Continued)
Cycles
Cycle
#
VMA
Line Address Bus
Rm
Line I Data Bus I
STS 1 1 Op Code Address Op Code
STX
2 1 Op Code Address + 1 Address of Operand (High Order 8yte)
INHERENT
ABA DAA SEC
2
1 T Op Code
ASL DEC SE I
ASR iNC SEV
2 1 OP Code of Next Instruction
T
1 Op Code
PSH 1 Op Code
IINHERENT
Address Mode
and Instructions
.
. ......,
(Continued)
Cycles
Cycle
#
VMA
Line Address Bus
R/~
Line Data Bus
I
1 1*:+* *$$ Vector Address FFFA (Hex) 1 Address of Subroutine (High Order
.>.<+Y,..:
~{.~$?,, BVte)
NOTES:
1. If device which IS addressed during this cycle uses VMA, then the Data Bus will go to the high-impedance three-state condition
Depending on bus capacitance, data from the previous cvcle may be retained on the Data Bus.
2. Data is Ignored by the MPU.
3. For TST, VMA= O and Operand data does not change.
4. MS BVte of Address Bus= MS Byte of Address of BSR instruction and LS Byte of Address Bus= LS Byte of Sub-Routine Address.