Single Bus Processor Architecture Final

Output Input
RD Memory Input / Output EIP
WR (External) (External) LOP
OC2-0
Address Bus Data <pn>
Bus
SPC Address Operand EOR
SSP Selector Register (OR) LOR

A Carry B
EPC In
IPC Program OC7-4
LPC Counter (PC)
<af> ALU Flags
OC7-0 SAL

ESP LR0
R0 R1 .. LRN
DSP Stack Pointer
ISP (SP) Register Array ERO
LSP (RN) ERN
<rn>
OC2-0 <fl>

Instruction
LIR Flag Register
Register (IR)

OC7-0 Selected
Flag FL
EFL
Control Code Generator
SIF

Control Bits to all the Modules

Nomenclature:
EXY / RD : Enables the Output of the module XY/Memory on to the Data Bus;
LXY / WR : Loads the Data Input applied to module XY/Memory at the next Active Clock edge;
IXY / DXY : Increments/Decrements the value stored in module XY;
SPC / SSP :Selects the PC/SP output as the Memory Address (both = 0 selects R0);
SIF : Selects the Instruction Fetch operation, subject to the values of EFL and FL.
SAL : Selects the ALU output as the Data Input to the Register Array;
The ALU has 16 functions (4-bit Select provided by the leading 4 bits of the Op Code):
Unary 8 [Codes 0 7]: Zero, A, A, B, A + 1, A 1, Shift Left & C MSB, Shift Right & C LSB.
Arithmetic 4 [Codes 8 B]: A + B, A B, A + B + C, A B C [Codes 8 B].
Logic 4 [Codes C F]: A AND B, A OR B, A XOR B, (A XOR B).
The ALU generates 4 flags Zero (Z), Carry (C), Sign (S), Parity (P). Flags are not affected by the
Unary Logic functions. Only the C flag is affected by the Left/Right Shift function. All flags are affected
by all other ALU functions.
The FETCH cycle is initiated at the next Active Clock edge if (FL + EFL) SIF = 1.