Communication System Lab Manual

EC2307 Communication System Laboratory,DGCT
SYLLABUS
EC2307 COMMUNICATION SYSTEM LABORATORY
1. Amplitude modulation and Demodulation.

2. Frequency Modulation and Demodulation
3. Pulse Modulation PAM / PWM / PPM
4. Pulse Code Modulation
5. Delta Modulation, Adaptive Delta Modulation.
6. Digital Modulation & Demodulation ASK, PSK, QPSK, FSK (Hardware &
MATLAB)
7. Designing, Assembling and Testing of Pre-Emphasis / De-emphasis Circuits.
8. PLL and Frequency Synthesizer
9. Line Coding
10. Error Control Coding using MATLAB.
11. Sampling & Time Division Multiplexing.
12. Frequency Division Multiplexing,
1
LIST OF EXPERIMENTS
Ex.N Name of the Experiment Pg.No

o
1 Sampling 5
2 Amplitude modulation and Demodulation. 19
3 Frequency Modulation and Demodulation. 29
4 Pulse Modulation [PAM,PWM,PPM] 43
5 Pulse Code Modulation 61
6 Delta Modulation 71
7 Adaptive Delta Modulation 79
8 PLL and Frequency Synthesizer 85
9 Line Coding 97
10 Time Division Multiplexing. 105
11 Frequency Division Multiplexing 115
12 Designing, Assembling and Testing of Pre-Emphasis / De- 121
emphasis Circuits
13 Digital Modulation & Demodulation ASK, PSK, QPSK, 129
FSK using kit
MATLAB PROGRAMS
14 Digital Modulation & Demodulation ASK, PSK, QPSK, 140
FSK using Matlab programs
15 Error Control Coding using MATLAB 149
INDEX
Ex.N Date Experiments Pg.No Marks Signature of
o the Staff
2
Signature of the Staff Marks (Out of / )
BLOCK DIAGRAM:
3
NOTE: Keep All The Switch Faults (Except Switch 1) In Off Position
TABULATION:
S.NO SIGNAL AMPLITUDE TIME
(VOLTS) PERIOD(ms)
1 Modulating Signal
2 Carrier Signal
3 Output Signal
EX. NO.1 SAMPLING
DATE:
4
AIM:
To study different types of signal samplings and its reconstruction
1) Natural Sampling,
2) Sample and Hold,
3) Flat top sampling.
APPARATUS REQUIRED:
S.NO APPARATUS RANGE QUANTITY
1 Sampling Kit 1
2 Connecting Chords
3 Power supply 1
4 20 MHz Dual Trace Oscilloscope 1
THEORY:
The Sample and Hold circuit uses two buffers to keep a voltage level stored
in a capacitor. Ssample will charge the capacitor to the present signal level, while the
input buffer ensures the signal won't be changed by the charging process. From there,
the output buffer will make sure that the voltage level across the storage cap won't
decrease over time. Sclear will short out the storage cap, discharging it and setting the
output to 0V. In actual practice, the switches used are various forms of transistor switch, which
provides cleaner switching and also allows another circuit to control the sample and clearing
operations. Excellent Sample and Hold circuits like the LF398 are available on a single chip for
cheap and easy use.Sample and Hold circuits are used internally in Analog to Digital conversion. We
might also use them to hold a given signal value from any particular sensor on a robot, for analysis
and later use.
MODEL GRAPH:
5
FORMULA USED:
6
1
fS = T
1
fm = T
fS 2 fm
PROCEDURE
1) Natural Sampling And Its Reconstruction
1.Connections are given as per the the Block Diagram (Fig. 1.1) & Carry out the following
connections and switch settings.
2. Connect power supply in proper polarity to the kit DCL-01 & switch it on.
3.Connect the 1 KHz, 5Vpp Sine wave signal, generated on board, to the BUF IN post of the
BUFFER and BUF OUT post of the BUFFER to the IN post of the Natural Sampling block by
means of the Connecting chords provided.
4. Connect the sampling frequency clock in the internal mode INT CLK using
switch (SW4).
5. Using clock selector switch (S1) select 8 KHz sampling frequency.
6 Using switch SW2 select 50% duty cycle.
7 Connect the OUT post of the Natural sampling block to the input IN1 post of the 2nd Order
Low Pass Butterworth Filter and take necessary observation as mentioned below. (Fig. 1.4)
8 Repeat the procedure for the 2KHz sine wave signal as input.
BLOCK DIAGRAM FOR FLAT TOP SAMPLING:

7
TABULATION:
(VOLTS) PERIOD(ms)
1 Modulating Signal
2 Carrier Signal
3 Output Signal
PROCEDURE:
Flat Top Sampling And Its Reconstruction

8
1.Refer to the Block Diagram (Fig. 1.3) & Carry out the following connections
and switch settings.
2 Connect power supply in proper polarity to the kit DCL-01 & switch it on.
3 Connect the 1 KHz, 5Vpp Sine wave signal, generated onboard to the BUF IN post of the
Buffer and the BUF OUT post of the Buffer to the IN post of the Flat Top Sampling block by
4 Connect the sampling frequency clock in the internal mode INT CLK using switch (SW4).
5 Using clock selector switch S1 select 8 KHz sampling frequency.
6 Using switch SW2 select 50% duty cycle.
7 Connect the OUT post of the flat top sampling block to the input IN 1 of the 2nd Order Low
Pass Butterworth Filter and take necessary observation as mentioned below. (Fig. 1.6)
8 Repeat the procedure for the 2 KHz sine wave signal as input.
MODEL GRAPH:
9
10
11
BLOCK DIAGRAM FOR SAMPLE AND HOLD CIRCUIT:
TABULATION:

(VOLTS) PERIOD(ms)
1 Modulating Signal
2 Carrier Signal
3 Output Signal
12
PROCEDURE:
Sample And Hold And Its Reconstruction
1. Refer to the Block Diagram (Fig. 1.2) & Carry out the following connections and switch
settings.
3. Connect the 1 KHz, 5Vpp Sine wave signal, generated onboard, to the BUF IN post of the
BUFFER and the BUF OUT post of the BUFFER to the IN post of the Sample and Hold Block by
4. Connect the sampling frequency clock in the internal mode INT CLK using switch (SW4).
5.Using clock selector switch SW1 select 8 KHz sampling frequency.
6. Using switch SW2 select 50% duty cycle.
7. Connect the OUT post of the Sample and Hold block to the input IN 1 post of the 2nd Order
Low Pass Butterworth Filter and take necessary observation as mentioned below.(Fig. 1.5)
8. Repeat the procedure for the 2KHz sine wave signal as input.
VIVA QUESTIONS:
1.Define Sample and hold circuit?

2.Define sampling.
3.Define Nyquist rate.
4.State application of Sample and hold circuit
5.State Sampling theorem.
13
MODEL GRAPH:
14
15
16
RESULT:
Thus the given input sinusoidal waveform is sampled and the sampling frequency
greater than 2fm is verified and the graph is plotted.
17
AMPLITUDE MODULATION TRANSMITTER:
18
EX. NO.2 AMPLITUDE MODULATION AND DEMODULATION
DATE:
AIM:
To perform the amplitude modulation and demodulation by the given circuit
and draw the graph.
APPARATUS REQUIRED:
1 AM KIT 1
2 Power supply (0-30)V 1
3 CRO (0-30)Mhz 1
THEORY:
Amplitude modulation is the process of changing the amplitude of a relatively high

frequency carrier signal in proportion with the instantaneous value of the modulating signal.Let the
carrier and modulating voltage be ec = Ec sin ct and em = Em sin mt
Where Em is maximum amplitude of modulating signal
Ec is maximum amplitude of carrier signal
m is frequency of modulating signal

c is frequency of carrier signal
The ratio of maximum amplitude of modulating signal to maximum amplitude of carrier

signal is called modulating index. Modulation index, m = Em/Ec , value of Em must be less than
value of Ec to avoid any distortion in the modulated signal.AM demodulation is the reverse
process of AM modulation. It is the process of separating message signal from the modulated
carrier signal.
BLOCK DIAGRAM:
19
TABULATION:
(VOLTS) PERIOD(ms)
1 Message Signal
2 Carrier Signal
3 Envelope Signal
4 Demodulated Signal
FORMULA USED:
Modulation index m = (Em /Ec )* 100

20
m = [(Emax - Emin) / (Emax + Emin)]*100

Bandwidth = 2Fm
PROCEDURE:
1.Refer to the FIG. 1.14 & Carry out the following connections.Connect SINE OUT post of
FUNCTION GENERATOR SECTION (ACL-01) to the i/p of Balance Modulator1 (ACL-01)
SIGNAL IN Post
2. Connect o/p of VCO (ACL-01) RF OUT post to the input of Balance
3. Connect the power supply with proper polarity to the kit ACL-01 & ACL-02 , modulator1
CARRIER IN post (ACL-01). while connecting this; ensure that the power supply is OFF.
4. Switch on the power supply and Carry out the following presetting:
5. FUNCTION GENERATOR: LEVEL about 0.5Vpp; FREQ. about 1 KHz. - VCO: LEVEL
about 1 Vpp; FREQ. about 450 KHz, Switch on 500KHz.- BALANCED 6.MODULATOR1:
CARRIER NULL completely rotated Clockwise or counter clockwise, so as to unbalance the
modulator and to .
7. Connect the oscilloscope to the inputs of the modulator post (SIG and CAR) and detect the
modulating signal and the carrier signal (FIG. 1.16 A/B). Move the probe from post SIG to post
OUT (output of the modulator), where signal modulated in amplitude is detected (FIG. 1.16 C).
Note that the modulated signal envelope corresponds to the wave form of the DSB AM modulating
signal. 8. Vary the amplitude of the modulating signal and check the 3 following conditions:
Modulation percentage lower than the 100% (FIG. 1.16 C), equal to the100% (FIG. 1.16 D),
superior to 100% (over modulation, FIG. 1.16 E).
9. Vary the frequency and amplitude of the modulating signal, and check the . corresponding
variations of the modulated signal.
10. Vary the amplitude of the modulating signal and note that the modulated.
MODEL GRAPH
21
BLOCK DIAGRAM:
PROCEDURE:
1 Refer to the FIG. 2.8 & Carry out the following connections.
22
2 Connect o/p of FUNCTION GENERATOR section (ACL-01) OUT post to the

i/p of Balance Modulator1 (ACL-01) SIGNAL IN post.
3 Connect o/p of VCO (ACL-01) OUT post to the input of Balance modulator 1 (ACL-01)
CARRIER IN post.
4 Connect the power supply with proper polarity to the kit ACL-01 & ACL -02,While connecting
this, ensure that the power supply is OFF.
5 Switch on the power supply and Carry out the following presetting:- FUNCTION
GENERATOR: Sine LEVEL about 0.5 Vpp; FREQ. about 1KHz.- VCO: LEVEL about 2Vpp;
FREQ. about 850 KHz, Switch on 1500KHz.- BALANCED MODULATOR1: CARRIER NULL
completely rotates Clockwise or counter clockwise, so that the modulator is unbalanced and an
AM signal with not suppressed carrier is obtained across the output: adjust OUTLEVEL to obtain
an AM signal across the output whose amplitude is about 100mVpp LOCAL OSCILLATOR
(ACL-02): 1300KHz, 2V.
6 Connect local oscillator OUT post to LO IN of the mixer section.
7 Connect balance modulator1 out to RF IN of mixer section in ACL-02.
8 Connect mixer OUT to IF IN of 1st IF AMPLIFIER in ACL-02.
9 Connect IF OUT1 of 1st IF to IF IN 1 and IF OUT2 of 1st IF to IFIN 2 of 2ND IF
AMPLIFIER.
10 Connect OUT post of 2nd IF amplifier to IN post of envelope detector.
11 Connect post AGC1 to post AGC2 and jumper position as per diagram.
12 Observe the modulated signal envelope, which corresponds to the waveform of the modulating
signal at OUT post of the balanced modulator1 of ACL-01.Connect the oscilloscope to the IN and
OUT post of envelope detector and detect the AM signal and the detected one (FIG. 2E) If the
central frequency of the amplifier and the carrier frequency of the AM signal and local oscillator
frequency coincides, you obtain two signals similar to the ones of FIG.2E.Check that the detected
signal follows the behavior of the AM sign a envelope. Vary the frequency and amplitude of the
modulating signal, and check the corresponding variations of the demodulated signal
23

(VOLTS) PERIOD(ms)
1 Message Signal
2 Carrier Signal
3 Modulated Signal
24
VIVA QUESTIONS:
1.Define Amplitude modulation?

2.What are the types of AM.
3.What is the Bandwidth of AM..
4.State application of AM.
5.What type of modulation used in this circuit..
25
26
RESULT:
Thus the amplitude modulation and demodulation reading was observed and the
graph was plotted.
27
BLOCK DIAGRAM:
TABULATION:

(VOLTS) PERIOD(ms)
1 Message Signal
2 Carrier Signal
3 Modulated Signal
EX. NO.3 FREQUENCY MODULATION AND DEMODULATION
28
DATE:
AIM:
To perform the frequency modulation and demodulation by the given circuit
and draw the graph.
APPARATUS REQUIRED:
1 Frequency modulation kit 1
2 Power Supply 1
3 CRO 0-30MHZ 1
4 Voltmeter 1
5 Frequency meter 1
6 Connecting wires As required
THEORY:
Frequency modulation is defined as change in frequency of carrier signal with

respect to change in amplitude of modulating signal. The maximum frequency deviation is
produced during positive half cycle of the message signal. Similarly minimum deviation is
produced during negative half cycle of message signal. The modulation index is calculated
by difference of maximum and minimum deviation to the message signal frequency.
The instantaneous frequency f of the frequency modulated wave is given by
f= fc (1 + k Em cos m t)
Where
k = proportionality constant
Em cos m t = instantaneous modulating voltage
MODEL GRAPH:
29
30
FORMULA USED:
The modulation index for FM is given by
mf = maximum frequency deviation () / modulating frequency (fm)
Modulation index m = f/fm
1
f = T
PROCEDURE:
The characteristic modulation curve is given by the output frequency of the modulator as function
of the input modulating voltage (FIG. 1.6). It is possible to plot the curve of FIG. 1.6 post by post,
using a potentiometer to statically vary amplitude of the modulating signal, and measuring the
corresponding output frequency of the modulator this is done using following procedure.
1. Connect the power supply with proper polarity to the kit ACL-03. While onnecting this,
ensure that the power supply is OFF.
2. Switch ON the power supply and Carry out the following presetting
3. FREQUENCY MODULATOR: LEVEL about 2Vpp; FREQ. to the minimum; switch on
1500KHz Connect the oscilloscope and frequency meter to the output of the modulator
FM/RF OUT.
4. Connect the voltmeter to the cursor of the frequency regulation potentiometer post V below
SW2.
5. Vary the voltage in steps of 0.5 Volt and fill a table with the voltage values and the
corresponding frequencies.
6. Plot a graph with the measured voltage and frequency values. You obtain a curve similar to
the one of FIG. 1.8.
7. From the analysis of the curve you can note that some segments have not a linear behavior,
while if you consider the whole characteristic you find a high non-linearity.
FM DEMODULATION:
31
PROCEDURE:
32
The demodulation characteristic curve is given by the output voltage of the demodulator as
function of the input instantaneous frequency (FIG. 3.2A). It is possible to plot the curve of FIG.
3.2 a post by post, varying the input frequency to the discriminator and measuring the
corresponding output voltages.
Calibration Of The Demodulator
1. Refer to the FIG. 3.10 & Carry out the following connections.
2. Connect the power supply with proper polarity to the kit ACL-03 & ACL-04, while
connecting this; ensure that the power supply is OFF.
3. Connect the o/p of FREQUENCY MODULATOR FM/RF OUT post to the I/p of Foster-
Seeley Demodulator of ACL-04 FM IN post.
4. Switch ON the power supply and Carry out the following presetting:
FREQUENCY MODULATOR LEVEL about 1 Vpp; switch on 500KHz.
5. Set the frequency demodulator in Foster-Seeley (jumpers in the FS position).
6. Connect the Oscilloscope or frequency-meter to the input of the demodulator FM IN post.
7. Connect the voltmeter (or the DC oscilloscope) to the output of the demodulator (between
post FS OUT and ground).
8. Set the input frequency to 450KHz, and check that the output voltage is 0 volt.
9. In the contrary, adjust the central frequency of the discriminator.
10. Vary the input frequency from 400 to 500KHz, with steps of 5KHz, and report the
frequencies and the corresponding output voltages on a table. The output voltage must vary
from about 100 mV to about +100mV.
11. Fill a graph with the measured values. You obtain a curve similar to the one of
FIG. 3.2.
33
34
35
TABULATION:
(VOLTS) PERIOD(ms)
1 Message Signal
2 Carrier Signal
3 Modulated Signal
36
1 IC XR 2206 1
NE 565
2 Resistor 1
3 Capacitor Each 1
4 Inductor 1
5 CRO 0-30MHZ 1
6 Function generator 0-30MHZ 1
37
38
39
40
PROCEDURE:
1. Connections are given as per the circuit diagram.

2. By switching off the modulating signal m(t), note down the carrier sine wave frequency of
fc at pin 2 of IC 8038.
3. Apply the modulating signal m(t) with suitable amplitude to get undistorted FM signal.
4. Note down maximum and minimum frequency of the carrier in FM signal (i.e., fc max and
fcmin).
5. Find the frequency deviation, modulation index and operation bandwidth.
VIVA QUESTIONS:
1.Define Frequency modulation?

2.What are the types of FM.
3.Define Modulation index.
4.What are the advantages of FM.
5. List the disadvantages of FM..
RESULT:
Thus the frequency modulation and demodulation reading was observed and the
graph was plotted.
41
BLOCK DIAGRAM:
42
EX. NO.4 PULSE AMPLITUDE MODULATION
DATE:
AIM:
To generate pulse amplitude modulated signals and demodulates it to get the
original signal.
APPARATUS REQUIRED:
1 Phase modulation kit 1
2 Power Supply 1
3 CRO 0-30MHZ 1
4 Frequency meter 1
THEORY:
In pulse amplitude modulation, the amplitudes of regularly spaced
rectangular pulses vary with the instantaneous sample values of a continuous message
signal in a one to one fashion. The pulse in PAM can be of rectangular or the type that
we have arrival in natural sampling. The carrier under goes amplitude modulation in
PAM. The width of the pulse remains fixed. Natural sample method is used here to
generate the PAM signal. The diodes are used as a switching element. If the closing
time t of the diode approaches zero, the output gives only the instantaneous value.
Since the width of the pulse approaches zero. The instantaneous sampling gives
train of impulses. The area of each sampled section is equal to the instantaneous
value of the signal input. This signal is modulated with the message signal. Thus we
get the PAM output.
43
TABULATION:

(VOLTS) PERIOD(ms)
1 Message Signal
2 Carrier Signal
3 Modulated Signal
MODEL GRAPH:
44
PROCEDURE:
1.Refer to the block diagram (Fig. 1) and carry out the following connections and switch settings.
2. Connect the Power Supply with proper polarity to the kit DCL-08 and switch it on.
3. Select 16KHz sampling frequency by jumper JP1.
4. Connect the 1KHz, 2Vp-p sine wave signal generated onboard to PAM IN Post.
5. Observe the Pulse Amplitude Modulation output at PAM OUT Post.
6. Short the following posts with the Connecting chords provided as shown in block diagram.
PAM OUT and AMP IN. AMP OUT and FIL IN.
7. Keep the amplifier gain control potentiometer P5 to maximum completely clockwise.
Observe the Pulse Amplitude Demodulated signal at FIL OUT, which is same as the input signal.
9. Repeat the experiment for different input signal and sampling frequencies.
VIVA QUESTIONS:
1.Define PAM?
2.What are the types of PAM.
3.Which type of PAM is widely used.
4.What are the operations involved in PAM.
5. List the disadvantages of PAM..
6.What is the bandwidth of PAM.
45
46
RESULT:
Thus the PAM reading was observed and the graph was plotted.
47
BLOCK DIAGRAM:
48
EX. NO.5 PULSE WIDTH MODULATION
DATE:
AIM:
To generate pulse width modulated signals and demodulates it to get the original
signal.
APPARATUS REQUIRED:
2 Power Supply 1
3 CRO 0-30MHZ 1
4 Frequency meter 1
THEORY:
PULSE WIDTH MODULATION :

This technique of modulation controls the variation of duty cycle of the square wave (With
some fundamental frequency) according to the input modulating signal. Here the amplitude
variation of the modulation signal is reflected in the ON period variation of square wave. Hence, it
is a technique of V to T conversion.
PULSE WIDTH DEMODULATION :
The input signal is Pulse Width Modulated, so the ON time of the signal is changing according to
the modulating signal. In this demodulation technique during the ON time of PWM signal one
counter is enabled. At the end of ON time, counter gives a particular count, which directly
corresponds to the amplitude of input signal. Then this count is fed to a DAC. The output of DAC
corresponds to the amplitude of input signal. Thus train of varying pulse widths gives varying
count values and accordingly DAC give outputs, which is directly proportional to amplitude of
input signal. This is then filtered to get original signal. Thus at the output we get the original
modulating signal extracted from PWM wave.
49
TABULATION:
Amplitude Time Frequency
Message Signal
Carrier signal
PWM signal
Demodulated
Signal
MODEL GRAPH:
50
PROCEDURE:
1.Refer to the block diagram (Fig. 2) and carry out the following connections and switch
settings.
2. Connect the Power Supply with proper polarity to the kit DCL-08 and switch it on. Put
jumper JP3 to 2nd position.
3. Select 1KHZ 1v-pp sine wave signal generated onboard.Connect this signal to PWM/PPM IN.
4.. Observe the Pulse Width Modulated output at PWM OUT post. Note that since the sampling
frequency is high, only blurred band in waveform will be observed due to persistence of vision. In
absence of input signal only square wave of fundamental frequency and fixed on time will be
observed and no width variation are present. To observe the variation in pulse width, apply 1-30Hz
sine wave signal to PWM/PPM IN post. Vary the frequency from 1-30 Hz.
5. Short the following posts with the Connecting chords provided as shown in block diagram for
demodulation section. PWM OUT and BUF IN. BUF OUT and PWM DMOD IN. DMOD OUT
and FIL IN.
8. Observe the Pulse Width Demodulated output at FIL OUT.
9. Repeat the experiment for different input signal and different sampling clocks with the help of
jumper JP3.
VIVA QUESTIONS:
1.Define PWM.
2. What is the disadvantage of uniform quantization over the non-uniform Quantization?
3.Define deviation ratio
4.What is carrier recovery?
5.Define bandwidth efficiency.
51
52
RESULT:
Thus the PWM signal is obtained and the original signal is demodulated from
PWM signal.
53
BLOCK DIAGRAM:
54
55
EX. NO.6 PULSE POSITION MODULATION
DATE:
AIM:
To generate pulse position modulated signals and demodulates it to get the
original signal.
APPARATUS REQUIRED:
2 Power Supply 1
3 CRO 0-30MHZ 1
4 Frequency meter 1
THEORY:
PPM Signal
The position of a constant- width pulse within a prescribed time slot is varied according to
the amplitude of the sample of the sample of the analog signal. The higher the amplitude of the
sample, the farther to the right the pulse is positioned within the prescribed time slot. The highest
amplitude sample produces a pulse to the far right, and the lowest amplitude sample produces a
pulse a far left.
TABULATION:
56
Amplitude Time Frequency
Message Signal
Carrier signal
PWM signal
Demodulated
Signal
MODEL GRAPH:
PROCEDURE:
57
1.Refer to the block diagram (Fig. 3) and carry out the following connections and switch settings.
2. Connect the Power Supply with proper polarity to the kit DCL-08 and switch it on.
3. Put jumper JP3 to 2nd position.
4. Select 1KHZ,1v-pp sine wave signal generated onboard.
5. Connect the selected signal to the PWM/PPM IN.
6.Observe the Pulse Position Modulated output at PPM OUT post with shifted position on time
scale. Please note amplitude and width of pulse are same and there is shift in position which is
proportional to input Analog signal.
7. To observe the variation in pulse positions, apply 1-30Hz sine wave signal to PWM/PPM IN
post vary the frequency from 1-30 Hz and observe the signal on
oscilloscope in dual for posts PPM OUT and PWM OUT simultaneously.
8. Then short the following posts with the link provided as shown in block diagram for
Demodulation section. PPM OUT and BUFIN. BUFOUT and PPM DMOD IN. DMOD OUT and
FIL IN.
9. Observe the Pulse Position Demodulated signal at FIL OUT.
10. Repeat the experiment at different input signal and different sampling
frequencies.
VIVA QUESTIONS:
1.Define PWM.
2. What is the disadvantage of uniform quantization over the non-uniform Quantization?
3.Define deviation ratio
58
59
RESULT:
Thus the PPM signal is obtained and the original signal is demodulated .
60
BLOCK DIAGRAM FOR PCM MODULATION AND DEMODULATION:
61
62
EX. NO.7 PULSE CODE MODULATION
DATE:
AIM:
To generate pulse code modulated signals and demodulates it to get the
original signal.
APPARATUS REQUIRED:
1 PCM KIT 1
2 CRO 0-30Mhz 1
3 Power Supply Each 1

0-30V
THEORY:
Pulse Code modulation come under digital communication technique. In PCM the
message signal is represented by a sequence of coded pulse which accomplished by
representing the signal in discrete form in both time and amplitude.PCM consist of a
receiver and transmitter part. Transmitter section consists of sampler, quantizer,
encoder and parallel to serial converter. Receiver part consists of serial to parallel set
converter. Digital to analog converter and LPF are constituted as receiver part.
Sampling, Quantizing and Encoding operations are performed in the same circuit which
is called as analog to digital converter. The sine waves (analog signal) of frequency
500Hz and 1KHz and DC Signal DC1 and DC2 whose amplitude can be varied
accordingly are generated onboard on DCL-03. These signals are fed to the input of the
Sampling logic CH0 & CH1 and their samples are multiplexed by interleaving them
properly in their assigned time slots.The crystal oscillator generates a clock of 6.4MHz
from which all the transmitter data and timing signals are derived. For fast mode
operation the transmitter clock is 240KHz, and Sampling clock is 16KHz. For slow mode
operation depending on jumper position the transmitter clock is 1.23Hz or 0.6Hz and
sampling clock is 0.088Hz or 0.044Hz i.e. the sampling rate per channel is 11 or 22S
63
TABULATION:
WAVEFORM AMPLITUDE(VOLTS) Time period(ms)
PCM
Modulation
PCM
Demodulation
The multiplexed data is Pulse Code Modulated before transmission. At the receiver after
the Pulse Code Demodulation, the recovered multiplexed data is sent to Demultiplexing
logic. The two demultiplexed samples are fed to reconstruction unit. which consist of 4th
order Low Pass Butterworth Filter, where frequency components are filtered out to
recover the original base band signal at the receiver
PROCEDURE
1.Refer to the Block Diagram (Fig. 1.1) & Carry out the following connections.
2.Connect power supply in proper polarity to the kits DCL-03 and DCL-04 and
64
switch it on. 3.Connect sine wave of frequency 500Hz and 1KHz to the input CH0
and CH1 of the sample and hold logic.
4. Connect OUT 0 to CH0 IN & OUT 1 to CH1 IN.
5. Set the speed selection switch SW1 to FAST mode.
6. Select parity selection switch to NONE mode on both the kit DCL-03 and DCL-
04 as shown in switch setting diagram (Fig. A).
7. Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCL-03 to
the corresponding RXDATA, RXCLK, and RXSYNC of the receiver section
DCL-04.
8. Connect posts DAC OUT to IN post of demultiplexer section on DCL-04.
9. Ensure that FAULT SWITCH SF1 as shown in switch setting diagram (Fig. A)
introduces no fault.
10. Take the observations as mentioned below.
11. Repeat the above experiment with DC Signal at the inputs of the Channel
CH 0 and CH 1.
12. Connect ground points of both the kits with the help of Connecting chord
provided during all the experiments.
OBSERVATION:
Observe the following signal on oscilloscope and plot it on the paper. ON KIT
DCL-03 (Fig. 1.2) & (Fig. 1.3)
1. Input signal CH 0 and CH 1.
2. Sample and Hold output OUT 0 and OUT1
3. Multiplexer clock CLK 1 and CLK 2
4. Multiplexed data MUX OUT. 5. PCM Data TX DATA, TXCLK, TXSYNC
MODEL GRAPH :
PCM MODULATION:
65
66
67
PCM DEMODULATION:
68
69
70
71
VIVA QUESTIONS:
1.Define PCM.
2. What are the advantages of PCM?
3.Write the word size of PCM.
RESULT:
Thus the PCM signal is obtained and the original signal is demodulated and the graph is
plotted
72
BLOCK DIAGRAM:
73
EX. NO:8 DELTA MODULATION AND DEMODULATION
DATE:
AIM:
To determine the input and output waveform using delta modulation and
demodulation.
APPARATUS REQUIRED:
APPARATUS RANGE QUANTITY

S.NO
1 Delta modulation and 1
demodulation kit
2 CRO 1
3 Function generator 1
THEORY:
DELTA MODULATION:
Delta modulation is the differential pulse code modulation scheme in which the difference signal is
encoded into just a single bit. In digital modulation system, the analog signal is sampled and
digitally coded. This code represents the sampled amplitude of the analog signal. The digital
signal is sent to the receiver through any channel in serial form. At the receiver the digital signal is
decoded and filtered to get reconstructed analog signal. Sufficient number of samples are required
to allow the analog signal to be reconstructed accurately. Delta modulation is a process of
converting analog signal into one bit code, means only one bit is sent per sample. This bit indicates
whether the signal is larger or smaller than the previous samples. The advantage of DM is that the
modulator and demodulator circuits are much simpler than those used in traditional PCM. Delta
modulation is an encoding process where the logic levels of the transmitted pulses indicate
whether the decoded output should rise or fall at each pulse. This is a true digital encoding process
as compare to PAM, PWM and PPM. If signal amplitude has increased in DM then modulated
output is a logic level 1. If the signal amplitude has decreased the modulator output is logic level 0.
Thus the output from the modulator is a series of zeroes and ones to indicate rise and fall of the
waveform from the previous value.
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TABULATION:
WAVEFORM AMPLITUDE(VOLTS) Time period(ms)
MODEL GRAPH:
75
The block diagram (Fig. 1.1) of Delta Modulation illustrates the components at the transmitter end.
It consists of Digital Sampler and an Integrator at the feedback path of Digital sampler. Let assume
that the base band signal a(t) and its quantized approximation i(t) are applied as inputs to the
comparator. A comparator as its name suggests simply makes a comparison between inputs. The
comparator has one fixed output c(t) when a(t) > i(t) and the different output when a(t) < i(t) the
comparator output is then latched in to a D-flip/flop which is clocked by the selected transmitter
clock. Thus the output of the D-flip/flop is latched 1 or 0 synchronous with the clock edge. This
binary data stream is transmitted to the receiver and is also fed to the input of integrator. The
integrator output is then connected to the negative terminal of voltage comparator, thus completing
the modulator circuit. The waveform of the Delta Modulator is as shown in the figure 1.5.
The Delta Demodulator

(Fig. 1.2) consists of a D-flip/flop, followed by an integrator and a 2nd and 4th order low pass
butterworth filter. The Delta Demodulator receives the data stream from D-flip/flop of Delta
Modulator. It latches this data at every rising edge of receiver clock. This data stream is then fed to
integrator, its output tries to follow the analog signal in ramp fashion and hence is a good
approximation of the signal itself. The integrator output contains sharp edges, which is smoothened
out by the 2nd order, and 4th order low pass butterworth filter whose cut-off frequency is just
above the audio band. The practical use of Delta Modulation is limited due to following
drawbacks:
i) NOISE: A noise is defined, as any unwanted random waveform accompanying the information
signal. When the signal is received at the receiver irrespective of any channel it is always
accompanied by noise.
ii) DISTORTION: Distortion means that the receiver output is not the true copy of the analog
input signal at the transmitter. In Delta modulation, when the analog signal is greater than the
integrator output the integrator ramps up to meet the analog signal. The ramping rate of integrator
is constant. Therefore if the rate of change of analog input is faster than the ramping rate, the
modulator is unable to catch up with the input signal. This causes a large disparity between the
information signal and its quantised approximation. This error phenomenon is known as Slope
over loading and causes the loss of rapidly changing information. The slope overloading waveform
is as shown in the figure.
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The problem of slope overload can be solved by increasing the ramping rate of the integrator. But
as it can be seen from the figure the effect of the large step size is to add edges at the integrator
output and hence it adds to noise.
iii) Another problem of Delta Modulation is that it is unable to pass DC information.
This is not a serious limitation of the speech communication.
PROCEDURE:
1. Refer to the block diagram (Fig. 1.3) and carry out the following connections.
2. Connect the power supply with the proper polarity to the Kit DCL-07 and switch it ON.
3.Select sine wave input 250Hz of 0V through pot P1 and connect post 250Hz to post IN of input
buffer.
4. Connect output of buffer post OUT to Digital Sampler input post IN1.
5. Then select clock rate of 8 KHz by pressing switch S1 selected clock is indicated by LED
glow.
6. Keep Switch S2 in (Delta) position.
7. Connect output of Digital Sampler post OUT to input post IN of Integrator 1.
8. Connect output of Integrator 1 post OUT to input post IN2 of Digital Sampler.
9. Then observe the Delta modulated output at output of Digital Sampler post OUT and compare it
with the clock rate selected. It is half the frequency of clock rate selected.
10. Observe the integrator output test point. It can be observe that as the clock rate is increased
amplitude of triangular waveform decreases. This is called minimum step size. These waveforms
are as shown in figure 1.4. Then increase the amplitude of 250Hz sine wave upto 0.5V. Signal
approximating 250Hz is available at the integrator output. This signal is obtained by integrating the
digital output resulting from Delta modulation.
11. Then go on increasing the amplitude of selected signal through the respective pot from 0 to 2V.
It can be observed that the digital high makes the integrator output to go upward and digital low
makes the integrator output to go downwards. Observe that the integrator output follow the input
signal. The waveforms are as shown in the figure 1.5. Observe the waveforms at various test-points
in the Delta modulator section.
12.Increase the amplitude of 250Hz sine wave through pot P1 further high and observe that the
integrator output cannot follow the input signal. State the reason.
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13. Repeat the above mention procedures with different signal sources and selecting the different
clock rates and observe the response of Delta Modulator.
14. Connect Delta modulated output post OUT of Digital Sampler to the input of Delta
Demodulator section post IN of Demodulator.
15. Connect output of Demodulator post OUT to the input of Integrator 3 post IN.
16. Connect output of Integrator 3 post OUT to the input of output buffer post IN.
17. Connect output of output buffer post OUT to the input of 2nd order filter post IN.
18. Connect output of 2nd order filter post OUT to the input of 4th order filter post IN.
19. Keep Switch S4 in HIGH position.
20. Then observed various tests points in Delta Demodulator section and observ the reconstructed
signal through 2nd order filter and 4th order filter. Observe the waveforms as shown in figure 1.5.
VIVA QUESTIONS:
1.Define Delta modulation.

2. What are the advantages of delta modulation
3.How to avoid slope overload error.
4.What is Slope overload noise?
5.List the disadvantages of delta modulation.
RESULT:
Thus the input and output waveform are determined at different stages using delta
modulation and demodulation technique.
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81
EX . NO.9 ADAPTIVE DELTA MODULATION AND DEMODULATION
DATE:
AIM:
To determine the input and output waveform using adaptive delta modulation
and demodulation.
APPARATUS REQUIRED:
1 Delta modulation and demodulation 1

kit
2 CRO 1
3 Function generator 1
THEORY:
As seen in earlier system Delta Modulation system is unable to chase the rapidly changing
information of the analog signal, which gives rise to distortion and poor quality reception. The
problem can be overcome by increasing the integrator gain. Adaptive Delta Modulation is a
variation of Delta Modulation, which offers relief from disadvantage of DM by adopting the step
size to accommodate changing signal conditions. If the input signal is large, step is cause to
increase, there by reducing slope overload effects. The block diagram of ADM is as shown in fig
3.1. It is same as Delta Modulation except the variable gain circuit and step size controller. The
controller keeps sensing the slope condition of the message conveyed. If the slope is large the
controller output causes the variable gain circuit to have large gain. If the slope is small, the
controller output causes a small gain. In certain cases Adaptive Delta Modulation do not change
step size on a pulse-to-pulse basis, but changes are made much more slowly, such slow control is
referred to as syllabic. The usual implementation involves a continuously variable slope Delta
(CVSD). There are varieties of ICs for CVSD encoding and decoding in todays semiconductor
market. The CVSD is the simple alternative to more complex conventional conversion techniques
in system requiring digital communication of analog signals.
82
MODEL GRAPH:
83
The comparator output is the difference between the input voltage and the integrator output. That
sign bit is the digital output and also control the direction of ramp in the integrator. The output of
comparator is fed to the sampler. Then the sampler output is fed to the slope polarity switch and
level detect algorithm. The level detect algorithm is again fed to the slope magnitude control
followed by slope polarity switch. The output slope polarity switch is fed to the integrator in the
control loop. With no input at the transmitter a continuous 1 and 0 alternations are transmitted. The
outstanding characteristic is its ability to transmit the intelligible voice out at relatively low data
rate. Companded PCM for telephone quality transmission requires about 64Kbits/sec. data
rate/channel. CVSD produces equal quality at 32Kbit/sec. In CVSD Decoder CVSD mod output is
fed to the input of comparator. The comparator output is fed to the internal shift register. Then the
output of internal shift register is fed to the digital logic followed by slope polarity switch and
integrator. The output of integrator is fed to the low pass filters for the reconstruction of original
signal.
PROCEDURE:
1.Refer to the block diagram (Fig. 3.2) and carry out the following connections.
2. Connect the power supply with the proper polarity to the Kit DCL-07 and switch it ON.
3. Select sine wave input 500Hz of 2V or above through pot P2 and connect post 1KHz to post IN
of input buffer.
4. Connect output of buffer post OUT to Digital Sampler input post IN1.
5. Then select clock rate of 32 KHz by pressing switch S1 selected clock is indicated by LED
glow.
6. Keep Switch S2 in (Delta) position.
7. Connect output of Digital Sampler post OUT to input post IN of Integrator 2.
8. Connect output of Integrator 2 post OUT to input post IN2 of Digital Sampler.
9. Keep Switch S3 in LOW position.
10. Connect Delta modulated output post OUT of Digital Sampler to the input of Delta
Demodulator section post IN of Demodulator.
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11. Connect output of Demodulator post OUT to the input of Integrator 3 post IN.
12. Connect output of Integrator 3 post OUT to the input of output buffer post IN.
13. Connect output of output buffer post OUT to the input of 2nd order filter post IN.
14. Connect output of 2nd order filter post OUT to the input of 4th order filter post IN.
15. Keep Switch S4 in LOW position.
16. Observe the output of filter at post OUT of 4th order filter.
17. Repeat the above mention procedures with different signal sources and selecting the different
clock rates and observe the response of Adaptive delta modulation. Which follows input signal
even if amplitude & frequency of input signal increases. Adaptive delta modulator matches the
slope of the input signal due to low time constant.
VIVA QUESTIONS:
1.How was the SNR of ADM over DM.

2. What are the advantages of ADM.
3.What is the method to avoid the slope overload noise.
4.How was the quantization of ADM occur?
5. What is the method to avoid the granular noise.
RESULT:
Thus the input and output waveform are determined at different stages using adaptive delta
modulation and demodulation technique.
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87
EX. NO.10 PLL AND FREQUENCY SYNTHESIZER
DATE:
AIM:
1.To measure Capture range and Lock in range of PLL 565 .
2. Design and test frequency multiplier using PLL 565.
S.N COMPONENTS RANGE QUANTITY

O
1 DSO (0 - 6)MHz 1
2 PLL 565 1
3 Power supply 15V 1
4 Capacitor 0.001f, 1f 2, 1
5 Resistor 10K 1
6 Function generator (0 - 1)MHz 1
7 Binary Counter 7490 1
8 Bread board 1
9 Connecting wires
THEORY:
The phase look loop, commonly called PLL, is a closed loop feedback system, whose
output frequency and phase are in lock with the frequency and phase of the input signal. The PLL
is an important building blocks of a linear system, which can detect the phases of two signals and
reduce the difference in the presence of a phase difference. The main elements of the PLL are a
phase detector/ comparator, a low- pass filter, an error amplifier and a voltage controlled oscillator
(VCO).
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89
PROCEDURE
1. Refer to the FIG. 3.13 & Carry out the following connections.
2. Connect the o/p of Function Generator (ACL-03) OUT post to the MOD IN (ACL-03) post.
3. Connect the o/p of FREQUENCY MODULATOR FM/RF OUT post to the I/p of RF IN of
mixer in ACL-03.
4. Connect the power supply with proper polarity to the kit ACL-03 & ACL-04, while
5. Switch ON the power supply and Carry out the following presetting:
6. FREQUENCY MODULATOR: Switch on 500KHz; LEVEL about 1 Vpp FREQ. About
450 KHz Function Generator: Sine wave (JP1); LEVEL about 100mVpp; FREQ. about
500Hz. LOCAL OSCILLATOR: LEVEL about 1 Vpp; FREQ. About 1000KHz on
(Center).
7. Connect the LOCAL OSCILLATOR OUT to the LO IN of the MIXER and MIXER OUT
to the LIMITER IN post with the help of shorting links. Then connect the LIMITER OUT
post to the IN of phase locked loop Detector and OUT post to the IN of LOW PASS
FILTER. Then observe frequency modulated signal at FM/RF OUT post of FREQUENCY
MODULATOR and achieve the same signal by setting frequency of LOCAL
OSCILLATOR at OUT post of MIXER, then observe LIMITER OUT post where output
is clear from noise and stabilize around a value of about 1.5Vpp.
8. Connect the oscilloscope across post OUT of PLL DETECT0R ACL-04 (detected signal)
and FUNCTION GENERATOR OUT post (modulating signal) of ACL-03. The incoming
FM signal is taken to one input of the PHASE COMPARATOR CIRCUIT, where its phase
is compared with the square-wave output from the VOLTAGE- CONTROLLED
OSCILLATOR (VCO). If the central frequency of the detector and the carrier frequency of
the FM signal and local oscillator frequency coincide, you obtain two signals. The fact that
there is still some high-frequency ripple at the output of the PLL DETECT0R block, we use
the LOW PASS FILTER block to overcome this problem. The LOW - PASS FILTER block
strongly attenuates the high-frequency ripple component at the detectors output, and also
blocks the d.c. offset voltage. Consequently, the signal at the output of the LOW - PASS
FILTER block should very closely resemble the original audio modulating signal. Note
that the demodulated signal has null continuous component.
CIRCUIT DIAGRAM:
90
APPARATUS REQUIRED:
91
S.N COMPONENTS RANGE QUANTITY

O
1 DSO (0 - 6)MHz 1
2 PLL 565 1
3 Power supply 15V 1
4 Capacitor 0.001f, 1f 2, 1
5 Resistor 10K 1
6 Function generator (0 - 1)MHz 1
7 Binary Counter 7490 1
8 Bread board 1
9 Connecting wires
DESIGN (FM)
Let f0 = 5 fm and fm = 1.5 to 2.2 KHz
Center frequency of fin = (1.5 + 2.2)/ 2 = 1.85 KHz
Therefore f0 = 5 * 1.85 = 9.25 KHz
Where f0 = 0.25 / Rt Ct
Choose Ct = 0.05f, Rt = 5.6K
EXPERIMENTAL CALCULATION
LOCK IN RANGE:
= (f2 f4)
CAPTURE RANGE:
= (f3 f1)
THEORITICAL CALCULATION
LOCK IN RANGE (fl)
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TABULATION
fin (KHz) fout (KHz)
PROCEDURE
fL = 8f0/ V
V= Vcc (-Vcc) = 7.13 + 7.13 = 14.36 V
93
f0 = designed free running frequency = 25 KHz
fL = 8*25K / 14.26 = 14.02KHz

fL = 28.06 KHz
CAPTURE RANGE
fC = [fL / 2 *3.6 * 103 *C2]1/2

= [14.03K / 2 *3.6 * 103 *1]1/2
= 787 Hz
fC = 1.574 KHz
PLL
Free running frequency of PLL f0 = 25 KHz
f0 = 0.25 / Rt Ct
Choose Ct = 0.001f
Rt = 0.25/ 25* 103 * 0.001 *10-6 = 10 K
PLL:
1. Rig up PLL circuit as shown in circuit diagram with designed value of Rt and Ct.
2. A capacitor C1= 0.001f is connected between pins 7 and 8 to eliminate possible
oscillations. The filter capacitor C2 = 1f is large enough to stabilize VCO frequency.
3. Connect DSO probe to pin 4 to measure free frequency of VCO.
4. Set the voltage sensitivity and time base on DSO suitably
MODEL GRAPH:
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95
5. Further continue to increase input signal frequency, fill PLL tracks input signal, up to a
frequency f3. This frequency f2 gives upper end of lock in range. If input frequency is
6. increased further PLL will get unlocked. Note down f2. Measure demodulated output
voltage at pin7
7. Now gradually decrease input frequency till PLL is again locked. This frequency f3 is
upper end of capture range. Note down f3. Measure demodulated output voltage at pin7
8. Further decrease input signal frequency until PLL is unlocked. This frequency f4 lower end
of lock in range. Note down f4. Measure demodulated output voltage at pin7.
VIVA QUESTIONS:
1.Name the block present in PLL?

2. What are the application of PLL?
3.Define Locking Range?
4.Define PLL.
5. Define Capture range?
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97
RESULT:
Thus the PLL and Frequency synthesizer output waveform are verified using given circuit
diagram.
98
BLOCK DIAGRAM:
99
EX. NO.11 LINE CODING
DATE:
AIM:
To obtain the standard digital codes from the source coded signals using various
techniques.
APPARATUS REQUIRED:
APPARATUS RANGE QUANTITY

S.NO
1 Trainer kit
2 CRO
3 Patch card
THEORY:
In digital systems, the electrical waveforms are coded representations of the
original information. If the original information is an analog signal, this must be
converted to a series of discrete values that can be transmitted digitally. The process of
converting the original information into a data sequence is referred to as source coding.The line
coding is the process of converting source coded signals into standard digital codes for the
purpose of transmission over the channel. There are many possible ways of assigning the
waveforms into the digital data. Simplest form of coding is ON- OFF, where a 1 is
transmitted by a pulse and a 0 is transmitted by no pulse. Generally the line coding is used in
transmitter section while decoding in receiver section. The line decoding is the process of
converting standard digital codes into source coded waveforms.
Various line coding formats are
1. Unipolar RZ
2. Polar RZ
3. Polar NRZ
4. Bipolar NRZ
5. Bipolar RZ
100
TABULATION:
WAVEFORM AMPLITUDE(VOLTS) TIME(ms)
6. Manchester coding
Line coding is one of the method of Digital to Digital Conversion. It performs coding &
Decoding which uses the combinational circuits.The sent data needs to be somehow coded into an
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electromagnetic signal to be sent over the wire, and later decoded back. There are many ways of
encoding signals, with each scheme having some pros and cons.Primarily, there are three major
categories of line coding: Unipolar, Polar, and Bipolar.
UNIPOLAR
The most primitive encoding technique is Unipolar. The signal is basically this: high voltage on a
1 bit, and low (zero) voltage on a 0 bit. There is no synchronization information, and the signal
has a DC component.
POLAR
There are three categories of Polar line coding: NRZ, RZ, and Biphase.
NRZ
NRZ is Nonreturn to Zero. This basically means that after each bit is transmitted, the signal doesnt
return to zero voltage. There are two major categories of NRZ, the NRZ-L, and NRZ-I. The NRZ-
L is similar to Unipolar, in that the voltage directly depends on the bit it represents. A positive
voltage generally represents a 1, and a negative voltage represents a 0 (or vice versa). Unlike
the unipolar scheme, NRZ-L alleviates the problem of the DC component. The NRZ-I does a
voltage transition (positive to negative, or negative to positive) on a 1 bit, and no change on a 0
bit. It is the change in the voltage that matters, not the actual voltage itself. NRZ-I is better than
NRZ-L because the destination can use the voltage change to synchronize its clock with the sender
assuming messages dont have long sequences of 0 bits (which dont have a transition).
RZ:A pretty simple scheme. Positive voltage indicates a 1, negative voltage indicates a 0. The
voltage goes down to zero in the middle of every tick.
BIPHASE:There are two primary Biphase coding schemes: Manchester (Ethernet LANs), and
Differential Manchester (Token Ring LANs).Manchester, like RZ has a transition in the middle of
a bit interval. There is a transition for every bit. A low to high transition indicates a 1 bit, and a
high to low transition indicates a 0 bit. Differential Manchester is somewhat similar to NRZ-I. In
the beginning of a bit interval, there is a voltage change on a 0 bit, and no voltage switch on a 1
bit. There is always a voltage change in the middle of a bit interval.
BIPOLARBipolar scheme is similar to RZ (also has 3 voltage levels). It uses zero voltage to
represent a 0 bit, and a 1 bit is represented by either a positive or negative voltage (alternating).
MODEL GRAPH :
102
PROCEDURE:
NRZ:
1.Refer to the block diagram and carry out the following connections and switch settings.
2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch it on.
3. Connect CLOCK and DATA generated on DCL-05 to CODING CLOCK IN and DATA
INPUT respectively by means of the patch-chords provided.
4. Connect the coded data BIO-L on DCL-05 to the corresponding DATA INPUT BIO-L of the
decoding logic on DCL-06.
5. Keep the switch SW2 for BIO-L to ON position for decoding logic as shown in the block
diagram.
6. Connect the coded data URZ on DCL-05 to the corresponding DATA INPUT
URZ of the decoding logic on DCL-06. 7
7. Keep the switch SW2 for URZ to ON position for decoding logic as shown in
the block diagram.
8.Observe the coded and decoded signal on the oscilloscope.
9.Connect the coded data BIO-M on DCL-05 to the corresponding DATA INPUT BIO-M of the
10. Keep the switch SW2 for BIO-M to ON position for decoding logic as shown in the block
diagram.
11. Observe the coded and decoded signal on the oscilloscope.
12. Connect the coded data BIO-S on DCL-05 to the corresponding DATA INPUT BIO-S of the
13. Keep the switch SW2 for BIO-S to ON position for decoding logic as shown in the block
diagram.
14. Observe the coded and decoded signal on the oscilloscope.
15. Use RESET switch for clear data observation if necessary.
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VIVA QUESTIONS:
1.Define Line coding?

2. What are the types of Line coding?.
3.List the Properties of Line coding?.
4.Give the spectrum of line coding?
5.What is NRZ line coding?
RESULT:
Thus the various line encoding and decoding techniques were studied and the
corresponding waveforms were drawn by using VCT-37 trainer kit.
105
BLOCK DIAGRAM FOR TDM MODULATION AND DEMODULATION:
106
EX. NO.12 TIME DIVISION MULTIPLEXING
DATE:
AIM:
To obtain ime division multiplexed signal from different channel and make it to
transmit in a single channel.
APPARATUS REQUIRED:
1 TDM kit
2 CRO
3 Patch
card
THEORY:
Time Division multiplexing is a digital process that can be applied when the data rate capacity of the
transmission medium is greater than the data rate required by the sending and receiving devices. In
such a case, multiple transmission can occupy a single link by subdividing them and interleaving the
portions. TDM can be implemented in two ways. Synchronous TDM and Asynchronous TDM. In
107
synchronous, the multiplexer allocates exactly the same time slot to each device at all times whether
or not a device has anything to transmit
MODEL GRAPH:
TRANSMITTER SECTION:
108
PROCEDURE:
1.Refer to the Block Diagram (Fig. 1) & Carry out the following connections and switch settings.
109
3. Connect 250Hz, 500Hz, 1KHz, and 2KHz sine wave signals from the Function Generator to the
multiplexer inputs channel CH0, CH1, CH2, CH3 by means of the connecting chords provided.
4. Connect the multiplexer output TXD of the transmitter section to the demultiplexer input RXD of
the receiver section.
5. Connect the output of the receiver section CH0, CH1, CH2, CH3 to the IN0, IN1, IN2, IN3 of the
filter section.
6. Connect the sampling clock TX CLK and Channel Identification Clock TXSYNC of the
transmitter section to the corresponding RX CLK and RX SYNC of the receiver section respectively.
7. Set the amplitude of the input sine wave as desired.
8. Take observations as mentioned below.
OBSERVATIONS:
Observe the following waveforms on oscilloscope and plot it on the paper.

a. Input Channel CH0, CH1, CH2, CH3.
b. Channel Selection Signal.
c. TX CLK and RX CLK.
d. Channel Identification Signal TX SYNC And RX SYNC.
e. Multiplexer Output TXD.
f. Demultiplexer Input RXD.
g. Demultiplexer output CH0, CH1, CH2, CH3.
h. Reconstructed signal OUT 0,OUT 1,OUT 2,OUT 3.
RECEIVER SECTION
110
111
112
113
114
TABULATION:
WAVEFORM AMPLITUDE(VOLT TIME(ms)
S)
115
VIVA QUESTIONS:
1.Define TDM technique?

2. What is the need for multiplexing.
3.What are the types of multiplexing.
4.List the merits and demerits of TDM?
5.Give some application of TDM?
RESULT:
Thus the TDM signal is obtained and the original signal is demodulated from
TDM signal.
116
CIRCUIT DIAGRAM:
TABULATION:
WAVEFORM AMPLITUDE(VOLTS) TIME(ms)
117
EX. NO.13 FREQUENCY DIVISION MULTIPLEXING
DATE:
AIM:
To obtain frequency division multiplexed signal from different channel and make it
to transmit in a single channel.
APPARATUS REQUIRED:
2 CRO
3 Patch
card
THEORY:
An important signal processing us multiplexing whereby a number of independent signals can be

contained into a composite signal suitable for transmission over a common channel.In this method of
multiplexing each message of maximum frequency function is translated to different frequency
spectrum by the use of the carrier.These messages are combined in the adder circuit.At the receiving
end a broad band receiver receives this signal and passes it onto base band receiver which receives
signals corresponding to the respective baseband frequency.
118
MODEL GRAPH:
119
PROCEDURE:
1. The circuit connections are made as per the circuit diagram
2. A power supply of 15 V is given to the circuit.
3. Two input signals of different frequencies are given to the circuit.
4. Now note down the amplitude and time period of the input signals.
5. The fdm o/p is observed from the pin no. 6.
6. Now note down the amplitude and time period for the fdm o/p.
7. Plot the graph.

VIVA QUESTIONS:
1.Define FDM?
2. List the component used in FDM?
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121
RESULT:
Thus the FDM signal is obtained and the original signal is demodulated from
FDM signal.
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123
EX. NO.14 PRE-EMPHASIS AND DE-EMPHASIS CIRCUIT
DATE:
AIM:
Study of Pre-emphasis and its responses.
APPARATUS REQUIRED:
1 Pre- emphasis and De-emphasis kit 1
2 Function generator 0 1MHz 1
3 DSO 1
4 Power Supply 1
5 Connecting wires
THEORY:
PRE-EMPHASIS
The circuits are the transmitting side of the frequency modulator. It is used to increase the gain of the
higher frequency component as the input signal frequency increased, the impendence of the collector
voltage increase. If the signal frequency is lesser then the impendence decrease which increase the
collector current and hence decrease the voltage.
With FM, there is a non uniform distribution of noise. Noise at the higher- modulating- signal
frequencies is inherently greater in amplitude than noise at the lower frequencies. This includes both
single- frequency interference and thermal noise. Therefore for information signals with uniform
signals level, a non uniform signal to noise ratio is produced, and the higher- modulating- signal
frequencies have a lower signal- to noise ratio than the lower frequencies. To compensate for this,
the high- frequency modulating signals are emphasized or boosted in amplitude in the transmitter prior
to performing modulation.
124
MODEL GRAPH:
TABULATION:

S)
125
DESIGN FORMULA
fc = (assume:R = 10 K, C = 0.01f)
R = 2 pfcL; L=
PROCEDURE:
The characteristic of pre-emphasis circuit is given by output voltage of the pre-emphasis circuit as the
function of instantaneous input frequency. It is possible to plot the curve of fig. By varying the input
frequency and measuring the corresponding output voltage.
1. Make the connections as shown in the block diagram Fig.2.1.

2. Connect the power supply with proper polarity to the kit ACL-03 while connecting this; ensure
that the power supply is OFF.
3. Connect the output of function generator to the IN of pre-emphasis circuit.
4. Switch on the power supply and carry out the following presetting.
5. FUNCTION GENERATOR: Frequency about 1KHz and level of 100mV p-p sine wave
6. Now vary the frequency in steps of 500Hz and note down the output voltage at the OUT post
of pre-emphasis circuit.
7. Plot the graph of output voltage v/s input frequency on graph paper. The response should come
as shown in the theory above.
8. From the response you can easily understand that using the pre-emphasis Circuit we can
increase the amplitude of modulating signal at higher frequencies thus improving the Signal to
Noise ratio at higher frequencies.
DE-EMPHASIS
The circuit is placed at the receiving side. It acts as allow pass filter. The boosting gain for
higher frequency signal in the transmitting side is done by the pre-emphasis circuit is filtered to
the same value by the low pass filter. De-emphasis is the reciprocal of pre-emphasis. A de-
emphasis network restores the original amplitude- versus- frequency characteristics to the
information signal. The high- frequency signals are propagated through the system at an
elevated level, demodulated and then restored to their original amplitude proportions.
126
The cut off frequency is given by the formula

fc = 1/(2p RC)
127
(4-1) Where
R= 2 p fc L
PROCEDURE:
The characteristic of de-emphasis circuit is given by output voltage of the deemphasize circuit as the
function of instantaneous input frequency. It is possible to plot the curve of fig. By varying the input
frequency and measuring the corresponding output voltage.
1. Make the connections as shown in the block diagram Fig.4.1.

2. Connect the power supply with proper polarity to the kit ACL-04 while
3. Connect the output of function generator(ACL-03) to the IN of de-emphasis circuit(ACL-04).
4. Switch on the power supply and carry out the following presetting. FUNCTION
GENERATOR: Frequency about 1KHz and level of 100mV p-p sine wave
5. Now vary the frequency in steps of 500Hz and note down the output voltage
at the OUT post of de-emphasis circuit.
6. Plot the graph of input frequency v/s output voltage on graph paper. The response should come
as shown in theory.
VIVA QUESTIONS:
1.Define Pre-emphasis?
2. List the advantages of Pre-emphasis?
3.Define De-emphasis?
4. List the advantages of De-emphasis?
5.Define Improvement factor.
7.
128
129
RESULT:
Thus the design of pre-emphasis and de-emphasis circuit is implemented and the frequency
response is drawn.
130
BLOCK DIAGRAM:
131
EX. NO.15 DIGITAL MODULATION AND DEMODULATION
DATE:
AIM:
To obtain the modulated and demodulated output waveform for ASK,PSK,FSK and QPSK.
APPARATUS REQUIRED:
1 Digital modulation kit
2 CRO
3 Patch card
THEORY:
ASK or ON-OFF key is the simplest digital modulation technique. In this method
there is only one unit energy carrier it is switched ON/OFF depending upon the input
binary sequence to transmit symbol 0 & 1. No pulse is transmitted output contains some
complete no of cycle of carrier frequency.The disadvantage of ASK is the modulated
carrier signal is not continuously transmitted. The peak power requirement is also
high. The bit error probability rate is also not required in this technique.
132
TABULATION:
S)
133
ASK TRANSMITTER:
The input binary symbols are represented in polar form with symbols 1 & 0 represented by
constant amplitude levels Eb & -Eb. This binary wave is multiplied by a sinusoidal carrier in
a product modulator. The result is a ASK signal.
ASK RECEIVER:
The received ASK signal is applied to a correlator which is also supplied with a locally
generated reference signal 1 (t). The correlated o/p is compared with a threshold of zero volts.
If x1> 0, the receiver decides in favour of symbol 1. If x1< 0, it decides in favour of symbol 0
PROCEDURE
2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch it
on.
3. Connect CLOCK and DATA generated on DCL-05 to CODING CLOCK IN and
DATA INPUT respectively by means of the patch-chords provided.
4. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator
logic.
5.Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2 of the
Carrier Modulator Logic.
6. Connect ASK modulated signal MODULATOR OUTPUT on DCL-05 to the
ASK IN of the ASK DEMODULATOR on DCL-06 Observe various waveforms
VIVA QUESTIONS:
1. .Define ASK?
2. .Define OOK.
3. Define information capacity
4. .What is the Baud rate for ASK?
5. .What is Digital Transmission?

MODELGRAPH:
BLOCK DIAGRAM OF PHASE SHIFT KEYING:
THEORY:
In Frequency Shift Keying modulation techniques, the modulated output shifts between two
frequencies for all `one (mark) to `zero (space) transitions. The carrier frequency chosen for
FSK modulation are 500KHz and 1MHz. Note that the above frequencies are greater than twice
the modulating frequency. Note that the FSK may be thought of as an FM system in which the
carrier frequency is midway between the mark and space frequencies, and modulation is by a
square wave. CARRIER GENERATOR block on DCL-05 generates the carrier waves 500KHz
and 1 MHz, which are available at SIN1 and SIN2 post. The FSK modulator is also built
around the 2 to 1 Analog Multiplexer which switches between the 500KHz and 1MHz signals
for all one to `zero transitions.
PROCEDURE:
4. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator logic.
5. Connect carrier component SIN 1 to INPUT2 and SIN 2 to INPUT1 of the Carrier
Modulator Logic.
6. Connect FSK modulated signal MODULATOR OUTPUT on DCL-05 to the FSK IN of the
FSK DEMODULATOR on DCL-06.
VIVA QUESTIONS:
1.Explain Coherent detection
2.Difference between PSK and FSK
3.Advantages of PSK
4. What is maximum likelihood detector?
5.What is correlator?
MODEL GRAPH:
THEORY:
PSK is a digital modulation scheme which is analogues to phase modulation. In

binary phase shift keying two output phases are possible for a single carrier frequency
one out of phase represent logic 1 and logic 0. As the input digital binary signal change
o
state the phase of output carrier shift two angles that are 180 out of phase.In a PSK
modulator the carrier input signal is multiplied by the digital data. The input carrier is
multiplied by either a positives or negatives consequently the output signal is either
+1sinwct or -1sinwct. The first represent a signal that is phase with the reference
oscillator the latter a signal that is 180o out of phase with the reference oscillator. Each
time a change in input logic condition will change the output phase consequently for
PSK the output rate of change equal to the input rate range and widest output
bandwidth occurs when the input binary data are alternating 1/0 sequence. The
fundamental frequency of an alternate 1/0 bit sequence is equal to one half of the bit rate.
PROCEDURE
1. Refer to the block diagram and carry out the following connections and switch settings.
4. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator logic.
5. Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of the Carrier
Modulator Logic.
6. Connect PSK modulated signal MODULATOR OUTPUT on DCL-05 to the PSK IN of
the PSK DEMODULATOR on DCL-06. Observe various waveforms as mentioned below.
MODEL GRAPH:
VIVA QUESTIONS:
1.What are the Different types of Digital modulation?

2.Define PSK,QPSK.
3.Advantage of PSK over ASK&FSK?
4.What is base band signal receiver?
5.Define h-factor in FSK
RESULT:
Thus modulated output waveform is obtained and it is justified with
theoretical calculation.
PROGRAM
clc;
clear all;
close all;
t=0:0.000001.01;
disp(digital message signal);
vm=input(amplitude:);
fm=input(frequency);
wm=2*pi*fm;
disp(carrier signal);
vm=input(amplitude:);
fm=input(frequency);
wm=2*pi*fc;
vm=vm*(square(wm*t));
subplot(5,1,1);
plot(t,vm);
title(digital message signal);
xlabel(time);
ylabel(amplitude);
vc=vc*sin(wc*t));
subplot(5,1,2);
plot(t,vc);
title(carrier signal);
xlabel(time);
ylabel(amplitude);
EX. NO.18 DIGITAL MODULATION USING MATLAB
DATE:
AIM:
To generate the waveform of ASK,FSK and PSK

using MATLAB commands
SOFTWARE PACKAGE:
MATLAB
ALGORITHM:
Step 1: Open the MATLAB software by double clicking the icon.

Step 2:MATLAB log will appear and after a few moments command prompt will appear.
Step 3 :Go to file menu and select a new M-file in the left corner a blank white paper will appear
and click it once.
Step 4: A blank M- file will appear with a time untitled.
Step 5:Now start typing the program after completing save the M-file with appropriate name.
Step 6:After execution output will appear in the command mindow. If there is an error rectify
the error and the error will appear in red colour.
Step 7: After rectifying the error go to debug and RUN the program.
q=vm.*vc+vc;
subplot(5,1,3);
plot(t,q);
title(ask signal);
xlabel(time);
ylabel(amplitude);
r=vm.*vc;
subplot(5,1,4);
plot(t,r);
title(psk signal);
xlabel(time);
ylabel(amplitude);
x=sin(2*pi*(fc+1500*vm).*t);
subplot (5,1,5);
plot(t,x);
title(fsk signal);
xlabel(time);
ylabel(amplitude);
RESULT:
Thus the waveform of ASK,FSK,PSK are generated using MATLAB commands.,
PROGRAM FOR ERROR CONTROL:
HUFFMAN CODING (SOURCE CODING TECHNIQUE)

clc; clear all; close all;
s=[0.25 0.25 0.3 0.1 0.05 0.05]; e=dsort(s);

for i=1:6 for j=1:6
c1(i,j)=0;
d(i,j)=0;
end;
end;
for i=1:6 for j=1:6
if j= =1 c1(:,j)=e;
end;
end;
end;
k=6;
for i=2:6; for j=2:6;
if(k>1) e(k-1)=e(k-1)+e(k); e(k)=0;
e=dsort(e);
c1(:,j)=e; k=k-1;
end;
end;
x=1;
y=5;
EX. NO.19 ERROR CONTROL USING MATLAB
DATE:
AIM:
To write a program in MATLAB for error control coding techniques.
SOFTWARE PACKAGE:
MATLAB
ALGORITHM:
1.Get the input binary sequcence.

2.Calculate the reundancy bits for the corrosponding code.
3.Transmit the signal that contains message bits+redundancy bits added at the end.
4.Calculate the redundancy bits once again for the received bits.
5.If the redundancy bits=0 then no error in the transmission otherwise some
error in the transmission.
while x<=6&&y>=1 if c1(x,y)~=0

d(x,y)=0;
d(x+1,y)=1;
x=x+1; y=y-1; end;
end;
p=0;
q=1;
p1=num2str(p);
p2=strcat(p1,p1);
q1=num2str(q);
pq=strcat(p1,q1);
qp=strcat(q1,p1);
qqp=strcat(q1,q1,p1);
qqqp=strcat(q1,q1,q1,p1);
qqqq=strcat(q1,q1,q1,q1);
disp(sprintf(`code(0.3)=%s,p2));
disp(sprintf(`code(0.25)=%s,pq));
disp(sprintf(`code(0.25)=%s,qp));
disp(sprintf(`code(0.1)=%s,qqp));
disp(sprintf(`code(0.05)=%s,qqqp));
disp(sprintf(`code(0.05)=%s,qqqq));
length=length(p2)*0.3+length(pq)*0.25+length(qP)*0.25+length(qqp)*0.1+length(qqqp)*0.005+le
ngth(qqqq)*0.05;
entropy=-(0.3*(log(0.3)?log(2))+2*(0.25*(log(0.25)?log(2)))+0.1*(log(0.1)?log(2))
+2*(0.05*(log(0.05)?log(2))));
efficiency+[entropy/length]; redundancy=[1-
efficiency]; disp(sprint(`\nlength:%d,length));
disp(sprint(`\nentropy:%d,entropy));
disp(sprint(`\nefficiency:%d,efficiency));
disp(sprint(`\nredundancy:%d,redundancy));
end
OUTPUT:
RESULT:
Thus the waveform of Error control is generated using MATLAB commands.,

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EC2307 Communication System Laboratory,DGCT

EC2307 COMMUNICATION SYSTEM LABORATORY

1. Amplitude modulation and Demodulation.

Ex.N Name of the Experiment Pg.No

FSK using kit

FSK using Matlab programs

15 Error Control Coding using MATLAB 149

Signature of the Staff Marks (Out of / )

EX. NO.1 SAMPLING

S.NO APPARATUS RANGE QUANTITY

4 20 MHz Dual Trace Oscilloscope 1

BLOCK DIAGRAM FOR FLAT TOP SAMPLING:

Flat Top Sampling And Its Reconstruction

BLOCK DIAGRAM FOR SAMPLE AND HOLD CIRCUIT:

S.NO SIGNAL AMPLITUDE TIME

1.Define Sample and hold circuit?

AMPLITUDE MODULATION TRANSMITTER:

EX. NO.2 AMPLITUDE MODULATION AND DEMODULATION

S.NO APPARATUS RANGE QUANTITY

2 Power supply (0-30)V 1

Amplitude modulation is the process of changing the amplitude of a relatively high

Where Em is maximum amplitude of modulating signal

Ec is maximum amplitude of carrier signal

m is frequency of modulating signal

The ratio of maximum amplitude of modulating signal to maximum amplitude of carrier

Modulation index m = (Em /Ec )* 100

m = [(Emax - Emin) / (Emax + Emin)]*100

2 Connect o/p of FUNCTION GENERATOR section (ACL-01) OUT post to the

S.NO SIGNAL AMPLITUDE TIME

1.Define Amplitude modulation?

S.NO SIGNAL AMPLITUDE TIME

EX. NO.3 FREQUENCY MODULATION AND DEMODULATION

S.NO APPARATUS RANGE QUANTITY

1 Frequency modulation kit 1

6 Connecting wires As required

Frequency modulation is defined as change in frequency of carrier signal with

Modulation index m = f/fm

Calibration Of The Demodulator

S.NO APPARATUS RANGE QUANTITY

6 Function generator 0-30MHZ 1

7 Connecting wires As required

1. Connections are given as per the circuit diagram.

1.Define Frequency modulation?

EX. NO.4 PULSE AMPLITUDE MODULATION

1 Phase modulation kit 1

5 Connecting wires As required

S.NO SIGNAL AMPLITUDE TIME

3. Select 16KHz sampling frequency by jumper JP1.

5. Observe the Pulse Amplitude Modulation output at PAM OUT Post.

7. Keep the amplifier gain control potentiometer P5 to maximum completely clockwise.

EX. NO.5 PULSE WIDTH MODULATION

S.NO APPARATUS RANGE QUANTITY

1 Phase modulation kit 1

5 Connecting wires As required

PULSE WIDTH MODULATION :

Amplitude Time Frequency

8. Observe the Pulse Width Demodulated output at FIL OUT.

EX. NO.6 PULSE POSITION MODULATION

S.NO APPARATUS RANGE QUANTITY

1 Phase modulation kit 1

5 Connecting wires As required

Amplitude Time Frequency

BLOCK DIAGRAM FOR PCM MODULATION AND DEMODULATION:

EX. NO.7 PULSE CODE MODULATION

fC = [fL / 2 3.6 103 *C2]1/2