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9450

Gilman Drive, 80391


La Jolla, San Diego , CA 92092
HARSHA BASAVARAJ (858)-291-2229
hbasavar@ucsd.edu
https://www.linkedin.com/in/harsha-basavaraj

EDUCATION

Master of Science (MS) University of California, San Diego June 2017(expt.d)
Major in Computer Science and Engineering, GPA:3.73

Coursework: Principles of Computer Architecture; VLSI circuits; Parallel Computation; Embedded systems;
Algorithms; Advance Compiler design.
B.Engg M S Ramaiah Institute of Technology, Bangalore 2009-2013
Major in Telecommunication Engineering, GPA: 9.56/10

Coursework: Digital Design; Hardware Description languages; Data Structures; Microprocessors; Micro-controllers;
Communication Systems; DSP Architecture; Engineering Entrepreneurship

RESEARCH AND PROFESSIONAL EXPERIENCE


Research Assistant Computer Architecture Group, UCSD April 2016 present
Implemented customizable Verilog model of x86 instruction decoder pipeline for evaluating the power and areas

implications of using heterogeneous and customizable ISAs (Verilog, C++)


Exploring design space for reduction of memory latency in processors for Big data, Machine learning and Security

applications under the guidance of Prof. Dean Tullsen. The project involves performance analysis of state of the art
big data and cloud computing workloads and tradeoffs for achieving higher performance (C, DPDK, Vtune)

Research Assistant San Diego Super Computer Center(SDSC), UCSD January 2016 March 2016
Implemented cache blocking based optimizations for on efficient memory utilization for improvement of single core

and multi-core performance of Earthquake Simulations (C++, CUDA)


Instrumented and profiled automatic wave propagation(AWP) earthquake simulation code on Intel Xeon Phi and

Haswell processors for detection of bottlenecks in performance


Software Development Engineer Cisco Systems, Bangalore, India August 2013 August 2015
Successfully completed firmware development for next generation MLOM network adapter (VIC1227T) which saved

a PCIE slot on Cisco servers (C, Shell)


Developed Auto VNIC placement feature for PCIE cards which substantially improved load balancing of Virtual NICs

over PCIe links


Contributed to the firmware code refactoring by automating most of the sanity checking

Automated steps involved in development testing process such as installing and activating the new firmware image,


sanity unit test cases for link testing, traffic testing, link failover and status management features
Teaching Assistant University of California, San Diego March 2016 present

Courses: Introduction to Computer Architecture; Advanced Computer Architecture Project; Digital Design Lab;

LANGUAGE AND TOOLS


C; Verilog; C++; Shell Scripting; MPI; Cuda; Python; LateX.

Synopsys Design Compiler; Primetime; Vtune amplifier; DPDK; Arduino.


PROJECTS
Many-core implementation of Stream-it Programming language: Designed and implemented hardware

enhancements for many-core processor based on RISC V ISA, this comprised of changes to Network on Chip (NOC),
I/O devices, Synchronization mechanisms and compilation tool chain for supporting Stream-it programming
language (Technologies: Verilog, C, Vivado)
4 Component O-GEHL Branch predictor: Designed and implemented Verilog and C simulation model of a geometric

history length branch predictor and verified using SPEC benchmarks. The predictor was 98.7% accurate with small
budget sizes (32-64k bits) (Technologies: C, C++)
Aliev-Panfilov model based High-Performance Cardiac Electrophysiology Simulator: MPI implementation of

Cardiac simulations which can scale to run on 1-1024 cores with maximum performance of up to 3000 GFlops on
Stampede Super Computer (Technologies: C, C++, MPI)
High Performance Matrix Multiplication: Optimization of large matrix operations on GPUs and single core CPUS

using cache/memory optimizations techniques and SSE intrinsics (Technologies: C, C++, MPI, CUDA)
Custom ALU: RTL to GDSII synthesis of fully customized power and area optimized 64 bit ALU, the ALU was built

using high speed Carry save adder and radix 8 booth multiplier (Technologies: Verilog, Tcl, SDC, Primetime)
Cache Simulator: Any size, Any way LRU cache simulator in C evaluated using SPEC benchmarks (C, C++)


Program Optimization Analysis Framework: LLVM based framework for carrying out Client analyses such as Data-
flow, Reaching Definitions, Pointer, Branch bias, Liveness etc which helps in optimization of program compiled
(Technologies: C, C++, LLVM)
Optimization of RTL-to-GDSII Design, Verification & Physical Implementation Processes: Leakage power
minimization through sensitivity factor based gate-sizing and Vt swapping, achieving up to 93% leakage reduction
without timing violations. Clock tree-optimization with useful skew by greedy heuristic algorithm achieving up to
95% less timing violations (Technologies: Verilog, Tcl)
Probabilistic models for Artificial Intelligence systems: Python based AI models for applications such as Stock
Market prediction, sentence prediction, Hangman game and Speech Recognition using N-gram, Markov, Stochastic
modelling regression and Reinforcement Learning techniques (Technologies: Python)
Context based Home Automation: Raspberry Pi and Arduino based Home automation system which learns the
context over a period of time with help of data from the sensors and a cloud based analytics system (Technologies:
Python)
Design and Establishment of Satellite Communication link: FDMA Dedicated channel for Voice and Data
Communication between ground and space station, at ISRO Telemetry Tracking and Command Network (ISTRAC)
Bangalore
Publication: CHAMP A Low Cost Modular Humanoid Platform", International Conference on Control, Automation,
Robotics & Embedded Systems (CARE), 2013. DOI: 10.1109/CARE.2013.6733738