Birla Institute of technology and Sciuence -Pilani Goa Campus

Sem II (2009-2010)
Test 2(OB)
Solution Key

Course Name: Analog and Digital VLSI (EEE C443) Max Time: - 1 Hr MM: 60 Date: 31/03/2010

Q1:- Answer:- F1(A,B,C)= sum bar circuit of a 1 bit full adder (A xor B xor C) F2(A,B,C)= is a Carry
bar Circuit of a 1 bit full adder.

The CPL implementation of the above ckt is

Answer
Q3 the output expression in the form X = ((A + B) (C + D + E) + F) G = (((AB + CDE)F) + G )
allows us to build the pulldown network by inspection (parallel devices implement an OR, and series
devices implement an AND). The pullup network is the dual of the pulldown network.
 The plot shows sizes that meet the requirement - in the worst case, the output resistance of the
circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS W/L=6
The worst case pull-up resistance occurs whenever a single path exists from the output node to
Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110. The best case pull-
up resistance occurs when ABCDEFG=0000000.
The worst case pull-down resistance occurs whenever a single path exists from the output node to
GND. Examples of vectors for the worst case are ABCDEFG=0000001 and
0011110.
The best case pull-down resistance occurs when ABCDEFG=1111111.
Q4
a)

E F G
0 0 z
0 1 z
1 0 0
1 1 1

b) Vtp

Q5: a) To calculate the optimum number of stages, we need,

The effective fan-out of the path:

F = CL/Cg1 = 900/6 = 150

Using the entries given in table 6-5 in the book, the path logical effort is given by:
G = g1*g2*g3*g4 = 1*4/3*5/3*6/3 = 120/9
 Path branching effort:
B = b1*b2*b3*b4 = 3x/x * 2y/y * 1 * 1 = 6

Hence, H = FGB = 4000. Since the optimal stage effort h = 4, hence

h = (H)1/N where N represents the number of stages
Therefore,
4 = (4000)1/N or N ~ 6.

If N =6, we keep the logic intact by adding two min-sized inverters in the path in the following
way:

Notice that adding fixed minimum sized inverters does not keep the stage effort intact for each
stage. The ideal way would be to add inverters sized a and b and to calculate their sizes
respectively.

N
N (N H )
b) Delay = t p 0
p j

Where,

j 1
tp0 = 15ps
6

p
j 1
j = 1+1+1+2+2+4 = 11

And Delay = 15p * (11+6*4/1) = 525ps = 0.525ns

c) To calculate x, y and z, we start from the last stage and repeatedly apply the formula:

Cin,i = (Cout,i * gi )/ h

So, z = (CL * g4 )/4 = 900*2/4 = 450

And, y = (z * g3)/4 = 450*5/3*1/4 = 187.5

And x = (2*y * g2)/4 = 2*187.5*4/3*1/4 = 125