Fully passive third-order noise shaping (STF) and noise transfer function (NTF) become:

SAR ADC STF(z) = 1 (1)

P. Payandehnia , H. Mirzaie, H. Maghami, J. Muhlestein and
G.C. Temes
In this Letter, an opamp-free noise shaping successive-approximation
register (SAR) ADC is proposed. Third-order noise shaping is
achieved by implementing a second-order passive lter and a passive
error feedback topology. In the proposed scheme, the SAR error
signals (including quantisation noise, comparator thermal noise,
DAC thermal noise and settling error) are subjected to third-order
noise shaping. Therefore, the thermal noise specications of the
comparator can be relaxed. Also, since no active element is used, the
proposed scheme achieves a higher power efciency than earlier
SAR ADCs.
1
NTF( z) = 1 0.75z (2)
In this scheme, the quantisation noise, comparator thermal noise, DAC
thermal noise, and DAC settling error are all ltered with a rst-order
noise shaping [4]. Since the comparator thermal noise requirement is
relaxed, a more power efcient comparator can be used. Moreover,
since DAC settling error is shaped, a higher sampling rate can be
achieved.
Proposed scheme: The proposed noise-shaping SAR ADC is shown in
Fig. 2. In this gure, a single-ended architecture is shown for simplicity.
The actual implementation is differential. Compared to conventional
SAR ADC operation, three more clock phases, NS0,1,2, are added.

Introduction: The successive-approximation register (SAR) ADC is a fC

fS fNS1 fNS2 fS
popular architecture for medium-resolution medium-speed applications.
For higher resolution applications, several design issues, including C2 = aC1
comparator thermal noise, DAC settling error and thermal noise, limit fNS0 C3 = C4 = bC1
the performance of the SAR ADC. To resolve these issues, a rst-order
noise shaping technique was introduced in [1] where an FIR lter and an C1 SAR Asynch.
opamp-based IIR lter were used to reduce the quantisation noise and logic
comparator thermal noise within signal band. To save power, passive VCM
VCM
lters [2, 3] can be used in the loop lter. In [4], a rst-order noise VREF

shaping SAR was introduced in which the loop lter is implemented C2

using a passive integrator. In [5], a passive error feedback architecture
was used to implement a rst-order noise shaping SAR.
In this Letter, a novel fully passive third-order noise shaping SAR
ADC is proposed. Compared to prior works, higher order noise
shaping is achieved by implementing a passive error feedback topology
and a second-order passive lter. Using higher-order passive lters,
higher-order noise shaping can be achieved without signicant power
overhead. Using the proposed scheme, the thermal noise of the compara-
tor and DAC, and DAC settling error as well as quantisation noise are
ltered out of signal band.
fS fc fNS0 fNS1 fS
fE fE
VIN SAR
VREFN logic
VREFP
fS fC
fE
VRES
C1 = C VINT 1X
4X
fS fNS0 fNS1
1X
C2 = C C3 = C
3
Fig. 1 Passive noise shaping SAR ADC presented in [4]
Prior art review: Fig. 1 shows the passive rst-order noise shaping
SAR ADC presented in [4]. During sampling phase, S, the input
signal is sampled on the bottom plate of DAC capacitors (C1). Next,
during the conversion cycle, C, the SAR logic generates the proper
controlling signals, and output bits are extracted. At the end of the
conversion cycle, the residue voltage VRES is stored on C1. During the
following clock phases VRES is applied to a passive integrator
implemented by C2 and C3. Next, during NS0, C2 which has been
earlier reset is connected to C1 to sample the residue voltage. In the
next phase, NS1, the voltage on C2 is passively integrated on C3. The
comparator used in this scheme needs an additional scaled input path
compared with the comparator used in conventional SAR ADCs. The
passive integrator output VINT is connected to the second input of
comparator. The voltage VINT provides an offset for comparator in
the next conversion cycle. In the comparator design, the size of input
differential pair of preamp stage connected to VINT, is four times
larger than the input differential pair connected to VRES [4]. This way,
a gain of four is implemented at the passive integrator output. By
choosing the capacitor sizes shown in Fig. 1, the signal transfer function
fC
fS fNS0 V
VIN C2
1X
VC4
kX
fNS1 fNS2 1X
C3 C4
VCM
Fig. 2 Proposed fully passive third-order noise shaping SAR ADC
During the sampling phase, S, the input signal is sampled on the DAC
capacitors (C1). After that, NS0 goes high and the initial voltage on C2,
which is the residue voltage from the previous conversion, is added to the
sampled voltage on C1 passively. Thus, passive error feedback is
implemented. Next, the SAR conversion cycle C begins, and the
output bits are extracted while the SAR logic generates the proper
controlling signals. During C, NS0 remains high. At the end of C,
the residue voltage is stored on both C1 and C2, and NS0 goes low.
The voltage VC2 stored on C2 remains unchanged until the next sampling
phase. The voltage stored on C1 which is equal to VC2 is applied to a
second-order passive lter which is implemented using C3 and C4.
During NS1 and NS2, C1 is connected to C3 and C4, respectively. The
VC4 voltage stored on C4 provides an offset for comparator during the
next conversion cycle. The comparator used in this scheme has a
similar architecture to that used in [4], where the gain of input path
related to VC4 is k. The passive lter used here is similar to the passive
lter reported in [3] where C1 is functioning as charge rotating
capacitor and C3,4 are functioning as history capacitors. This passive
lter features low thermal noise level and high operating speed. By
increasing the number of history capacitors, higher order of ltering
can be implemented with a minimal thermal noise and power overhead.
Other passive lter topologies similar to [2] could also be used here. The
signal ow graph of the proposed ADC is shown in Fig. 3. In this gure,
E represents the combination of quantisation noise, DAC settling error,
and DAC and comparator thermal noise. Using this signal ow graph,
the STF and NTF can be found:
STF(z) = 1 (3)


 2
1 (a/(1 + a))z1 1 (b/(1 + b))z1
NTF( z) = 
2 
2
1 + (k/ b + 1 ) (2b/(1 + b)) z1 + b/(1 + b) z2
(4)
where and are capacitor ratios, as shown in Fig. 2. To keep the loop
stable, the poles should be located within the unit circle in the z plane.
The stability condition of the loop is therefore:

2
1 , k , 2b + 1 (5)

ELECTRONICS LETTERS 13th April 2017 Vol. 53 No. 8 pp. 528530

 As (4) shows, the proposed scheme provides third-order noise a 0.18 m 1P4M CMOS technology. The SAR logic and switches were
shaping. The zero positions can be set by choosing desired values for represented by macro-models. The comparator was simulated on the
and . The magnitude of NTF at zero frequency is equal to: transistor level, but without thermal noise. The comparator had the
same architecture as the one used in [4] but the gain of input path
1
NTF(z = 1) = (6) related to VC4 in Fig. 2 is increased to 6 (k = 6). Based on (5), the
(1 + a)(1 + k ) maximum value of k for keeping the loop stable is 9. A 10-bit DAC
To increase the DC attenuation in the NTF, the values of and k should was implemented using the merged capacitor switching (MCS)
be increased. Increasing results in a larger C2 size. The maximum architecture [6]. The capacitors C14 were all chosen to be equal to
value of k is determined by the stability requirements in (5). 3 pF ( = = 1). The output power spectral density (PSD) of the
proposed scheme is shown in Fig. 5. The input signal magnitude
applied to the ADC is 1 dBFS, OSR is 10, and the sampling frequency
k = comparator
gain in VC4 path (
1
)
2 is 20 MHz. The SQNR and ENOB of the proposed scheme within a
1+b(1z 1) 01 MHz band is compared to that of an ideal third-order noise
shaping NTF (1 z 1)3 and of the schemes reported in [4] and [5] in
z 1
Table 1. A 10-bit MCS DAC is used in all the architectures.
k E
Table 1: SQNR for different lter topologies in the 01 MHz band
VIN + + + VOUT with a sampling frequency of 20 MHz
Architecture SQNR, dB ENOB, bit
az 1
1+a + Ideal third-order noise shaping 110 18
+
VC2
Guo [4] 82 13.3
Chen [5] 80 13
Fig. 3 Signal ow graph of proposed architecture Proposed scheme 92 15.1

Using similar circuitry, it is also possible to get a second-order NTF

by using a rst-order passive lter with somewhat reduced performance.
In Fig. 4, the NTF of the proposed scheme is compared with an ideal
third-order response NTF(z) = (1 z 1)3, and the NTF plot of the
scheme reported in [4]. In this simulation, = = 1. For a fair compari-
son, the comparator gain in VC4 path in Fig. 2 is chosen to be same as the
comparator gain in VINT path in Fig. 1 (k = 4). As Fig. 4 shows, the NTF
at DC is improved by 8 dB in the proposed scheme when compared with
[4]. Also, by increasing the value of k, the NTF attenuation at DC can be
improved even more in the proposed scheme.
20
ideal third-order
W. Guo [4]
10 proposed scheme
NTF magnitude, dB
As Table 1 shows, while the proposed scheme does not have as good
SQNR and ENOB as an ideal third-order noise shaping, but it improves
the SQNR by 10 dB compared with [4] and by 12 dB compared with [5].
Conclusion: A novel fully passive noise shaping SAR ADC was
presented. Using a second-order passive lter and a passive error feed-
back topology, third-order noise shaping was achieved. In the proposed
scheme, DAC settling error and the thermal noise requirements of
both comparator and DAC can be relaxed. This is achieved, since the
quantisation noise as well as the thermal noise of the comparator
and DAC are shaped with the same NTF. These features make this
architecture power efcient.
Acknowledgments: This work was supported by the Semiconductor
Research Center (SRC), the NSF Center for the Design of

Analogue-Digital Integrated Circuits (CDADIC) and by the Asahi

0 Kasei Microdevices Corporation (AKM).

10 The Institution of Engineering and Technology 2017

Submitted: 20 January 2017 E-rst: 14 March 2017
20
doi: 10.1049/el.2017.0318
P. Payandehnia, H. Mirzaie, H. Maghami, J. Muhlestein and G.C.
105 106 107
Temes (School of EECS, Oregon State University, Corvallis, OR
frequency, Hz
97330, USA)
Fig. 4 NTF comparison for = = 1, k = 4, Fs = 20 MHz, BW = 1 MHz E-mail: payandep@eecs.oregonstate.edu

0 References
20 SNR = 92.4 dB at OSR = 10 1 Fredenburg, J.A., and Flynn, M.P.: A 90-MS/s 11-MHz-bandwidth 62-dB
ENOB = 15.05 bits at OSR = 10 SNDR noise-shaping SAR ADC, IEEE J. Solid-State Circuits, 2012, 47,
40 (12), pp. 28982904
2 Payandehnia, P., Maghami, H., Kareppagoudr, M., and Temes, G.C.:
60 dB/Dec
60
Passive switched-capacitor lter with complex poles for high-speed
PSD, dB

80 applications, Electron. Lett., 2016, 52, (19), pp. 15921594

3 Tohidian, M., Madadi, I., and Staszewski, R.B.: Analysis and design of
100 a high-order discrete-time passive IIR low-pass lter, IEEE J. Solid State
Circuits, 2014, 49, (11), pp. 25752587
120 4 Guo, W., and Sun, N.: A 12b-ENOB 61W noise-shaping SAR ADC
140
with a passive integrator. IEEE European Solid-State Circuits Conf.
104 105 106 107 (ESSCIRC), Lausanne, Switzerland, 2016, pp. 405408
frequency, Hz 5 Chen, Z., Miyahara, M., and Matsuzawa, A.: A 9.35-ENOB, 14.8 fJ/conv.-
step fully-passive noise-shaping SAR ADC. IEEE Symp. on VLSI
Fig. 5 Simulated PSD with 1 dBFS input signal and = = 1, k = 6, Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C64C65
Fs = 20 MHz, BW = 1 MHz 6 Hariprasath, V., Guerber, J., Lee, S.H., and Moon, U.K.: Merged capacitor
switching based SAR ADC with highest switching energy-efciency,
Simulation result: The third-order passive noise shaping SAR ADC of Electron. Lett., 2010, 46, (9), pp. 620621
Fig. 2 was designed and simulated using Cadence SPECTRE assuming

ELECTRONICS LETTERS 13th April 2017 Vol. 53 No. 8 pp. 528530