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AIM
Control Unit
Arithmetic Logic Unit
Registers
Accumulator
Flags
Program Counter (PC)
Stack Pointer (SP)
Instruction Register/Decoder
Memory Address Register
General Purpose Registers
Control Generator
Register Selector
Microprogramming
CONTD..
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
Logic operations
Implied Addressing:
The addressing mode of certain instructions is implied by the instructions function.
For example, the STC (set carry flag) instruction deals only with the carry flag, the
DAA (decimal adjust accumulator) instruction deals with the accumulator.
Register Addressing:
Quite a large set of instructions call for register addressing. With these instructions,
specify one of the registers A through E, H or L as well as the operation code. With
these instructions, the accumulator is implied as a second operand. For example,
the instruction CMP E may be interpreted as 'compare the contents of the E register
with the contents of the accumulator.
Most of the instructions that use register addressing deal with 8-bit values.
However, a few of these instructions deal with 16-bit register pairs. For example, the
PCHL instruction exchanges the contents of the program counter with the contents
of the H and L registers.
Immediate Addressing:
Instructions that use immediate addressing have data assembled as a part of the
instruction itself. For example, the instruction CPI 'C' may be interpreted as
compare the contents of the accumulator with the letter C. When assembled, this
instruction has the hexadecimal value FE43. Hexadecimal 43 is the internal
representation for the letter C. When this instruction is executed, the processor
fetches the first instruction byte and determines that it must fetch one more byte.
The processor fetches the next byte into one of its internal registers and then
Getthe
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operation.
ADDRESSING MODES
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CONTD
Direct Addressing:
Jump instructions include a 16-bit address as part of the instruction. For example,
the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by
replacing the current contents of the program counter with the new value 1000H.
Instructions that include a direct address require three bytes of storage: one for the
instruction code, and two for the 16-bit address
Register Indirect Addressing:
Register indirect instructions reference memory via a register pair. Thus, the
instruction MOV M,C moves the contents of the C register into the memory address
stored in the H and L register pair. The instruction LDAX B loads the accumulator
with the byte of data specified by the address in the B and C register pair.
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Procedures
Macros
DIAGRAM
In the 8088, these bytes come in on the 8-bit data bus. In the 8086, bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15).
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations. The 8088 needs two operations in either case.
lower address.
SP
BH BL
BX
SI
CH CL
DI
CX
DH DL
DX Segment
CS
Flags DS
IP ES
The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
The EU decodes and executes the instructions using the 16-bit ALU.
The BIU fetches instructions using the CS and IP, written CS:IP, to contract
the 20-bit address. Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode.
ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer
EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
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8086/88 internal from16
registers www.Rejinpaul.com
bits (2 bytes each)
Registers
Registers are in the CPU and are referred to by specific names
Data registers
Hold data for an operation to be performed
There are 4 data registers (AX, BX, CX, DX)
Address registers
Hold the address of an instruction or data element
Segment registers (CS, DS, ES, SS)
Pointer registers (SP, BP, IP)
Index registers (SI, DI)
Status register
Keeps the current status of the processor
On an IBM PC the status register is called the FLAGS register
In total
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registers in an 8086/8088
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Data Registers: AX, BX, CX, DX
BX
Base Register
Also serves as an address register
Used in array operations
Used in Table Lookup operations (XLAT)
CX
Count register
Used as a loop counter
Used in shift and rotate operations
DX
Data register
Used in multiplication and division
Also used in I/O operations
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Pointer and Index Registers
F0000
E0000 8000:FFFF
D0000
C0000
B0000
A0000
one segment
90000
80000
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs
00000
Adder
Offset: 0000000000101001
SEGMENT:OFFSET ADDRESS
0H
4000H
CS: 0400H
CS:IP = 400:56
4056H Logical Address
IP 0056H
The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.
0H
05C00H
DS: 05C0
05C50H
EA 0050 DS:EA
Memory
05C0 0
Segment Register
Offset + 0050
0FFFFFH
Physical Address 05C50H
0H
0A00 0A000H
SS:
0A100H
SP 0100 SS:SP
Segment Register
Memory
0A00 0
Offset
+ 0100
Physical Address
0FFFFFH
0A100H
The offset is given by the SP register.
The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.
Carry flag
Overflow
Direction Parity flag
Trap Zero
Sign
6 are status flags
3 are control flag
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Flag Register
Conditional flags:
They are set according to some results of arithmetic operation. You do
not need to alter the value yourself.
Control flags:
Used to control some operations of the MPU. These flags are to be set
by you in order to achieve some specific purposes.
Flag O D I T S Z A P C
1
Bit no. 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0
0
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic.
%let dsn=LAB;
run;
run;
Input/Output
String Instructions
Machine Control
Flag Manipulation.
Immediate addressing.
Register addressing.
Direct addressing.
Indirect addressing
Implied addressing.
Indexed addressing
Relative addressing
Routine
An interrupt signals the processor to suspend its current activity
(i.e. running your program) and to pass control to an interrupt service
program (i.e. part of the operating system).
Maximum mode
All the control signals (except RD) are not generated by the microprocessor.
Solution:
8288.
modes
8086 maximum & minimum modes
The mode is controlled by MN/MX.
Maximum mode is obtained by connecting MN/MX to low and
minimum mode is by connecting it to high.
Having two different modes (minimum and maximum) is used
only 8088/8086.
Each mode enables a different control structure.
Minimum mode operation and control signals are very similar to
those of 8085.
So 8085 8-bit peripherals can be used with 8086 without special
considerations.
Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O port IORC
0 1 0 Write I/O port IOWC, AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC, AMWC
1 1 1 Passive none
Coprocessor Configuration
Data types
Two Units
Control Unit
Execution Unit
Control unit: To synchronize the operation of the coprocessor and the processor.
This unit has a Control word and Status word and Data Buffer
If instruction is an ESCape (coprocessor) instruction, the coprocessor executes it, if not
the microprocessor executes.
Status register reflects the over all operation of the coprocessor.
Status Register
IC Infinity control
RC Rounding control
PC Precision control
PM Precision control
UM Underflow mask
OM Overflow mask
ZM Division by zero mask
DM Denormalized operand mask
IM Invalid operand mask
IC Infinity control selects either affine or projective infinity. Affine allows positive and
negative infinity, while projective assumes infinity is unsigned.
INFINITY CONTROL
0 = Projective
1 = Affine
RC Rounding control determines the type of rounding.
ROUNDING CONTROL
00=Round to nearest or even
01=Round down towards minus infinity
10=Round up towards plus infinity
11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table
PRECISION CONTROL
00=Single precision (short)
01=Reserved
10=Double precision (long)
11=Extended precision (temporary)
Exception Masks It Determines whether the error indicated by the exception affects
the error bit in the status register. If a logic1 is placed in one of the exception control bits,
corresponding status register bit is masked off.
This performs all operations that access and manipulate the numeric data in the
coprocessors registers.
Numeric registers in NUE are 80 bits wide.
NUE is able to perform arithmetic, logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM.
Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit sign/exponent bus.
Internally, all data operands are converted to the 80-bit temporary real format.
We have 3 types.
Integer data type
Packed BCD data type
Real data type
Example
Converting a decimal number into a Floating-point number.
1) Converting the decimal number into binary form.
2) Normalize the binary number
3) Calculate the biased exponent.
4) Store the number in the floating-point format.
Example
Step Result
1) 100.25
2) 1100100.01 = 1.10010001 * 26
3) 110+01111111=10000101
4 ) Sign = 0
Exponent =10000101
Significand = 10010001000000000000000
In step 3 the biased exponent is the exponent a 26 or 110,plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH.
IN step 4 the information found in prior step is combined to form the floating point no.
Architecture of 8051
Signals
Operational features
Memory and I/O addressing
Interrupts
Instruction set
Applications.
A smaller computer
On-chip RAM, ROM, I/O ports...
ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC
16X
Microprocessor
CPU is stand-alone, RAM, Microcontroller
ROM, I/O, timer are separate CPU, RAM, ROM, I/O and
designer can decide on the timer are all on a single chip
amount of ROM, RAM and fix amount of on-chip ROM,
I/O ports. RAM, I/O ports
expansive for applications in which cost,
versatility power and space are critical
general-purpose single-purpose
External interrupts
On-chip Timer/Counter
CPU
Bus Serial
4 I/O Ports
OSC Control Port
P0 P1 P2 P3 TxD RxD
Address/Data
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
Vcc
+
10 uF
31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST
Vcc
10 K
P0.0
Port
DS5000 P0.1
P0.2
8751 P0.3
8951 P0.4 0
P0.5
P0.6
P0.7
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R5
R6
R7
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits:
1 2 3 4 5 6 7 8 9 A B C D E F
A=10
B=11
C=12
D=13
E=14
F=15
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(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
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Register Addressing Mode
MOV DPTR, A
MOV Rm, Rn
MOV A,#65H
MOV R6,#65H
MOV DPTR,#2343H
MOV P1,#65H
SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR =1
SETB 05 ;set high D5 of RAM loc. 20h
Note:
INC R7
DEC A
DEC 40H ; [40]=[40]-1
Conditional Jumps :
JZ Jump if A=0
JB Jump if bit=1
SETB P0.0
.
.
CALL UP
.
.
.
UP:CLR P0.0
.
.
RET
(contd)
Accessing I/O ports in Pentium
Register I/O instructions
in accumulator, port8 ; direct format
Useful to access first 256 ports
in accumulator,DX ; indirect format
DX gives the port address
Block I/O instructions
ins and outs
Both take no operands---as in string instructions
ins: port address in DX, memory address in
ES:(E)DI
outs: port address in DX, memory address in
ES:(E)SI
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We can use rep prefix for block transfer of data
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An Example I/O Device
Keyboard
Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code
Scan code is like a sequence number of the key
Keys scan code depends on its position on the
keyboard
No relation to the ASCII value of the key
(contd)
8255 PPI has three 8-bit registers
Port A (PA)
Port B (PB)
Port C (PC)
These ports are mapped as follows
8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
(contd)
Mapping of 8255 I/O ports
(contd)
Mapping I/O ports is similar to mapping
memory
Partial mapping
Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be
read from port 60H
7-bit scan code is available from
PA0 PA6
Key status is available from PA7
PA7 = 0 key depressed
PA0
Get= 1 key
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I/O Data Transfer
Data transfer involves two phases
A data transfer phase
It can be done either by
Programmed I/O
DMA
An end-notification phase
Programmed I/O
Interrupt
Three basic techniques
Programmed I/O
DMA
Interrupt-driven I/O (discussed in Chapter 20)
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I/O Data Transfer (contd)
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Programmed I/O
Done by busy-waiting
This process is called polling
Example
Reading a key from the keyboard involves
Waiting for PA7 bit to go low
Indicates that a key is pressed
Reading the key scan code
Translating it to the ASCII value
Waiting until the key is released
Program 19.1 uses this process to read input
from the keyboard
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I/O Data Transfer (contd)
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Interrupt to
I/O Control
Processor
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Inside the Timer
High Byte Low Byte
Counter Register
at offsets 0x04, 0x00 (write only)
GO Register
offset 0x08, immediately moves
Counter Reg value into Current Counter
Current Counter
(not directly readable by software)
Latch Register
offset 0x0C, write a ``1'' to immediately write
Current Counter value to readable Latch Reg
Latched Counter
at offsets 0x04, 0x00 (read only)
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Setting the Timer's
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Counter Registers
Counter is usually programmed to reach
zero X times per second
To program the timer to reach zero 100 times
per second
Example: For a 2 MHz-based timer, 2MHz /
100 = 20,000
Polled I/O requires the CPU to ask a device (e.g. toggle switches) if the device requires
servicing
For example, if the toggle switches have changed position
Software plans for polling the devices and is written to know when a device will be
serviced
Interrupt I/O allows the device to interrupt the processor, announcing that the device
requires attention
This allows the CPU to ignore devices unless they request servicing (via interrupts)
Software cannot plan for an interrupt because interrupts can happen at any time
therefore, software has no idea when an interrupt will occur
This makes it more difficult to write code
Processors can be programmed to ignore interrupts
We call this masking of interrupts
Different types of interrupts can be masked (IRQ vs. FIQ)
Steps in Interfacing
Methods of interfacing
a) I/O Mapped
b) Memory Mapped.
Output Mode
1)Display Scan
2) Display Entry
Command words.
Mohamed Ali Mazidi, Janice Gillispie Mazidi, The 8051 microcontroller and
embedded systems, Pearson education, 2004.