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ARINC 429
September 2011
Line Driver
output levels
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The +5V and A unity gain buffer receives the internally generated slopes
-5V levels are generated internally using a on-chip band- and differentially drives the ARINC line. Current is limited
gap reference. Currents for slope control are set by zener by the series output resistors at each pin. There are no
voltages across on-chip resistors. fuses at the outputs of the HI-8585 as exists on the
Hi-8382.
The TX0IN and TX1IN inputs receive logic signals from a
control transmitter chip such as the HI-6010, HI-3282 or The HI-8585 has 37.5 ohms in series with each output and
HI-8282. TXAOUT and TXBOUT hold each side of the the HI-8586 has 2 ohms in series with each output. The
ARINC bus at Ground until one of the inputs becomes a HI-8586 is for applications where external series resis-
One. If for example TX1IN goes high, a charging path is tance is required, typically for lightning protection devices.
enabled to 5V on an A side internal capacitor while the
B side is enabled to -5V. The charging current is se- Both the HI-8585 and HI-8586 are built using high-speed
lected by the SLP1.5 pin. If the SLP1.5 pin is high, the CMOS technology. Care should be taken to ensure the
capacitor is nominally charged from 10% to 90% in 1.5s. V+ and V- supplies are locally decoupled and that the
If SLP1.5 is low, the rise and fall times are 10s. input waveforms are free from negative voltage spikes
which may upset the chips internal slope control circuitry.
5V
A SIDE
ONE
TXAOUT
CURRENT
CONTROL HI-8585 = 37.5 OHMS
NULL HI-8586 = 2 OHMS
ZERO
-5V
TX0IN CONTROL
ESD LOGIC SLP1.5
PROTECTION
AND
VOLTAGE
5V
TX1IN
TRANSLATION B SIDE
ONE
TXBOUT
CURRENT
CONTROL HI-8585 = 37.5 OHMS
NULL HI-8586 = 2 OHMS
ZERO
-5V
CONTROL
LOGIC
5V
1
{
VCC
HARDWIRED 2 TESTA 6
ROUTA RXD1
OR 8
DRIVEN FROM LOGIC TESTB
ROUTB
7
RXD0
4 HI-8588
RINA
APPLICATION INFORMATION ARINC
Channel 3
HI-6010
RINB
Figure 2 shows a possible application 5
of the HI-8585/86 interfacing an ARINC
15V
transmit channel from the HI-6010. 8 BIT BUS
1 8
SLP1.5 V+
6 TXAOUT 3
TX1IN TXD1
ARINC
Channel 7 HI-8585 2
TXBOUT TX0IN TXD0
GND V-
4 5
-15V
DC ELECTRICAL CHARACTERISTICS
V+ = +12V to +15V, V- = -12V to -15V, T A = Operating Temperature Range (unless otherwise stated)
PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS
V+ = 15.0V, V- = -15V, T A = Operating Temperature Range (unless otherwise stated)
5V
pin 3 0V
t phlx
t plhx t plhx
5V
pin 2 0V
t phlx
t rx
t rx
90% 10V
VDIFF 10%
90%
10%
0V
pin 6 - pin 7
10% -10V
t fx
t fx
ORDERING INFORMATION
HI - 85XX xx x x
PART LEAD
NUMBER FINISH
PART PACKAGE
NUMBER DESCRIPTION
PD 8 PIN PLASTIC DIP (8P)
PS 8 PIN PLASTIC NARROW BODY ESOIC (8HNE)
CR 8 PIN CERDIP (8D) not available Pb-free
HI - 8585 PS I - N
PART LEAD
NUMBER FINISH
PART PACKAGE
NUMBER DESCRIPTION
PS 8 PIN PLASTIC NARROW BODY SOIC (8HN)
REVISION HISTORY
0 to 8
.0025 .002
(.064 .038)
.050 BSC .033 .017
BSC = Basic Spacing between Centers (1.27) (.838 .432)
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
DETAIL A
.194 .004
(4.92 .09)
.0085 .0015
(.216 .038)
See Detail A
.0165 .003
(.419 .089)
.055 .005
(1.397 .127)
0 to 8 .0069 .003
(.1753 .074)
BSC = Basic Spacing between Centers .050 BSC .033 .017
is theoretical true position dimension and (1.27) (.838 .432) Detail A
has no tolerance. (JEDEC Standard 95)
.385 .015
(9.799 .381)
.250 .010
(6.350 .254)
.100
BSC
(2.54)
.300 .010
(7.620 .254)
.025 .010
.135 .015
(.635 .254)
(3.429 .381)
.0115 .0035
.1375 .0125
(.292 .089)
(3.493 .318)
.055 .010 .335 .035
.019 .002 (1.397 .254) (8.509 .889)
(.483 .102)
BSC = Basic Spacing between Centers
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.380 .004
(9.652 .102)
.005 min
(.127 min)
.248 .003
(6.299 .076)