SOGIFLL Based Adaptive Filter for

DSTATCOM Under Variable Supply

Frequency
Journal of The Institution of Engineers (India): Series B

August 2017, Volume 98, Issue 4, pp 423431 | Cite as

Vishal Puranik (1)

Sabha Raj Arya (1) Email author (sabharaj1@gmail.com)View author's OrcID
profile (View OrcID profile)

1. Department of Electrical Engineering, Sardar Vallabhbhai National Institute of

Technology, Surat, India

Original Contribution
First Online: 08 December 2016
Received: 21 January 2015
Accepted: 24 November 2016

Abstract

This paper presents an adaptive filter based on second order generalized integrator
frequency locked loop (SOGIFLL) for distribution static compensator (DSTATCOM)
operating under variable supply frequency with nonlinear load. It is observed that
under variable supply frequency, the FLL provides an excellent frequency tracking
performance. Necessary compensation can be provided by DSTATCOM at any
frequency with the help of SOGIFLL. The MATLAB simulink model of DSTATCOM is
developed with SOGIFLL based control algorithm and rectifier based nonlinear load.
This three wire system is simulated in power factor correction and zero voltage
regulation mode under variable supply frequency.

Keywords

DC bus FLL SOGI Power factor correction Zero voltage regulation

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Introduction

DSTATCOM has been extensively used in the present era to mitigate power quality
issues in a distribution network [1]. DSTATCOM is a shunt connected device placed in
parallel with loads. It is used in a distribution system either to make power factor
correction at point of common coupling (PCC) or to improve its voltage profile [2, 3, 4].
Various topologies of DSTATCOM have been proposed in literature for three phase
three wire and three phase four wire distribution system [5, 6, 7, 8, 9]. Application of
DSTATCOM topologies depend upon type of supply system and required
compensation. Effective use of DSTATCOM depends on its power circuit design and
control algorithm [10].

Performance of DSTATCOM is extremely depends on its control algorithm used for

extraction of fundamental active load current component. Various control algorithm
has been proposed in literature including synchronous reference frame theory based
control algorithm, sliding mode control, instantaneous symmetrical component theory,
adaptive sinusoidal tracer and constant switching frequency current control algorithm
etc. [11, 12, 13, 14, 15]. George and Mishra [16] have analyzed use define current control
switching technique for DSTATCOM in four wire system. In this technique, three legs
of DSTACOM is switched using hysteresis current control and fourth leg is switched by
square switched pulses. Young and Dougal [17] have discussed synchronous reference
frame phase lock loop (SRF-PLL) for accurate phase detection for control of inverter
performance. It is most useful in weak three phase system where frequency is
continuously varying. Francisco Beltran-Carbajal [18] has discussed PLL based method
for grid voltage phase angle tracking for switches of converters. Rani et al. [19] have
proposed algorithm of frequency estimation for grid synchronization of converters.
They have made use of three phase PLL to detect frequency under wide range of grid
frequency variation. Ghartemani et al. [20] have discussed problems in PLL during
dynamic operation. This paper has suggested an adaptive phase-locked loop (PLL) to
soft start and avoids undesired frequency swings. Rodriguez et al. [21] have reported
multi resonant frequency locked loop for grid synchronization of power converters
under non ideal ac mains. This proposed frequency lock loop (FLL) system is able to
estimate sequence of harmonics. In this paper, FLL has been used in single and three
phase system. Other advance PLL used for grid synchronization are dual second order
generalized integratorFLL [22], second-order generalized integrator (SOGI) [23, 24].
In SOGI based system, generated orthogonal signals are filtered without causing delay.
It is used for extraction of phase, frequency and amplitude of input signal. An improved
SOGI is considered as SOGIFLL which is based on two adaptive filters [25]. It is used
for grid synchronization and is able to estimate instantaneous symmetrical components
very fast and accurate.

In this paper, an adaptive filter is implemented using second order generalized

integrator along with frequency lock loop (SOGIFLL) in the area of power quality. It is
used for the extraction of fundamental component of supply voltage where FLL detects
supply frequency. The conventional SOGI [24] structure is used to extract fundamental
components of load current where tuning frequency is provided by SOGIFLL. In the
SOGI structure, the is a centre frequency which determines quality of an extracted
signals ir and iq. These are in and quadrature phase outputs respectively. Hence under
varying supply frequency centre frequency of SOGI must be adapted to supply
frequency to achieve balanced and good quality signals. This frequency adaptation is
done by using FLL structure. Thus combination of SOGI and FLL becomes an adaptive
filter.

This algorithm provides fast and accurate extraction of fundamental component of load
current under variable supply frequency because of use of FLL. SOGIFLL structure
can detect fundamental component of supply voltage under distorted voltage
conditions. DSTATCOM performance is found to be satisfactory under adverse grid
condition. The excellent detection accuracy, fast dynamic performances are the features
of this control algorithm.

DSTATCOM Configuration

Figure 1 shows schematic of 3 leg VSC-based DSTATCOM connected to a three phase

three wire distribution system. The three phase uncontrolled rectifier based nonlinear
load having large inductance on dc side is fed by ac mains. The source impedance of ac
mains is considered as ZS. The Lf is an interfacing inductor used for reducing ripple
components in DSTATCOM current and to make it continuous. Series combination of
Rf Cf are connected at PCC in parallel with connected load. It is a first order high pass
passive filter used for filtering of higher order switching harmonics produced by voltage
source converter (VSC). Cdc is dc bus capacitor with voltage vdc, which is kept constant
by providing signal vdc to dc bus voltage control loop. PCC phase voltages (vsa, vsb, vsc),
load currents (iLa, iLb, iLc) and supply currents (isa, isb, isc) are sensed and given to control
algorithm as input signals. The DSTATCOM currents (ifa, ifb, ifc) are injected as required
for compensation of reactive and harmonic components of the load current generated
by the non linear load.

Fig. 1

Schematic diagram of 3 leg VSC-based DSTATCOM

Control Algorithm

Figure 2 shows the block diagram of SOGIFLL based adaptive control algorithm for
estimation of reference supply currents. In this algorithm, PCC voltages (vsa, vsb, vsc),
load currents (iLa, iLb, iLc) and supply currents(isa, isb, isc) are required for the estimation
of reference supply currents (isa , isb , isc ). Mathematical expressions used in control
algorithm for the extraction of various control signals are discussed in next section.

Fig. 2

Block diagram of an adaptive filtering based control used for DSTATCOM

Estimation of Unit Voltage Templates

Sensed PCC voltages (vsa, vsb, vsc) are used to calculate in phase and quadrature unit
templates as follow [15].


2(v2sa + v2sb + v2sc )
vt =
3
(1)

In phase unit templates with phase voltages (wsa, wsb, wsc) are calculated as,
vsa vsb vsc
wsa = , wsb = , wsc =
vt vt vt
(2)

Similarly, the quadrature unit templates (wqa, wqb, wqc) are calculated as,
(wpb + wpc ) (3wpa + wpb wpc ) (3wpa + wpb wpc )
wqa = , wqb = , wqc =
3 23 23
(3)

Extraction of Fundamental Active and Reactive Component

from Distorted Load Current and Supply Frequency

Sensed PCC phase voltages (vsa, vsb, vsc) are passed to SOGIFLL [25]. The SOGI
extracts only fundamental component of input supply voltage hence it makes this
control algorithm to work satisfactorily under distorted supply condition. The presence
of harmonics as well as switching noise due to VSC also gets filtered. The FLL estimates
tuned frequency for SOGI block in adaptive nature used in supply system. Because of
the non linear load, load current contains fundamental reactive component and
harmonic components along with fundamental active component. It is desired that
source should supply only fundamental component of active current and rest of the
components should be compensated by DSTATCOM. Another SOGI is used for the
extraction of active and reactive components of the load current while tuning frequency
for SOGI is provided by SOGIFLL. They are called as current SOGI and voltage SOGI
in further analysis to avoid confusion. Figure 3a, b shows a block diagram of SOGI and
SOGIFLL respectively.

Fig. 3

Block diagram of (a) SOGI and (b) SOGIFLL

Selection of Gain Parameter of SOGIs

The structure of SOGI is shown in Fig. 3a. Its transfer function (T.F) is written as,
ir (s) ks
T. F = = 2
iL (s) s + 2 + ks
(4)
where centre frequency is fed by FLL, for heal their grid conditions centre frequency
is 314 rad/s.

The gain parameter k decides dynamic response of SOGI. After considering the input
frequency constant and it is equal to 314 rad/s, the TF becomes
ir (s) 314ks
T. F = =
iL (s) s2 + 3142 + 314ks
(5)
Response of SOGI to step input for different values of k is observed as shown in Fig. 4.

Fig. 4

Step response of second order generalized integrator

It is found that for higher values of k, the dynamics of SOGI is faster but simultaneously
it affects its bandwidth. For lower values of k bandwidth is small hence better filtering
performance, on other hand larger values of k larger is bandwidth hence quality of
extracted frequency component becomes poor. The supply voltages normally do not
contain significant amount of distortion, hence value of k is chosen as 1.2 for voltage
SOGI. Another side, load current contains higher percentage of distortion under non
linear loading. Ensuring good dynamic response as well as good quality of an extracted
signal value of k is chosen as 0.9 for current SOGI.

Putting values for k = 1.2 TF for voltage SOGI becomes,

ir (s) 376.8s
T. F = =
iL (s) s + 3142 + 376.8s
2
(6)

Poles of TF come out as 188.4 + j251.2 and 188.4 j251.2 which are located on left
half of s-plane which ensures stable response.

Similarly, TF of current SOGI after putting value of k = 0.9 is written as,

ir (s) 282.6s
T. F = =
iL (s) s2 + 3142 + 282.6s
(7)

Poles of TF comes out as 141.3 + j 280.41 and 141.3 j 280.41, located on left half of
s-plane.
Selection of Gain Parameter of FLL

Figure 3b shows structure of SOGIFLL. The f is called as frequency error variable and
it is considered as product of qv1 and v. The average value of f is taken as positive
when < ff and negative when > ff. The feed ward variable (ff) is considered as
rated value of grid frequency in normal condition to speed up synchronous process.
Hence integral controller with gain () is used to cancel dc component and shifting
SOGI resonant frequency to match supply frequency [25]. Dynamic response of FLL
depends on gain (). In order to select value of , FLL is simulated for various values
of . Figure 5 shows frequency tracking performance of FLL for equal to 25, 50 and
100.
Fig. 5
 Response of FLL with different value of gain (). a = 25. b = 50. c
= 100

From Fig. 5, it can be seen that for higher value of response of FLL is faster. Further
increase in value of causes oscillations at edges where frequency changes occur.
Hence value of is chosen as 100.

Estimation of Supply Reference Currents

The ir and iq are fundamental active and reactive component of load currents. Their
RMS values are calculated in software. Average values of are calculated as for load
balancing operation as follow,
ira + irb + irc iqa + iqb + iqc
ir = and iq =
3 3
(8)

These signals pass through low pass filter and multiplied by 2 to get peak value. The
above averaging is done for load balancing operation under unbalance loading.

The reference dc voltage vdc and measured dc bus voltage are compared and voltage
error at rth sampling instant is calculated as,
vde (r) = vdc (r) vdc (r)
(9)

The dc bus voltage is regulated by using PI regulator. The output of PI controller at rth
sampling instant is expressed as,
idc (r) = idc (r 1) + kdp (vde (r) vde (r 1)) + kdi vde
(10)
where idc(r) considered as loss components of VSC. The kdp and kdi are the proportional
and integral gain constants of dc bus PI voltage controller.

Total active component of supply current (Ir) is calculated as,

Ir = ir + idc
(11)

Similarly in ZVR mode, PCC voltage is regulated by PI regulator. The output of PI

regulator at rth sampling instant is expressed as,
iqt (r) = iqt (r 1) + ktp (vte (r) vte (r 1)) + kti vte
(12)
where iqt(r) is per phase reactive component required to regulate PCC voltage drop.

Total reactive component of supply current (Iq) is calculated as,

Iq = iq + iqt
(13)

In phase and quadrature components of reference supply current are calculated as,
isap = Ir wsa , isbp = Ir wsb , iscp = Ir wsc
(14)
isaq = Iq wqa , isbq = Iq wqb , iscq = Iq wqc
(15)

Total supply reference currents are calculated as,

isa = isap + isaq , isb = isbp + isbq , isc = iscp + iscq
(16)

The sensed supply currents (isa, isb, isc) and reference supply currents isa , isb , isc are
compared for respective phases and current error components are used for generation
of gating signals for six IGBTs of VSC.

Results and Discussion

Simulink and Simscape Power System toolbox are used for modelling of
DSTATCOM with SOGIFLL based adaptive filtering control algorithm. The
performance of this time domain control algorithm is observed through simulation in
three phase system under nonlinear loads. The performance of control algorithm is
recorded under varying supply frequency as well as dynamic load conditions. Data
related for this implementation is given in Appendix.

Steady State Performance During Frequency Variation

from 50 to 60 Hz in PFC Mode

Figure 6 shows dynamic performance of DSTATCOM during change of supply

frequency from 50 to 60 Hz. This figure includes PCC voltage (vs), load currents (iLa, iLb
and iLc), DSTATCOM currents (ifa, ifb,ifc), dc bus voltage (vdc) and supply frequency ().
At time instant (t) = 1 s, supply frequency of ac main is changed from 50 to 60 Hz. It
can be seen that how fast FLL tracks to supply frequency within a cycle. The change in
frequency can be observed from load current as 6 cycles appears in 100 ms after t = 1 s.
The filtering performance of DSTATCOM is found satisfactory and unaltered during
60 Hz frequency, keeping supply current and voltage distortions (THDs) is 2.11 and
4.94% respectively. The FFT windows for THDs are shown in Fig. 7ac.
Fig. 6

Dynamic performance of DSTATCOM during change in frequency 50

60 Hz
Fig. 7
 FFT windows showing THD of (a) PCC phase voltage (b) load current (c)
supply current at 60 Hz supply frequency

Performance of DSTATCOM in PFC Mode

The dynamic performance of DSTATCOM in PFC mode is shown in Fig. 8. The

performance indices are PCC phase voltages (vs), supply currents (is), load currents (iLa,
iLb,iLc), DSTATCOM currents (ifa, ifb, ifc) and dc bus voltage (vdc) which are shown under
load injection at time (t) = 2.8 s.

Fig. 8

Dynamic performance of DSTATCOM during unbalance loading at 50 Hz

supply frequency in PFC mode

During time (t) = 2.72.8 s, load is unbalanced but still supply currents are balanced
which verifies load balancing operation of DSTATCOM. At time (t) = 2.8 s, phase b
load is injected, which results into dip in dc bus voltage but it gets recovered within few
cycles. It is observed that THD in phase voltages, supply currents are found to be 4.61
and 1.84% respectively where load current distortion is 28.07%. The harmonic spectra
is shown in Fig. 9ac. Table 1 compares performance of DSTATCOM under 50 and
60 Hz supply frequency which demonstrates the adaptive nature of this control
algorithm for power quality improvement during supply voltage frequency variations.
Fig. 9

FFT windows showing THDs at 50 Hz supply frequency. a PCC voltage. b

 Load current. c Supply current

Table 1

Performance of DSTATCOM under supply frequency variation in PFC mode

Performance parameters at Supply frequency Supply frequency

PFC mode (fs) = 50 Hz (fs) = 60 Hz

PCC phase voltage (V) THD 227.43 V, 4.61 227.15 V, 4.94

Load current (A) THD 41.42 A, 28.07 41.41 A, 27.57

Supply current (A) THD 41.64 A, 1.84 41.57 A, 2.11

Performance of DSTATCOM in ZVR Mode

In ZVR mode, the main objective is to regulate PCC voltage under dynamic or an
unbalance load conditions. DSTATCOM regulates PCC voltage by injecting an extra
leading VAR through ac bus PI regulator. In this mode, supply power factor at PCC
becomes slightly leading nature. Figure 10 shows dynamic performance of DSTATCOM
which is regulating the PCC voltage from 228.1 to 231.21 V under nonlinear loads. DC
bus voltage is also recovered within three cycles.
 Fig. 10

Dynamic performance of DSTATCOM in ZVR mode during unbalance

loading

In ZVR mode DSTACOM regulates PCC voltage along with harmonics elimination and
load balancing. Figure 11 demonstrates harmonic spectra of PCC voltage, load current
and supply current after compensation. In PFC and ZVR mode voltage and current
THD are within 5% as per IEEE standard 519 and performance of DSTACOM in ZVR
mode is indicated in Table 2.

Fig. 11

FFT windows showing THDs at 50 Hz supply frequency. a PCC voltage. b

load current. c Supply current

Table 2

Performance of DSTATCOM under ZVR mode at 50 Hz supply frequency

 Performance parameters (at ZVR mode) Supply frequency (fs) = 50 Hz
(%) (%)

PCC phase voltage (V), THD 230.55 V, 4.97

Load current (A), THD 41.35 A, 28.24

Supply current (A), THD 42.67 A, 2.01

Conclusion

An adaptive filter based control algorithm for DSTATCOM has been simulated in order
to improve performance of DSTATCOM under adverse grid conditions. An adaptive
filter is implemented by making use of SOGIFLL, which has satisfactory performance
of extracting desired frequency by tracking supply frequency. Performance of
DSTATCOM under changing frequency is observed and it remains almost constant with
different supply frequencies. Results indicate merits of control algorithm where supply
current THD remains within 5%. The performance of DSTACOM in PFC and ZVR
found satisfactory during load dynamics.

Appendix

AC supply: Three phase, 400 V(LL), 50 Hz; source impedance: Rs = 0.07 ,

Ls = 1.7 mH; Load-three phase diode rectifier fed RL load Ra = 10 , La = 100mH;
Ripple filter :Rf = 7 , Cf = 10 F; dc bus capacitance Cdc = 8000 F; Reference dc bus
voltage Vdc = 700 V; Interfacing inductors Lf = 2 mH; Gains of dc bus PI controller
kdp = 1.01, kdi = 0.9; Gains of PCC voltage PI controller ktp = 2.38, kti = 1.90, Cut off
frequency of low pass filter = 10 Hz.

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Cite this article as:
Puranik, V. & Arya, S.R. J. Inst. Eng. India Ser. B (2017) 98: 423. https://doi.org/10.1007/s40031-016-
0274-0

DOI (Digital Object Identifier) https://doi.org/10.1007/s40031-016-0274-0

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