Professional Documents
Culture Documents
IN+ + IN+ +
OUT OUT
IN IN
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N SEPTEMBER 1978 REVISED JULY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 TL07xBC, TL07xI ..................................................... 19
2 Applications ........................................................... 1 6.18 Typical Characteristics .......................................... 20
3 Description ............................................................. 1 6.1 Parameter Measurement Information ..................... 25
4 Revision History..................................................... 2 7 Detailed Description ............................................ 26
7.1 Overview ................................................................. 26
5 Pin Configuration and Functions ......................... 4
7.2 Functional Block Diagram ....................................... 26
6 Specifications....................................................... 10
7.3 Feature Description................................................. 27
6.1 Absolute Maximum Ratings .................................... 10
7.4 Device Functional Modes........................................ 27
6.2 ESD Ratings............................................................ 10
6.3 Recommended Operating Conditions..................... 10 8 Application and Implementation ........................ 28
8.1 Application Information............................................ 28
6.4 Thermal Information: TL071x.................................. 11
8.2 Typical Application .................................................. 28
6.5 Thermal Information: TL072x.................................. 11
8.3 Unity Gain Buffer..................................................... 29
6.6 Thermal Information: TL072x (cont.)....................... 11
8.4 System Examples ................................................... 30
6.7 Thermal Information: TL074x.................................. 11
6.8 Thermal Information: TL074x (cont)........................ 12 9 Power Supply Recommendations...................... 32
6.9 Thermal Information: TL074x (cont)........................ 12 10 Layout................................................................... 32
6.10 Electrical Characteristics: TL071C, TL072C, 10.1 Layout Guidelines ................................................. 32
TL074C .................................................................... 13 10.2 Layout Example .................................................... 33
6.11 Electrical Characteristics: TL071AC, TL072AC, 11 Device and Documentation Support ................. 34
TL074AC .................................................................. 14 11.1 Documentation Support ........................................ 34
6.12 Electrical Characteristics: TL071BC, TL072BC, 11.2 Related Links ........................................................ 34
TL074BC .................................................................. 15
11.3 Community Resources.......................................... 34
6.13 Electrical Characteristics: TL071I, TL072I,
TL074I ...................................................................... 16 11.4 Trademarks ........................................................... 34
6.14 Electrical Characteristics: TL071M, TL072M ........ 17 11.5 Electrostatic Discharge Caution ............................ 34
6.15 Electrical Characteristics: TL074M ....................... 18 11.6 Glossary ................................................................ 34
6.16 Switching Characteristics: TL07xM ....................... 19 12 Mechanical, Packaging, and Orderable
6.17 Switching Characteristics: TL07xC, TL07xAC, Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Updated data sheet text to latest documentation and translation standards ......................................................................... 1
Added TL072M and TL074M devices to data sheet ............................................................................................................. 1
Rewrote text in Description section ....................................................................................................................................... 1
Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table .................................................. 1
Deleted 20-pin LCCC package from Device Information table ............................................................................................. 1
Added 2017 copyright statement to front page schematic ..................................................................................................... 1
Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ........................ 4
Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................................... 5
Deleted differential input voltage parameter from Absolute Maximum Ratings table ......................................................... 10
Deleted table notes from Absolute Maximum Ratings table ............................................................................................... 10
Added new table note to Absolute Maximum Ratings table ................................................................................................ 10
Changed minimum supply voltage value from 18 V to 0.3 V in Absolute Maximum Ratings table ................................. 10
Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table ............................................... 10
Changed minimum input voltage value from 15 V to VCC 0.3 V in Absolute Maximum Ratings table........................... 10
Changed maximum input voltage from 15 V to VCC + 36 V in Absolute Maximum Ratings table....................................... 10
Added input clamp current parameter to Absolute Maximum Ratings table ....................................................................... 10
Changed common-mode voltage maximum value from VCC+ 4 V to VCC+ in the Recommended Operating
Conditions table .................................................................................................................................................................... 10
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
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Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section ........................................................................................................................................................... 1
Moved Typical Characteristics into Specifications section. ................................................................................................. 20
OFFSET N1 1 8 NC
IN 2 7 VCC+
IN+ 3 6 OUT
VCC 4 5 OFFSET N2
Not to scale
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1OUT 1 8 VCC+
1IN 2 7 2OUT
1IN+ 3 6 2IN
VCC 4 5 2IN+
Not to scale
TL072x U Package
10-Pin CFP
Top View
NC 1 10 NC
1OUT 2 9 VCC+
1IN 3 8 2OUT
1IN+ 4 7 2IN
VCC 5 6 2IN+
Not to scale
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
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TL072 FK Package
20-Pin LCCC
Top View
VCC+
1OUT
NC
NC
NC
3
20
19
NC 4 18 NC
1IN 5 17 2OUT
NC 6 16 NC
1IN+ 7 15 2IN
NC 8 14 NC
10
11
12
13
9
Not to scale
NC
VCC
NC
2IN+
1OUT 1 14 4OUT
1IN 2 13 4IN
1IN+ 3 12 4IN+
VCC+ 4 11 VCC
2IN+ 5 10 3IN+
2IN 6 9 3IN
2OUT 7 8 3OUT
Not to scale
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
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TL074 FK Package
20-Pin LCCC
Top View
1OUT
4OUT
1IN
4IN
NC
3
20
19
1IN+ 4 18 4IN+
NC 5 17 NC
VCC+ 6 16 VCC
NC 7 15 NC
2IN+ 8 14 3IN+
10
11
12
13
9
Not to scale
2IN
2OUT
NC
3OUT
3IN
NC- no internal connection
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC+ - VCC Supply voltage 0.3 36 V
(2)
VI Input voltage VCC 0.3 VCC + 36 V
IIK Input clamp current 50 mA
Duration of output short circuit (3) Unlimited
TJ Operating virtual junction temperature 150 C
Case temperature for 60 seconds - FK package 260 C
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 C
Tstg Storage temperature 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Differential voltage only limited by input voltage.
(3) The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the dissipation
rating is not exceeded.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) VCC+ and VCC are not required to be of equal magnitude, provided that the total VCC (VCC+ VCC) is between 10 V and 30 V.
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
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(3)
TA = 25C 65 200 pA
IIB Input bias current VO = 0
TA = Full range 7 nA
Common-mode input voltage
VICR TA = 25C 11 12 to 15 V
range
RL= 10 k TA = 25C 12 13.5
Maximum peak output
VOM RL 10 k 12 V
voltage swing TA = Full range
RL 2 k 10
Large-signal differential VO = 10 V TA = 25C 25 200
AVD V/mV
voltage amplification RL 2 k TA = Full range 15
B1 Utility-gain bandwidth TA = 25C 3 MHz
rI Input resistance TA = 25C 1012
VIC = VICR(min)
Common-mode rejection
CMRR VO = 0 TA = 25C 70 100 dB
ratio
RS = 50
VCC = 9 V to 15 V
Supply voltage rejection ratio
kSVR VO = 0 TA = 25C 70 100 dB
(VCC/VIO)
RS = 50
Supply current (each
ICC VO = 0; no load TA = 25C 1.4 2.5 mA
amplifier)
VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 dB
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0C to 70C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
(3)
TA = 25C 65 200 pA
IIB Input bias current VO = 0
TA = Full range 7 nA
Common-mode input voltage
VICR TA = 25C 11 12 to 15 V
range
RL= 10 k TA = 25C 12 13.5
Maximum peak output
VOM RL 10 k 12 V
voltage swing TA = Full range
RL 2 k 10
Large-signal differential VO = 10 V TA = 25C 50 200
AVD V/mV
voltage amplification RL 2 k TA = Full range 25
B1 Utility-gain bandwidth TA = 25C 3 MHz
rI Input resistance TA = 25C 1012
VIC = VICR(min)
CMRR Common-mode rejection ratio VO = 0 TA = 25C 75 100 dB
RS = 50
VCC = 9 V to 15 V
Supply-voltage rejection ratio
kSVR VO = 0 TA = 25C 80 100 dB
(VCC / VIO)
RS = 50
Supply current
ICC VO = 0; no load TA = 25C 1.4 2.5 mA
(each amplifier)
VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 dB
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0C to 70C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
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(3)
TA = 25C 65 200 pA
IIB Input bias current VO = 0
TA = Full range 7 nA
Common-mode input
VICR TA = 25C 11 12 to 15 V
voltage range
RL= 10 k TA = 25C 12 13.5
Maximum peak output
VOM RL 10 k 12 V
voltage swing TA = Full range
RL 2 k 10
Large-signal differential VO = 10 V TA = 25C 50 200
AVD V/mV
voltage amplification RL 2 k TA = Full range 25
B1 Utility-gain bandwidth TA = 25C 3 MHz
rI Input resistance TA = 25C 1012
VIC = VICR(min)
Common-mode rejection
CMRR VO = 0 TA = 25C 75 100 dB
ratio
RS = 50
VCC = 9 V to 15 V
Supply-voltage rejection
kSVR VO = 0 TA = 25C 80 100 dB
ratio (VCC/VIO)
RS = 50
Supply current (each
ICC VO = 0; no load TA = 25C 1.4 2.5 mA
amplifier)
VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 dB
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0C to 70C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
(3)
TA = 25C 65 200 pA
IIB Input bias current VO = 0
TA = Full range 7 nA
Common-mode input voltage
VICR TA = 25C 11 12 to 15 V
range
RL= 10 k TA = 25C 12 13.5
Maximum peak output
VOM RL 10 k 12 V
voltage swing TA = Full range
RL 2 k 10
Large-signal differential VO = 10 V TA = 25C 50 200
AVD V/mV
voltage amplification RL 2 k TA = Full range 25
B1 Utility-gain bandwidth TA = 25C 3 MHz
rI Input resistance TA = 25C 1012
VIC = VICR(min)
Common-mode rejection
CMRR VO = 0 TA = 25C 75 100 dB
ratio
RS = 50
VCC = 9 V to 15 V
Supply-voltage rejection ratio
kSVR VO = 0 TA = 25C 80 100 dB
(VCC/VIO)
RS = 50
Supply current (each
ICC VO = 0; no load TA = 25C 1.4 2.5 mA
amplifier)
VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 dB
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) TA = 40C to 85C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
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(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be
used.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = 55C to +125C.
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be
used .
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = 55C to +125C.
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
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Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
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100 15
VCC = 15 V VCC = 15 V RL = 10 k
10
10
VCC = 10 V
1 7.5
5 VCC = 5 V
IIIB
0.1
2.5
VOM
0.01
0
75 50 25 0 25 50 75 100 125 100 1k 10 k 100 k 1M 10 M
TA Free-Air Temperature C f Frequency Hz
Figure 1. Input Bias Current vs Free-Air Temperature Figure 2. Maximum Peak Output Voltage vs Frequency
15
RL = 2 k
VOM Maximum Peak Output Voltage V
VCC = 15 V TA = 25C
12.5 See Figure 2
10
VCC = 10 V
7.5
5
VCC = 5 V
VOM
2.5
8
0
100 1k 10 k 100 k 1M 10 M
f Frequency Hz
Figure 3. Maximum Peak Output Voltage vs Frequency Figure 4. Maximum Peak Output Voltage vs Frequency
15 15
RL = 10 k
VCC = 15 V
OM Maximum Peak Output Voltage V
TA = 25C
12.5 12.5 See Figure 2
RL = 2 k
10 10
7.5 7.5
5 5
2.5 2.5
VOM
VOM
VCC = 15 V
8 8
V
See Figure 2
0 0
75 50 25 0 25 50 75 100 125 0.1 0.2 0.4 0.7 1 2 4 7 10
TA Free-Air Temperature C RL Load Resistance k
Figure 5. Maximum Peak Output Voltage vs Free-Air Figure 6. Maximum Peak Output Voltage vs Load
Temperature Resistance
TA = 25C 400
12.5
VD Large-Signal Differential
Voltage Amplification V/mV
200
10 100
40
7.5
20
5 10
AAVD
4 VCC = 15 V
2.5
VOM
VO = 10 V
2 RL = 2 k
0 1
0 2 4 6 8 10 12 14 16 75 50 25 0 25 50 75 100 125
|VCC| Supply Voltage V TA Free-Air Temperature C
Figure 7. Maximum Peak Output Voltage vs Supply Figure 8. Large-Signal Differential Voltage Amplification vs
Voltage Free-Air Temperature
1.3 1.03
Phase Shift 1
1
0.9 0.99
VCC = 15 V
0.8 0.98
RL = 2 k
f = B1 for Phase Shift
0.7 0.97
75 50 25 0 25 50 75 100 125
TA Free-Air Temperature C
Figure 9. Large-Signal Differential Voltage Amplification Figure 10. Normalized Unity-Gain Bandwidth and Phase
and Phase Shift vs Frequency Shift vs Free-Air Temperature
89 2
VCC = 15 V
CMRR Common-Mode Rejection Ratio dB
TA = 25C
ICC Supply Current Per Amplifier mA
RL = 10 k 1.8 No Signal
88 No Load
1.6
1.4
87
1.2
86 1
0.8
85
0.6
0.4
84
I CC
0.2
83 0
75 50 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TA Free-Air Temperature C |VCC| Supply Voltage V
Figure 11. Common-Mode Rejection Ratio vs Free-Air Figure 12. Supply Current Per Amplifier vs Supply Voltage
Temperature
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1.4 175
TL074
1.2 150
1 125
0.8 100
TL072
0.6 75
0.4 50 TL071
I CC
0.2 25
0 0
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125
TA Free-Air Temperature C TA Free-Air Temperature C
Figure 13. Supply Current Per Amplifier vs Free-Air Figure 14. Total Power Dissipation vs Free-Air
Temperature Temperature
50
nV/ Hz
VCC = 15 V
30
20
10
0
10 40 100 400 1 k 4 k 10 k 40 k 100 k
f Frequency Hz
Figure 15. Normalized Slew Rate vs Free-Air Temperature Figure 16. Equivalent Input Noise Voltage vs Frequency
1 6
VCC = 15 V VCC = 15 V
VI and VO Input and Output Voltages V
AVD = 1 RL = 2 k
0.4
THD Total Harmonic Distortion %
VI(RMS) = 6 V 4 CL = 100 pF
TA = 25C TA = 25C
Output
0.1 2
0.04
0
0.01 2
Input
0.004
4
0.001 6
100 400 1k 4 k 10 k 40 k 100 k 0 0.5 1 1.5 2 2.5 3 3.5
f Frequency Hz t Time s
Figure 17. Total Harmonic Distortion vs Frequency Figure 18. Voltage-Follower Large-Signal Pulse Response
VIO (mV)
0
-2
-4
-6
-8
-10
-13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 17
VCM (V) D003
Figure 19. Output Voltage vs Elapsed Time Figure 20. VIO vs VCM
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OUT
VI +
CL = 100 pF RL = 2 k
10 k
1 k
VI
OUT
+
RL CL = 100 pF
7 Detailed Description
7.1 Overview
The JFET-input operational amplifiers in the TL07xx series are similar to the TL08x series, with low input bias
and offset currents, and a fast slew rate. The low harmonic distortion and low noise make the TL07xx series
ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high
input impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for
operation from 40C to +85C. The M-suffix devices are characterized for operation over the full military
temperature range of 55C to +125C.
VCC+
IN+
IN 64
128
OUT
64
C1
18 pF
1080 1080
VCC
OFFSET OFFSET
N1 N2
TL071 Only
All component values shown are nominal.
COMPONENT COUNT
COMPONENT
TL071 TL072 TL074
TYPE
Resistors 11 22 44
Transistors 14 28 56
JFET 2 4 6
Diodes 1 2 4
Capacitors 1 2 4
epi-FET 1 2 4
Includes bias and trim circuitry
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
RI Vsup+
VOUT
+
VIN
Vsup-
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0.5
Volts
-0.5
-1
-1.5
-2
0 0.5 1 1.5 2
Time (ms)
Figure 25. Input and Output Voltages of the Inverting Amplifier
U1 TL072
+
VIN + VOUT
+ 10 k
12
12 1.5
10 1
8 0.5
Gain (V/V)
VOUT (V)
6 0
4 -0.5
2 -1
0 -1.5
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) D001
VIN (V) D002
Figure 27. Output Voltage vs Input Voltage Figure 28. Gain vs Input Voltage
VCC+
R1 R2
Input + Output
C3 VCC
R1 = R2 = 2R3 = 1.5 MW
R3 C3
C1 C1 C1 = C2 = = 110 pF
2
1
fo = = 1kHz
2p R1 C1
Figure 30. High-Q Notch Filter
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CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of 18 V for a
dual-supply can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
10 Layout
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RIN
VIN +
VOUT
RG
RF
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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www.ti.com 2-Jun-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
81023052A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023052A
TL072MFKB
8102305HA ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 8102305HA
TL072M
8102305PA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8102305PA
TL072M
81023062A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023062A
TL074MFKB
8102306CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306CA
TL074MJB
8102306DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306DA
TL074MWB
JM38510/11905BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/11905BPA
M38510/11905BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/11905BPA
TL071ACD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071AC
& no Sb/Br)
TL071ACDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071AC
& no Sb/Br)
TL071ACDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071AC
& no Sb/Br)
TL071ACP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL071ACP
(RoHS)
TL071ACPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL071ACP
(RoHS)
TL071BCD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071BC
& no Sb/Br)
TL071BCDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071BC
& no Sb/Br)
TL071BCDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071BC
& no Sb/Br)
TL071BCDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 071BC
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL072MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8102305PA
TL072M
TL072MUB ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 8102305HA
TL072M
TL074ACD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACN ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL074ACN
(RoHS)
TL074ACNE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL074ACN
(RoHS)
TL074ACNSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074A
& no Sb/Br)
TL074BCD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
& no Sb/Br)
TL074BCDE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
& no Sb/Br)
TL074BCDG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
& no Sb/Br)
TL074BCDR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
& no Sb/Br)
TL074BCDRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
& no Sb/Br)
TL074BCDRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
& no Sb/Br)
TL074BCN ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL074BCN
(RoHS)
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL074MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023062A
TL074MFKB
TL074MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL074MJ
TL074MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306CA
TL074MJB
TL074MWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306DA
TL074MWB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2017
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Apr-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Apr-2017
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Apr-2017
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL074ACDR SOIC D 14 2500 333.2 345.9 28.6
TL074ACNSR SO NS 14 2000 367.0 367.0 38.0
TL074BCDR SOIC D 14 2500 333.2 345.9 28.6
TL074CDR SOIC D 14 2500 333.2 345.9 28.6
TL074CDRG4 SOIC D 14 2500 333.2 345.9 28.6
TL074CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TL074IDR SOIC D 14 2500 333.2 345.9 28.6
Pack Materials-Page 3
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
7 8
C SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A
1 14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
7 8
SYMM
METAL
4214771/A 05/2017
www.ti.com
MECHANICAL DATA
0.400 (10,16)
0.355 (9,00)
8 5
0.280 (7,11)
0.245 (6,22)
1 4
0.065 (1,65)
0.045 (1,14)
0.023 (0,58)
015
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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