1294 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO.

4, APRIL 2017

A Self-Biased Mixer in 0.18m CMOS

for an Ultra-Wideband Receiver
Darshak Bhatt, Graduate Student Member, IEEE, Jayanta Mukherjee, Senior Member, IEEE,
Jean-Michel Redout, Senior Member, IEEE

Abstract A self-biased CMOS analog mixer for ultra-

wideband (UWB) applications is presented in this paper. The
proposed mixer is complementary and self-biased, and has lower
power consumption, superior isolation, and larger bandwidth.
The proposed low-power, down conversion mixer is designed and
fabricated in UMC 0.18m CMOS technology. The measurement
results show that it can operate at UWB frequencies that range
from 1 to 6 GHz. The proposed mixer provides a maximum
conversion gain of 13 dB, 4.5 dBm of third-order input intercept
point, and a minimum double sideband noise figure of 12 dB.
The maximum values of the measured local oscillator LO-to-
RF, RF-to-IF, and LO-to-IF isolations are 50, 45, and 52 dB,
respectively.
Index Terms Mixer common mode rejection ratio (MCMRR),
mixer feedthrough, mixer linearity, self-biased mixer, ultra-
wideband (UWB).

I. I NTRODUCTION

A CMOS mixer is an essential component in various

applications that requires mixing, phase-difference detec-
tion, modulationdemodulation, and frequency translation. Fig. 1. The proposed self-biased mixer.

The important features of the mixer are the conversion

efficiency, isolation between the inputs and the output, power
consumption, linearity, and noise. Recent developments in
mixer design focus on ultra-wideband (UWB) applications
with lesser power consumption, increased linearity, and lower
noise figure (NF). Earlier reported works report UWB mixers
with on-chip LC resonant circuitry [1], [2]. However, these
circuits occupy a large chip area. The mixer presented in [3]
uses a bulk local oscillator (LO) injection method, which
increases the noise of the mixer. Similarly, [4] has proposed an
improved bulk LO injection mixer with lower NF. However,
it still shows a low third-order input intercept point (IIP3).
Another important parameter in mixers is the isolation between
mixer ports. Due to the stringent requirements of orthogonal
frequency-division multiplexing [5] and UWB applications,
the isolation between mixer ports should be as high as possible.
Manuscript received July 2, 2016; revised October 6, 2016; accepted
November 20, 2016. Date of publication January 23, 2017; date of current
version April 3, 2017. This work was supported in part by the IITB-Monash
Research Academy, by the Government of India, by the Intel Corporation,
and by the Tata Center for Technology and Design at IIT Bombay.
D. Bhatt is with the IITB-Monash Research Academy, IIT Bombay, Bombay
400076, India (e-mail: darshak.bhatt@iitb.ac.in).
J. Mukherjee is with the Department of Electrical Engineering, IIT Bombay,
Bombay 400076, India.
J.-M. Redout is with the Department of Electrical and Computer Systems
Engineering, Monash University, Clayton, VIC 3800, Australia.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2016.2640949
0018-9480 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
As proposed in [6], the isolation depends on the circuit sym-
metry. Generally, this symmetry is measured by parameters
such as common mode rejection ratio (CMRR).
In this paper, a self-biased fully differential mixer with
an integrated quadrature multiplication circuit is described.
The proposed mixer is not only self-biased but the biasing
is also switched, which lowers the flicker noise produced by
the mixer [7]. This approach of multiplication-based design
achieves better performance when compared with conventional
mixer circuits. We have provided a detailed derivation of the
proposed mixer CMRR (MCMRR) in this paper.
This paper is divided into five sections. Section II describes
the operating principle of the proposed mixer. Section III
describes the derivation of various parameters, such as con-
version gain (CG), NF, isolation, and linearity. In Section IV,
the measured results are discussed in detail. Finally, Section V
concludes this paper.
II. P ROPOSED M IXER C ORE
The proposed self-biased mixer incorporates a quadrature
multiplying circuit with self-biasing in a fully complementary
configuration. The proposed self-biased mixer is shown in
Fig. 1. It has a stacked configuration with nMOS and pMOS
transistors to provide the multiplication operation. The mixer
consists of four inverters M1M8 whose currents are varied
by four transistors M9M12 to achieve multiplication between
BHATT et al.: SELF-BIASED MIXER IN 0.18m CMOS FOR UWB RECEIVER 1295

Fig. 2. The proposed self-biased mixer working principle.

the VLO and VRF inputs. As shown in Fig. 1, the biasing of the
mixer is generated by connecting the circuit output nodes to
the gate of the tail transistors. This stabilizes the bias voltage
of the entire mixer.
The working principle of the proposed mixer is explained
+
in Fig. 2. When the differential input voltage (VLO VLO )
is large, the transistor pairs M1M3 and M2M4 operate as
switches. During the first half cycle of the input signal, the
transistors M1 and M4 are turned ON and M2 and M3 are
turned OFF. So, the equivalent small signal current i y ( v RF ) Fig. 3. (a) The single-balanced mixer. (b) Single-balanced equivalent circuit
generated by transistors M11 and M9 is passed through the of the proposed self-biased mixer.
differential load R L . Similarly, during the negative half cycle,
transistors M2 and M3 are turned ON and the small signal
The overall G m of the proposed self-biased mixer is given by
current generated by transistors M9 and M11 is passed through
G m = gmRFn + gmRFp , and the load of the circuit, G load =
the load. The proposed mixer output is expressed as [8]:
goLOn + goLOp. So, the overall CG of the self-biased mixer (in
 Fig. 1) is given by:
 
VIF = 2(n1 + p3 )(n9 + p11 )VRF VLO Rload , (1) 2 gm9 + gm11
CG = . (3)
go1 + go3 + go5 + go7
where n = n Cox Wn /L n , p = p Cox W p /L p , and Rload =
(ro1 ||ro3 ||ro5||ro7 ). This equation is valid for a small signal Where gm9 and gm11 are the input transconductances of the
that is applied to the mixer. RF input transistors M9 and M11, respectively. Similarly,
go1, go3, go5 , and go7 are the output conductances of the LO
input transistors M1, M3, M5, and M7, respectively. Fig. 3(a)
III. P ROPOSED M IXER PARAMETERS
shows a conventional single-balanced mixer with capacitance
There are basically two kinds of mixer topologies that are C P appearing at high frequencies at node P. This capacitance
widely studied and discussed in the literature: transconduc- limits the mixer operation at higher frequencies and reduces
tance switch (GmSw) [9] and the switched transconductance the CG of the mixer. The CG of this mixer considering the
(SwGm) [10]. The proposed mixer is connected in a GmSw C P effect is given by:
configuration. As shown in Fig. 1, the RF signal applied at 2 gm2
VRF (= VRF+
VRF
) of the mixer core is converted to an CG = gm1 R D . (4)
gm2 + j C P
equivalent gm v RF current and multiplied by the LO switching
actions carried out by transistors M1M8 of the mixer core. Fig. 3(b) shows the single-balanced equivalent circuit of the
The derivation of the various mixer performance parameters, proposed self-biased mixer. The modified CG of the proposed
such as CG, feedthrough, NF, and linearity, is explained in mixer is given from (4) as:
Sections III-AIII-D. 2 Gm G mLO
CG = . (5)
G load G mLO + j C P
A. Conversion Gain Where G mLO = gm1 + gm3 and C P = C p9 + C p11 . As shown
in Fig. 3(b), G m of the circuit is equal to gm /gm Z s + 1 and
The proposed self-biased mixer is complementary in nature. G load is equal to 1/G load = Z load = ro /1 + sCo ro . The CG
This means that the CG is double that of a conventional Gilbert in (5) is, therefore, rewritten as:
cell mixer. The CG of a Gilbert cell mixer is given by:
2 gm (1 + sCs Rs ) ro G mLO
2 Gm CG = . (6)
CG = . (2) 1 + gm R S + sCs Rs 1 + sCoro G mLO + j C P
G load
1296 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 4, APRIL 2017
Fig. 4. Simulated and calculated CG of the proposed mixer.
TABLE I
VALUES OF PARAMETERS
Fig. 5. Equivalent circuit for the feedthrough calculations of the proposed
mixer.
As explained in [11], the capacitive degeneration introduced
by Z s increases the effective gm of the proposed mixer at
higher frequencies. The poles and the zeros of the proposed
design depend on the values of Z load , Z s , C P , and gm of
the transistors. Equation (7) is plotted in Fig. 4 by using
the parameters that are tabulated in Table I. It shows that
the calculated results follow the simulation results closely.
The tabulated parameters are calculated during the initial bias
conditions. The difference in the plots is due to the parasitics
that are not captured in the calculated parameters.
Fig. 6. Monte Carlo Simulation of the MCMRR of (a) the proposed mixer
and (b) Gilbert cell mixer.
Fig. 7. Calculated MCMRR compared with that of the designed Gilbert cell
mixer.
B. Feedthrough
The proposed mixer that is shown in Fig. 1 is symmetrical.
In a conventional Gilbert cell mixer, either nMOS or pMOS
transistors act as the LO switch. However, in the proposed
mixer, the CMOS inverter acts as the LO switch. Thus,
the ac currents generated by the incoming RF signals in
the transistors M9 and M11 are switched by the CMOS
inverter, which improves the switching in the proposed mixer.
Eventually, due to better switching in the mixer, the CM
components that appear at the output are reduced. Hence, the
proposed mixer achieves an improved isolation compared with
the conventional Gilbert cell. The isolation parameter of the
proposed mixer is analyzed by evaluating the CMRR. The
CMRR of the differential amplifier indicates the amount of
BHATT et al.: SELF-BIASED MIXER IN 0.18m CMOS FOR UWB RECEIVER 1297

Fig. 10. Simulated NF of the proposed self-bias mixer with fixed-biasing

and with switched biasing.

Fig. 8. Equivalent schematic for the NF calculation.

Fig. 11. Micrograph of the proposed self-biased mixer.

Fig. 9. Measured, simulated, and calculated NF of the proposed mixer.

CM signal that is appearing at the differential output. From

Fig. 5, the MCMRR calculations for the proposed mixer are
as follows [6]:

VIF = VIFP VIFN

[(gm9 + gm11) (gm10 + gm12 )]
=
[1 + (gm9 + gm10 + gm11 + gm12 )Z ssRF ]
2
VinCMRF . (7)
G load

The RF CM-to-IF differential mode rejection is defined as Fig. 12. Designed PCB of the proposed self-biased mixer.
MCMDM :

VIF
MCMDM = given by:
VinCMRF
[(gm9 + gm11 ) (gm10 + gm12 )]
=
[1 + (gm9 + gm10 + gm11 + gm12 )Z ssRF ] (gm9 + gm11 ) + (gm10 + gm12 )
2
. (8) + 4(gm9 + gm11 )(gm10 + gm12 )Z ssRF
G load MDM =
1 + (gm9 + gm10 + gm11 + gm12 ) Z ssRF
1
The differential gain, by considering all the transcon- . (9)
ductances of the input transistors to be nonidentical is G load
1298 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 4, APRIL 2017

TABLE II
CPW PARAMETERS

Fig. 13. Block diagram of the test setup using PCB.

TABLE III
T EST PARAMETERS

The MCMRR is then defined as: Fig. 14. (a) S11 plots of the RF and LO input. (b) S11 plot of the IF output.
 
 MDM 
MCMRR =  
M 
CMDM
(gm9 + gm11 ) + (gm10 + gm12 )
+ 4(gm9 + gm11 )(gm10 + gm12 )Z ssRF
= .
2[(gm9 + gm11) (gm10 + gm12 )]
(10)

Similarly, for the Gilbert mixer, the MCMRR is calculated as

[see the Appendix, (A9)]:
gm1 + gm2 + 4gm1 gm2 Z ssRF
MCMRR Gilbert = . (11)
2(gm1 gm2 )
In order to compare the MCMRR, the Gilbert cell mixer is
designed by keeping the power consumption identical to that of
the proposed self-biased mixer. The MCMRR of the proposed
mixer and the designed Gilbert cell mixer is simulated using
the Monte Carlo methods in Cadence. The simulations of Fig. 15. CG variation with change in IF when the LO input is at 7 dBm
and the RF frequency is at 3 GHz.
the CM gain are carried out by applying CMRF and CMLO
signals. The Monte Carlo CMRR simulation data with 1000
samples and RF input at 4 GHz is shown in Fig. 6. It can between ports is higher in the self-biased mixer compared with
be seen that the proposed mixer MCMRR is higher than that of the conventional Gilbert cell mixer.
that of the Gilbert cell mixer. For the calculation of the
MCMRR, the values of the transconductances of the input
transistors are taken from the Monte Carlo simulation results. C. Noise Figure
The Z ssRF (= Z s ) value is the same as that mentioned in the The NF of the proposed mixer depends on three sources of
CG equations. Equations (10) and (11) are plotted by assuming noise. These are the noise sources from the transconductance
that the transconductances are not equal and shown in Fig. 7. stage (M9M12), from the switching stage, and from the
It shows that the calculated MCMRR of the proposed mixer is load stage (M1M8). The calculation of the thermal NF has
higher than that of the Gilbert cell mixer. Thus, the isolation been done using the method explained in [12]. Referring to
BHATT et al.: SELF-BIASED MIXER IN 0.18m CMOS FOR UWB RECEIVER 1299

Fig. 16. CG variation with change in the RF input frequency when the LO Fig. 19. Measured third-order intermodulation (IIP3) plot of the proposed
input is at 7 dBm and the IF band is at 170 MHz. self-biased mixer.

Fig. 20. Measured isolations between the RF, LO, and IF ports.
Fig. 17. CG versus LO input power at an RF input of 3 GHz and an IF
at 170 MHz.

2 . So, the
source from the switching stage is given by Vn,Sw
noise output at node Z+ is derived as:
1 2  2
2
Vn,z+ = In,M9 + In,M11
2 + Vn,Sw
2 C 2p 2 Z load , (12)
2
which translates to

1
2
Vn,z+ = 4kT gm9 + 4kT gm11
2

4kT 2 2 2
+ (C p9 + C p11 ) Z load . (13)
(gm1 + gm3 )
Let T represent the fractional period during which the
switching transistors (M1M8) behave as a differential circuit.
The output differential noise that is generated by the switching
CMOS pair is given by:
2
Vn,diffSw = 2[4kT (gm1 + gm3 )(ro1 ||ro3 )]. (14)
Fig. 18. Measured NF versus the IF frequency.
As explained in [12], the noise due to the switching LO
differential pair is weighted by a factor of 2(= 2T /TLO ),
2
Fig. 8: the two RF noise current sources In,M9 2
and In,M11 are and the noise generated by RF transconductance stage and
generated by transistors M9 and M11, respectively. The noise switching stage is weighted by a factor of (1-2). The total
1300 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 4, APRIL 2017
Fig. 21. Measured MCMRR versus RF input frequency.
Fig. 22. Equivalent Gilbert cell mixer for MCMRR calculation.
input referred noise is therefore given by:
(1 2)Vn,z+
2 + 2Vn,2 diffSw
2 =
Vn,in , (15)
(1 2)2 CG2
2
Vn,in
NF = 1 + . (16)
2
Vn,R s
The NF of the proposed mixer is shown in Fig. 9 with
equal to 0.1. It also shows the measured and simulated NF
of the proposed mixer. The measured and simulated NF of
the proposed design follows the calculated values closely. The
initial parameter values for calculating the NF of the proposed
mixer are obtained from the data in Table I. The NF of
the proposed circuit will further reduce due to the switched
biasing technique employed. As explained in [4], [7], and [13],
the switched biasing will improve the noise performance
and reduce the MOSFET flicker noise. Fig. 10 shows the
comparison between the simulated NF of the proposed mixer
for both the fixed-bias and switched-bias cases.
D. Linearity
The linearity of the mixer is dependent on the overdrive
voltage of the RF input transistors. When stacking multiple
transistors, it is difficult to achieve a higher overdrive voltage
with a limited supply voltage. This can limit the ability of this
circuit to provide high linearity at a lower supply voltage.
IV. M EASUREMENT OF THE P ROPOSED M IXER
The proposed mixer shown in Fig. 1 was fabricated in
the 180-nm RFCMOS process provided by UMC, Taiwan.
A micrograph of the fabricated chip is shown in Fig. 11. The
area, including the pads of the chip, is 819 m 665 m. The
circuit is self-biased such that all transistors except M13M16
remain in saturation. A PCB has been designed specifically
to test the proposed self-biased mixer up to 6 GHz. The
fabricated PCB with the packaged die connected is shown
in Fig. 12. The PCB tracks have been designed as coplanar
waveguides (CPWs). An external termination resistance of
50  was connected to provide input matching at the LO and
the RF ports over a wide frequency band. The CPW linewidth
is calculated using the technique mentioned in [14]. The CPW
line parameters are shown in Table II. The block diagram of
the mixer test setup is shown in Fig. 13. The differential signals
were produced by using wide bandwidth baluns connected to
the RF and LO inputs and at the IF output. The RF transistor
inputs were biased using a bias tee connected between the
signal input and the inputs of the SMA connectors of the PCB.
The test parameters are tabulated in Table III. The testing
of the proposed mixer is carried out at room temperature.
Moreover, the typical corner of the device has been considered
while characterizing the proposed mixer. The current drawn
by the proposed self-biased mixer, including the buffer during
test was 7 mA from the 1.8 V supply, when the input RF
transistors are biased at 0.9 V. The power consumption of the
mixer core excluding the buffer is 3.45 mW when a 1.8 V
supply is provided. The input reflection coefficients (S11 ) at
the RF, LO, and IF ports are shown in Fig. 14. The S11 values
measured at the RF and LO input ports are less than 10 dB
for the band that spanned from 1 to 10 GHz. The S11 values
measured at the IF output port are less than 10 dB for an IF
frequency range from 10 to 500 MHz.
The measured and simulated CG at 3 GHz RF input with
variation in IF frequencies between 40 and 500 MHz is shown
in Fig. 15. It can be observed that the measured CG of the
proposed mixer is around 13 dB until 170 MHz. The CG
of the proposed mixer drops at higher IF frequencies. The
3-dB IF bandwidth for the proposed mixer is measured to be
around 500 MHz. The simulated and measured CG at various
RF input frequencies and at IF of 170 MHz is shown in
Fig. 16. The measured gain of the proposed mixer is between
10 and 13 dB for an RF band between 1 and 6 GHz. Fig. 17
shows the CG variation with change in the LO input power
at 3 GHz RF input and 170 MHz IF output. The measured NF
plotted at various IF values is shown in Fig. 18. The NF of the
proposed mixer is between 12 and 15.5 dB when the RF input
is between 2 and 4 GHz. The linearity of the proposed mixer
was measured using a two-tone analysis. Fig. 19 shows the
BHATT et al.: SELF-BIASED MIXER IN 0.18m CMOS FOR UWB RECEIVER 1301

TABLE IV
P ERFORMANCE S UMMARY

measured IIP3. The maximum IIP3 observed for the proposed across impedance Z ssRF .
mixer is 4.5 dBm at 6 GHz RF input, 170 MHz IF output,
and LO input power at 7 dBm. (VinCMRF VpRF )
The measured LO-RF, LO-IF, and RF-IF isolations are 1
= VinCMRF , (A2)
shown in Fig. 20. The maximum isolations observed between 1 + (gm1 + gm2 )Z ssRF
ports: RF-to-IF is 45 dB, LO-to-RF is 50 dB, and LO-to-IF 2 gm1 1
is 52 dB. The measured MCMRR for various RF input VIFP = VinCMRF . (A3)
G load 1 + (gm1 + gm2 )Z ssRF
frequencies with the IF at 170 MHz and the LO input power 2 gm2 1
at 7 dBm is shown in Fig. 21. The CMRF and the CMLO VIFN = VinCMRF . (A4)
G load 1 + (gm1 + gm2 )Z ssRF
for the MCMRR measurement were provided by using a
power divider. The measured results of the proposed mixer are From (A3) and (A4), the output IF voltage is given by:
summarized and compared with other state-of-the-art mixers
in Table IV. This mixer can operate over a wide bandwidth of VIF = VIFP VIFN
6 GHz, and also consumes lower power. gm1 gm2 2
= VinCMRF . (A5)
1 + (gm1 + gm2 )Z ssRF G load
V. C ONCLUSION The CM component that appears at the output is defined as:
A self-biased CMOS mixer designed in the UMC VIF
0.18m technology is presented in this paper. The mixer is a MCMDM =
VinCMRF
complementary, symmetrical self-biased circuit. It consumes gm1 gm2 2
3.45 mW of power and operates between 1 and 6 GHz. = . (A6)
1 + (gm1 + gm2 ) Z ssRF G load
The measurement results show that for the proposed mixer,
a maximum CG of 13 dB, a maximum IIP3 of 4.5 dBm, The differential gain of the Gilbert cell mixer is given by:
a minimum NF of 12 dB, and more than 45 dB of isolation
2 Gm
across a frequency band that spans between 1 and 6 GHz, can MDM = , (A7)
be obtained. This makes the proposed mixer highly suitable G load
for UWB RF applications. where equivalent G m = 1/2((gm1 + gm2 + 4gm1 gm2 Z ssRF )/
(1 + (gm1 + gm2 )Z ssRF )). Therefore, the MDM is rewritten as:
A PPENDIX gm1 + gm2 + 4gm1 gm2 Z ssRF 1
MCMRR D ERIVATION OF THE G ILBERT C ELL M IXER MDM = . (A8)
1 + (gm1 + gm2 ) Z ssRF G load
Fig. 22 shows the equivalent circuit of the Gilbert cell mixer
for calculating the MCMRR. While calculating the MCMRR, The CMRR of the mixer is the ratio of the differential gain
the LO switching is considered ideal and the tail transistor of to the CM component that appears at the differential output,
the Gilbert cell mixer is replaced with Z ssRF . VinCMRF is a and is written as [from (A6) and (A8)]:
CMRF signal that is applied to the Gilbert cell. VIFP is given gm1 + gm2 + 4gm1 gm2 Z ssRF
by: MCMRRGilbert = . (A9)
2(gm1 gm2 )
2 gm1
VIFP = (VinCMRF VpRF ). (A1)
G load ACKNOWLEDGMENT
where G load = 1/Z load is the transconductance load of the The authors would like to thank the associate editor and
mixer, and V p R F is the voltage that appears at the tail node reviewers for their constructive comments during the revision.
1302 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 4, APRIL 2017
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Darshak Bhatt (GS14) received the B.E. degree
in electronics from Sardar Patel University, Gujarat,
India, in 2004, and the M.E. degree in communi-
cation from the Birla Institute of Technology and
Science, Rajasthan, India, in 2011. He is currently
pursuing the Ph.D. degree at the IITB-Monash
Research Academy, IIT Bombay, Mumbai, India.
He was a Graduate Engineering Trainee with the
Department of Wireless and Voice Fault Manage-
ment, Tata Communication Transformation Services,
from 2008 to 2009. He was a Research Intern with
the Indian Space Research Organization Satellite Centre, Bangalore, India.
His current research interests include monolithic microwave integrated circuit
and analog circuit design for wireless applications.
Mr. Bhatt is currently a Prime Ministers Fellow for his Ph.D. research. He
was the recipient of the Gold Medal for outstanding academic performance
from Sardar Patel University.
Jayanta Mukherjee (M07SM13) received the
B.Eng. degree in electrical and electronics engineer-
ing from the Birla Institute of Technology, Mesra,
India, and the M.S. and Ph.D. degrees from The
Ohio State University, Columbus, OH, USA.
He was an Intern with Thomson Multimedia,
Princeton, NJ, USA, from 2002 to 2003. He is cur-
rently an Associate Professor with the Department of
Electrical Engineering, IIT Bombay, Mumbai, India.
He has authored or co-authored over 50 research
papers in peer-reviewed journals and conferences.
He also authored three books on RF oscillators and antennas. His research
interests include antennas, RFIC design, and bio-medical VLSI circuits.
Dr. Mukherjee was a Texas Instruments Fellow during his Ph.D. studies
from 2001 to 2004. He was the recipient of the Gold Medal on the basis of
the order of merit from the Birla Institute of Technology.
Jean-Michel Redout (SM12) received the M.S.
degree in electronics from the University College
of Antwerp, Antwerp, Belgium, in 1998, and the
M.Eng. degree in electrical engineering from Vrije
Universiteit Brussel, Brussels, Belgium, in 2001.
In 2001, he was with Alcatel Bell, Antwerp, where
he was involved in the design of analog micro-
electronic circuits for telecommunications systems.
From 2005 to 2009, he was with the ESAT-MICAS
Laboratories, Katholieke Universiteit Leuven, Leu-
ven, Belgium, as a Ph.D. Research Assistant. In
2009, he was with the Berkeley Wireless Research Center, University of
California at Berkeley, Berkeley, CA, USA, as a Post-Doctoral Scholar. In
2010, he was with Monash University, Melbourne, VIC, Australia, as a
Senior Lecturer. His current research interests include robust mixed-signal
integrated circuit design with a high immunity to electromagnetic interference,
electromagnetic compatibility and exposure, biomedical circuit design, and
radio frequency integrated circuit design.