TECNOLGICO NACIONAL DE

MXICO
Instituto Tecnolgico de matamoros

Diseo digital con VHDL

Memorias
Ing. Electrnica
Practica #7

Nombre(s) de alumno(s): Nm. de control:

Joel ivan teran ramirez 15260142
Santiago pablo Alberto.....15260092
Jesus Alberto medrano Ortiz ...15260147
Edgar Oziel Olvera rivera.....15260128

Profesor: Arturo Rdz. Casas

H. MATAMOROS, TAM. 15 de Noviembre 2017

Practica #7 Memorias 15 de Noviembre de 2017 1

 Objetivos:
. El objetivo de la realizacin de esta prctica es implementar un cdigo vhdl con el cual
se pueda controlar la salida de la suma de dos memorias diseadas.

Material:
- ISE WebPack
- Board BASYS2.
Desarrollo
1.- Escriba un codigo en VHDL que desarrolle la siguiente funcion, los datos de ROM1 y
ROM2 son sumados y el resultado es almacenado en la memoria RAM. Primero se deben
de disenar cada modulo y despues todos los modulos usando las tecnicas de diseno de
port map.

2. En base a lo anterior. Implementar el siguiente cdigo:

Top
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Top is

Port ( Clock : in STD_LOGIC;

Addres : in STD_LOGIC_VECTOR (1 downto 0);

Upload : in STD_LOGIC;

Add : in STD_LOGIC;

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 Show : in STD_LOGIC;

Data_Out : out STD_LOGIC_VECTOR (7 downto 0));

end Top;

architecture Behavioral of Top is

component ROM is

port(

Clk : in std_logic;

Rd : in std_logic;

Addr : in std_logic_vector(1 downto 0);

S : out std_logic_vector(7 downto 0));

end component;

component RAM is

port( Clk, Wt,Rd :in std_logic;

Addr : in std_logic_vector(1 downto 0);

S: out std_logic_vector(7 downto 0);

E: in std_logic_vector(7 downto 0));

end component;

component SUM is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

Upload : in STD_LOGIC;

Add : in STD_LOGIC;

X : out STD_LOGIC_VECTOR (7 downto 0));

end component;

Signal a, b, x : STD_LOGIC_VECTOR (7 downto 0);

begin

U1 : ROM

port map(

Clk => Clock,

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 Rd => Upload,

Addr => Addres,

S => a);

U2 : ROM

port map(

Clk => Clock,

Rd => Upload,

Addr => Addres,

S => b);

U3 : SUM

port map(

A => a,

B => b,

Upload => Upload,

Add => Add,

X => x );

U4 : RAM

port map(

Clk => Clock,

Wt => Add,

Rd => Show,

Addr => Addres ,

S => Data_Out ,

E => x );

end Behavioral;

U1 ROM
library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;

entity ROM is

port(

Clk : in std_logic;

Rd : in std_logic;

Addr : in std_logic_vector(1 downto 0);

S : out std_logic_vector(7 downto 0));

end ROM;

architecture Behavioral of ROM is

type ROM_Array is array (0 to 3)of std_logic_vector(7 downto 0);

constant Content: ROM_Array := (

0 => "00000001", -- value in ROM at location 0H

1 => "00000010", -- value in ROM at location 1H

2 => "00000011", -- value in ROM at location 2H

3 => "00000100", -- value in ROM at location 3H

OTHERS => "11111111");

begin

process(Clk)--, Read, Address)

begin

if( Clk'event and Clk = '0' ) then

if( Rd = '1' ) then

S <= Content(conv_integer(Addr));

else

S <= "ZZZZZZZZ";

end if;

end if;

end process;

end Behavioral;

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U2 ROM
library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity ROM is

port(

Clk : in std_logic;

Rd : in std_logic;

Addr : in std_logic_vector(1 downto 0);

S : out std_logic_vector(7 downto 0));

end ROM;

architecture Behavioral of ROM is

type ROM_Array is array (0 to 3)of std_logic_vector(7 downto 0);

constant Content: ROM_Array := (

0 => "00000001", -- value in ROM at location 0H

1 => "00000010", -- value in ROM at location 1H

2 => "00000011", -- value in ROM at location 2H

3 => "00000100", -- value in ROM at location 3H

OTHERS => "11111111");

begin

process(Clk)--, Read, Address)

begin

if( Clk'event and Clk = '0' ) then

if( Rd = '1' ) then

S <= Content(conv_integer(Addr));

else

S <= "ZZZZZZZZ";

end if;

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 end if;

end process;

end Behavioral;

SUM
library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity SUM is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

Upload : in STD_LOGIC;

Add : in STD_LOGIC;

X : out STD_LOGIC_VECTOR (7 downto 0));

end SUM;

architecture Behavioral of SUM is

signal Num1, Num2 : std_logic_vector(7 downto 0);

begin

process(Upload, Add)

begin

if Upload = '1' then

Num1 <= A;

Num2 <= B;

elsif Add = '1' then

X <= ( Num1 + Num2);

end if;

end process;

end Behavioral;

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RAM
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity RAM is

port( Clk, Wt,Rd :in std_logic;

Addr : in std_logic_vector(1 downto 0);

S: out std_logic_vector(7 downto 0);

E: in std_logic_vector(7 downto 0));

end RAM;

architecture Behavioral of RAM is

type ram_type is array (0 to 3) of std_logic_vector(7 downto 0);

signal tmp_ram: ram_type;

begin

process(Clk)

begin

if (Clk'event and Clk='1') then

if Wt='1' then

tmp_ram(conv_integer(Addr)) <= E; --write

s <= "ZZZZZZZZ";

elsif Rd = '1' then

s <= tmp_ram(conv_integer(Addr));

else

s<= "ZZZZZZZZ";

end if;

end if;

end process;

end Behavioral;

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UCF
NET "Clock" LOC = "B8";

NET "Addres<0>" LOC = "P11";

NET "Addres<1>" LOC = "L3";

NET "Upload" LOC = "N3";

NET "Add" LOC = "E2";

NET "Show" LOC = "F3";

NET "Data_Out<0>" LOC = "M5";

NET "Data_Out<1>" LOC = "M11";

NET "Data_Out<2>" LOC = "P7";

NET "Data_Out<3>" LOC = "P6";

NET "Data_Out<4>" LOC = "N5";

NET "Data_Out<5>" LOC = "N4";

NET "Data_Out<6>" LOC = "P4";

NET "Data_Out<7>" LOC = "G1";

NET "Upload" CLOCK_DEDICATED_ROUTE = FALSE;

3. Implemente el cdigo VHDL en el board Basys 2.

Anlisis de resultados y conclusiones

Se concluy de forma correcta la prctica desarrollando nuevas formas de poner en

prctica los conocimientos adquiridos al igual de los diferentes usos que se le pueden dar
al programador BASYS 2 por medio de memorias.

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