ECE-238L

Lab 30903, Section 1

Teammates:
Cyrus Stephens
Mike Chu
 For part A of the lab, we wrote the VHDL code for a D-Latch that “locks” the logic when
the clock is on, otherwise ignoring all input.
While VHDL is not difficult in and of itself, Vivado takes a while to acclimatize to, and
that was the only issue that we ran into.
For those that need help with the lab, the best thing to do is to keep the powerpoint open
on the side to ensure that no steps are missed, and to have a concise naming convention to ease
coding and file-searching.

Part B was quite similar, but instead of a D-Latch, we made a flip-flop. Flip-flops only
read input when the clock is first turned on, otherwise it ignores subsequent input.
No issues to report.
Same as before, just follow the directions to the letter.

Part C had us create a D-Latch with a clear function. If the clear was on, no inputs would
be accepted at all.
No issues to report.
No particular advice, don’t overthink it.

Part D had us create 8 D-Latches in an 8-bit register, so that 8 separate inputs could be
handled at once. A 9th input (the clock) was also used.
No issues to report
No particular advice, code carefully.