TAS5630

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300-W STEREO / 600-W MONO PurePath™ HD ANALOG-INPUT POWER STAGE

Check for Samples: TAS5630

FEATURES APPLICATIONS
• PurePath™ HD Enabled Integrated Feedback • Mini Combo System
Provides: • AV Receivers
– Signal Bandwidth up to 80 kHz for • DVD Receivers
High-Frequency Content From HD Sources • Active Speakers
– Ultralow 0.03% THD at 1 W into 4 Ω
– Flat THD at all Frequencies for Natural DESCRIPTION
Sound The TAS5630 is a high-performance analog-input
– 80-dB PSRR (BTL, No Input Signal) class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
– >100-dB (A-weighted) SNR
technology) with the ability to drive up to 300 W (1)
– Click- and Pop-Free Start-Up stereo into 4-Ω to 8-Ω speakers from a single 50-V
• Multiple Configurations Possible on the Same supply.
PCB With Stuffing Options: PurePath HD technology enables traditional
– Mono Parallel Bridge-Tied Load (PBTL) AB-amplifier performance (<0.03% THD) levels while
– Stereo Bridge-Tied Load (BTL) providing the power efficiency of traditional class-D
amplifiers.
– 2.1 Single-Ended Stereo Pair and
Bridge-Tied Load Subwoofer Unlike traditional class-D amplifiers, the distortion
curve only increases once the output levels move into
– Quad Single-Ended Outputs
clipping.
• Total Output Power at 10% THD+N
PurePath HD technology enables lower idle losses,
– 600 W in Mono PBTL Configuration
making the device even more efficient. Coupled with
– 300 W per Channel in Stereo BTL TI’s class-G power-supply reference design for
Configuration TAS563x, industry-leading levels of efficiency can be
– 145 W per Channel in Quad Single-Ended achieved.
Configuration 3  OPA1632

• High-Efficiency Power Stage (>88%) With ♫♪

60-mΩ Output MOSFETs
• Two Thermally Enhanced Package Options: PurePathTM HD
ANALOG
AUDIO TAS5630 ♫♪
– PHD (64-Pin QFP) INPUT (2.1 Configuration)
– DKD (44-Pin PSOP3) ♫♪
• Self-Protection Design (Including 15 V 12 V 25 V–50 V
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting PurePathTM HD
• EMI Compliant When Used With Class-G Power Supply
Ref. Design
Recommended System Design

110 VAC  240 VAC

(1) Achievable output power levels are dependent on the thermal

configuration of the target application. A high-performance
thermal interface material between the exposed package heat
slug and the heat sink should be used to achieve high output
power levels.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath HD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5630
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

Terminal Assignment
The TAS5630 is available in two thermally enhanced packages:
• 64-Pin QFP (PHD) power package
• 44-Pin PSOP3 package (DKD)
The package types contain heat slugs that are located on the top side of the device for convenient thermal
coupling to the heat sink.
PHD PACKAGE DKD PACKAGE
(TOP VIEW) (TOP VIEW)
PSU_REF

GVDD_B
GVDD_A

PVDD_A
PVDD_A
GND_A
OUT_A
OUT_A
BST_A
GND
GND
VDD

NC
NC
NC
NC

PSU_REF 1 44 GVDD_AB
VDD 2 43 BST_A
OC_ADJ 3 42 PVDD_A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

RESET 4 41 PVDD_A
OC_ADJ 1 48 GND_A
RESET C_STARTUP 5 40 OUT_A
2 47 GND_B
C_STARTUP 3 46 GND_B INPUT_A 6 39 OUT_A
INPUT_A 4 45 OUT_B INPUT_B 7 38 GND_A
INPUT_B 5 44 OUT_B VI_CM 8 37 GND_B
VI_CM 6 43 PVDD_B GND 9 36 OUT_B

44 pins PACKAGE
GND 7 42 PVDD_B
AGND 8 41 BST_B 10 35 PVDD_B

(TOP VIEW)
AGND
VREG 9 40 BST_C VREG 11 34 BST_B
INPUT_C 10 39 PVDD_C
INPUT_D 11 38 PVDD_C INPUT_C 12 33 BST_C
FREQ_ADJ 12 37 OUT_C INPUT_D 13 32 PVDD_C
OSC_IO+ 13 36 OUT_C FREQ_ADJ 14 31 OUT_C
OSC_IO- 14 35 GND_C
SD 15 34 GND_C OSC_IO+ 15 30 GND_C
64-pins QFP package
OTW1 16 33 GND_D OSC_IO- 16 29 GND_D
26
17
18
19
20
21
22
23
24
25

27
28
29
30
31
32

SD 17 28 OUT_D
OTW 18 27 OUT_D
READY 19 26 PVDD_D
CLIP

M1
M2
M3
READY

GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
OTW2

M1 20 25 PVDD_D
M2 21 24 BST_D
M3 22 23 GVDD_CD

PIN ONE LOCATION PHD PACKAGE

Electrical Pin 1

Pin 1 Marker
White Dot

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MODE SELECTION PINS

MODE PINS OUTPUT
ANALOG INPUT DESCRIPTION
M3 M2 M1 CONFIGURATION
0 0 0 Differential 2 × BTL AD mode
0 0 1 — — Reserved
0 1 0 Differential 2 × BTL BD mode
Differential
0 1 1 1 × BTL +2 ×SE BD mode, BTL differential
single-ended
1 0 0 Single-ended 4 × SE AD mode
INPUT_C (1) INPUT_D (1)
1 0 1 Differential 1 × PBTL 0 0 AD mode
1 0 BD mode
1 1 0
Reserved
1 1 1

(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND).

PACKAGE HEAT DISSIPATION RATINGS(1)

PARAMETER TAS5630PHD TAS5630DKD
RJC (°C/W) – 2 BTL or 4 SE channels 2.63 1.4
RJC (°C/W) – 1 BTL or 2 SE channel(s) 4.13 2.04
RJC (°C/W) – 1 SE channel 6.45 3.45
Pad area (2) 64 mm2 80 mm2

(1) RJC is junction-to-case, RCH is case-to-heat sink

(2) RCH is an important consideration. Assume a 2-mil (0.051-mm) thickness of thermal grease with a thermal conductivity of 2.5 W/mK
between the pad area and the heat sink and both channels active. The R CH with this condition is 1.1°C/W for the PHD package and
0.44°C/W for the DKD package.

Table 1. ORDERING INFORMATION(1)

TA PACKAGE DESCRIPTION
0°C–70°C TAS5630PHD 64-pin HTQFP
0°C–70°C TAS5630DKD 44-pin PSOP3

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted (1)
VALUE UNIT
VDD to AGND –0.3 to 13.2 V
GVDD to AGND –0.3 to 13.2 V
PVDD_X to GND_X(2) –0.3 to 69 V
OUT_X to GND_X (2)
–0.3 to 69 V
BST_X to GND_X(2) –0.3 to 82.2 V
BST_X to GVDD_X(2) –0.3 to 69 V
VREG to AGND –0.3 to 4.2 V
GND_X to GND –0.3 to 0.3 V
GND_X to AGND –0.3 to 0.3 V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, –0.3 to 4.2 V
PSU_REF to AGND
INPUT_X –0.3 to 5 V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 to 7 V
Continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA
Operating junction temperature range, TJ 0 to 150 °C
Storage temperature, Tstg –40 to 150 °C
Human-body model(3) (all pins) ±2 kV
Electrostatic discharge
Charged-device model(3) (all pins) ±500 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Ensure operators
handling the device are adequately grounded through the use of ground straps or alternative ESD protection.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 25 50 52.5 V
Supply for logic regulators and gate-drive
GVDD_x DC supply voltage 10.8 12 13.2 V
circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 3.5 4
Output filter according to schematics in
RL(SE) Load impedance 1.8 2 Ω
the application information section
RL(PBTL) 1.6 2
LOUTPUT(BTL) 7 10
LOUTPUT(SE) Output filter inductance Minimum output inductance at IOC 7 15 H
LOUTPUT(PBTL) 7 10
Nominal 385 400 415
PWM frame rate selectable for AM
fPWM interference avoidance; 1% resistor AM1 315 333 350 kHz
tolerance.
AM2 260 300 335
Nominal; master mode 9.9 10 10.1
RFREQ_ADJ PWM frame-rate-programming resistor AM1; master mode 19.8 20 20.2 kΩ
AM2; master mode 29.7 30 30.3
Voltage on FREQ_ADJ pin for slave mode
VFREQ_ADJ Slave mode 3.3 V
operation
TJ Junction temperature 0 150 °C

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PIN FUNCTIONS
PIN
Function(1) DESCRIPTION
NAME PHD NO. DKD NO.
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST), external 0.033-F capacitor to OUT_A required.
BST_B 41 34 P HS bootstrap supply (BST), external 0.033-F capacitor to OUT_B required.
BST_C 40 33 P HS bootstrap supply (BST), external 0.033-F capacitor to OUT_C required.
BST_D 27 24 P HS bootstrap supply (BST), external 0.033-F capacitor to OUT_D required.
CLIP 18 — O Clipping warning; open drain; active-low
C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode
FREQ_ADJ 12 14 I PWM frame-rate-programming pin requires resistor to AGND
7, 23, 24, 57,
GND 9 P Ground
58
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate-drive voltage supply requires 0.1-F capacitor to GND_A
GVDD_B 56 — P Gate drive voltage supply requires 0.1-F capacitor to GND_B
GVDD_C 25 — P Gate drive voltage supply requires 0.1-F capacitor to GND_C
GVDD_D 26 — P Gate drive voltage supply requires 0.1-F capacitor to GND_D
GVDD_AB — 44 P Gate drive voltage supply requires 0.22-F capacitor to GND_A/GND_B
GVDD_CD — 23 P Gate drive voltage supply requires 0.22-F capacitor to GND_C/GND_D
INPUT_A 4 6 I Input signal for half-bridge A
INPUT_B 5 7 I Input signal for half-bridge B
INPUT_C 10 12 I Input signal for half-bridge C
INPUT_D 11 13 I Input signal for half-bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect; pins may be grounded.
Analog overcurrent-programming pin requires resistor to AGND. 64-pin
OC_ADJ 1 3 O
package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ
OSC_IO+ 13 15 I/O Oscillator master/slave output/input
OSC_IO– 14 16 I/O Oscillator master/slave output/input
OTW — 18 O Overtemperature warning signal, open-drain, active-low
OTW1 16 — O Overtemperature warning signal, open-drain, active-low
OTW2 17 — O Overtemperature warning signal, open-drain, active-low
OUT_A 52, 53 39, 40 O Output, half-bridge A
OUT_B 44, 45 36 O Output, half-bridge B
OUT_C 36, 37 31 O Output, half-bridge C
OUT_D 28, 29 27, 28 O Output, half-bridge D
PSU_REF 63 1 P PSU reference requires close decoupling of 330 pF to AGND.
Power-supply input for half-bridge A requires close decoupling of 0.01-F
PVDD_A 50, 51 41, 42 P
capacitor in parallel with 2.2-F capacitor to GND_A.
Power-supply input for half-bridge B requires close decoupling of 0.01-F
PVDD_B 42, 43 35 P
capacitor in parallel with 2.2-F capacitor to GND_B.
Power-supply input for half-bridge C requires close decoupling of 0.0- F
PVDD_C 38, 39 32 P
capacitor in parallel with 2.2-F capacitor to GND_C.

(1) I = Input, O = Output, P = Power

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PIN FUNCTIONS (continued)

PIN
Function(1) DESCRIPTION
NAME PHD NO. DKD NO.
Power-supply input for half-bridge D requires close decoupling of 0.01-F
PVDD_D 30, 31 25, 26 P
capacitor in parallel with 2.2-F capacitor to GND_D.
READY 19 19 O Normal operation; open-drain; active-high
RESET 2 4 I Device reset input; active-low
SD 15 17 O Shutdown signal, open-drain, active-low
Power supply for digital voltage regulator requires a 10-F capacitor in parallel
VDD 64 2 P
with a 0.1-F capacitor to GND for decoupling.
Analog comparator reference node requires close decoupling of 1 nF to
VI_CM 6 8 O
AGND.
VREG 9 11 P Digital regulator supply filter pin requires 0.1-F capacitor to AGND.

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TYPICAL SYSTEM BLOCK DIAGRAM

Caps
System for
microcontroller External
or Filtering
Analog circuitry &
(2)
Startup/Stop

/SD

/CLIP
/RESET

VI_CM
READY

PSU_REF

C_STARTUP
/OTW1, /OTW2, /OTW
BST_A
Oscillator OSC_IO+

Synchronization Bootstrap
OSC_IO-
BST_B Caps

INPUT_A OUT_A 2nd Order

ANALOG_IN_A Input DC L-C
Input Output 2
Blocking Output
INPUT_B H-Bridge 1 H-Bridge 1 OUT_B
ANALOG_IN_B Caps Filter for
2
each
Hardwire H-Bridge
PWM Frame 2 -CHANNEL
Rate Adjust
FREQ_ADJ
H -BRIDGE
& BTL MODE
Master/Slave
Mode

INPUT_C 2nd Order

ANALOG_IN_C Input DC OUT_C
Input Output L-C
Blocking 2
Output
INPUT_D H-Bridge 2 H-Bridge 2 OUT_D
ANALOG_IN_D Caps Filter for
2
each
H-Bridge
M1 BST_C
GVDD_A, B, C, D
PVDD_A, B, C, D

Hardwire
GND_A, B, C, D

M2
Mode Bootstrap
M3 BST_D Caps
OC_ADJ

Control
VREG

AGND
GND

VDD

88 4

PVDD PVDD GVDD, VDD, Hardwire

50V Power Supply Over-
& VREG
Decoupling Current
SYSTEM Power Supply
Power Decoupling Limit
Supplies
GND
GND

GVDD (12V)/VDD (12V)

12V

VAC

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FUNCTIONAL BLOCK DIAGRAM

/CLIP

READY

/OTW1

/OTW2

/SD

M1

PROTE CTI ON & I/O LOGIC

M2 VDD

M3
POWER-UP
UVP VREG VREG
RESET
/ RESET
AGND
TEMP GVDD_A GVDD _C
STARTUP SENSE
GND
C_STARTUP CONTROL GVDD_B GVDD_D

OVER-LOAD CURRENT
CB3C OC_ADJ
PROTECTION SENSE
OSC_SYNC _IO+

4
OSC_SYNC_IO- OSCILLATOR PVDD_X
4
PPSC OUT_X
4
FREQ _ADJ GND_X

GVDD_A

PWM
ACTIVITY BST_A
DETECTOR
4
PSU_REF PVDD_X PVDD _A
PSU_FF
VI_CM GND
PWM TIMING
CONTROL GATE-DRIVE OUT_A
RECEIVER CONTROL

GND_A

GVDD_B

-
BST_B
ANALOG
+
INPUT_A LOOP FILTER
PVDD _B

+ PWM TIMING
CONTROL GATE-DRIVE OUT_B
ANALOG - RECEIVER CONTROL
INPUT_B LOOP FILTER
GND_B
ANALOG COMPARATO R MUX

GVDD_C
ANALOG I NP UT MUX

BST_C

-
INPUT_C PVDD _C
ANALOG
+
LOOP FILTER
PWM TIMING OUT_C
CONTROL GATE-DRIVE
RECEIVER CONTROL

+
INPUT_D GND_C
ANALOG -
LOOP FILTER
GVDD_D

BST_D

PVDD _D

PWM TIMING OUT_D

CONTROL GATE-DRIVE
RECEIVER CONTROL

GND_D

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AUDIO CHARACTERISTICS (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 H, CDEM = 680 nF,
MODE = 010, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 4 Ω, 10% THD+N, clipped output signal 300
RL = 6 Ω, 10% THD+N, clipped output signal 210
RL = 8 Ω, 10% THD+N, clipped output signal 160
PO Power output per channel W
RL = 4 Ω, 1% THD+N, unclipped output signal 240
RL = 6 Ω, 1% THD+N, unclipped output signal 160
RL = 8 Ω, 1% THD+N, unclipped output signal 125
THD+N Total harmonic distortion + noise 1W 0.03%
A-weighted, AES17 filter, input capacitor
Vn Output integrated noise 270 V
grounded
|VOS| Output offset voltage Inputs ac-coupled to AGND 40 150 mV
SNR Signal-to-noise ratio(1) A-weighted, AES17 filter 100 dB
DNR Dynamic range A-weighted, AES17 filter 100 dB
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2)
2.7 W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

AUDIO SPECIFICATION (Single-Ended Output)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 15 H, CDEM = 470 F,
MODE = 100, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 2 Ω, 10% THD+N, clipped output signal 145
RL = 3 Ω, 10% THD+N, clipped output signal 100
RL = 4 Ω, 10% THD+N, clipped output signal 75
PO Power output per channel
RL = 2 Ω, 1% THD+N, unclipped output signal 110 W
RL = 3 Ω, 1% THD+N, unclipped output signal 75
RL = 4 Ω, 1% THD+N, unclipped output signal 55
THD+N Total harmonic distortion + noise 1W 0.07%
Vn Output integrated noise A-weighted, AES17 filter, input capacitor grounded 340 V
SNR Signal-to-noise ratio(1) A-weighted, AES17 filter 93 dB
DNR Dynamic range A-weighted, AES17 filter 93 dB
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2)
2 W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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AUDIO SPECIFICATION (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 2 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 H, CDEM = 1.5 F,
MODE = 101-10, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 2 Ω, 10% THD+N, clipped output signal 600
RL = 3 Ω, 10% THD+N, clipped output signal 400
RL = 4 Ω, 10% THD+N, clipped output signal 300
PO Power output per channel W
RL = 2 Ω, 1% THD+N, unclipped output signal 480
RL = 3 Ω, 1% THD+N, unclipped output signal 310
RL = 4 Ω, 1% THD+N, unclipped output signal 230
THD+N Total harmonic distortion + noise 1W 0.05%
Vn Output integrated noise A-weighted 260 V
(1)
SNR Signal to noise ratio A-weighted 100 dB
DNR Dynamic range A-weighted 100 dB
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching(2) 2.7 W

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 22.5
IVDD VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
IGVDD_X GVDD_x gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output
13.3 mA
IPVDD_X Half-bridge supply current filter
Reset mode, No switching 870 A
ANALOG INPUTS
RIN Input resistance READY = HIGH 33 kΩ
VIN Maximum input voltage swing 5 V
IIN Maximum input current 342 A
G Voltage gain (VOUT/VIN) 23 dB
OSCILLATOR
Nominal, master mode 3.85 4 4.15
fOSC_IO+ AM1, master mode FPWM × 10 3.15 3.33 3.5 MHz
AM2, master mode 2.6 3 3.35
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) TJ = 25°C, excludes metallization 60 100 mΩ
RDS(on)
Drain-to-source resistance, high side (HS) resistance, GVDD = 12 V 60 100 mΩ

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ELECTRICAL CHARACTERISTICS (continued)

PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
Vuvp,G 9.5 V
VDD
(1)
Vuvp,hyst 0.6 V
(1)
OTW1 Overtemperature warning 1 95 100 105 °C
OTW2(1) Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTW
OTWhyst (1) temperature for OTW to be inactive after 25 °C
OTW event
Overtemperature error 145 155 165 °C
OTE(1)
OTE-OTW differential 30 °C

OTEhyst (1) A reset must occur for SD to be released 25 °C

following an OTE event.
OLPC Overload protection counter fPWM = 400 kHz 2.6 ms
Resistor – programmable, nominal peak
current in 1-Ω load,
19 A
64-pin QFP package (PHD)
ROCP = 22 kΩ
Overcurrent limit protection
Resistor – programmable, nominal peak
IOC current in 1-Ω load,
19 A
44-Pin PSOP3 package (DKD),
ROCP = 24 kΩ
Resistor – programmable, nominal peak
Overcurrent limit protection, latched current in 1-Ω load, 19 A
ROCP = 47 kΩ
Time from switching transition to flip-state
IOCT Overcurrent response time 150 ns
induced by overcurrent

Internal pulldown resistor at output of each Connected when RESET is active to

IPD provide bootstrap charge. Not used in SE 3 mA
half-bridge
mode
STATIC DIGITAL SPECIFICATIONS
VIH High-level input voltage 2 V
INPUT_X, M1, M2, M3, RESET
VIL Low-level input voltage 0.8 V
Ilkg Input leakage current 100 A
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW1 to VREG,
RINT_PU 20 26 32 kΩ
OTW2 to VREG, SD to VREG
Internal pullup resistor 3 3.3 3.6
VOH High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low-level output voltage IO = 4 mA 200 500 mV

FANOUT Device fanout OTW1, OTW2, SD, CLIP, No external pullup 30 devices
READY
(1) Specified by design.

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TAS5630
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com

TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC+NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 340
TC = 75°C 320 TC = 75°C
THD+N - Total Harmonic Distortion + Noise - %

5
300 THD+N at 10% 4 
280
2 260

PO - Output Power - W
1 240
220 6 
0.5 200
180 8 
0.2 4  160
140
0.1 6 
120
0.05 100
80
0.02 8  60
40
0.01
20
0.005 0
20m 100m200m 1 2 5 10 20 50 100 400 25 30 35 40 45 50
PO - Output Power - W PVDD - Supply Voltage - V

Figure 1. Figure 2.

UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY

vs vs
SUPPLY VOLTAGE OUTPUT POWER
300 100
280 95
TC = 75°C
90
260 85
240 4  80
6  4 
220 75 8 
PO - Output Power - W

70
200 65
6 
Efficiency - %

180 60
160 55
50
140 8 
45
120 40
100 35
30
80 25
60 20
15 TC = 25°C
40
10 THD+N at 10%
20 5
0 0
25 30 35 40 45 50 0 100 200 300 400 500 600 700
PVDD - Supply Voltage - V 2 Channel Output Power - W
Figure 3. Figure 4.

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 TAS5630
www.ti.com SLES220B – JUNE 2009 – REVISED FEBRUARY 2010

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

SYSTEM POWER LOSS OUTPUT POWER
vs vs
OUTPUT POWER CASE TEMPERATURE
80 340
75 TC = 25°C 320
70 THD+N at 10% 300
4 
65 280
4  260 6 

PO - Output Power - W
60
55 240
Power Loss - W

50 220 8 
200
45
180
40 6  160
35
140
30 120
25 100
20 80
15 60
10 8  40 THD+N at 10%
5 20
0 0
0 100 200 300 400 500 600 10 20 30 40 50 60 70 80 90 100 110 120
2 Channel Output Power - W TC - Case Temperature - °C

Figure 5. Figure 6.

NOISE AMPLITUDE
vs
FREQUENCY
+0
-10 TC = 75°C,
-20 VREF = 31.9 V,
-30 Sample Rate = 48 kHz,
FFT Size = 16384
-40
Noise Amplitude - dB

-50
-60
-70
-80
-90
-100
-110
-120
-130 4 
-140
-150
-160
0k 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
f - Frequency - Hz
Figure 7.

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TAS5630
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com

TYPICAL CHARACTERISTICS, SE CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 170
TC = 75°C
THD+N - Total Harmonic Distortion + Noise - %

160 T = 75°C
5 4  C
150 THD+N at 10%
2 
140
2 3  130

PO - Output Power - W
1 120 3 
110
0.5 2 
100
90 4 
0.2 80
0.1 70
60
0.05 50
40
0.02 30
20
0.01
10
0.005 0
20m 200m 1 2 5 10 20 50 100 25 30 35 40 45 50
PO - Output Power - W PVDD - Supply Voltage - V
Figure 8. Figure 9.

OUTPUT POWER
vs
CASE TEMPERATURE
180
170 2 
160
150
140
130 3 
PO - Output Power - W

120
110
100
90
80
70 4 
60
50
40
30
20 THD+N at 10%
10
0
10 20 30 40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 10.

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Product Folder Link(s): TAS5630

 TAS5630
www.ti.com SLES220B – JUNE 2009 – REVISED FEBRUARY 2010

TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 650
THD+N - Total Harmonic Distortion + Noise - %

5
TC = 75°C 2  600 TC = 75°C 2 
THD+N at 10%
550
3 
2 3 
500
4 

PO - Output Power - W
1 450
4 
0.5 400
6  6 
350
0.2 8  8 
300
0.1 250
0.05 200
150
0.02
100
0.01 50
0.005 0
20m 100m 200m 1 2 5 10 20 50 100 200 700 25 30 35 40 45 50
PO - Output Power - W PVDD - Supply Voltage - V
Figure 11. Figure 12.

OUTPUT POWER
vs
CASE TEMPERATURE
700
650 2  THD+N at 10%
600
550
500 3 
PO - Output Power - W

450
400
4 
350
300
6 
250
200 8 

150
100
50
0
10 20 30 40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 13.

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APPLICATION INFORMATION

PCB MATERIAL RECOMMENDATION

FR-4 2-oz. (70-m) glass epoxy material is recommended for use with the TAS5630. The use of this material can
provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace
inductance).

PVDD CAPACITOR RECOMMENDATION

The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 F, 63-V supports more applications.
The PVDD capacitors should be the low-ESR type, because they are used in a circuit associated with high-speed
switching.

DECOUPLING CAPACITOR RECOMMENDATIONS

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, quality decoupling capacitors should be used. In practice, X7R should be used in this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2.2-F capacitor that is placed on the power supply to each half-bridge. It must withstand the
voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the
ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V
power supply.

SYSTEM DESIGN RECOMMENDATIONS

The following schematics and PCB layouts illustrate best practices used for the TAS5630.

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 www.ti.com

GVDD/VDD (+12V)

R30 PVDD
C64
3.3R
R31 1000uF
C40
33nF
3.3R
C25 C26 L10
10uF 100nF 7uH GND
C30 C31 OUT_LEFT_M
100nF 100nF

GND GND C60 R70

C23
2.2uF 3.3R
GND
GND
C50 C70
VREG 680nF 1nF
330pF
C74
GND 10nF
R19 -
R18 47k
/RESET +
100R C18 C75 GND

Copyright © 2009–2010, Texas Instruments Incorporated

100pF GND 10nF
R20
GND 1 48
OC_ADJ GND_A
22.0k 2 47 C51 C71
C10 C20 /RESET GND_B 680nF 1nF R71
R10
3 46 L11 3.3R
IN_LEFT_P GND C_STARTUP GND_B GND 7uH
10uF 100R C11 4.7nF 4 45
100pF INPUT_A OUT_B OUT_LEFT_P
5 44
C12 C21 INPUT_B OUT_B C61 C41
R11
GND 6 43 2.2uF 33nF
IN_LEFT_N VI_CM PVDD_B
10uF 100R C13 1nF 7 42
100pF GND PVDD_B PVDD

8 U10 41 C68 R74

C22 VREG GND AGND BST_B 1000uF 1000uF 47uF C69 3.3R
9 40 C65 C66 63V 2.2uF
GND VREG TAS5630PHD BST_C
C14 R12 GND GND
100nF 10 39 C78
IN_RIGHT_P INPUT_C PVDD_C 10nF
10uF 100R C15 11 38 GND GND GND GND
100pF INPUT_D PVDD_C C62 C42 GND
R21
12 37 2.2uF 33nF
C16 FREQ_ADJ OUT_C GND
R13 10k
13 36 OUT_RIGHT_M
R_RIGHT_N OSC_IO+ OUT_C
10uF 100R C17 GND 14 35 7uH R72
100pF OSC_IO- GND_C L12 3.3R
15 34
/SD GND_C GND
16 33 C52 C72
/OTW1 GND_D 680nF 1nF C76
10nF

OSC_IO+
-

Product Folder Link(s): TAS5630

OSC_IO- GND +
C77
10nF
/SD
GND
/OTW1
C63 C53 C73 R73
/OTW2
2.2uF 680nF 1nF 3.3R
L13
/CLIP
GND 7uH
READY
OUT_RIGHT_P
VREG
PVDD
C43 C67
33nF 1000uF

R32
GND
3.3R GND
R33
GVDD/VDD (+12V)
3.3R

C33 C32
100nF 100nF

GND GND

Figure 14. Typical Differential-Input BTL Application With BD Modulation Filters

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17
TAS5630
 18
TAS5630

3.3R
VDD (+12V) GVDD (+12V)
3.3R
PVDD

100nF 100nF 3.3R

10uF 100nF 33nF 7uH
1000uF 47uF 2.2uF
63V 63V 100V
10nF
GND GND GND GND 100V
VREG
2.2uF
100V

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GND GND GND GND GND
47k GND
100R
/RESET 330pF

100pF GND
1000uF
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010

63V

GND 22.0k
GND
100R 1 48
OC_ADJ GND_A
IN_P 4.7nF
GND 2 47
/RESET GND_B
10uF OUT_LEFT_M
100pF
3 46
C_STARTUP GND_B
GND 7uH
GND 4 45
INPUT_A OUT_B
3.3R
100R GND 5 44
INPUT_B OUT_B 1uF
2.2uF
IN_N 33nF
6 43 100V 250V
VI_CM PVDD_B
10uF 100pF
1nF 7 42 1nF 10nF
GND GND PVDD_B 100V
100V
100nF VREG 8 41 -
AGND BST_B
GND
GND 9 TAS5630PHD 40
VREG BST_C
VREG +
GND 10 39 GND 1nF 10nF GND
INPUT_C PVDD_C
100V 100V
11 INPUT_D PVDD_C 38
10k 2.2uF 1uF
33nF
12 37 100V 250V
FREQ_ADJ OUT_C
GND 7uH
3.3R
13 36
GND OSC_IO+ OUT_C
14 35
OSC_IO- GND_C
15 34 OUT_LEFT_P
/SD GND_C
GND
16 33
/OTW1 GND_D

Product Folder Link(s): TAS5630

1000uF
63V
OSC_IO+

OSC_IO-
2.2uF GND
100V
/SD PVDD
GND GND
1000uF
/OTW1
VREG 7uH 63V
/OTW2
33nF
/CLIP
3.3R GND
READY
3.3R
GVDD (+12V)

100nF 100nF

GNDGND

Figure 15. Typical Differential (2N) PBTL Application With BD Modulation Filters

Copyright © 2009–2010, Texas Instruments Incorporated

www.ti.com
 3.3R
VDD (+12V)
3.3R
GVDD (+12V)
100nF 100nF
10uF 100nF 33nF 15uH
A
GND GND GND GND
PVDD
VREG
2.2uF
GND
47k GND
100R
/RESET 330pF
64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49
GND
100pF
GND

GND

GVDD_B

GVDD_A

BST_A

PVDD_A

PVDD_A
PSU_REF
VDD

NC

NC

NC

NC

OUT_A

OUT_A

GND_A
GND 22.0k
100R 1 48
OC_ADJ GND_A
IN_A 10nF
GND 2 47
10uF
/RESET GND_B
100pF
3 46
C_STARTUP GND_B GND 15uH
GND 4 45
INPUT_A OUT_B B
100R GND 5 44
INPUT_B OUT_B
IN_B 2.2uF 33nF
6 43
10uF
VI_CM PVDD_B
100pF
1nF 7 42
GND PVDD_B PVDD
GND
100nF VREG 8 41
AGND BST_B 3.3R
GND
100R GND 9
VREG
TAS5630PHD BST_C
40 47uF
2.2uF
63V
IN_C
GND 10 39
INPUT_C PVDD_C 10nF
10uF
100pF
11 38
INPUT_D PVDD_C
10k 2.2uF 33nF
12 37
FREQ_ADJ OUT_C 15uH GND GND GND
100R GND 13 36
OSC_IO+ OUT_C C
GND
IN_D
14 35
10uF
OSC_IO- GND_C
100pF
15 34
/SD GND_C GND
16 33
/OTW1 GND_D
GND

GVDD_C

GVDD_D

PVDD_D

PVDD_D

GND_D
READY

OUT_D

OUT_D
BST_D
/OTW2

/CLIP

GND

GND
M1

M2

M3

24

27

28

29
17

18

19

20

21

22

23

25

30

31

32
26
OSC_IO+
OSC_IO-
2.2uF
/SD PVDD
GND
/OTW1
VREG 15uH
/OTW2 D
33nF
/CLIP
GND
3.3R
READY GVDD (+12V)
3.3R
100nF 100nF
10nF 10nF
100V GND GND 100V
GND GND
3.3R 3.3R
OUT_A_M OUT_B_M
A B
100nF 100nF
R_COMP 100V - R_COMP 100V -
470nF 470nF
10k 10k
PVDD 250V PVDD 250V
+ +
470uF 10k 100nF GND 470uF 10k 100nF GND
50V 1% 100V 50V 1% 100V
OUT_A_P OUT_B_P
470uF 10k 470uF 10k
PVDD R_COMP 50V 1% 3.3R 50V 1% 3.3R
50V 147k GND
100V
GND
100V
49V 165k 10nF GND 10nF GND
48V 187k 10nF 10nF
<48V 191k 100V 100V
3.3R GND 3.3R GND
OUT_C_M OUT_D_M
C D
100nF 100nF
R_COMP 100V - R_COMP 100V -
470nF 470nF
10k 10k
PVDD 250V PVDD 250V
+ +
470uF 10k 100nF GND 470uF 10k 100nF GND
50V 1% 100V 50V 1% 100V
OUT_C_P OUT_D_P
470uF 10k 470uF 10k
50V 1% 50V 1%
3.3R 3.3R
GND GND
100V 100V
10nF GND 10nF GND
 20
TAS5630

GVDD (+12V)

PVDD

3.3R
1000uF
VDD (+12V)
63V
3.3R

100nF GND
100nF
10uF 100nF 33nF 7uH
OUT_CENTER_M

GND GND GND GND

VREG
3.3R
2.2uF
100V 680nF

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GND GND 250V
47k
100R
1nF 10nF
/RESET 330pF
100V 100V
100pF GND -
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010

+
GND 1nF 10nF GND
GND 22.0k 100V 100V

100R 1 48 680nF
OC_ADJ GND_A
250V
IN_CENTER_P 10nF
GND 2 47
/RESET GND_B 3.3R
10uF
100pF
3 46
C_STARTUP GND_B
GND 7uH
GND 4 45
INPUT_A OUT_B
OUT_CENTER_P
100R GND 5 44
INPUT_B OUT_B
2.2uF
IN_CENTER_N 33nF
6 43 100V
VI_CM PVDD_B
10uF 100pF
1nF 7 42
GND PVDD_B PVDD
GND
100nF VREG 8 41
AGND BST_B 3.3R
GND
100R GND 9 TAS5630PHD 40 1000uF 47uF 2.2uF
VREG BST_C 63V 63V 100V 10nF
IN_LEFT
GND 10 39 10nF 100V
INPUT_C PVDD_C
10uF 100pF 100V
11 38
INPUT_D PVDD_C 2.2uF
10k 33nF 3.3R
12 37 100V GND GND GND GND
FREQ_ADJ OUT_C
15uH GND
100R GND 13 36 OUT_LEFT_M
OSC_IO+ OUT_C
GND
IN_RIGHT
14 35
OSC_IO- GND_C 100nF
10uF
100pF R_COMP -
15 34 100V
/SD GND_C 470nF
GND
10k
16 33 250V
/OTW1 GND_D PVDD
+
GND 470uF 10k 100nF GND
50V 1% 100V

OUT_LEFT_P
470uF 10k
3.3R
50V 1%

Product Folder Link(s): TAS5630

OSC_IO+ 100V
GND GND 10nF
OSC_IO-
2.2uF
VREG 100V 10nF
100V
/SD
GND GND
/OTW1
3.3R
15uH GND
/OTW2
OUT_RIGHT_M
33nF
/CLIP
3.3R
100nF
READY R_COMP -
3.3R 100V
470nF
10k
250V
PVDD
+
470uF 10k 100nF GND
100nF 100nF
50V 1% 100V

OUT_RIGHT_P
470uF 10k
3.3R
GND GND 50V 1%

100V
GND GND 10nF

PVDD

GVDD (+12V)

Figure 17. Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application

Copyright © 2009–2010, Texas Instruments Incorporated

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 www.ti.com

R34
GVDD (+12V)
1.5R

C38 C87
PVDD
100nF 100nF

1000uF
63V
VDD (+12V)
GND

C44 C35
10uF 100nF 7uH GND
OUT_LEFT_M

GND GND
C86 3.3R
VREG 680nF
GND
250V

Copyright © 2009–2010, Texas Instruments Incorporated

330pF
R44 1nF 10nF
47k U12 100V 100V
R13
/RESET 1
GVDD_AB
44 -
PSU_REF
C33
100R C78 2 43
VDD BST_A
100pF +
R14
3 42 33nF GND 1nF 10nF GND
GND OC_ADJ PVDD_A
100V 100V
24k 4 41
/RESET PVDD_A 680nF
R45 C45
5 40 C83 250V
IN_LEFT_P GND C_STARTUP OUT_A
2.2uF
3.3R
10uF 100R C82 4.7nF 6 39
INPUT_A OUT_A
100pF
7 38 7uH
INPUT_B GND_A
R54 C85
8 37 OUT_LEFT_P
IN_LEFT_N GND VI_CM GND_B
GND
10uF 100R C79 1nF 9 36
GND OUT_B PVDD
100pF
C42 VREG 10 35
AGND PVDD_B 3.3R
GND C90
GND C41 33nF 1000uF 1000uF
11 34 2.2uF 47uF 2.2uF
GND 100nF VREG TAS5630DKD BST_B 63V
R53 63V 100V
63V
12 33 10nF
IN_RIGHT_P INPUT_C BST_C
C91 100V
C37 33nF
10uF 100R C80 13 32 2.2uF GND
INPUT_D PVDD_C
100pF R20
14 31 GND GND GND GND
FREQ_ADJ OUT_C
R60 GND
10k
15 30 7uH
IN_RIGHT_N OSC_IO+ GND_C
GND OUT_RIGHT_M
10uF 100R C81 16 29
OSC_IO- GND_D
100pF
17 28
/SD OUT_D
GND
C34 3.3R
18 27
/OTW OUT_D 680nF
2.2uF
19 26 250V
READY PVDD_D

Product Folder Link(s): TAS5630

20 25 1nF 10nF
M1 PVDD_D
VREG 100V 100V
21 M2 BST_D 24 -
OSC_IO+ 33nF
22 23
M3 GVDD_CD C88 +
OSC_IO- GND 1nF 10nF GND
100V 100V
GND
/SD 680nF
250V
/OTW
3.3R
READY

7uH
OUT_RIGHT_P

PVDD

1000uF
1.5R
63V
R31
100nF 100nF
C89 C84 GND
GVDD (+12V)

GND

Figure 18. Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package

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TAS5630
TAS5630
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THEORY OF OPERATION

POWER SUPPLIES
To facilitate system design, the TAS5630 needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-F ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5630 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630 is fully protected against erroneous
power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within
the specified range (see the Recommended Operating Conditions table of this data sheet).

SYSTEM POWER-UP/POWER-DOWN SEQUENCE

Powering Up
The TAS5630 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.

Powering Down
The TAS5630 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.

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 TAS5630
www.ti.com SLES220B – JUNE 2009 – REVISED FEBRUARY 2010

ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).

OTW2, DESCRIPTION
SD OTW1
OTW
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
0 0 1
warning)
0 1 1 Overload (OLP) or undervoltage (UVP)
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)

Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).

DEVICE PROTECTION SYSTEM

The TAS5630 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5630 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device functions on errors, as shown in the following table.

BTL Mode PBTL Mode SE Mode

Local error in Turns Off or in Local error in Turns Off or in Local error in Turns Off or in
A A A
A+B A+B
B B B
A+B+C+D
C C C
C+D C+D
D D D

Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.

PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC

Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Link(s): TAS5630
TAS5630
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com

filter. The typical duration is <15 ms/F. While the PPSC detection is in progress, SD is kept low, and the device
does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and
SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection
system is not tripped, it is recommended not to insert resistive load to GND_X or PVDD_X.

OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.
PHD Package:
The TAS5630 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package:
The TAS5630 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.

UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)

The UVP and POR circuits of the TAS5630 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach the levels stated in the Electrical Characteristics
table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold
on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.

DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-
Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output; i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after
an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the
falling edge of SD.

SYSTEM DESIGN CONSIDERATIONS

A rising-edge transition on the reset input allows the device to execute the startup sequence and starts switching.
Apply audio only when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device inverts the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.

24 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated

Product Folder Link(s): TAS5630

 TAS5630
www.ti.com SLES220B – JUNE 2009 – REVISED FEBRUARY 2010

OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower-value switching frequencies together result in the fewest cases of interference throughout the AM band,
and can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave-mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs, which must be slaved from an external clock.

PRINTED CIRCUIT BOARD RECOMMENDATION

Use an unbroken ground plane to have a good low-impedance and -inductance return path to the power supply
for power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
of the audio input should be kept short and together with the accompanying audio-source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 14.

Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X
pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins
and without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, preferably metal film types.

Figure 19. Printed Circuit Board – Top Layer

Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Link(s): TAS5630
TAS5630
SLES220B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com

Note B1: It is important to have a direct-low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short, low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors

Figure 20. Printed Circuit Board – Bottom Layer

REVISION HISTORY

Changes from Original (July 2009) to Revision A Page

• Deleted Product Preview from the PHD package .................................................................................................................. 3

Changes from Revision A (September 2009) to Revision B Page

• Changed several frame-rate specifications in Recommended Operating Conditions ............................................................ 4

• Changed oscillator frequency specifications in Electrical Characteristics ............................................................................ 10
• Changed specification for overload protection counter in Electrical Characteristics ............................................................ 11

26 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated

Product Folder Link(s): TAS5630

 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

TAS5630DKD NRND HSSOP DKD 44 29 Green (RoHS CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5630

& no Sb/Br)
TAS5630DKDR NRND HSSOP DKD 44 500 Green (RoHS CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5630
& no Sb/Br)
TAS5630PHD NRND HTQFP PHD 64 90 Green (RoHS CU NIPDAU Level-5A-260C-24 HR 0 to 70 TAS5630
& no Sb/Br)
TAS5630PHDR NRND HTQFP PHD 64 1000 Green (RoHS CU NIPDAU Level-5A-260C-24 HR 0 to 70 TAS5630
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-May-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5630DKDR HSSOP DKD 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1
TAS5630PHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-May-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5630DKDR HSSOP DKD 44 500 367.0 367.0 45.0
TAS5630PHDR HTQFP PHD 64 1000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DKD0044A PowerPAD TM SSOP - 3.6 mm max height
S CALE 1.000

PLASTIC SMALL OUTLINE

C
14.5 SEATING PLANE
TYP
13.9
A 0.1 C
PIN 1 ID AREA
42X 0.65
1 44

EXPOSED
THERMAL PAD
12.7 2X
16.0 12.6
13.65
15.8
NOTE 3

22
23
0.38
44X
(2.95) 0.25
0.12 C A B
5.9
5.8
11.1
B 10.9
NOTE 4
(0.15)
EXPOSED THERMAL PAD

3.6
3.1

(0.28) TYP
SEE DETAIL A
0.35
GAGE PLANE

1.1 0.3
0-8 0.8 0.1

DETAIL A
TYPICAL

4218846/A 07/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. The exposed thermal pad is designed to be attached to an external heatsink.

www.ti.com
 EXAMPLE BOARD LAYOUT
DKD0044A PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE

44X (2) SEE DETAILS

SYMM
1
44

44X (0.45)

42X (0.65)

SYMM

(R0.05) TYP

22 23

(13.2)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

0.05 MAX 0.05 MIN

AROUND AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218846/A 07/2016
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DKD0044A PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE

44X (2)
SYMM
1
44

44X (0.45)

42X (0.65)

SYMM

(R0.05) TYP

22 23

(13.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE:6X

4218846/A 07/2016
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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