Professional Documents
Culture Documents
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NVIDIA Corporation
NXP Semiconductors
Octasic, Inc.
Open-Silicon, Inc.
Optichron Inc.
Oxford Semiconductor, Inc.
ParkerVision, Inc.
Phyworks Ltd.
PicoChip Designs Limited
Pixelworks, Inc.
Pixim, Inc.
PLX Technology, Inc.
PMC-Sierra, Inc.
Powerchip Semiconductor Corporation (PSC)
Powervation Ltd.
Primarion, An Infineon Technologies Company
Pulse-Link Inc.
PulseCore Semiconductor
QP Semiconductor, Inc.
QUALCOMM
QuickLogic Corporation
Quintic Corporation
Rapid Bridge LLC *
Rapport, Inc.
Redpine Signals Inc.
RF Micro Devices (RFMD)
RichWave Technology Corp.
RMI Corporation
Samsung Electronics Co., Ltd.
SanDisk Corporation
Scintera Networks, Inc.
Semtech Corporation
Sequoia Communications
Shanghai Huahong Integrated Circuit Co., Ltd.
SiBEAM, Inc.
Sicon Semiconductor AB
SiGe Semiconductor, Inc.
Silicon Laboratories
Silicon Motion
Silicon Storage Technology, Inc. (SST)
Silterra Malaysia Sdn. Bhd. *
Simtek Corporation
SiPort
SiRF Technology, Inc.
SiTel Semiconductor B.V.
Skyworks Solutions, Inc.
Solid State Devices Inc.
Spreadtrum Communications Inc.
Staccato Communications
Standard Microsystems Corporation (SMSC)
STATS ChipPAC Ltd. *
STMicroelectronics
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26. Give the logic expression for an AOI gate. Draw its transistor
level equivalent. Draw its stick diagram
27. Why don’t we use just one NMOS or PMOS transistor as a
transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is
connected to VDD, give the output for a square pulse input going
from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write
operations
30. Draw the Differential Sense Amplifier and explain its working. Any
idea how to size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential
Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the
SRAM cell? How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit-
lines) affect SRAM’s performance?
35. What’s the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we
delay the enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your
placements of SRAM Cells, Row Decoders, Column Decoders, Read
Circuit, Write Circuit and Buffers
38. In a SRAM layout, which metal layers would you prefer for Word
Lines and Bit Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What’s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you
test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You
can expect a circuit with some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a
CMOS Inverter. How do you avoid Latch Up?
====================================================
===========
1. Give two ways of converting a two input NAND gate to an inverter
2. Given a circuit, draw its exact timing response. (I was given a
Pseudo Random Signal Generator; you can expect any sequential
ckt)
3. What are set up time & hold time constraints? What do they
signify? Which one is critical for estimating maximum clock frequency
of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint:
Double the Clock)
6. Suppose you have a combinational circuit between two registers
driven by a clock. What will you do if the delay of the combinational
circuit is greater than your clock signal? (You can’t resize the
combinational circuit transistors)
7. The answer to the above question is breaking the combinational
circuit and pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
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9. Give the truth table for a Half Adder. Give a gate level
implementation of the same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you
convert it to XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from a
signal line?
14. Design any FSM in VHDL or Verilog.
15. Explain RC circuit’s charging and discharging.
16. Explain the working of a binary counter.
17. Describe how you would reverse a singly linked list.
There are lot of constraints and will vary for tool to tool ,I am listing
some of Xilinx constraints
a) Translate on and Translate off: the Verilog code between
Translate on and Translate off is ignored for synthesis.
b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a
clock signal goes through combinatorial logic before being connected
to the clock input of a flip-flop, XST cannot identify what input pin or
internal net is the real clock signal. This constraint allows you to
define the clock net.
c) XOR_COLLAPSE: is synthesis constraint. It controls whether
cascaded XORs should be collapsed into a single XOR.
For more constraints detailed description refer to constraint guide.
3) Suppose for a piece of code equivalent gate count is 600 and for
another code equivalent gate count is 50,000 will the size of bitmap
change?in other words will size of bitmap change it gate count
change?
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not synthesizable->>>>
initial
ignored for synthesis.
delays
ignored for synthesis.
events
not supported.
real
Real data type not supported.
time
Time data type not supported.
force and release
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synthesizable constructs->>
assign,for loop,Gate Level Primitives,repeat with constant value...
These stuck-at problems will appear in ASIC. Some times, the nodes
will permanently tie to 1 or 0 because of some fault. To avoid that, we
need to provide testability in RTL. If it is permanently 1 it is called
stuck-at-1 If it is permanently 0 it is called stuck-at-0.
FPGA:
a)SRAM based technology.
b)Segmented connection between elements.
c)Usually used for complex logic circuits.
d)Must be reprogrammed once the power is off.
e)Costly
CPLD:
a)Flash or EPROM based technology.
b)Continuous connection between elements.
c)Usually used for simpler or moderately complex logic circuits.
d)Need not be reprogrammed once the power is off.
e)Cheaper
13)what is slice,clb,lut?
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YES.
16) What is FPGA you are currently using and some of main reasons
for choosing it?
17) Draw a rough diagram of how clock is routed through out FPGA?
18) How many global buffers are there in your current fpga,what is
their significance?
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Dynamic timing:
a. The design is simulated in full timing mode.
b. Not all possibilities tested as it is dependent on the input test
vectors.
c. Simulations in full timing mode are slow and require a lot of
memory.
d. Best method to check asynchronous interfaces or interfaces
between different timing domains.
Static timing:
a. The delays over all paths are added up.
b. All possibilities, including false paths, verified without the need for
test vectors.
c. Much faster than simulations, hours as opposed to days.
d. Not good with asynchronous interfaces or interfaces between
different timing domains.
PLL:
PLLs have disadvantages that make their use in high-speed designs
problematic, particularly when both high performance and high
reliability are required.
The PLL voltage-controlled oscillator (VCO) is the greatest source of
problems. Variations in temperature, supply voltage, and
manufacturing process affect the stability and operating performance
of PLLs.
24) Given two ASICs. one has setup violation and the other has hold
violation. how can they be made to work together without modifying
the design?
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28)What is DFT ?
29) There are two major FPGA companies: Xilinx and Altera. Xilinx
tends to promote its hard processor cores and Altera tends to
promote its soft processor cores. What is the difference between a
hard processor core and a soft processor core?
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DFT:
· manufacturing defects like stuck at "0" or "1".
· test for set of rules followed during the initial design stage.
Formal verification:
· Verification of the operation of the design, i.e, to see if the design
follows spec.
· gate netlist == RTL ?
· using mathematics and statistical analysis to check for equivalence.
32)What is Synthesis?
Many, many problems have this sort of variable rate requirement, yet
we are usually constrained with a constant clock frequency. One trick
is to implement a digital NCO (Numerically Controlled Oscillator). An
NCO is actually very simple and, while it is most naturally understood
as hardware, it also can be constructed in software. The NCO, quite
simply, is an accumulator where you keep adding a fixed value on
every clock (e.g. at a constant clock frequency). When the NCO
"wraps", you sample your input or do your action. By adjusting the
value added to the accumulator each clock, you finely tune the
AVERAGE frequency of that wrap event. Now - you may have
realized that the wrapping event may have lots of jitter on it. True, but
you may use the wrap to increment yet another counter where each
additional Divide-by-2 bit reduces this jitter. The DDS is a related
technique. I have two examples showing both an NCOs and a DDS
in my File Archive. This is tricky to grasp at first, but tremendously
powerful once you have it in your bag of tricks. NCOs also relate to
digital PLLs, Timing Recovery, TDMA and other "variable rate"
phenomena.
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What you would use in RTL a 'boolean' type or a 'std_logic' type and
why.
Metastability
What are Async counters, what are advantages of using these over
sync counters. and what are the disadvantages
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Sensitivity List:
How does it matter.What will happen
if you dont include a signal in the sensitivity list
and use/read it inside the process
Why does a pass gate requires two transistors(1 N and 1 P type) Can
we use a
single transistor N or P type in a pass gate? If not why? and if yes
then in what conditions?
Why CMOS why not N-MOS or P-MOS logic, when we know that the
number
of gates required in CMOS are grater than in n-mos or p-mos logic.
What are dynamic logic gates? What are their advantages over
conventional logic gates
Design a digital circuit to delay the negative edge of the input signal
by 2 clock cycles
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Give the truth table for a Half Adder. Give a gate level
implementation of it.
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Design a 4:1 Mux using 2:1 Muxes and some combo logic.
What is metastability ?
Design a D and T flip flop using 2:1 mux; use of other components
not allowed, just the mux.
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You are given a 100 MHz clock. Design a 33.3 MHz clock with and
without 50&37; duty cycle.
What are FIFO's? Can you draw the block diagram of FIFO? Could
you modify it to make it asynchronous FIFO ?
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Intel
The resistivity of top metal layers are less and hence less IR drop is
seen in power distribution network. If power stripes are routed in
lower metal layers this will use good amount of lower routing
resources and therefore it can create routing congestion.
Answer:
Answer:
Answer:
* What would you do in order to not use certain cells from the library?
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Answer:
Answer:
For a given wireload model the delay are estimated based on the
number of fanout of the cell driving the net.
Answer:
Answer:
No. You should not increase clock buffers in the clock network.
Increase in clock buffers cause more area , more power. When
everything is fine why you want to touch clock tree??
Answer:
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For multi clock domain, group the clocks while building the clock tree
so that skew is balanced across the clocks. (Inter clock skew
analysis).
* How you go about fixing timing violations for latch- latch paths?
* As an engineer, let’s say your manager comes to you and asks for
next project die size estimation/projection, giving data on RTL size,
performance requirements. How do you go about the figuring out and
come up with die size considering physical aspects?
* How will you design inserting voltage island scheme between
macro pins crossing core and are at different power wells? What is
the optimal resource solution?
* What are various formal verification issues you faced and how did
you resolve?
* How do you calculate maximum frequency given setup, hold, clock
and clock skew?
* What are effects of metastability?
STmicroelectronics
* What are the challenges you faced in place and route, FV (Formal
Verification), ECO (Engineering Change Order) areas?
* How long the design cycle for your designs?
* What part are your areas of interest in physical design?
* Explain ECO (Engineering Change Order) methodology.
* Explain CTS (Clock Tree Synthesis) flow.
* If there are too many pins of the logic cells in one place within core,
what kind of issues would you face and how will you resolve?
* Define hash/ @array in perl.
* Using TCL (Tool Command Language, Tickle) how do you set
variables?
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Qualcomm
Answer:
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Answer:
* What constraints you add in CTS (Clock Tree Synthesis) for clock
gates?
Answer:
Answer:
Hughes Networks
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Hynix Semiconductor
About Contributor
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a. Useful skew
b. Local skew
c. Global skew
d. Slack
a. Clock nets
b. Signal nets
c. IO nets
d. PG nets
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a. Metal1
b. Metal2
c. Metal3
d. Metal4
a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack
a. Before Placement
b. After Placement
c. Before CTS
d. After CTS
* 10) To achieve better timing ____ cells are placed in the critical
path.
a. HVT
b. LVT
c. RVT
d. SVT
a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage
a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None
a. .lib
b. .v
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c. .tf
d. .sdc
* 16) The minimum height and width a cell can occupy in the design
is called as ___.
a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths
a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio
a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing
a. VDD
b. VSS
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* 22) If the data is faster than the clock in Reg to Reg path ___
violation may come.
a. Setup
b. Hold
c. Both
d. None
a. Before placement
b. After placement
c. Before CTS
d. After CTS
a. Max tran
b. Max cap
c. Max fanout
d. Max current density
a. Setup violation
b. Hold violation
c. Skew
d. None
a. CLKBUF
b. BUF
c. INV
d. CLKINV
* 28) Max voltage drop will be there at(with out macros) ___.
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c. Middle
d. None
a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing
a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS
* 33) In technology file if 7 metals are there then which metals you
will use for power?
* 34) If metal6 and metal7 are used for the power in 7 metal layer
process design then which metals you will use for clock ?
a. 1ns
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b. 3ns
c. 5ns
d. 6ns
* 38) What is the effect of high drive strength buffer when added in
long net ?
* 40) After the final routing the violations in the design ___.
a. Constant
b. Decrease
c. Increase
d. None of the above
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a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.
a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above
* Answers:
1)b
2)c
3)b
4)c
5)b
6)d
7)a
8)c
9)d
10)b
11)d
12)d
13)b
14)c
15)b
16)a
17)c
18)a
19)d
20)a
21)b
22)b
23)d
24)d
25)c
26)b
27)a
28)c
29)d
30)c
31)d
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32)c
33)d
34)c
35)d
36)c
37)a
38)c
39)b
40)d
41)c
42)a
43)a
44)c
Backend (Physical Design) Interview Questions and Answers
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If you have both IR drop and congestion how will you fix it?
* -Spread macros
* -Spread standard cells
* -Increase strap width
* -Increase number of straps
* -Use proper blockage
* -Spread macros
* -Spread standard cells
* -Use proper blockage
In a reg to reg path if you have setup problem where will you insert
buffer-near to launching flop or capture flop? Why?
* (buffers are inserted for fixing fanout voilations and hence they
reduce setup voilation; otherwise we try to fix setup voilation with the
sizing of cells; now just assume that you must insert buffer !)
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* Switching of the signal in one net can interfere neigbouring net due
to cross coupling capacitance.This affect is known as cros talk. Cross
talk may lead setup or hold voilation.
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* -High frequency noise (or glitch)is coupled to VSS (or VDD) since
shilded layers are connected to either VDD or VSS.
Why double spacing and multiple vias are used related to clock?
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level design?
* Chip design uses all metal layes available; block design may not
use all metal layers.
* First check flylines i.e. check net connections from macro to macro
and macro to standard cells.
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What are the input files will you give for primetime correlation?
If the routing congestion exists between two macros, then what will
you do?
* By checking the total area of the design you can decide die size.
* Poly
If the full chip design is routed by 7 layer metal, why macros are
designed using 5LM instead of using 7LM?
* Because top two metal layers are required for global routing in chip
design. If top metal layers are also used in block level it will create
routing blockage.
* Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc
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* Clock definitions
How did you do power planning? How to calculate core ring width,
macro ring width and strap or trunk width? How to find number of
power pad and IO power pads? How the width of metal and number
of straps calculated for power and ground?
* Get the total core power consumption; get the metal layer current
density value from the tech file; Divide total power by number sides of
the chip; Divide the obtained value from the current density to get
core power ring width. Then calculate number of straps using some
more equations. Will be explained in detail later.
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* Next lower layer to the top two metal layers(global routing layers).
Because it has less resistance hence less RC delay.
If in your design has reset pin, then it’ll affect input pin or output pin
or both?
* Output pin.
During power analysis, if you are facing IR drop problem, then how
did you avoid?
Define antenna problem and how did you resolve these problem?
* Decrease the length of the net by providing more vias and layer
jumping.
How delays vary with different PVT conditions? Show the graph.
* P increase->dealy increase
* P decrease->delay decrease
* V increase->delay decrease
* V decrease->delay increase
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* T increase->delay increase
* T decrease->delay decrease
Explain the flow of physical design and inputs and outputs for each
step in flow.
* Gate delay
* Cell delay
* Intrinsic delay
* Intrinsic delay is the delay internal to the gate. Input pin of the cell to
output pin of the cell.
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* The difference between the time a signal is first applied to the net
and the time it reaches other devices connected to that net.
What are delay models and what is the difference between them?
* Wire load model is NLDM which has estimated R and C of the net.
Why higher metal layers are preferred for Vdd and Vss?
* Upsizing
* Downsizing
* Buffer insertion
* Buffer relocation
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* Due to high current flow in the metal atoms of the metal can
displaced from its origial place. When it happens in larger amount the
metal can open or bulging of metal layer can happen. This effect is
known as Electro Migration.
* Global Routing
* Track Assignment
* Detail Routing
* Source Latency
* The time a clock signal takes to propagate from its ideal waveform
origin point to the clock definition point in the design.
* Network latency
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* The time clock signal (rise or fall) takes to propagate from the clock
definition point to a register clock pin.
What is congestion?
* If the number of routing tracks available for routing is less than the
required tracks then it is known as congestion.
* Routing
* Distribution of clock from the clock source to the sync pin of the
registers.
* What is the difference between hard macro, firm macro and soft
macro?
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or
* Hard macro, firm macro and soft macro are all known as IP
(Intellectual property). They are optimized for power, area and
performance. They can be purchased and used in your ASIC or
FPGA design implementation flow. Soft macro is flexible for all type
of ASIC implementation. Hard macro can be used in pure ASIC
design flow, not in FPGA flow. Before bying any IP it is very important
to evaluate its advantages and disadvantages over each other,
hardware compatibility such as I/O standards with your design
blocks, reusability for other designs.
Soft macros
* From the physical design perspective, soft macro is any cell that
has been placed and routed in a placement and routing tool such as
Astro. (This is the definition given in Astro Rail user manual !)
* Soft macros are editable and can contain standard cells, hard
macros, or other soft macros.
Firm macros
* Firm macros are more flexible and portable than hard macros.
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Hard macro
* Hard macros are block level designs which are silicon tested and
proved.
* In physical design you can only access pins of hard macros unlike
soft macros which allows us to manipulate in different way.
* You have freedom to move, rotate, flip but you can't touch anything
inside hard macros.
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Answer:
Clock net is one of the High Fanout Net(HFN)s. The clock buffers are
designed with some special property like high drive strength and less
delay. Clock buffers have equal rise and fall time. This prevents duty
cycle of clock signal from changing when it passes through a chain of
clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time
and fall time is minimum. They too are designed for higher drive
strength.
What is difference between HFN synthesis and CTS?
Answer:
Answer:
Theoretically it is possible....!
Practically it is impossible....!!
Below are the important interview questions for VLSI physical design
aspirants. Interview starts with flow of physical design and goes
on.....on....on..... I am trying to make your life easy..... let me prepare
answers to all these if soft form.... as soon as it happens those
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*
What parameters (or aspects) differentiate Chip Design & Block level
design??
*
How do you place macros in a full chip design?
*
Differentiate between a Hierarchical Design and flat design?
*
Which is more complicated when u have a 48 MHz and 500 MHz
clock design?
*
Name few tools which you used for physical verification?
*
What are the input files will you give for primetime correlation?
*
What are the algorithms used while routing? Will it optimize wire
length?
*
How will you decide the Pin location in block level design?
*
If the routing congestion exists between two macros, then what will
you do?
*
How will you place the macros?
*
How will you decide the die size?
*
If lengthy metal layer is connected to diffusion and poly, then which
one will affect by antenna problem?
*
If the full chip design is routed by 7 layer metal, why macros are
designed using 5LM instead of using 7LM?
*
In your project what is die size, number of metal layers, technology,
foundry, number of clocks?
*
How many macros in your design?
*
What is each macro size and no. of standard cell count?
*
How did u handle the Clock in your design?
*
What are the Input needs for your design?
*
What is SDC constraint file contains?
*
How did you do power planning?
*
How to find total chip power?
*
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How to calculate core ring width, macro ring width and strap or trunk
width?
*
How to find number of power pad and IO power pads?
*
What are the problems faced related to timing?
*
How did u resolve the setup and hold problem?
*
If in your design 10000 and more numbers of problems come, then
what you will do?
*
In which layer do you prefer for clock routing and why?
*
If in your design has reset pin, then it’ll affect input pin or output pin
or both?
*
During power analysis, if you are facing IR drop problem, then how
did u avoid?
*
Define antenna problem and how did u resolve these problem?
*
How delays vary with different PVT conditions? Show the graph.
*
Explain the flow of physical design and inputs and outputs for each
step in flow.
*
What is cell delay and net delay?
*
What are delay models and what is the difference between them?
*
What is wire load model?
*
What does SDC constraints has?
*
Why higher metal layers are preferred for Vdd and Vss?
*
What is logic optimization and give some methods of logic
optimization.
*
What is the significance of negative slack?
*
What is signal integrity? How it affects Timing?
*
What is IR drop? How to avoid .how it affects timing?
*
What is EM and it effects?
*
What is floor plan and power plan?
*
What are types of routing?
*
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*
What is the difference between core filler cells and metal fillers?
*
How to decide number of pads in chip level design?
*
What is tie-high and tie-low cells and where it is used
*
What is LEF?
*
What is DEF?
*
What are the steps involved in designing an optimal pad ring?
* What are the steps that you have done in the design flow?
* What are the issues in floor plan?
* How can you estimate area of block?
* How much aspect ratio should be kept (or have you kept) and what
is the utilization?
* How to calculate core ring and stripe widths?
* What if hot spot found in some area of block? How you tackle this?
* After adding stripes also if you have hot spot what to do?
* What is threshold voltage? How it affect timing?
* What is content of lib, lef, sdc?
* What is meant my 9 track, 12 track standard cells?
* What is scan chain? What if scan chain not detached and
reordered? Is it compulsory?
* What is setup and hold? Why there are ? What if setup and hold
violates?
* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps,
Tsetup 50ps, tskew is 100ps. Then what is the maximum operating
frequency?
* How R and C values are affecting time?
* How ohm (R), fared (C) is related to second (T)?
* What is transition? What if transition time is more?
* What is difference between normal buffer and clock buffer?
* What is antenna effect? How it is avoided?
* What is ESD?
* What is cross talk? How can you avoid?
* How double spacing will avoid cross talk?
* What is difference between HFN synthesis and CTS?
* What is hold problem? How can you avoid it?
* For an iteration we have 0.5ns of insertion delay and 0.1 skew and
for other iteration 0.29ns insertion delay and 0.25 skew for the same
circuit then which one you will select? Why?
* What is partial floor plan?
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